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Authors (I)
I McCrum:
7807: 97/10/17: Xilinx delay reports?
7808: 97/10/17: [Reposted due to Enlow UCE cancel]: Xilinx delay reports?
9604: 98/03/25: Re: Lowest POWER FPGAs???
I. Purnhagen:
28336: 01/01/08: Viewlogic to Eagle and vs.
28778: 01/01/24: ACTEL 54SX bidir IF Problem
29282: 01/02/12: Virtex Symbol for eDesigner/Viewlogic
I. Servan Uzun:
32079: 01/06/13: Altera PCI developement Kit (PCI-BOARD/A4E)
32241: 01/06/21: Re: LVDS questions
36513: 01/11/10: mixed language synthesis with Synplify
41514: 02/04/01: ALTERA Apex Device
I. Ulises Hernandez:
71032: 04/07/06: Re: [Xilinx 2VP] DDR + Differential Input
71059: 04/07/07: Re: [Xilinx 2VP] DDR + Differential Input
81295: 05/03/21: Re: rocketio
81296: 05/03/21: Re: DDR simulation
81346: 05/03/22: Re: rocketio
81348: 05/03/22: Re: rocketio
89092: 05/09/05: PPC405 32 bit aligned accesses
89095: 05/09/05: Re: PPC405 32 bit aligned accesses
89114: 05/09/06: Re: PPC405 32 bit aligned accesses
89122: 05/09/06: Re: SPARATAN 2E - input clock
89142: 05/09/06: Re: PPC405 32 bit aligned accesses
89167: 05/09/07: Re: PPC405 32 bit aligned accesses
90967: 05/10/26: Re: ETHERNET MAC
91204: 05/11/01: Virtex4 temperature-sensing feature... does it work?
91236: 05/11/02: Re: Virtex4 temperature-sensing feature... does it work?
91237: 05/11/02: Re: can ethereal detect an ethernet packet for which crc is wrong
91239: 05/11/02: Re: FPGA : PCI-CORE
91871: 05/11/15: Re: Having trouble Detecting ethernet packets using ethereal
93061: 05/12/13: Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
93173: 05/12/15: Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
93392: 05/12/21: FPGA DDR controller - CKE signal... do I need a pull down?
I.S.Uzun:
48755: 02/10/23: Xilinx 16 point FFT in schematics.
I.U. Hernandez:
71007: 04/07/05: [Xilinx 2VP] DDR + Differential Input
71050: 04/07/06: Re: [Xilinx 2VP] DDR + Differential Input
<-597i1468vn4848nc3958vn32858238@knrymmup.edu>:
<i_s_uzun@yahoo.com>:
121148: 07/06/26: Re: |!|!|!|!|!|!|!Sparten 3E : !!!USB 2.0 Driver in the FPGA!!!|!!|!|!|!|!|!|!|!
Iain McClatchie:
22603: 00/05/12: Re: Q: simplest FPGA structure for novel technology demonstration
92791: 05/12/06: Re: Multi-layer switch network?
Iain Rankin:
1083: 95/04/26: Altera new FLEX 10000 - a worlds first
1084: 95/04/26: Compression algo's for FPGA's
2177: 95/10/26: FPID's
14869: 99/02/22: Re: PLX9050 Dev. Software
Iain Richardson:
12561: 98/10/16: Re: Fixed-point arithmetic coding
12739: 98/10/27: Architectures for Reed-Solomon coding/decoding
Iain Waugh:
42842: 02/05/04: Setting max skew in Xilinx software...
43956: 02/06/07: Help - Xilinx SRL16 primitive gives 'X's in simulation
44002: 02/06/09: Re: Help - Xilinx SRL16 primitive gives 'X's in simulation
Iakovos Stamoulis:
5415: 97/02/14: Re: Altera BitBlaster
6544: 97/06/02: Re: Altera Versus Xilinx
6606: 97/06/05: Re: Altera Versus Xilinx
7414: 97/09/08: Re: FPGA-to-ASIC Conversion Advice Appreciated
12724: 98/10/26: Re: VHDL Editor
<iam@deathsdoor.fsworld.co.uk>:
31358: 01/05/21: Spambot Fodder - Dont Bother To Read - Thanks
<iammayank@gmail.com>:
140893: 09/05/28: Has ST's FPGA project GOSPL transformed to Morpheus ?
ian:
66799: 04/02/26: DPRAM design issue
66807: 04/02/26: DPRAM issue
67433: 04/03/11: Xilinx RAMB16_Sm_Sn timing diagram
Ian:
5574: 97/02/25: Who's there?
63652: 03/11/27: modular design flow in Xilinx ISE 6.1.
65419: 04/01/28: Partial Reconfig Spartan 2 - Bus Macros, which one?
65450: 04/01/29: Re: Partial Reconfig Spartan 2 - Bus Macros, which one?
66262: 04/02/16: Partial Reconfig - PAR fails with ISE 6.1 SP3
66332: 04/02/17: Re: Partial Reconfig - PAR fails with ISE 6.1 SP3
66631: 04/02/24: Spartan 2 XC2S400E and XC2S600E availabillity
85810: 05/06/16: Xilinx MAP problem (>1 External Macro Output Pin on single net)
86988: 05/07/12: Re: Xilinx MAP problem (>1 External Macro Output Pin on single net)
87068: 05/07/14: Re: Xilinx MAP problem (>1 External Macro Output Pin on single net)
95337: 06/01/22: Re: OT:Shooting Ourselves in the Foot
108013: 06/09/04: Re: Performance Appraisals
108014: 06/09/04: Re: Performance Appraisals
108016: 06/09/04: Re: Performance Appraisals
111294: 06/11/01: Re: SPDIF receiver
111321: 06/11/01: Re: SPDIF receiver
114432: 07/01/15: Registered?
114473: 07/01/17: Re: Registered?
Ian & Hilda Dedic:
75957: 04/11/20: Re: Xilinx and Altera -- maximum total bitrate for high-speed serial
76192: 04/11/28: Re: Xilinx and Altera -- maximum total bitrate for high-speed serial
Ian Atkinson:
2654: 96/01/19: Re: GRRR!!! Xilinx Makebits defaults changing
Ian Baines:
1909: 95/09/19: Re: Why does MAX5000 is getting hot?
2020: 95/10/03: Re: FlexLogic download cable/schematics for one ?
Ian Bell:
85294: 05/06/07: Re: Sch & Layout Free Program
105457: 06/07/24: Re: Hardware book like "Code Complete"?
Ian Buckner:
Ian Dedic:
36112: 01/10/30: Re: Phase noise of Xilinx/Altera DLL/PLL
36753: 01/11/19: Re: Decoupling capacitors on Virtex II
37520: 01/12/13: Re: Phase noise (jitter) of XILINX logic elements - ?
38183: 02/01/08: Virtex-II parallel LVDS demo board (FAO Austin Lesea?)
73936: 04/10/01: Re: FPGA vs ASIC area
74168: 04/10/05: Re: FPGA vs ASIC area -- the crucial issue is power consumption
74215: 04/10/06: Re: FPGA vs ASIC area -- the crucial issue is power consumption
74334: 04/10/08: Re: FPGA vs ASIC area -- the crucial issue is power consumption
75626: 04/11/11: Xilinx and Altera -- maximum total bitrate for high-speed serial I/O
75687: 04/11/12: Re: Xilinx and Altera -- maximum total bitrate for high-speed serial I/O
75781: 04/11/15: Re: Xilinx and Altera -- maximum total bitrate for high-speed serial I/O
76126: 04/11/25: Re: Xilinx and Altera -- maximum total bitrate for high-speed serial I/O
78291: 05/01/28: Re: LVDS through connectors
79158: 05/02/15: Re: LVDS through connectors
Ian Field:
8736: 98/01/23: Re: PCI Bus
Ian Harrison:
2090: 95/10/12: Bet you can't do these....
Ian Hickey:
54838: 03/04/20: Very low pin count FPGA
54856: 03/04/21: Re: Very low pin count FPGA
Ian J. Smith:
23974: 00/07/19: Re: Dual Port RAM
Ian Jamison:
15939: 99/04/22: Job Advert Netiquette?
Ian Kemmish:
5371: 97/02/11: Re: DES Challenge
19766: 00/01/11: Re: HW resources increased
Ian Lance Taylor:
14459: 99/01/30: Re: The development of a free FPGA synthesis tool
Ian Lazarus:
1276: 95/05/25: Re: altera vs xilinx ???
4675: 96/11/28: Xilinx Foundation
Ian Mackereth:
693: 95/02/08: Re: "on-fly" reprogrammable devices/research
Ian McCarthy:
30112: 01/03/23: Simplified ISP of XCR3256XL from BIF file fails
30185: 01/03/27: Re: Simplified ISP of XCR3256XL from BIF file fails
Ian McCrum STAFF:
3232: 96/04/30: Simple Xilinx board
Ian McCrum, MI5AFL:
55412: 03/05/07: Re: LPM_ROM problem with Altera EP1K50 parts
59244: 03/08/13: Re: speeding up quartus
Ian McEwen:
101: 94/08/15: Re: FPGA Hobbyist and their software/programmer/hardware
119: 94/08/17: Re: FPGA Hobbyist and their software/programmer/hardware
234: 94/09/29: Re: Xilinx 4000
991: 95/04/09: Re: Xilinx XC3000a/4000 as LCD-driver
2419: 95/12/02: Re: NeoCAD and AT&T vs. Xilinx
Ian McLaren:
14895: 99/02/23: Re: Xilinx de-compiler
Ian Miller:
21961: 00/04/10: Java to HDL compiler, Free Beta
22646: 00/05/16: Re: c -> FPGA netlist compiler
25366: 00/09/08: test
Ian Muncaster:
88959: 05/09/01: New FPGA development board.
95846: 06/01/26: Re: Hi :-) Someone build a parallel JTAG cable like the xilinx one ?
96704: 06/02/09: Re: realize pci in fpga
96713: 06/02/09: Re: realize pci in fpga
96715: 06/02/09: Re: realize pci in fpga
97097: 06/02/16: Re: pci express ac coupling
100127: 06/04/04: Re: Cheap Spartan 3 PCI express starter kit
100132: 06/04/04: Re: Cheap Spartan 3 PCI express starter kit
106854: 06/08/21: Re: Using an FPGA as USB HOST without PHY
113166: 06/12/07: Re: How to find an FPGA board
Ian Okey:
62610: 03/11/03: Re: Shannon Entropy for Black Holes
Ian Packer:
710: 95/02/13: JTAG BSDL S/W Source
851: 95/03/13: Re. DSP for FPGA
855: 95/03/14: Re: Questions of implementing asynchronous circuits using FPGAs.
890: 95/03/22: AT&T FPGA Mail List
902: 95/03/27: AT&T FPGA Mailing List
908: 95/03/28: Re: AT&T FPGA Mailing List
915: 95/03/29: AT&T FPGA #6 - Application Notes
942: 95/03/31: Re: Neocad merges with Xilinx
965: 95/04/05: AT&T Statement ref Neocad
990: 95/04/08: Re: Vendor Info
1162: 95/05/08: Re: How to choose an FPGA vendor
Ian Page:
361: 94/10/28: Re: Memory
2826: 96/02/13: ARM-based ASICs
3844: 96/08/08: Re: Xilinx/FPGA Timing Problems
5849: 97/03/20: Research Posts Available at Oxford
Ian Poole:
32455: 01/06/27: XAPP268 - Dynamic Clock Data Allignment
59112: 03/08/08: Re: Block ram simulation
59202: 03/08/12: Re: Webpack sees 2 clocks when there is only one
59204: 03/08/12: Re: Win2k service packs for running Xilinx tools
59256: 03/08/13: Re: Error please Help
59331: 03/08/15: Re: Old Xilinx FPGAs
59332: 03/08/15: Re: Free VHDL Simulator
61140: 03/09/29: Re: Counting ones
62703: 03/11/05: Re: Problem in Implementation Costraints
63500: 03/11/24: Re: verification vs validation
63731: 03/12/02: Re: Design analyse methods
65933: 04/02/10: Re: Xilinx training
66081: 04/02/12: Re: Sine Wave Generation
Ian Pratt:
127: 94/08/18: ppr bug? Xilinx 3100A
649: 95/01/27: Re: Xilinx failures
Ian Robertson:
40577: 02/03/11: Re: Xilinx EDA support for run-time reconfiguration
Ian Shef:
147952: 10/06/03: Re: OT and Newbie: SDRAM Auto Refresh
149552: 10/11/05: Re: combinatorial process not simulating correctly
149587: 10/11/08: Re: PCI Parallel port detection in XILINX
151694: 11/05/05: Re: NULL POINTER DEREFERENCE
Ian Smith:
34509: 01/08/28: Re: Which is the best Design Toolchain?
36553: 01/11/12: Re: Log2(x) for vhdl?
37853: 01/12/21: Re: How to make an implementable big counter?
40136: 02/02/28: Re: Xilinx ISE 3.3 upgrade to 4.1
41131: 02/03/21: Re: 1,5V power supply?
45666: 02/07/31: Re: Who can compare the synthesis tools for me ?
Ian St John:
15585: 99/04/01: Re: Reconfigurable Computing
15944: 99/04/22: Re: Job Advert Netiquette?
15950: 99/04/22: Re: Job Advert Netiquette?
Ian St. John:
10542: 98/05/28: Re: Compiling a HLL to FPGA
10605: 98/06/05: Re: minimalist FPGA - C API for FPGA
16889: 99/06/16: Re: FPGA board for ISA bus wanted
Ian Stevenson:
9621: 98/03/27: Newbie question - FAQ for this group?
9656: 98/03/28: Re: Newbie question - FAQ for this group?
9669: 98/03/30: Re: Newbie question - FAQ for this group?
Ian Stirling:
7170: 97/08/09: Re: free FPGA software from actel
54827: 03/04/19: Re: ISE WebPack under Linux (use of command line tools)
54853: 03/04/20: Re: Very low pin count FPGA
54869: 03/04/21: Re: ISE WebPack under Linux (use of command line tools)
54890: 03/04/21: Xilinx programming (xc9500)
55170: 03/04/29: Re: Xilinx programming (xc9500)
55478: 03/05/09: Re: Encrypted bitstream - battery lifetime problem
95751: 06/01/25: Re: Constellation symbol to bit's soft-probability?
95946: 06/01/27: Re: Constellation symbol to bit's soft-probability?
Ian Yellowley:
22004: 00/04/11: Re: Is there any DSP and FPGA based board suitable to motor drive
Ian Young:
31993: 01/06/10: Re: Xilinx webpack annoyances (long and whiny)
32022: 01/06/11: Re: Xilinx webpack annoyances (long and whiny)
54276: 03/04/07: Re: Spartan-3 in docsan Webpack release notes... a joke???
54278: 03/04/07: Re: Spartan-3 in docsan Webpack release notes... a joke???
54307: 03/04/07: Re: Spartan-3 in docsan Webpack release notes... a joke???
<ian.barnes@renishaw.com>:
131794: 08/05/02: Quartus v7.x fitting bug
<Ian.Page@comlab.oxford.ac.uk>:
607: 95/01/18: FPGAs and Hardware Compilation : job offer
<ian.peikon@gmail.com>:
111816: 06/11/10: Area Constraints in Xilinx
111843: 06/11/10: Re: Area Constraints in Xilinx
111866: 06/11/11: Re: Area Constraints in Xilinx
<ian@myhost.subdomain.domain>:
299: 94/10/15: Re: PALASM versions?
Ian_Ameline:
10513: 98/05/26: Re: [++] Fast Life code (Was:Re: FPGA-based CPUs (was Re: Minimal ALU instruction set))
IB:
118360: 07/04/25: XPS and inout ports: is it possible?
<ibaggett@bagotronix.com>:
14782: 99/02/17: Re: Xilinx Spartan and pin-locking
14938: 99/02/26: Re: Xilinx ABEL?
15076: 99/03/05: Re: Looking for advice on CPLD's
Ibrahim Magdy:
85960: 05/06/19: clock domain : DDR read enable
<ibrahim_magdy_ibrahim@hotmail.com>:
80867: 05/03/13: DDR- reliable model
81278: 05/03/21: DDR simulation
IC-BOOK:
19557: 99/12/31: Bad ALTERA data
19617: 00/01/04: Bad ALTERA data
ICCAD Conference:
40402: 02/03/06: ICCAD 2002 Call for Papers
iccra:
11192: 98/07/24: [***] SRAM Controller
11260: 98/07/31: [****] VHDL Compile Error ( +, & Operator )
13045: 98/11/13: Help] Altera FloorPlan Editor
iCE65 Ultra-Low Power FPGAs:
132748: 08/06/05: ANNOUNCE: SiliconBlue Pioneers New FPGA Technology for Handheld, Ultra-Low Power Applications
icefish711:
142667: 09/08/25: [help]error from my own hard macro by FPGA edit
icegray:
81072: 05/03/17: picoblaze
84669: 05/05/24: ethernet
84717: 05/05/25: Re: ethernet
84718: 05/05/25: Re: ethernet
84721: 05/05/25: Re: ethernet
84818: 05/05/28: Re: ethernet
89983: 05/09/30: Re: PCB Software....
122507: 07/07/29: Microblaze Interrupt Handler
122519: 07/07/30: Re: Microblaze Interrupt Handler
123253: 07/08/21: MicroBlaze and ChipScope
124492: 07/09/24: Automotive Electronic Control
<icegray@gmail.com>:
110192: 06/10/12: VGA timing
110271: 06/10/12: Re: VGA timing
112483: 06/11/23: Re: Xilinx EDK - using EMC with Intel Strata Flash - assistance needed
112672: 06/11/27: Microblaze Code and XMP functions
112675: 06/11/27: Re: Microblaze Code and XMP functions
iceman:
74066: 04/10/03: FPGA servo motor controller
74113: 04/10/04: Re: FPGA servo motor controller
74323: 04/10/07: Re: FPGA servo motor controller
75727: 04/11/13: PWM using FPGA
.::[ IchiGeki ]::.:
75352: 04/11/03: FPGA for Game and Amusement
75377: 04/11/03: Re: FPGA for Game and Amusement
75378: 04/11/03: Re: FPGA for Game and Amusement
75393: 04/11/04: Re: FPGA for Game and Amusement
Icky Thwacket:
114374: 07/01/13: Re: Will FPGAs suit my need?
114393: 07/01/14: Re: Will FPGAs suit my need?
114396: 07/01/14: Re: Will FPGAs suit my need?
116490: 07/03/10: Re: ddr sdram controller
118254: 07/04/20: Re: FPGA Newbie
118905: 07/05/07: Re: About DDR SDRAM
119464: 07/05/20: Re: Signal Assignment bugs in Quartus-II ... AGAIN!
122046: 07/07/18: Re: Generating video noise.
122047: 07/07/18: Re: Generating video noise.
124249: 07/09/16: Re: sounds
130643: 08/03/29: Re: async clk input, clock glitches
130677: 08/03/30: Re: async clk input, clock glitches
130679: 08/03/30: Re: async clk input, clock glitches
132556: 08/05/31: Re: cutoff frequency
132559: 08/05/31: Re: cutoff frequency
132560: 08/05/31: Re: cutoff frequency
132794: 08/06/06: Re: HDL tricks for better timing closure in FPGAs
133000: 08/06/12: Re: Automotive Temperature +100 deg C+ FPGA's -- who's parts are available from stock
133213: 08/06/20: Re: altera technical question?
133584: 08/07/04: Re: Serial Pheripheral Interface for XILINX FPGA
133679: 08/07/09: Re: Can I store the output of my FPGA logic inside FPGA memory for debug data values?
133732: 08/07/12: Re: How to simulate baud rate generator?
134119: 08/07/26: Re: Creating new operators
134123: 08/07/26: Re: Creating new operators
134388: 08/08/08: Re: RTL Schematic as EDIF
Ico:
85072: 05/06/03: edk 6.3 : INTERNEL_ERROR
88097: 05/08/09: Re: START /STOP sync pattern
102225: 06/05/12: Re: clock multiplier in spartan 2
Ico Doornekamp:
82003: 05/04/05: ISE 7.1 unisims and cver simulation
85098: 05/06/04: Re: edk 6.3 : INTERNEL_ERROR
IDDLife:
122758: 07/08/06: Need suggestion for my project
122782: 07/08/06: Re: Need suggestion for my project
122789: 07/08/07: Re: Need suggestion for my project
122845: 07/08/08: Exception handling code in the OR1200
122869: 07/08/08: Re: Exception handling code in the OR1200
122935: 07/08/10: Re: embedded tips
124342: 07/09/18: Re: Looking for fast AES cores with low latency
124369: 07/09/19: Re: Looking for fast AES cores with low latency
Idealab Talent Team:
Identity Hidden:
98190: 06/03/07: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
idkiller:
98847: 06/03/17: help!! my modelsim occur error on strting
Ido Kleinman:
7521: 97/09/19: Altera FLEX8000
7522: 97/09/19: Altera FLEX8000
7634: 97/09/30: Re: vme vs compact pci
7826: 97/10/19: FLEX8000 configuration
7878: 97/10/26: Re: FLEX8000 configuration
12321: 98/10/09: Software tool
12322: 98/10/09: Software tool
12324: 98/10/09: VHDL'93 in MaxPlus
12391: 98/10/10: Re: Software tool
12458: 98/10/12: Re: I2C Core
12579: 98/10/17: Re: What's wrong at this Address decoder?
13491: 98/12/05: Two questions
13712: 98/12/19: Implementing an internal tri-state bus
13777: 98/12/25: Aldec integration
13944: 99/01/04: 1.5i changes
14121: 99/01/14: Hard porting to FPGA Express
14279: 99/01/23: Re: Hard porting to FPGA Express
Ido Nir:
2280: 95/11/16: 2nd Global Clocks in ALTERA MAX7000E ? Help !!!
idp2:
113966: 06/12/31: Help with ISE (multi-source in unit error)
113969: 06/12/31: Re: Help with ISE (multi-source in unit error)
114015: 07/01/02: Re: Help with ISE (multi-source in unit error)
114109: 07/01/04: Unconnected Blocks??
114113: 07/01/04: Re: Virtex 4 FIFO question
114114: 07/01/04: Re: Virtex 4 FIFO question
115011: 07/01/29: Global Clocks in Xilinx ISE
115036: 07/01/29: Re: Global Clocks in Xilinx ISE
115071: 07/01/30: Re: Global Clocks in Xilinx ISE
115172: 07/02/01: Re: Global Clocks in Xilinx ISE
115173: 07/02/01: Xilinx (without init value) has a constant value of 0?
115177: 07/02/01: Re: Xilinx (without init value) has a constant value of 0?
118933: 07/05/07: Re: DMA with ipif / user_logic
118946: 07/05/07: Re: DMA with ipif / user_logic
<idr@iss-dsp.com>:
14838: 99/02/19: Jobs in Silicon DSP IP - any takers?
<idvrlb@peerweeer.com>:
IEC5:
19217: 99/12/06: Actel Programming Information Sought
IEEE member:
117895: 07/04/12: Re: How do I use the Xilinx USB download cable for testing?
Ieromnimon F:
703: 95/02/10: Re: VERILOG
if.raso:
157942: 15/05/19: IIR filter bus width
<75if@dsdfs.com>:
17403: 99/07/24: XXX 6579
Igal K.:
26318: 00/10/12: LCELL in MAX+plusII
<igalkogan@gmail.com>:
138697: 09/03/05: Spartan 3AN wake up problem
igelado@gmail.com:
97782: 06/02/27: PCI configuration for ML310
97816: 06/02/28: Re: PCI configuration for ML310
97875: 06/03/01: Re: PCI configuration for ML310
IgI:
71572: 04/07/22: Re: 32-channel PC-based logic analyzers
73140: 04/09/14: Re: Virtex 4 released today
73165: 04/09/15: Re: Virtex 4 released today
73247: 04/09/16: Re: Virtex 4 released today
79419: 05/02/18: Issues with a batch of Virtex-II chips
79445: 05/02/19: Re: Issues with a batch of Virtex-II chips
79447: 05/02/19: Re: Issues with a batch of Virtex-II chips
79593: 05/02/21: Re: Issues with a batch of Virtex-II chips
80221: 05/03/02: Re: Signal Integrity, ground bounce, crosstalk, SSOs, BGA pin-outs, parasitic inductance...
iglam:
31741: 01/06/05: Re: Help in FIFO design
31870: 01/06/07: Re: Help in FIFO design
31881: 01/06/07: Re: Help in FIFO design
31927: 01/06/08: Re: safe state machine design problem
<iglasner@my-deja.com>:
21488: 00/03/23: Re: Good book on learning FPGA/VHDL/Verilog programming
22067: 00/04/17: Re: FPGA/PLD design tools?
22656: 00/05/16: Re: Best choice between FPGA and CPLD
22974: 00/06/06: Re: Free tools "OpenTech cdrom"
23066: 00/06/12: Re: Altera vs Xilinx
23277: 00/06/20: Re: How to cut the power disipation down ?
23294: 00/06/21: Re: How to cut the power disipation down ?
23329: 00/06/22: Re: How to cut the power disipation down ?
23332: 00/06/22: Re: 500 million transistor FPGA's
23382: 00/06/23: Re: Error: Clock skew plus hold time of destination register exceeds register-to-register delay
23386: 00/06/23: Re: 500 million transistor FPGA's
23495: 00/06/27: Re: Electronic Drivers for Brushless D C Motors
24482: 00/08/10: Re: ASIC SCAN TEST
24686: 00/08/16: Re: what does 0.35 micron mean
<iglasner@zumanetworks.com>:
22018: 00/04/12: Re: Multiple Clock design, setup & hold time violation
27176: 00/11/14: Re: CRC, LFSR and scramblers
28195: 00/12/27: Re: Methodology
Igmar Palsenberg:
54642: 03/04/15: Re: Selling CPU cores
Ignacy Kudla:
35425: 01/10/04: ISE4 - HDL Bencher
35426: 01/10/04: Xilinx ISE 4.1, HDL Bencher
Igor:
45996: 02/08/13: Reed-Solomon polynom transform....
Igor Koulikov:
33406: 01/07/25: Bound Scan
Igor Orlovich:
50276: 02/12/07: Re: Clocking in a Spartan IIE
50905: 02/12/22: Re: Hi xilinx
51086: 02/12/31: Re: dualport ram instantiation in Spartan IIE
53328: 03/03/11: Re: Using divided clock
53413: 03/03/13: Adding delay to a signal?
53474: 03/03/14: Re: Adding delay to a signal?
53475: 03/03/14: Re: Adding delay to a signal?
53485: 03/03/14: Re: Adding delay to a signal?
53527: 03/03/15: Re: Adding delay to a signal?
53535: 03/03/15: Re: Adding delay to a signal?
Igor Peker:
39114: 02/01/31: Leonardo=>MaxPlus/Quartus Vs Synopsys=>MaxPlus/Quartus
39146: 02/02/01: Re: Leonardo=>MaxPlus/Quartus Vs Synopsys=>MaxPlus/Quartus
39333: 02/02/06: Re: Leonardo=>MaxPlus/Quartus Vs Synopsys=>MaxPlus/Quartus
39334: 02/02/06: Preliminary timing simulation (Leonardo SDF => ModelSim)
39442: 02/02/09: Re: Preliminary timing simulation (Leonardo SDF => ModelSim)
<igorft@my-dejanews.com>:
16115: 99/05/04: StateCad, Renoir, EASE feedback
16116: 99/05/04: Multi-cycle path analysis in MaxPlus II
<@ihr.mrc.ac.uk>:
7069: 97/07/29: MEM_CS16 timing on ISA BUS
ii:
53922: 03/03/27: DSP-FPGA interface
Ijaz Ahmad:
69224: 04/04/30: SpyGlass Software
ikauranen:
36238: 01/11/02: Implementing NIOS softcore in ACEX
36261: 01/11/04: A problem configuring APEX device
36298: 01/11/05: Re: A problem configuring APEX device
36305: 01/11/05: Re: count and divide Idea needed
37394: 01/12/09: Re: ISA syncronization?
38165: 02/01/07: Re: Article FPGA + Reliable Systems
38250: 02/01/09: Re: FPGA and CCD : any experience?
39706: 02/02/16: Re: FPGA choices and questions
40879: 02/03/17: Re: PCI design in a Spartan II which crashes in some wintel PCs
50943: 02/12/23: Re: embedded programming of an ACEX1k30
Iker Pryszo:
70065: 04/06/01: Testing a lot of FPGA
ikki:
136156: 08/11/04: RS-232 Bus controller design in VHDL
136160: 08/11/04: Re: RS-232 Bus controller design in VHDL
136274: 08/11/09: Re: RS-232 Bus controller design in VHDL
136292: 08/11/10: Re: RS-232 Bus controller design in VHDL
136629: 08/11/27: Problem with post-route simulation / timing simulation
136684: 08/11/30: Re: Problem with post-route simulation / timing simulation
136685: 08/11/30: Re: Problem with post-route simulation / timing simulation
136686: 08/12/01: what is the difference between post-synthesis simulation and timing simulation?
<ikogan@alumni.technion.ac.il>:
123747: 07/09/03: Actel IGLOO FPGA has lower power consumption then Xilinx Coolrunner-II CPLD?
Ilan Ron:
5163: 97/01/28: FPGA power dissipation
6225: 97/04/30: Interface between WVo731 VHDL and ORCA
7356: 97/08/31: MCS - intel86 format
ilaroche:
147269: 10/04/21: Synplify synthesis error
147300: 10/04/22: Re: Synplify synthesis error
147407: 10/04/26: Re: Synplify synthesis error
<ilewg@osodru.to>:
Ilia Oussorov:
12765: 98/10/28: !Recommendation wanted! Which CAD for shematic entry of Xilinx FPGA'based devices choose
14998: 99/03/02: Student edition!
17161: 99/07/06: Re: Xilink FPGA
17518: 99/08/05: serial multiplier with LogiCore scaled 1/2 accumulator
17526: 99/08/06: Re: serial multiplier with LogiCore scaled 1/2 accumulator
17543: 99/08/09: Re: serial multiplier with LogiCore scaled 1/2 accumulator
17555: 99/08/10: Re: serial multiplier with LogiCore scaled 1/2 accumulator
18155: 99/10/04: Clock multiplexing in Virtex
18489: 99/10/27: Timing & bidirectional buses
18626: 99/11/04: which is the maximum freqency?
<ilia_2s@mail.ru>:
154352: 12/10/12: Re: SPDIF receiver
Ilija Hadzic:
6724: 97/06/19: Re: Flex 8000 confuguartion question - DCLK pin
7841: 97/10/21: Re: FLEX8000 configuration
9165: 98/02/26: Re: Questions about FPGA
14904: 99/02/24: Re: Your view on this article?
Ilko Iliev:
40102: 02/02/27: PAL to JEDEC convertor
Illan:
37246: 01/12/04: Re: Synplify 7 and Xilinx 4.1 Pair
37247: 01/12/04: Re: Synplify and clk discovery
37249: 01/12/04: Re: the timing of LPM_RAM_DP
Ilpo Hamunen:
10690: 98/06/10: Re: How about Lattice ispLSI?
<iluvfpgas@yahoo.ca>:
78459: 05/02/01: Re: Evaluating EDIF netlist
<iluvmylife@gmail.com>:
104161: 06/06/20: Need help reg Power Estimation using PowerPlay
Ilya Kalistru:
156156: 13/12/24: Re: Use of latches in FSMs
156158: 13/12/26: Re: Use of latches in FSMs
158118: 15/08/11: Strange way to route design.
158119: 15/08/11: Re: Strange way to route design.
158122: 15/08/11: Re: Strange way to route design.
158123: 15/08/12: Re: Strange way to route design.
158512: 15/12/15: modulo 2**32-1 arith
158531: 15/12/19: Re: modulo 2**32-1 arith
158532: 15/12/19: Re: modulo 2**32-1 arith
158534: 15/12/19: Re: modulo 2**32-1 arith
158536: 15/12/19: Re: modulo 2**32-1 arith
158537: 15/12/19: Re: modulo 2**32-1 arith
158539: 15/12/20: Re: modulo 2**32-1 arith
158542: 15/12/20: Re: modulo 2**32-1 arith
158543: 15/12/20: Re: modulo 2**32-1 arith
158550: 15/12/21: Re: modulo 2**32-1 arith
158623: 16/02/07: Source control and ip cores
158625: 16/02/07: Re: Source control and ip cores
158652: 16/02/26: Re: Source control and ip cores
158909: 16/05/21: Multi-port memory
158913: 16/05/21: Re: Multi-port memory
158953: 16/05/28: Re: Explicitly setting a variable to undefined
158956: 16/05/28: Re: Explicitly setting a variable to undefined
158957: 16/05/28: Re: Explicitly setting a variable to undefined
158966: 16/05/29: Re: Explicitly setting a variable to undefined
160044: 17/05/17: Re: Test Driven Design?
160080: 17/05/19: Re: Test Driven Design?
160083: 17/05/20: Re: Test Driven Design?
160087: 17/05/20: Re: Test Driven Design?
160088: 17/05/20: Re: Test Driven Design?
160093: 17/05/23: Re: Test Driven Design?
160120: 17/06/02: Re: Test Driven Design?
160121: 17/06/02: Article about using Non-Project Mode
160124: 17/06/03: Re: Article about using Non-Project Mode
160126: 17/06/10: Re: Article about using Non-Project Mode
160128: 17/06/12: Re: Article about using Non-Project Mode
160130: 17/06/13: Re: Article about using Non-Project Mode
160250: 17/08/23: Re: Article about using Non-Project Mode
160251: 17/08/23: Re: Test Driven Design?
160253: 17/08/27: Re: Article about using Non-Project Mode
Ilyin:
3913: 96/08/19: Test - please ignore
im.de:
86678: 05/07/03: xapp 482 and add custom function
87469: 05/07/24: DCM.
Imadur Rahman:
51609: 03/01/17: Problem in compiling EDIF in Handel-C
51885: 03/01/24: Using Xilinx Logicores in Handel-C!
51910: 03/01/25: Re: DK1 grunt
52090: 03/01/31: WLAN Implementation using Handel-C?
Image Simulation:
19364: 99/12/16: Re: Virtex boards
Iman SedehZadeh:
28816: 01/01/25: how to reduce number of gates in xor reducing in crc computing?
<imanpreet@gmail.com>:
80834: 05/03/12: (Stupid/Newbie) Question on UART
Imanuddin Amril Account:
11233: 98/07/29: TRISTATE in FPGA
11356: 98/08/06: Re: TRISTATE in FPGA
11617: 98/08/27: compile -ungroup_all
imaslacker:
77687: 05/01/14: Re: Does SPI from NIOS II work?
imavroid:
99844: 06/03/29: how can one get a netlist consisting of SLICEs?
99852: 06/03/30: Re: how can one get a netlist consisting of SLICEs?
<imclaren@california.com>:
20529: 00/02/13: Re: xilinx
20902: 00/02/26: Re: Design security
20903: 00/02/26: Re: Foundation 2.1i device support?
<imity>:
114810: 07/01/24: Does xiling cpld's need a power supply bypass cap?
114831: 07/01/24: Re: Does xiling cpld's need a power supply bypass cap?
iml:
88887: 05/08/31: usb and xc95
Immo Birnbaum:
90381: 05/10/11: Question regarding FPGA startup ROMs
imp.chris:
100884: 06/04/20: Xilinx OPB Arbiter
impana:
156601: 14/05/08: Re: DDR speed of the XUPV2P Board from Digilent
<impanaeng@gmail.com>:
156597: 14/05/07: Re: DDR speed of the XUPV2P Board from Digilent
Imti:
121110: 07/06/25: Re: Can anyone identify the manufacturer of this Chip ?
<imtiazali77@gmail.com>:
156663: 14/05/27: Re: Quartus II under Windows7?
In Memory of tecNovia:
39106: 02/01/31: Linking IP
39490: 02/02/11: Re: Xilinx EDIF to BIT transation
39519: 02/02/12: Re: Xilinx EDIF to BIT transation
40609: 02/03/11: Re: Xilinx Download Cable Connectors
41022: 02/03/19: Re: Xilinx JTAG Cables
In2Home User:
17264: 99/07/15: I was wondering if anyone could help..
<in_spb3@yahoo.com>:
108151: 06/09/06: Packages for ORCAD
inamikadika:
52997: 03/02/27: Altera APEX20KE timing issue
Inder:
39626: 02/02/14: Orca ngdbuild error: could not expand block
39647: 02/02/15: Re: Orca ngdbuild error: could not expand block
39689: 02/02/15: Re: Orca ngdbuild error: could not expand block
Indie Tinde:
149233: 10/10/11: Is Spartan 6 good for this project?
149237: 10/10/11: Re: Is Spartan 6 good for this project?
Indroneel Ganguly:
85099: 05/06/04: Xilinx ISE Webpack download problem
ines_fr:
144419: 09/12/05: spartan 3 and multiprocessor
144431: 09/12/07: Re: spartan 3 and multiprocessor
144442: 09/12/08: dual core microblaze
144545: 09/12/14: multiprocessors MB and shared BRAM
144580: 09/12/16: Re: multiprocessors MB and shared BRAM
144582: 09/12/16: Re: multiprocessors MB and shared BRAM
144623: 09/12/21: multiprocessor on spartan 3
144669: 09/12/22: Re: multiprocessor on spartan 3
144686: 09/12/22: multiprocessor architecture
144780: 10/01/02: MB debug module
144781: 10/01/02: MB debug module
150154: 10/12/21: using a cordic on EDK
<inesviskic@gmail.com>:
99751: 06/03/28: How to set the Chipscope trigger to the very start of the user appl?
99890: 06/03/30: Re: How to set the Chipscope trigger to the very start of the user appl?
info:
667: 95/02/01: Interesting DA Sources - issue 101 (Feb 95)
15219: 99/03/15: APS, Xilinx FPGA Boards Now Available Direct In Europe
15474: 99/03/25: DesignWorks now available direct in Europe from EuroEDA
16282: 99/05/13: Trade-In Offer - ABEL, MINC & Synario Users in Europe
16755: 99/06/07: WaveFormer Pro & TestBencher Pro V6.0 Released
17824: 99/09/08: SynaptiCAD Timing Analysis & HDL Test Bench Generation Tools
20768: 00/02/21: GateVision - Netlist to Schematic Generation Tools
Info:
13290: 98/11/24: Wafer mapping software
<info2@rayed.de>:
129300: 08/02/20: Re: From ASIC RTL to FPGA, what are the things I should take care of?
129340: 08/02/21: Re: Software Defined Radio auf Xilinx Virtex 4
129953: 08/03/11: Re: SiliconBlue enters the FPGA fray
135769: 08/10/15: Re: XMOS XC-1 kits are shipping
<info@bostonsemiconductor.com>:
76619: 04/12/07: Re: doubt on configuring SPARTAN2E FPGA
77371: 05/01/05: Re: Whither common courtesy ?
<info@embednet.com>:
15363: 99/03/20: Affordable and reliable IrDA infrared communications for 8/16/32/64 bit CPU's
<info@forpctechs.com>:
<info@igoor.net>:
<info@lykjxowq.edu>:
12853: 98/11/02: bestore.com º¸Çè»óÇ°¾È³»
<info@mage.com>:
5011: 97/01/12: Internet Fax Service
<info@pgrs.com>:
7465: 97/09/13: WANT A FREE PAGER? LOOK HERE!
<info@r-and-d.de>:
18872: 99/11/19: ARM7TDMI compatible synthesisable Module available
<info@seriousmonkey.com>:
26609: 00/10/22: - Major automotive website
<info@taotech.com>:
10540: 98/05/28: make PADS software run on fast computers
10541: 98/05/28: make PADS software run on fast computers
info_:
81114: 05/03/18: Re: Tornado Board and Education Kit is available.
81187: 05/03/19: Re: Using XC2V6000 to send/receive test vectors.
81214: 05/03/19: Re: One-hot statemachine design problems
81216: 05/03/19: Re: Spartan 3 to tempsensor interface
81221: 05/03/19: Re: Post-Trasnlation Simulation using ModelSim in XST
81223: 05/03/19: Re: One-hot statemachine design problems
81253: 05/03/20: Re: One-hot statemachine design problems
81254: 05/03/20: Re: Question from Newbie about FPGAs
81269: 05/03/21: Re: RS 232 receiver using spartan 3 board
81526: 05/03/26: Re: DSP designs that exceed provided embedded arithmetic hardware
81541: 05/03/27: Re: some +. for Altera
81549: 05/03/27: Re: Mixing synchronous and asynchronous reset
81564: 05/03/28: Re: some +. for Altera
81565: 05/03/28: Re: Problem with flip-flops on Spartan 3
81567: 05/03/28: Re: Xilinx backups
81735: 05/03/30: Re: PID Controller implemented on FPGA
81736: 05/03/30: Re: Out of Memory Error comes suddenly.
81737: 05/03/30: Re: How to map FPGA pin outputs and use User Constraints File (UCF)
81786: 05/03/31: Re: Quartus II 4.1 Problem
81788: 05/04/01: Re: newbie verilog question
81868: 05/04/03: Re: USB blaster
81869: 05/04/03: Re: Initializing Altera MEGARAMs in simulation
82023: 05/04/06: Re: FPGA with 2 JTAG ports
82024: 05/04/06: Re: File I/O with Synplify
82356: 05/04/11: Re: lcd controller - how to realize it?
82357: 05/04/11: Re: vhdl code for the 2-line lcd on xilinx boards
83132: 05/04/24: Re: READ/WRITE files using TEXTIO using Quartus
83133: 05/04/24: Re: slow peripherals and modelsim
83138: 05/04/24: Re: slow peripherals and modelsim
83195: 05/04/26: Re: Spartan 3 to tempsensor interface
83196: 05/04/26: Re: "Correct design" and practical trouble and simulation trouble
83197: 05/04/26: Re: slow peripherals and modelsim
83198: 05/04/26: Re: bad syncronous description
83209: 05/04/26: Re: Spartan 3 to tempsensor interface
83276: 05/04/27: Re: Sync + FIFO
83277: 05/04/27: XC4k parts obsolete ?
83333: 05/04/28: Re: Sync + FIFO
83334: 05/04/28: Re: XC4k parts obsolete ?
83387: 05/04/28: Re: crazy behaviour of fpga, timing ?
83422: 05/04/29: Re: how can I improve my code?
83423: 05/04/29: Re: signals in modelsim
83424: 05/04/29: Re: signals in modelsim
83437: 05/04/29: Re: signals in modelsim
83442: 05/04/29: Re: Sync + FIFO
83455: 05/04/30: Re: crazy behaviour of fpga, timing ?
83456: 05/04/30: Case statement illusions ?
83460: 05/04/30: Re: Case statement illusions ?
83467: 05/04/30: Re: Case statement illusions ?
83469: 05/04/30: Re: problems getting flex10k10 to work
83479: 05/05/01: Re: Case statement illusions ?
83482: 05/05/01: Re: problems getting flex10k10 to work
83501: 05/05/01: one hot decoder
83651: 05/05/04: Re: one hot decoder
83652: 05/05/04: Re: Case statement illusions ?
83837: 05/05/07: Re: crazy behaviour of fpga, timing ?
83839: 05/05/07: Re: crazy behaviour of fpga, timing ?
83842: 05/05/08: Re: FPGA choice advice needed
83855: 05/05/08: Re: FPGA choice advice needed
83976: 05/05/10: Re: crazy behaviour of fpga, timing ?
84055: 05/05/12: Re: RS 232 receiver using spartan 3 board
84056: 05/05/12: Re: Slice Virtex II = Equivalent gates ??
84057: 05/05/12: Re: 8051 IP core
84059: 05/05/12: Re: crazy behaviour of fpga, timing ?
84208: 05/05/14: Re: Quartus II Fitter Problem
86259: 05/06/23: Re: Good FPGA introduction book ?
86260: 05/06/23: Re: FPGA :FFT Core in Xilinx
86355: 05/06/26: Re: Module integration, odd state machine behaviour (verilog), etc!
86356: 05/06/26: Re: good bye nios (o;
92984: 05/12/11: Re: Post PAR Simulation and Actual FPGA results differ
<Information>:
6867: 97/07/04: Metrics
Infraglobe Pte Ltd:
15469: 99/03/25: Singapore Job Opportunity : ASIC Design Engineer
Ing. Cristiano Golin:
13622: 98/12/14: FAQ Address Please
Ing. Salvatore Di Fazio:
20006: 00/01/23: Cypress programming information for old 370i devices.
InGenius Engineering:
27669: 00/12/01: Hey there anybody!!
29587: 01/02/27: ASIC ASIC ASIC - CANADA - ASIC ASIC ASIC ASIC ASIC
inGenius People:
33248: 01/07/20: Senior IC Engineer
Ingenrepons:
100822: 06/04/18: cannot be synthesized, bad synchronous description
Ingmar Hohmann:
15899: 99/04/20: How to use TDO pin of Xilinx4000 in Exemplar ?
15938: 99/04/22: Re: How to use TDO pin of Xilinx4000 in Exemplar ?
33583: 01/07/31: Re: i2c master
Ingmar Seifert:
108264: 06/09/07: Bitgen warning message DCM
Ingo Cyliax:
1674: 95/08/14: Question about intro. Xilinx software
1817: 95/09/06: Xilinx FPGA(XC3000) netlister for Chipmunk/diglog
1818: 95/09/06: Xilinx FPGA(XC3000) netlister for Chipmunk/diglog
2121: 95/10/18: Ceramic Resonators with xc3000 int. Oscillator
2127: 95/10/18: Re: Ceramic Resonators with xc3000 int. Oscillator (solution)
2310: 95/11/18: Re: [Q] FPGA Software for Linux
2370: 95/11/24: XNF netlister for Chipmunk
2374: 95/11/24: PC/Parallel poret Atmel Configuration EEPROM programmer
2903: 96/02/27: Re: Programming ATMEL config. PROMs ?
3678: 96/07/11: wireless loader for (Xilinx) FPGAs ?
5162: 97/01/28: Re: FPGA & division
7530: 97/09/19: Re: Atmel 17256 serial config EEPROMs
10201: 98/05/03: Re: Xilinx Foundation and Linux
11495: 98/08/19: Parallel Xilinx Xchecker Cable Pinouts
13650: 98/12/16: unbonded pads in Xilinx M1.4 with xc4000e
14206: 99/01/20: Re: The development of a free FPGA synthesis tool
15314: 99/03/18: Re: Xilinx Spartan configuration troubles
29279: 01/02/12: Re: Virtex XCV2000E-6 BG560C - Orcad capture symbol
Ingo Froehlich:
12312: 98/10/08: Xilinx Foundation forgets the pin assignment. Bug?
Ingo Purnhagen:
16895: 99/06/16: vhdl and viewlogic problem
17244: 99/07/14: Mixed Design Problem (FPGA Express/ACTEL)
17861: 99/09/14: ACTEL Viewlogic Problem
17898: 99/09/16: simple UART for ACTEL (SX) wanted
InHighPlace:
InmateRemo:
116905: 07/03/20: softcore CPU tools
Inquiring Guy:
70013: 04/05/27: Good Devlopement Board for learning
72541: 04/08/23: Re: Xilinx - Proper VHDL for Bidirectional Pins
ins:
3637: 96/07/05: Motorola 68000 Chips
INS122595:
70340: 04/06/13: Re: Cores into fpga
70462: 04/06/17: Re: Is there a verilog version of PicoBlaze?
71429: 04/07/18: Re: ChipScope Pro : Stimulation
72251: 04/08/12: Re: How to ? 2.1i to ISE6.2 SCHEMATIC converter!!
72319: 04/08/14: Re: How to ? 2.1i to ISE6.2 SCHEMATIC converter!!
72845: 04/09/05: Re: vga to ethernet converter
<Inside>:
8514: 98/01/01: A KILLER BULK EMAILING PACKAGE!..DYNAMITE INFO!...
Insight/Xilinx:
5766: 97/03/13: VHDL Training Course, April 10 & 11
5767: 97/03/13: Xilinx Schematic Based Training, Rockville,MD April 7-9
5788: 97/03/14: Free Xilinx 9500 Seminar. Gaithersburg,MD March 19
<insight@highwayman.tv>:
58738: 03/07/31: Spartan 3 Overshoot limit
-:Install:-:
34274: 01/08/18: Re: star-wars ascii-animation:)
int19h:
95629: 06/01/25: How to handle the "gate count" issue?
95780: 06/01/26: Re: How to handle the "gate count" issue?
101440: 06/05/01: Re: Question about the ip I developed
102829: 06/05/22: Re: How simple can FPGA design be? (Mission Possible 2006)
103138: 06/05/26: Re: Quartus and Cygwin X-server
Inter-BBS:
6320: 97/05/14: FreeNetAccessWorldwide
<Interfacebus.Engineer@gmail.com>:
96819: 06/02/10: Re: Async Processors
interHDL Inc:
9281: 98/03/05: Re: The case for Linux and EDA
intermilan:
140555: 09/05/16: Problem with ML410 board ethernet
143143: 09/09/23: Problem found in Xilinx icap driver for kernel 2.6
143175: 09/09/24: Virtex 4 configruation frame internal details
143246: 09/09/28: Re: Virtex 4 configruation frame internal details
143333: 09/10/02: Very interesting finding about V4 CLB configuration bits
1997 International Symposium on Physical Design:
4214: 96/09/28: CFP - 1997 Intl. Symp. on Physical Design, April 14-16, CA
4256: 96/10/05: CFP: 1997 Intl. Symp. on Physical Design, April 14-16, CA
4355: 96/10/19: CFP: 1997 Intl. Symp. on Physical Design, April 14-16, CA
4422: 96/10/27: CFP: 1997 Intl. Symp. on Physical Design, April 14-16, CA
4479: 96/11/03: CFP: 1997 Intl. Symp. on Physical Design, April 14-16, CA
4536: 96/11/10: CFP: 1997 Intl. Symp. on Physical Design, April 14-16, CA
4662: 96/11/26: CFP: 1997 Intl. Symp. on Physical Design, April 14-16, CA
4695: 96/12/02: ISPD-97 CFP (Dec 20 Submission Deadline)
4734: 96/12/09: ISPD-97 CFP (Dec 20 Submission Deadline)
4802: 96/12/17: ISPD-97 CFP (Dec 20 Submission Deadline)
5618: 97/03/01: ISPD-97 Advance Pgm & Registration: (April 14-16, Napa CA)
5702: 97/03/08: ISPD-97 (final week for early registration)
5794: 97/03/16: ISPD-97 (Important Announcement RE Hotel & Registration)
6112: 97/04/13: ISPD-97 Registration FULL
Internet-PC:
35899: 01/10/23: Re: Hardware help requested
<internet_checker@yahoo.com>:
128145: 08/01/16: Timing Analyzer hangs
interrogativo:
118912: 07/05/07: Help with ATF750CL and WinCUPL
119317: 07/05/16: Re: Help with ATF750CL and WinCUPL
<IntimateSVC@GetPaid.com>:
7956: 97/11/03: deleted spam
7957: 97/11/03: deleted spam
inv___:
154424: 12/10/28: TMDS CML PCB
154430: 12/10/29: Re: TMDS CML PCB
invalid:
145390: 10/02/08: Re: using an FPGA to emulate a vintage computer
Invalid IP:
83929: 05/05/10: Clock speed problem. How can I proceed?
Invalid User:
81396: 05/03/22: Re: OPB component for serial Flash?
81590: 05/03/28: Re: looking for keyboard scancode
<invalid@invalid.com>:
54650: 03/04/15: Re: request for simple UART
55755: 03/05/19: Re: smallest embedded cpu....and the most pain?
55791: 03/05/19: Re: smallest embedded cpu....and the most pain?
<invest@goldbergservices.com>:
4758: 96/12/11: $$$$ $50,000 for the New Year $$$$
Invincible:
63947: 03/12/10: Maximum bus speed of APB.
Invisible One:
65727: 04/02/05: Artificial Intelligence/FPGA
65914: 04/02/10: Re: Artificial Intelligence/FPGA
66766: 04/02/26: Suggestions: Eval/Demo Board.
67392: 04/03/11: Re: difference btw H/W & S/W implementations !!
67551: 04/03/14: Re: difference btw H/W & S/W implementations !!
io:
73224: 04/09/16: Quartus In-system Memory bug
73270: 04/09/17: Re: Quartus In-system Memory bug
73393: 04/09/21: Re: Quartus In-system Memory bug
91109: 05/10/29: Re: xilinx design reuse netlist format
<io@duke.edu>:
58963: 03/08/05: model sim block ram sim
58986: 03/08/05: Re: model sim block ram sim
Ioana Dabacan:
144721: 09/12/28: FPGA design contest
Iode:
54128: 03/04/03: CoolRunner freezes
56880: 03/06/18: Cyclone vs. Acex consumption?
56942: 03/06/19: Re: Cyclone vs. Acex consumption?
Ioiod:
122583: 07/08/01: Xilinx Webpack 9.2 and Windows 2000 Pro?
122584: 07/08/01: Re: Best CPU platform(s) for FPGA synthesis
122585: 07/08/01: Re: Best CPU platform(s) for FPGA synthesis
122586: 07/08/01: Altera Cyclone II and Cyclone III "distributed" RAM?
Iouri Besperstov:
31665: 01/06/01: Re: My80-- i8080A instruction compatible processor core
31681: 01/06/02: Re: My80-- i8080A instruction compatible processor core
33416: 01/07/25: Re: Homemade Xilinx parallel cable problem
iovanalex:
139312: 09/03/25: Avnet FX12 module, OLED example / problem
iPierre:
30128: 01/03/24: config FPGA OK but nothing running !?
30250: 01/03/29: VHDL Test bench
30252: 01/03/29: CLK / STARTUP PB
30260: 01/03/29: Re: Please help a poor student with virtexe
ippisl:
153716: 12/04/29: Tabula's fpga
<ipreuse@my-deja.com>:
19091: 99/11/29: Announcement: Opportunities at Intellectual Property Reuse/System-On-A-Chip Start Up Company
19121: 99/11/30: IP Reuse/System-On-A-Chip Start Up Company
IPSIS.news:
22999: 00/06/08: [JOB] Designer / FPGA
IPU:
16894: 99/06/16: vhdl and viewlogic problem
<iqbalmuh@hotmail.co.uk>:
127633: 08/01/04: What does this do ?
iquadri:
140951: 09/05/30: Xilinx PDR flow questions - Time function and DDR RAM access
141124: 09/06/07: Power Estimation for Dynamic Reconfiguration
141261: 09/06/13: Correlation Algorithm: converting user type integer array into
141266: 09/06/14: Re: Correlation Algorithm: converting user type integer array into
141610: 09/06/30: Formatting ML405 system compact flash card.;
Ira Baxter:
99519: 06/03/25: Re: OpenSPARC released
99527: 06/03/26: Re: OpenSPARC released
100094: 06/04/03: Re: OpenSPARC released
Ira Hart:
109168: 06/09/21: Re: Verification errors using Xilinx Spartan 3E board
Ira Thorpe:
100161: 06/04/04: Streamlining FIRs in System Generator
100502: 06/04/10: Interfacing to DDS v5.0 in System Generator
<irezki@gmail.com>:
91436: 05/11/06: The Xilinx MultiPoint Synthesis Flow - Synplify Pro
<irfan.mohammed@gmail.com>:
103734: 06/06/09: Requesting for an Actel Library
133598: 08/07/05: basic chipscope pro query
133616: 08/07/06: Re: basic chipscope pro query
133865: 08/07/17: example of counter for chipscope pro generator
134103: 08/07/25: chipscope pro
134295: 08/08/04: vhdl or verilog code for 64 point ifft
Iris Dimni:
80543: 05/03/08: ML310 boot settings
irish:
86512: 05/06/29: Quatech SPP-100 programs/verifies successfully but device is not "programmed"
87033: 05/07/13: Implement a JTAG controller in an FPGA
88066: 05/08/08: ZLIB anyone?
Irit:
20261: 00/02/03: Looking for a small, fast CPU core for FPGA
<irmadesrosiers85@gmail.com>:
159584: 17/01/04: Re: ISERDES2 divide factor
159585: 17/01/04: Re: ISERDES2 divide factor
irum4:
45872: 02/08/08: Spartan II IOBUF
61522: 03/10/06: Problem with PCI cards
61530: 03/10/06: Problem with PCI cards
61579: 03/10/07: Re: Problem with PCI cards
Irwin Kennedy:
36128: 01/10/30: Field Programmable Logic in energy poor environments
66854: 04/02/27: Re: Stratix 2 ALUT architecture patented ?
66940: 04/03/01: Re: Stratix 2 ALUT architecture patented ?
67010: 04/03/03: Re: frame length, frame addressing ?
83389: 05/04/28: Re: dynamic size of ports
<isa-->:
72747: 04/09/01: From good-old ISA bus cards to PCI bus
72772: 04/09/01: Re: From good-old ISA bus cards to PCI bus
72773: 04/09/01: Re: From good-old ISA bus cards to PCI bus
Isaac:
56896: 03/06/18: WR/RD Problem
56943: 03/06/19: Port Mode
57895: 03/07/09: How to change Read Only Constraint to Read-Write
57912: 03/07/09: Re: How to change Read Only Constraint to Read-Write
57946: 03/07/10: Re: How to change Read Only Constraint to Read-Write
58167: 03/07/16: How to edit encrypted NGC file produced using XILINX ISE 5
58221: 03/07/17: Problem Xilinx edif2ngd
58261: 03/07/18: Timming Specification Error
58336: 03/07/21: Clock DLL error
58383: 03/07/22: FPGA Editor
58666: 03/07/30: Downloading into XCV600
58701: 03/07/31: Downloading into XCV600
59051: 03/08/07: Error Generate Statement
59249: 03/08/13: Error please Help
59584: 03/08/22: Signal within block
60223: 03/09/08: Clock Synchronization of PC and FPGA
60259: 03/09/09: Re: Clock Synchronization of PC and FPGA
60427: 03/09/12: Downloading into XCV600 FPGA using PCI
60492: 03/09/15: Re: Downloading into XCV600 FPGA using PCI
60881: 03/09/24: Reading from FPGA Issue
61002: 03/09/26: Re: Reading from FPGA Issue
61209: 03/09/30: Re: Reading from FPGA Issue
63035: 03/11/13: Reading O value
Isaac B.:
95771: 06/01/25: Re: Spartan-3 Starter Board
Isaac Bosompem:
96516: 06/02/05: VGA and framebuffer interface (Waste of BlockRAM)
96517: 06/02/05: Re: VGA and framebuffer interface (Waste of BlockRAM)
96546: 06/02/06: Re: VGA and framebuffer interface (Waste of BlockRAM)
96555: 06/02/06: Re: VGA and framebuffer interface (Waste of BlockRAM)
96762: 06/02/09: Spartan3 embedded synchronous multipliers
96813: 06/02/10: Re: Spartan3 embedded synchronous multipliers
96870: 06/02/12: Re: DDR2 SDRAM controller
97124: 06/02/16: Re: Need some Advice, please
97126: 06/02/16: Re: WIFI Compact Flash
97243: 06/02/19: Re: Addressing BRAM in a V2 pro
97245: 06/02/19: Re: FPGA - software or hardware?
97247: 06/02/19: Re: help with VGA timings
97309: 06/02/20: Re: help with VGA timings
97382: 06/02/21: Re: Is FPGA code called gateware?
97406: 06/02/21: Re: Is FPGA code called gateware?
97407: 06/02/21: Re: Is FPGA code called gateware?
97563: 06/02/23: Re: Combinatorial Division?
97566: 06/02/23: Re: Combinatorial Division?
97634: 06/02/24: Re: Combinatorial Division?
97700: 06/02/26: Re: Combinatorial Division?
97724: 06/02/26: Re: Combinatorial Division?
97787: 06/02/27: Re: Combinatorial Division?
97983: 06/03/02: Re: Help wanted
98163: 06/03/06: Re: Which CPU and Screen Rez for ISE 6.3i ?
98183: 06/03/06: Re: Which CPU and Screen Rez for ISE 6.3i ?
98546: 06/03/12: Re: Question about multi write ports RAM in FPGA?
98608: 06/03/13: Re: Why does Xilinx hate version control?
98626: 06/03/13: Re: Why does Xilinx hate version control?
98806: 06/03/16: Re: risc processor in altera up3 kit
98810: 06/03/16: Re: Debugging ideas.
98951: 06/03/17: Re: Urgent Help Needed!!!!!
99062: 06/03/19: Re: Have you ever considered of mousing ambidextrously?
99076: 06/03/19: Re: FPGA FIR advice
99101: 06/03/20: Re: FPGA FIR advice
99130: 06/03/20: Re: FPGA FIR advice
99196: 06/03/21: Re: Virtex 4 deconfiguring itself ...
99323: 06/03/22: Re: Are Quad-processors advantageous?
99326: 06/03/22: Re: OpenSPARC released
99509: 06/03/25: Re: Nios II - Branch Prediction
99662: 06/03/27: Re: WARNING:Xst:1778 - Inout <AddrBus>
99675: 06/03/27: Re: WARNING:Xst:1778 - Inout <AddrBus>
99839: 06/03/29: Re: FpgaC developers wanted :)
100112: 06/04/03: Re: Problem erasing EEPROM XCF08P
100427: 06/04/08: Re: C-Compiler for free VHDL controller core ?
101789: 06/05/06: Re: CPU resource type
101939: 06/05/08: Re: Xilinx 3s8000?
102018: 06/05/09: Re: Xilinx 3s8000?
102124: 06/05/10: Re: Superscalar Out-of-Order Processor on an FPGA
102125: 06/05/10: Re: Superscalar Out-of-Order Processor on an FPGA
109191: 06/09/21: Re: Dell Laptop for Embedded Work
109286: 06/09/22: Re: OT: Google display of this thread
110260: 06/10/12: OT: Internships?
110268: 06/10/12: Re: OT: Internships?
110330: 06/10/13: Re: OT: Internships?
110331: 06/10/13: Re: OT: Internships?
110333: 06/10/13: Re: OT: Internships?
110382: 06/10/14: Looking for internship near Toronto
111069: 06/10/27: Re: FPGA-based music synthesizer (with MyHDL)
Isabel:
55660: 03/05/15: Do Service Pack of Xilinx really fixed the problems?
55726: 03/05/17: Urgent: About ModelSim XEII Starter
Isabelle:
27605: 00/11/29: Reverse-engineering FPGA's
Isabelle Gonthier:
8998: 98/02/12: Re: Devices and Prices
9106: 98/02/20: Re: Why altera CPLDS are slow to power-up?
9654: 98/03/27: Re: XactStep6 - The cure for a dongle
9738: 98/04/02: Re: Rees-Solomon
10166: 98/04/30: Re: Q: XILINX Foundation
19339: 99/12/15: Re: VirtexE availability?
<isabellelaroche@gmail.com>:
138480: 09/02/24: XST hangs on HDL Analysis
ischoi(etri.re.kr):
17096: 99/06/30: Q: About input/output_delay constraints in Synopsys Design compiler
18830: 99/11/18: How can I specify the fanout constraints at FPGA compiler II & M1
<iscyoh@hongkong.com>:
Isidoros Sideris:
80977: 05/03/15: Register file with LUTs in a SPARTAN3
Isidro Urriza:
24080: 00/07/26: Pad trireg in XLA FPGA
Islam Ossama:
117440: 07/03/30: Help with a face recognition system
117447: 07/03/30: Re: Help with a face recognition system
117452: 07/03/31: Re: Help with a face recognition system
117454: 07/03/31: Re: Help with a face recognition system
117498: 07/04/02: Re: Help with a face recognition system
120805: 07/06/17: Help configuring XUP PPC for Ethernet
Ismail Haritaoglu:
1364: 95/06/07: Some benchmark circuits in XNF
=?iso-2022-jp?B?GyRCMEIwZhsoQiAbJEI3chsoQg==?=:
21407: 00/03/22: Re: Clock nets using non-dedicated resources
21466: 00/03/23: Re: Clock nets using non-dedicated resources
21678: 00/03/29: Re: Clock on non-dedicate pin
24025: 00/07/24: Re: Virtex DLL problem.
=?iso-2022-jp?B?GyRCQFZMWjUxQ0sbKEI=?=:
18655: 99/11/05: =?iso-2022-jp?B?GyRCJUElYyVzJTkbKEI=?=
=?ISO-8859-15?Q?Andr=E9_Schieleit?=:
81801: 05/04/01: modelsim: Types do not match
81895: 05/04/04: Re: modelsim: Types do not match
=?ISO-8859-15?Q?Andreas_H=F6lscher?=:
135030: 08/09/11: How to install Xilinx ISE simulator?
<=?ISO-8859-15?Q?Andreas_K=FChn?=>:
78797: 05/02/08: Re: Xilinx Virtex2p configuration
=?ISO-8859-15?Q?Benjamin_Menk=FCc?=:
81297: 05/03/21: WLAN in VHDL
81722: 05/03/30: Software Defined Radio
81836: 05/04/01: Parallelsignal at 85 MHz
82215: 05/04/08: Getting started with Virtex-II Pro LC Dev Board
82244: 05/04/09: Re: Getting started with Virtex-II Pro LC Dev Board
82278: 05/04/10: clk_div illigal connection
82282: 05/04/10: vhdl and clock-pin
82284: 05/04/10: Re: vhdl and clock-pin
82291: 05/04/10: vhdl code for the 2-line lcd on xilinx boards
82303: 05/04/10: LVDS for lcd panel and RocketIO
82306: 05/04/10: Problem with appnote XAPP622 (SDR LVDS)
82322: 05/04/11: Re: LVDS for lcd panel and RocketIO
82342: 05/04/11: lcd controller - how to realize it?
82345: 05/04/11: Re: lcd controller - how to realize it?
82354: 05/04/11: Re: lcd controller - how to realize it?
82355: 05/04/11: Re: LVDS PCI card is needed
82360: 05/04/12: process trouble, error: multi source
82361: 05/04/12: Re: lcd controller - how to realize it?
82973: 05/04/20: LVDS pin assignment
82980: 05/04/21: Re: LVDS pin assignment
83131: 05/04/24: slow peripherals and modelsim
83134: 05/04/24: Re: slow peripherals and modelsim
83171: 05/04/25: Re: slow peripherals and modelsim
83179: 05/04/25: bad syncronous description
83181: 05/04/25: Re: bad syncronous description
83182: 05/04/25: Re: bad syncronous description
83185: 05/04/25: Re: bad syncronous description
83186: 05/04/25: Re: slow peripherals and modelsim
83194: 05/04/26: Re: slow peripherals and modelsim
83255: 05/04/26: Re: slow peripherals and modelsim
83314: 05/04/27: obufds attribute problem
83318: 05/04/27: Re: obufds attribute problem
83366: 05/04/28: clk-pad, ibufg, dcm Problem
83384: 05/04/28: Re: clk-pad, ibufg, dcm Problem
83386: 05/04/28: Re: clk-pad, ibufg, dcm Problem
83413: 05/04/29: how can I improve my code?
83419: 05/04/29: signals in modelsim
83428: 05/04/29: Re: signals in modelsim
83450: 05/04/30: Re: how can I improve my code?
83451: 05/04/30: Re: signals in modelsim
83536: 05/05/02: writing with impact to eeprom
83537: 05/05/02: 200+ MHz through a SCSI cable
83543: 05/05/02: Re: writing with impact to eeprom
83577: 05/05/03: I got it!
83687: 05/05/05: how to constrain this
83690: 05/05/05: Re: how to constrain this
83692: 05/05/05: DCM constraints
83693: 05/05/05: Re: DCM constraints
83697: 05/05/05: found out why, still some questions
83699: 05/05/05: Re: I got it!
83703: 05/05/05: Re: how to constrain this
83705: 05/05/05: Re: I got it!
83721: 05/05/06: cascaded dcms
83724: 05/05/06: including components, i.e. SRL16
83746: 05/05/06: Re: including components, i.e. SRL16
83749: 05/05/06: creating testbench with data from logic analyzer
83750: 05/05/06: wrong place
83760: 05/05/06: Re: cascaded dcms
83763: 05/05/06: on chip termination for DVI (TMDS) possible?
83765: 05/05/06: a note
83901: 05/05/09: DDR speed of the XUPV2P Board from Digilent
83912: 05/05/09: Re: DDR speed of the XUPV2P Board from Digilent
83921: 05/05/10: Re: DDR speed of the XUPV2P Board from Digilent
83962: 05/05/10: Re: DDR speed of the XUPV2P Board from Digilent
83966: 05/05/10: Re: DDR speed of the XUPV2P Board from Digilent
84031: 05/05/11: Re: signals in modelsim
86384: 05/06/27: vsync on dvi
86393: 05/06/27: Re: vsync on dvi
86577: 05/06/30: Re: FPGA for video processing
90604: 05/10/18: clock timing
90641: 05/10/18: Re: clock timing
90683: 05/10/19: Re: clock timing
90684: 05/10/19: Re: clock timing
90723: 05/10/19: Re: clock timing
90724: 05/10/19: Re: clock timing
=?ISO-8859-15?Q?G=F6ran_Bilski?=:
79691: 05/02/23: Re: Problems with a 4-MicroBlaze Multiprocessor Architecture
80001: 05/02/28: Re: Problems with a 4-MicroBlaze Multiprocessor Architecture
80344: 05/03/04: Re: How to profile performances of an OPB bus
80957: 05/03/15: Re: [Newbie] Microblaze and uC/OS-II on Spartan3
=?ISO-8859-15?Q?Gr=E9gory_Mermoud?=:
76813: 04/12/13: Re: UART receiver
=?ISO-8859-15?Q?Heinz=2DJ=FCrgen?= Oertel:
88069: 05/08/08: Re: NIOS Small C library
89985: 05/10/01: Re: Prevue - FPGA Dev Board Sale
=?ISO-8859-15?Q?J=FCrgen_B=F6hm?=:
150887: 11/02/19: ISEWebPack RTL schematic viewer and IMPACT problems
=?ISO-8859-15?Q?Johan_Bernsp=E5ng?=:
86588: 05/06/30: Re: PROM Generation question
=?iso-8859-15?Q?Manfred_M=FCcke?=:
58344: 03/07/21: Q: Quartus II Schematic Editor Limitations
63174: 03/11/17: Re: Altera's altsyncram MAXIMUM_DEPTH
63356: 03/11/20: Re: Altera's altsyncram MAXIMUM_DEPTH
63429: 03/11/21: Re: Altera's altsyncram MAXIMUM_DEPTH
63869: 03/12/06: Re: Altera's altsyncram MAXIMUM_DEPTH
=?iso-8859-15?Q?Michael_Sch=F6berl?=:
66502: 04/02/20: Serial ATA with Xilinx RocketIO (Virtex 2 Pro)??
68781: 04/04/18: Re: Microblaze Sub-Module Adventure
69492: 04/05/12: Re: How do I find where P&R has placed my BRAM?
70564: 04/06/21: Re: VDHL implementation of RAM with serial input and parallel outpout ? thx
71608: 04/07/24: Re: VHDL
71624: 04/07/25: Re: 1GHz FPGA counters
71632: 04/07/26: Re: 1GHz FPGA counters
=?ISO-8859-15?Q?Michael_Sch=F6berl?=:
96657: 06/02/08: Re: why does speed grade effect VHDL program??
97263: 06/02/20: Re: DDR SDRAM Controller
97819: 06/02/28: Re: How do I make dual-port RAM from single port RAM?
97832: 06/02/28: Re: conv_integer
99084: 06/03/20: Re: SerialATA with Virtex-II Pro
99264: 06/03/22: Re: need help on asynchronous buffer
102152: 06/05/11: Re: sqrt(a^2 + b^2) in synthesizable VHDL?
107427: 06/08/28: EDK 6.3 project file growth
109132: 06/09/21: Fast Platform for ISE?
109586: 06/09/29: Re: Fast Platform for ISE?
110053: 06/10/10: Re: ise 8.2 partitions
110795: 06/10/23: PowerPC somehow unstable at 300 MHz
110835: 06/10/24: Re: Fastest ISE Compile PC?
=?ISO-8859-15?Q?St=E9phane_Goujet?=:
103512: 06/06/05: Re: FPGA board for USB experiments?
103515: 06/06/05: Re: FPGA board for USB experiments?
103562: 06/06/06: Re: FPGA board for USB experiments?
=?ISO-8859-15?Q?Stefan_Brr=F6ring?=:
147215: 10/04/19: Re: Need to run old 8051 firmware
=?ISO-8859-15?Q?Uwe_Klo=DF?=:
66673: 04/02/25: Re: Dual-stack (Forth) processors
=?iso-8859-1?B?6U1L4A==?=:
78780: 05/02/07: FPGA Prototyping
=?iso-8859-1?B?R2FMYUt0SWtVc5k=?=:
86111: 05/06/21: choosing an fpga board
86112: 05/06/21: Re: choosing an fpga board
86114: 05/06/22: Re: choosing an fpga board
86115: 05/06/22: Re: choosing an fpga board
86142: 05/06/22: Re: choosing an fpga board
86170: 05/06/22: Virtex 4 and reconfigurable computer
86206: 05/06/22: Re: Virtex 4 and reconfigurable computer
86207: 05/06/22: Re: choosing an fpga board
89298: 05/09/12: place and route
89365: 05/09/13: Re: place and route
89395: 05/09/14: Re: place and route
89747: 05/09/23: jbits
89839: 05/09/27: Re: jbits
89840: 05/09/27: Re: jbits
90572: 05/10/17: XChecker cable and chipscope
90654: 05/10/18: Xilinx USB cable
90672: 05/10/18: Re: Xilinx USB cable
90784: 05/10/20: ML401
90789: 05/10/20: Re: ML401
91362: 05/11/04: ChipScope and Spartan-3 Starter Kit (DO-SPAR3-DK)
91372: 05/11/04: Re: ChipScope and Spartan-3 Starter Kit (DO-SPAR3-DK)
91376: 05/11/04: icarus verilog
91415: 05/11/05: Re: Anybody understand this ISE 7.1 error, and what to do about it???
91421: 05/11/06: Re: Anybody understand this ISE 7.1 error, and what to do about it???
91813: 05/11/14: Re: ISE, JTAG and ChipScopePro.
92367: 05/11/28: ML403 GPIO Switch not present
92369: 05/11/28: Re: ML403 GPIO Switch not present
92467: 05/11/30: ISE Simulator not present in Linux?
92480: 05/11/30: Re: ISE Simulator not present in Linux?
92481: 05/11/30: Re: ISE Simulator not present in Linux?
92655: 05/12/03: ML403 "small" problem
92667: 05/12/03: Re: ML403 "small" problem
92697: 05/12/05: Chipscope under Linux
92762: 05/12/06: Re: Chipscope under Linux
92779: 05/12/06: Re: ISE SP4 installer on Linux
92821: 05/12/07: A stupid question about constraints
92825: 05/12/07: Re: A stupid question about constraints
92921: 05/12/09: Re: What graphical entry/documentation tools?
93015: 05/12/12: Question about Xilinx UCF files
93023: 05/12/12: Re: Question about Xilinx UCF files
93024: 05/12/12: Re: modelsim settings in edk
93026: 05/12/12: Re: who can help me? i want to know the bitsream format of Virtex-II
93085: 05/12/13: Question about Progamming File generation report
93105: 05/12/13: ISE WebPack 8.1i
93107: 05/12/13: Re: Future of Microchip Development Tools?
93114: 05/12/13: Re: ISE WebPack 8.1i
93134: 05/12/14: Re: Question about Progamming File generation report
93230: 05/12/15: Re: ISE 8.1i on Fedora Core 4 (64-bit)
93298: 05/12/19: Virtex-4 Startup
93321: 05/12/19: Re: Virtex-4 Startup
93322: 05/12/19: Re: help: how to use ICAP of Virtex-II ?
94159: 06/01/06: Re: Virtex-4 FX12 EMAC with ISE WebPack
94638: 06/01/15: Re: ISE 8.1i WebPack available
94448: 06/01/11: Re: Downloading WebPack-8.1, server maxes out at 30 kB / second (= > 7 hours)?
95181: 06/01/21: Re: EDK 8.1, Finally!
95195: 06/01/21: Xilinx Partial Reconfiguration add-on module
95200: 06/01/21: ISE BaseX customers
96980: 06/02/14: Re: is there a way to initialize signals to a value
96981: 06/02/14: Re: ModelSim Licence problem
98396: 06/03/09: Re: since xilinx ise 8.1 support linux red hat 4.0 (with device Spartan-3 400k)
99026: 06/03/19: Virtex-4 BRAM control signal inversion
99203: 06/03/21: Virtex-4 RocketIO and G.709 OTU-2
99349: 06/03/23: Re: Virtex-4 RocketIO and G.709 OTU-2
99454: 06/03/24: System design methodology
100004: 06/04/01: Modular Design and Incremental Design in ISE
100404: 06/04/08: Re: Virtex-4 RocketIO and G.709 OTU-2
101344: 06/04/29: URGENT: Xilinx site
101385: 06/04/30: ML403 ZBT SRAM
101391: 06/04/30: Xilinx MPPR failing
101494: 06/05/02: Re: ML403 ZBT SRAM
101508: 06/05/02: Problem with DCM simulation models
101641: 06/05/04: Re: ML403 ZBT SRAM
103260: 06/05/29: IOB IO Standards in Spartan 3
103261: 06/05/29: Re: IOB IO Standards in Spartan 3
103262: 06/05/29: Personalization of Xilinx ISE
103264: 06/05/29: Re: IOB IO Standards in Spartan 3
103944: 06/06/15: Re: How to get lowest price for a ModelSim license?
103949: 06/06/15: Re: How to get lowest price for a ModelSim license?
104045: 06/06/17: Re: How to get lowest price for a ModelSim license?
104049: 06/06/17: Re: How to get lowest price for a ModelSim license?
105276: 06/07/19: PCIe: use 8*x1 PHY devices to form x8
105311: 06/07/19: Re: Combining Schematic and VHDL code in Webpack 8.1 ??
105323: 06/07/20: ISE 8.2i and EDK8.1i
106020: 06/08/05: Re: MIG 1.6 DDR2 testing problems (FIFO16 related?)
106188: 06/08/08: Question about SSTL
107054: 06/08/23: Checking syntax
107074: 06/08/24: ISERDES strange simulation behaviour
107141: 06/08/24: Re: Checking syntax
107142: 06/08/24: Re: ISERDES strange simulation behaviour
107173: 06/08/25: Re: ISERDES strange simulation behaviour
107197: 06/08/25: Re: ISERDES strange simulation behaviour
107264: 06/08/25: Re: ISERDES strange simulation behaviour
109216: 06/09/21: Re: Xilinx MIG fails
109716: 06/10/04: Re: Xilinx PowerPC & MicroBlaze Development Kit
109932: 06/10/08: Re: Xilinx-Modelsim on Linux
109941: 06/10/08: Re: Xilinx-Modelsim on Linux
110091: 06/10/10: Re: Xilinx-Modelsim on Linux
110276: 06/10/13: Spartan-3/3E Board
110298: 06/10/13: Re: Virtex-5 LXT orderable?
110479: 06/10/16: Re: Virtex-5 LXT orderable?
113422: 06/12/13: Re: Energy consumption estimation of Virtex-4
113513: 06/12/15: Re: Partial reconfiguration
124200: 07/09/14: Re: Is post-place and route simulation useful?
125277: 07/10/18: Re: Dynamic Reconfiguration books
125280: 07/10/19: Re: Dynamic Reconfiguration books
=?ISO-8859-1?B?RGlu52F5IEFr5/ZyZW4=?=:
145047: 10/01/22: Spartan 3E Starter Kit - Power problem
145055: 10/01/22: Re: Spartan 3E Starter Kit - Power problem
145060: 10/01/23: Re: Spartan 3E Starter Kit - Power problem
145065: 10/01/24: Re: How to connect two BNC connectors to FPGA board?
145452: 10/02/10: Re: Spartan-3E Starter Kit reconfiguration problems
147888: 10/05/30: Re: Programming Digilent Nexys 2 from Linux
148699: 10/08/18: Re: Getting started with FPGA
148700: 10/08/18: Re: Getting started with FPGA
148858: 10/09/04: Cyclone 3 clock pins
149156: 10/10/05: Re: External Circuit to FPGA.
149157: 10/10/05: Re: External Circuit to FPGA.
149464: 10/10/27: Re: FPGA I/O Issues.
151388: 11/04/01: Re: Ideal FPGA Development Kit
=?iso-8859-1?B?RmRvLkxl824=?=:
105211: 06/07/18: noob question: reset problem
=?iso-8859-1?B?RWRtb25kIENvdOk=?=:
117166: 07/03/25: Altera memory init file (.hex/.mif) generation using gcc objcopy - how to change base address??
118011: 07/04/16: Embedding Altera SignalTap II on 1st synthesis/implementation pass
118210: 07/04/19: Re: Embedding Altera SignalTap II on 1st synthesis/implementation pass
118874: 07/05/05: Re: Atom HDL
119418: 07/05/18: Precision RTL and DesignWare libraries
119424: 07/05/18: Re: Precision RTL and DesignWare libraries
119432: 07/05/18: Re: Precision RTL and DesignWare libraries
119876: 07/05/28: Re: Quartus-II 7.1 Systemverilog interface?
120133: 07/06/01: Re: Quartus-II 7.1 Systemverilog interface?
123531: 07/08/29: Registered output for Altera on-chip memory
=?iso-8859-1?B?SGFucyBI/GJuZXI=?=:
102698: 06/05/19: LISP Workshop at ECOOP06
102772: 06/05/19: Re: LISP Workshop at ECOOP06
=?iso-8859-1?B?SGVybuFuIFPhbmNoZXo=?=:
86735: 05/07/05: Re: PS/2 interface
120010: 07/05/30: Re: XS40 Download Cable
=?iso-8859-1?B?VPRG?=:
92483: 05/11/30: systemC vs VHDL
92502: 05/11/30: Re: systemC vs VHDL
101981: 06/05/09: Chipscope and FPGA
=?iso-8859-1?B?VXRrdSDWemNhbg==?=:
112222: 06/11/17: Re: FFT in VHDL (or Verilog) Tutorial
112564: 06/11/24: Re: Verilog problem: default case to set signal xxxx
116424: 07/03/08: Re: How best do I implement routing boxes in RTL?
<(=?iso-8859-1?Q?=AF=60=B7=2E=2E=2E=F8=A4=B0=60=B0=A4TEL4=20=A4=B0=60=B0=A4=2E=2E=2E=2E=B7=B4=AF?=)>:
=?iso-8859-1?Q?=C1ngel=20Guti=E9rrez?=:
23141: 00/06/15: PWM
23275: 00/06/20: PWM
23517: 00/06/28: How to do ...?
=?iso-8859-1?Q?=C8=AB=C0=BA=C1=BE?=:
17572: 99/08/11: PCI core
=?ISO-8859-1?Q?Adam_G=F3rski?=:
134031: 08/07/22: Re: powering fpga with lm317
135629: 08/10/10: Re: Lattice vs Altera (Mico32 / NIOS)....or?
135850: 08/10/17: Re: Port mapping (combining components)
137669: 09/01/27: Re: NIOS is stuck at alt_tick after reset
137817: 09/01/30: Re: byteblaster cloning
137957: 09/02/03: Re: NIOS is stuck at alt_tick after reset
144132: 09/11/12: Re: Altera/EPCS16 issues
144199: 09/11/19: Re: AvalonST to Avalon MM Bridge
145681: 10/02/18: Re: Derived clock violation in Virtex4
146088: 10/03/05: Re: Laptop for FPGA design?
146419: 10/03/17: Re: Nested interrupts in Nios system and hung system
155946: 13/10/19: Re: draw lines, circles, squares on FPGA by mouse and display on
155972: 13/10/30: Re: draw lines, circles, squares on FPGA by mouse and display on
156057: 13/11/16: Re: Cyclone V hard memory controller
156537: 14/04/17: Re: Spartan 3 JTAG problems
156605: 14/05/12: Re: need coding
156617: 14/05/14: Re: need coding
156625: 14/05/15: Re: need coding
156629: 14/05/16: Re: need coding
=?ISO-8859-1?Q?Alex_K=FChn?=:
48536: 02/10/19: altera lpm_divide megafunction
=?iso-8859-1?q?Andr=E9_Powell?=:
25437: 00/09/11: Re: Code distribution without loss of IP?
<=?ISO-8859-1?Q?Andr=E9_Schekatz?=>:
73799: 04/09/29: Evaluation Board for Xilinx Virtex
=?ISO-8859-1?Q?Andr=E9s?=:
78948: 05/02/10: Re: Virtual Pins in QuartusII
79013: 05/02/11: Re: Virtual Pins in QuartusII
79624: 05/02/22: Pin Declaration in new EC/ECP FPGAs
79629: 05/02/22: Tristate Discussion
79690: 05/02/23: Re: Tristate Discussion
79692: 05/02/23: Quartus DESIGN ASSISTANT tool
79773: 05/02/24: Re: Quartus DESIGN ASSISTANT tool
79865: 05/02/25: EC/ECP Map Problem
80617: 05/03/09: Global Reset paths
80764: 05/03/11: Re: Global Reset paths
80901: 05/03/14: Re: Global Reset paths
81353: 05/03/22: LogicAnalyzer ispTracy
=?ISO-8859-1?Q?Andre_Sch=E4fer?=:
98436: 06/03/10: Re: can bus protocol on fpga
98447: 06/03/10: Re: can bus protocol on fpga
98453: 06/03/10: Re: can bus protocol on fpga
98602: 06/03/13: Re: Soldering SMT/BGA
=?ISO-8859-1?Q?Andreas_H=F6lscher?=:
68928: 04/04/22: Re: Xilinx FPGA one project loadable, another not - any hint?
76837: 04/12/14: Re: Need help with CUPL
131860: 08/05/05: Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
<=?ISO-8859-1?Q?Andreas_K=FChn?=>:
92818: 05/12/07: Re: Partial Reconfiguration Problems
<=?ISO-8859-1?Q?Antonio_Mart=EDnez_=C1lvarez?=>:
44006: 02/06/09: Do you know a e-mail list where I can make questions about Handel-C
44301: 02/06/17: Does anyone have experience with HandelC and Celoxica's RC1000 with
45374: 02/07/20: Do you know a parallel algorithym for 2D convolution
=?iso-8859-1?q?Asbj=F8rn?= Djupdal:
48183: 02/10/13: hardmacro problem
48211: 02/10/14: Re: hardmacro problem
48216: 02/10/14: Re: hardmacro problem
49623: 02/11/18: xst and vhdl-generate
=?ISO-8859-1?Q?Barth=E9l=E9my__von_Halle?=:
62347: 03/10/27: Re: BoardScope
=?ISO-8859-1?Q?Barth=E9l=E9my_von_Haller?=:
62334: 03/10/27: BoardScope
=?ISO-8859-1?Q?Benjamin_Menk=FCc?=:
83137: 05/04/24: Re: New FPGA Development Board
83452: 05/04/30: Re: signals in modelsim
83459: 05/04/30: Re: Case statement illusions ?
83462: 05/04/30: Re: Case statement illusions ?
83571: 05/05/03: Re: 200+ MHz through a SCSI cable
83575: 05/05/03: Re: 200+ MHz through a SCSI cable
83747: 05/05/06: Re: DVI implementation
83748: 05/05/06: Re: Spartan-3 boards comparison
83890: 05/05/09: Re: DVI implementation
83963: 05/05/10: Re: DVI implementation
84012: 05/05/11: Re: An FPGA eval board at $49!!
84087: 05/05/12: Re: DDR speed of the XUPV2P Board from Digilent
84261: 05/05/16: Re: DDR speed of the XUPV2P Board from Digilent
86416: 05/06/27: Re: vsync on dvi
90610: 05/10/18: Re: clock timing
90642: 05/10/18: Re: clock timing
90655: 05/10/18: Re: clock timing
=?ISO-8859-1?Q?Beno=EEt?=:
32849: 01/07/10: ATMCAM & UTOPIA Bus in VHDL
33035: 01/07/16: can not create a distributed Memory
33990: 01/08/10: Orcad symbol for a Virtex II
35268: 01/09/27: altera APEX 20KE
=?ISO-8859-1?Q?Bernhard_M=E4der?=:
49219: 02/11/05: LVDS I/Os on Virtex-II Devices: Short circuit safety?
49272: 02/11/07: Re: LVDS I/Os on Virtex-II Devices: Short circuit safety?
49559: 02/11/15: Asynchronous FIFOs using Handel-C?
=?iso-8859-1?Q?Bj=F8rn?= B. Larsen:
5225: 97/01/31: Re: Steven K. Knapp - no such article
=?ISO-8859-1?Q?C=E9dric_Jeanneret?=:
93631: 05/12/27: Microblaze in a EDK pcore
=?ISO-8859-1?Q?Cristina_Rodr=EDguez?=:
144202: 09/11/19: IP core for Bluetooth or Wifi
=?iso-8859-1?Q?Cyrille_de_Br=E9bisson?=:
42306: 02/04/19: Re: 1000 I/O Pins -- What is cheapest FPGA?. What about Route and place needs
=?iso-8859-1?q?Dag-Erling_Sm=F8rgrav?=:
93338: 05/12/20: Re: real-time compression algorithms on fpga
=?ISO-8859-1?Q?Daniel_K=F6the?=:
60213: 03/09/08: IP-Core CAN-Controller
69034: 04/04/26: Re: Need last service pack for Xilinx ISE 4.2i
69732: 04/05/19: Initialize Blockram from file
<=?ISO-8859-1?Q?David_de_Andr=E9s_Mart=EDnez?=>:
71031: 04/07/06: BRAM problems using JBits
71205: 04/07/12: Re: Programable Logic & Video stuff
=?iso-8859-1?q?Dennis_Kr=F8ger?=:
67335: 04/03/10: Re: fpga
=?ISO-8859-1?Q?Didier_M=E9quignon?=:
79065: 05/02/13: Programmable clock problem
=?ISO-8859-1?Q?Eduardo_Wenzel_Bri=E3o?=:
54589: 03/04/14: Bus Macros:Power Supply
55593: 03/05/13: Problems with Leonardo Spectrum
55825: 03/05/20: Modular Design: Map error
56160: 03/05/29: MapLib Error (463 ) in Modular Design Flow
59579: 03/08/22: Problems with PAR tool in Modular Design flow
=?ISO-8859-1?Q?Enno_L=FCbbers?=:
137907: 09/02/02: Find instance name of BUFG inside DCM
137949: 09/02/02: Re: Find instance name of BUFG inside DCM
<=?ISO-8859-1?Q?Fernando_Peral_P=E9rez?=>:
95476: 06/01/23: =?ISO-8859-1?Q?obtaining_ABEL_code_from_schematics_sou?=
=?ISO-8859-1?Q?G=F3rski_Adam?=:
149616: 10/11/11: Re: Altera JTAG problem
150136: 10/12/16: Re: Question about SOPC and SOF file
151725: 11/05/11: Re: Soft Processors and Licensing
<=?ISO-8859-1?Q?G=F3rski_Adam?=>:
124866: 07/10/09: Re: Cyclone II - PLL differential output
127785: 08/01/08: Re: Bad micro blaze behaviour during power off
127789: 08/01/08: Re: Bad micro blaze behaviour during power off
128509: 08/01/29: Re: regarding DMA memory to memory copy in NIOS II
128542: 08/01/30: Re: regarding DMA memory to memory copy in NIOS II
129855: 08/03/07: Re: how to Load file data into memory by NIOS II IDE?
131003: 08/04/08: Re: NoisII or else.
131012: 08/04/08: Re: NoisII or else.
131059: 08/04/09: Re: NoisII or else.
131947: 08/05/08: Re: Quartus 7.2 and PCI Express
131987: 08/05/09: Re: Quartus 7.2 and PCI Express
=?iso-8859-1?Q?G=F6ran_Bilski?=:
127209: 07/12/14: Re: Newbee Microblaze system BRAM utlization confusion
=?ISO-8859-1?Q?G=F6ran_Bilski?=:
74231: 04/10/06: Re: FSL State machine to read data in
74239: 04/10/06: Re: FSL State machine to read data in
75796: 04/11/15: Re: Soft Processor Core
75806: 04/11/15: Re: Soft Processor Core
77532: 05/01/10: Re: San Jose job offer - need advice
77842: 05/01/18: Re: Creating a pyramid of shift registers
77868: 05/01/19: Re: Creating a pyramid of shift registers
78060: 05/01/24: Re: Comparison of LEON2, Microblaze and Openrisc processors
78071: 05/01/24: Re: Power Analisys with MicroBlaze
78085: 05/01/24: Re: Power Analisys with MicroBlaze
78759: 05/02/07: Re: warning messages,NgdBuild:454,DesignRules:331
78806: 05/02/08: Re: warning messages,NgdBuild:454,DesignRules:331
78834: 05/02/08: Re: BRAM utilization - how to calculate
79008: 05/02/11: Re: C program to big for microblaze?
79088: 05/02/14: Re: 2 microblaze access same BRAM ?
79100: 05/02/14: Re: 2 microblaze access same BRAM ?
79148: 05/02/15: Re: Weird Mircroblaze programm execution
79270: 05/02/16: Re: 2 microblaze access same BRAM ?
79285: 05/02/16: Re: 2 microblaze access same BRAM ?
79320: 05/02/17: Re: 2 microblaze access same BRAM ?
79380: 05/02/18: Re: microblaze with opb, brams?
79798: 05/02/24: Re: Prescalable counter
79804: 05/02/24: Re: 2 microblaze access same BRAM ?
79805: 05/02/24: Re: 2 microblaze access same BRAM ?
79997: 05/02/28: Re: Prescalable counter
79998: 05/02/28: Re: Implementing Multi-Processor Systems in FPGAs
80075: 05/03/01: Re: 2 microblaze access same BRAM ?
80081: 05/03/01: Re: 2 microblaze access same BRAM ?
80183: 05/03/02: Re: 2 microblaze access same BRAM ?
80351: 05/03/04: Re: 1,5Mhz Clock
81083: 05/03/17: Re: 2 microblazes, 1 opb, 2 BRAMs
81133: 05/03/18: Re: 2 microblazes, 1 opb, 2 BRAMs
81155: 05/03/18: Re: 2 microblazes, 1 opb, 2 BRAMs
82568: 05/04/14: Re: Embedded MicroBlaze solution
83146: 05/04/25: Re: Speed acceleration !!!
84268: 05/05/16: Re: How to implement this C function in FPGA
84375: 05/05/18: Re: Help needed!!interrupt handling in microblaze system
84970: 05/06/02: Re: How to speed up float computing--continued
85236: 05/06/07: Re: how to use FPU with EDK7.1i
85485: 05/06/10: Re: faster Spartan III adder
86685: 05/07/04: Re: Xilinx: XST synchronous FIFO using BRAMs
89337: 05/09/13: Re: Microblaze & Memory DMA operation
89442: 05/09/15: Re: Microblaze & Memory DMA operation
92158: 05/11/23: Re: Microblaze and custom peripherals
92221: 05/11/24: Re: Microblaze and custom peripherals
95869: 06/01/26: Re: Microblaze data cache question
95974: 06/01/27: Re: Microblaze data cache question
95973: 06/01/27: Re: Microblaze data cache question
95976: 06/01/27: Re: Multichannel Opb Memory Controller question
98203: 06/03/07: Re: Internal Signals in OPB EMC In XIlinx PLatform studio
98578: 06/03/13: Re: using EDK with the gcc -g option...
98583: 06/03/13: Re: using EDK with the gcc -g option...
99081: 06/03/20: Re: Microblaze FSL peripheral problem
99082: 06/03/20: Re: microprocessor design: where to go from here?
99770: 06/03/29: Re: How to set the Chipscope trigger to the very start of the user
100278: 06/04/06: Re: FSL to VHDL interface
100350: 06/04/07: Re: FSL to VHDL interface
102080: 06/05/10: Re: Superscalar Out-of-Order Processor on an FPGA
103452: 06/06/02: Re: Using ChipScope with EDK flow?
105240: 06/07/18: Re: Post Place and Route simulation for Microblaze....
105498: 06/07/24: Re: Soft processor performance
106845: 06/08/21: Re: CPU design
106885: 06/08/22: Re: CPU design
106895: 06/08/22: Re: CPU design
107395: 06/08/28: Re: FSL read/write problems
107478: 06/08/29: Re: FSL read/write problems
108335: 06/09/08: Re: microblaze startup problem
108413: 06/09/11: Re: microblaze startup problem
109012: 06/09/20: Re: Buffering the critical path.
109045: 06/09/20: Re: Buffering the critical path.
109125: 06/09/21: Re: Buffering the critical path.
=?ISO-8859-1?Q?GaLaKtIkUs(tm)?=:
126516: 07/11/26: ISE and Itanium
128824: 08/02/07: ML410 and documentation on ALi M1535D+
128855: 08/02/07: Re: ML410 and documentation on ALi M1535D+
=?ISO-8859-1?Q?Gerrit_Sch=FCnemann?=:
137019: 08/12/19: Custom IP Core DMA (Xilinx Virtex II Pro)
=?ISO-8859-1?Q?Glenn_M=F8ller-Holst?=:
134678: 08/08/26: Re: need fast FPGA suggestions [ AFPGA ? ]
=?ISO-8859-1?Q?Gr=E9gory_Mermoud?=:
76097: 04/11/24: Bus macro problem in dynamic partial reconfiguration
76120: 04/11/25: Re: Bus macro problem in dynamic partial reconfiguration
76123: 04/11/25: LUT use to control Xilinx bus macro
76127: 04/11/25: Re: LUT use to control Xilinx bus macro
76995: 04/12/19: Output macro pins
76996: 04/12/19: Bus macro pins
77538: 05/01/10: Editing bitstream
77546: 05/01/10: Re: Editing bitstream
77662: 05/01/13: Xilinx FPGA editor
77676: 05/01/13: Re: Xilinx FPGA editor
77725: 05/01/15: No respect of external pins (xilinx)
77737: 05/01/16: Re: No respect of external pins (xilinx)
77738: 05/01/16: Re: No respect of external pins (xilinx)
77739: 05/01/16: Re: No respect of exernal pins [xilinx]
77740: 05/01/16: Re: No respect of external pins (xilinx)
77750: 05/01/16: Re: No respect of external pins (xilinx)
77772: 05/01/17: Re: No respect of external pins (xilinx)
77773: 05/01/17: Re: No respect of external pins (xilinx)
77784: 05/01/17: Re: No respect of external pins (xilinx)
=?ISO-8859-1?Q?Guilherme_Corr=EAa?=:
130256: 08/03/18: Re: Using TimeQuest Timing Analyzer
130278: 08/03/19: Re: Using TimeQuest Timing Analyzer
=?ISO-8859-1?Q?H=E5kon?=:
34055: 01/08/13: Virtex-II and LVDS clocks.
=?ISO-8859-1?Q?Hans-Bernhard_Br=F6ker?=:
126784: 07/12/02: Re: lossless compression in hardware: what to do in case of uncompressibility?
=?ISO-8859-1?Q?Heinz=2DJ=FCrgen?= Oertel:
154898: 13/02/01: Using CAN on Zynq
154927: 13/02/17: Re: Using CAN on Zynq
=?iso-8859-1?Q?J=E9r=E9mie?= WEBER:
20063: 00/01/26: Pin to pin
=?iso-8859-1?Q?J=F6rg?= Ritter:
25575: 00/09/14: coregen or logiblox
25991: 00/09/29: Re: Synopsys FPGA Compiler II on Solaris
26444: 00/10/16: ordered list
26526: 00/10/19: Re: Synopsys FPGA Compiler II on Solaris
28485: 01/01/15: Re: Looking for prototyping board
28936: 01/01/30: Re: set/reset
30207: 01/03/28: Re: Xilinx par -m
30299: 01/04/02: pseudo random numbers
30306: 01/04/02: Re: pseudo random numbers
30369: 01/04/04: Re: pseudo random numbers
=?ISO-8859-1?Q?J=FCrgen_B=F6hm?=:
100990: 06/04/23: ISE 8.1i for Linux ?
112332: 06/11/20: Spartan 3 Starter Kit .mcs upload problem
112738: 06/11/28: Bus structures question (Spartan 3)
112819: 06/11/29: Re: Bus structures question (Spartan 3)
115697: 07/02/17: Re: Where to start???
126553: 07/11/27: CPU design uses too many slices
126578: 07/11/28: Re: CPU design uses too many slices
126579: 07/11/28: Re: CPU design uses too many slices
126701: 07/11/29: Re: CPU design uses too many slices
126708: 07/11/30: Re: CPU design uses too many slices
129118: 08/02/14: Spartan 3 configuration download error
129122: 08/02/14: Re: Spartan 3 configuration download error
129128: 08/02/15: Re: Spartan 3 configuration download error
129857: 08/03/07: Fixing design, leaving BRAMS variable
129908: 08/03/09: Re: Fixing design, leaving BRAMS variable
132324: 08/05/21: Re: RS232 Interface
=?iso-8859-1?q?Jaime_Andr=E9s_Aranguren_Cardona?=:
81515: 05/03/25: Re: Xilinx ISE 7.1 - Can this get any worse?
94118: 06/01/05: Re: What kind of cpu is suit for me?
95127: 06/01/20: Modelsim problem
95369: 06/01/22: Re: Modelsim problem
104323: 06/06/23: Spartan3 or 3E pins to GND
110696: 06/10/19: EDK - XPS 8.1i segmentation
111526: 06/11/04: Re: EDK - XPS 8.1i segmentation
=?ISO-8859-1?Q?Jaime_Andr=E9s_Aranguren_Cardona?=:
127419: 07/12/21: Re: PowerPC & Spartan-3E Embedded Processing Development Kit -
135204: 08/09/19: Virtex-II Pro to Stratix GX
135229: 08/09/22: Re: Virtex-II Pro to Stratix GX
135237: 08/09/22: Re: Virtex-II Pro to Stratix GX
138434: 09/02/23: MIG 2.0 for DDR - Spartan3E
138437: 09/02/23: Re: MIG 2.0 for DDR - Spartan3E
138439: 09/02/23: Re: MIG 2.0 for DDR - Spartan3E
138535: 09/02/26: Re: MIG 2.0 for DDR - Spartan3E
138949: 09/03/16: Re: MIG 2.0 for DDR - Spartan3E
138959: 09/03/17: Re: MIG 2.0 for DDR - Spartan3E
138961: 09/03/17: Re: libxdh_PartAnno.dll
139484: 09/03/31: Re: MIG 2.0 for DDR - Spartan3E
148572: 10/08/03: Accelogic is looking for a Senior FPGA Engineer
148577: 10/08/03: Re: Xilinx EasyPath Pricing
149271: 10/10/13: Re: Asynchronous Control Signals Synchronization Issues
149603: 10/11/10: XST - configuration - VHDL
149606: 10/11/10: Re: XST - configuration - VHDL
149607: 10/11/10: Re: XST - configuration - VHDL
149660: 10/11/15: Re: XST - configuration - VHDL
=?ISO-8859-1?Q?Jan_Vorbr=FCggen?=:
75622: 04/11/11: Re: Research Project Re: Graphics Processor
=?ISO-8859-1?Q?Jo=E3o_Ferreira?=:
37284: 01/12/06: Call for papers on CCMs for high-performance computing
=?ISO-8859-1?Q?Johan_Bernsp=E5ng?=:
70392: 04/06/15: pulse generation using SRL16E on a Virtex-II
71109: 04/07/08: extending a signal pulse
71317: 04/07/14: Re: extending a signal pulse
72576: 04/08/25: 6.1 vs. 6.2
72593: 04/08/26: Re: 6.1 vs. 6.2
72633: 04/08/27: Re: 6.1 vs. 6.2 - one more question
72714: 04/08/30: Re: 6.1 vs. 6.2 - one more question
75084: 04/10/26: Re: Bus interfaces & FSMs
74737: 04/10/18: Re: Metastability pipeline causes bad juju
74786: 04/10/19: Re: Metastability pipeline causes bad juju
74827: 04/10/20: Re: Metastability pipeline causes bad juju
74896: 04/10/21: Re: Metastability pipeline causes bad juju
75681: 04/11/12: Re: Xilinx Tshirts in football package.....
79306: 05/02/17: Re: FPGA programming newbie
79385: 05/02/18: Re: Printing in ChipScope
81694: 05/03/30: Re: Dividing a 24 bit std_logic_vector by a decimal number
86576: 05/06/30: Re: PROM Generation question
86625: 05/07/01: Re: PROM Generation question
86812: 05/07/07: Re: PC104 (ISA) bus in FPGA (Spatan 2E)
86824: 05/07/07: Re: EDK 6.3, Xilinx ML40x ML402, XBD files
88567: 05/08/23: Re: chipscope pro 6.3i clocking issue
88623: 05/08/24: Re: chipscope problems
89071: 05/09/05: Re: coe file of Xilinx MAC FIR core??
90746: 05/10/20: Re: to write the driver for my own ip core
91241: 05/11/02: differential clock in EDK
91248: 05/11/02: Re: differential clock in EDK
91252: 05/11/02: Re: differential clock in EDK
92157: 05/11/23: Re: Stupid reset question
94818: 06/01/18: Re: [RANT] Webpack 8.1 editor totally messed up ?
94828: 06/01/18: Re: [RANT] Webpack 8.1 editor totally messed up ?
94832: 06/01/18: Re: [RANT] Webpack 8.1 editor totally messed up ?
95649: 06/01/25: Re: undefined reference to `xilkernel_main'
95966: 06/01/27: XilNet server data streaming problem from PPC
97257: 06/02/20: Re: Addressing BRAM in a V2 pro
97606: 06/02/24: [EDK] XilNet throughput
97683: 06/02/26: Re: [EDK] XilNet throughput
101635: 06/05/04: Re: Unreactive Output Pins on Xilinx Virtex-II
101995: 06/05/09: Re: Can an FPGA be operated reliably in a car wheel?
102060: 06/05/10: Re: Can an FPGA be operated reliably in a car wheel?
103142: 06/05/26: Re: fpga debug
103144: 06/05/26: Re: ISE sends sensitive information to Xilinx site!
103229: 06/05/29: ngdbuild:604 - storing netlists in other directories than the project
103232: 06/05/29: Re: ngdbuild:604 - storing netlists in other directories than the
103239: 06/05/29: Re: ngdbuild:604 - storing netlists in other directories than the
104782: 06/07/06: Re: Incorporating CoreGen files in EDK 8.1 peripheral
105225: 06/07/18: Partial shift register extraction in ISE
105264: 06/07/19: Re: Partial shift register extraction in ISE
105315: 06/07/20: Re: Partial shift register extraction in ISE
106276: 06/08/10: Re: EDK peripherals and CoreGen netlists
106884: 06/08/22: ISE 8.1: Process "Map" failed
106896: 06/08/22: Re: ISE 8.1: Process "Map" failed
106899: 06/08/22: Re: ISE 8.1: Process "Map" failed
106965: 06/08/23: Re: ISE 8.1: Process "Map" failed
109691: 06/10/03: logarithm look-up table
113893: 06/12/28: ChipScope - impact on design or not?
113923: 06/12/29: Re: ChipScope - impact on design or not?
113927: 06/12/29: Re: ChipScope - impact on design or not?
113989: 07/01/02: Re: ChipScope - impact on design or not?
=?iso-8859-1?Q?Jos=E9?= Antonio Moreno Zamora:
11797: 98/09/10: Need Permutation generator
16607: 99/05/30: Re: Reconfiguarble chips.
16837: 99/06/12: Digital filters in VHDL
=?ISO-8859-1?Q?L=E4hteenm=E4ki?= Jussi:
30595: 01/04/18: ALTERA Nios software examples?
35589: 01/10/11: Re: High level synthesis will never work well :)
41050: 02/03/20: MAX7000 bypass capasitances
43415: 02/05/21: Re: Synchronous Single Clock Designs
43479: 02/05/22: Re: Synchronous Single Clock Designs
46011: 02/08/14: Altera APEX clock problem
=?ISO-8859-1?Q?Lu=EDs_Rossi?=:
149163: 10/10/05: Re: Starting a career with FPGAs
=?ISO-8859-1?Q?Markus_Knau=DF?=:
52425: 03/02/09: JTAG Download Problems iMPACT and Insight parallel cable
52429: 03/02/09: Re: JTAG Download Problems iMPACT and Insight parallel cable
52460: 03/02/10: Re: JTAG Download Problems iMPACT and Insight parallel cable
99456: 06/03/24: Re: Digital filter design software?
=?ISO-8859-1?Q?Matthias_M=FCller?=:
78618: 05/02/04: Xilinx Virtex4 / Spartan3 High Speed Designs
=?ISO-8859-1?Q?Michael_Kr=E4mer?=:
37406: 01/12/10: MaxplusII 9.6 under Win2k, any known problems?
=?iso-8859-1?Q?Michael_Sch=F6berl?=:
66525: 04/02/21: Re: Serial ATA with Xilinx RocketIO (Virtex 2 Pro)??
66527: 04/02/21: Re: GZIP algorithm in FPGA
66653: 04/02/24: Re: SRAM bidirectional bus
66705: 04/02/25: Re: SRAM bidirectional bus
66777: 04/02/26: Re: VHDL FSM Problem
67456: 04/03/12: Re: Virtex 2 P -> PPC write to block RAM
68883: 04/04/21: Re: calculate the number of logic gate in FPGA
69232: 04/05/01: Re: No net attached
69445: 04/05/11: Re: VHDL Beginner: Reset a counter (instead of "000000000....000000") - better way ?
69538: 04/05/13: Re: synthesising VHDL for Xilinx FPGAs using ISE 6.1i
70265: 04/06/11: Re: Avoid action on very short peak on input signal (Xilinx Spartan 2)
71477: 04/07/20: Re: IDE or ATA controler on a Fpga
77603: 05/01/12: Re: Synchronous Interface to XScale CPU
=?ISO-8859-1?Q?Michael_Sch=F6berl?=:
93716: 05/12/29: Re: real-time compression algorithms on fpga
96168: 06/01/31: Re: ATA controller in fpga
96170: 06/01/31: Re: Is there someone have the ata controller?
96338: 06/02/02: Re: high input to CPLD
96530: 06/02/06: Re: ATA controller in fpga
96532: 06/02/06: Re: ATA controller in fpga
96590: 06/02/07: Re: ATA controller in fpga
96648: 06/02/08: Re: why does speed grade effect VHDL program??
97344: 06/02/21: Re: Inactive signals are active!!! - Chipscope Pro 7.1i - SP4
97481: 06/02/23: Re: query!! need help!!
98135: 06/03/06: Re: The IDE interface
98281: 06/03/08: Re: speed control ac motor in FPGA
98311: 06/03/08: Re: The IDE interface
98574: 06/03/13: Re: fpga to 5v ttl logic
99263: 06/03/22: Re: Virtex-4 RocketIO and G.709 OTU-2
99685: 06/03/28: Re: C-based FPGA programming/mixed languages
99774: 06/03/29: Re: C-based FPGA programming/mixed languages
101191: 06/04/27: Re: the problem when I design the udma33 interface
102066: 06/05/10: Re: Xilinx 3s8000?
102067: 06/05/10: Re: Xilinx ISE 8.1 Makefile
102312: 06/05/15: Re: altera cyclone memory example
102546: 06/05/17: Re: getting good deals on small qty?
102547: 06/05/17: Re: IEEE-1394 (aka FireWire) Core
103282: 06/05/30: Re: hard disk drivers problem
105026: 06/07/12: Re: how to implement multi-port memory
105215: 06/07/18: Re: Opencore ddr_controller
109224: 06/09/22: Re: Fast Platform for ISE?
110148: 06/10/11: Re: ISE/EDK computer selection
110289: 06/10/13: Re: rocketIO in custom mode
110542: 06/10/17: Re: Virtex-5 LXT launched today !
110828: 06/10/24: Re: PowerPC somehow unstable at 300 MHz
110829: 06/10/24: Re: PowerPC somehow unstable at 300 MHz
110833: 06/10/24: Re: PowerPC somehow unstable at 300 MHz
111217: 06/10/31: Re: PowerPC somehow unstable at 300 MHz
116952: 07/03/21: Re: Xilinx ISE support for dual/quad core CPUs?
=?ISO-8859-1?Q?Mois=E9s?=:
56964: 03/06/19: Partial Reconfiguration
=?ISO-8859-1?Q?Narc=EDs_Nadal?=:
45885: 02/08/09: Re: Question: Xilinx schematic entry, constants, bit swapping
46311: 02/08/25: Any FSM optimizer?
46375: 02/08/27: Re: Any FSM optimizer?
46409: 02/08/28: Re: Any FSM optimizer?
46763: 02/09/07: Re: Neural hardware containing many neurons but very simple computation
47854: 02/10/05: Re: Goertzel algorithm tone detector
48143: 02/10/11: SBFT Single Bit Fourier Transform
=?ISO-8859-1?Q?Nicolas_Herv=E9?=:
54283: 03/04/07: price of fpga chips
60999: 03/09/26: Xpower report
131902: 08/05/06: Re: Xilinx ISE 10 in CentOS not showing in application menu list
139828: 09/04/15: installation of ISE & EDK 10.1.03 on OpenSuse 10.3
139851: 09/04/16: Re: installation of ISE & EDK 10.1.03 on OpenSuse 10.3
140225: 09/05/04: ML402 kernel config : option missing "CFI Flash device PetaLinux
=?iso-8859-1?Q?Pawe=B3?= J. Rajda:
20215: 00/02/01: Count 1's algorithm...
29712: 01/03/06: Virtex partial reconfig...
29769: 01/03/08: Foundation RLOC - help!
29785: 01/03/09: Re: Foundation RLOC - help!
29942: 01/03/19: Virtex gate count...?
34246: 01/08/17: Re: WinMe installation
42445: 02/04/24: SpartanII design considerations...
42948: 02/05/08: JTAG 5V tollerance...?
43004: 02/05/09: Re: JTAG 5V tollerance...?
44891: 02/07/04: Spartan II configuration ...
52938: 03/02/26: Spartan2 configuration pins 5V tolerance...?
=?iso-8859-1?q?peter=20ritchie?=:
29772: 01/03/08: Fanout
=?ISO-8859-1?Q?R=E9my?=:
129704: 08/03/03: Re: Xilinx's microblaze hangs when a timer interrupt occurs after a
=?ISO-8859-1?Q?Ralf_Oberl=E4nder?=:
53590: 03/03/17: new XC95xx global clock
=?iso-8859-1?q?Robert_Llu=EDs?=:
109761: 06/10/05: How to accelerate bitstream file generation?
=?ISO-8859-1?Q?Rodolfo_Galv=E3o?=:
135134: 08/09/17: Re: icap Xwicap_DeviceRead problems
=?ISO-8859-1?Q?Ronan_Paix=E3o?=:
139506: 09/04/01: Re: Programming Digilent Nexys 2 from Linux
=?ISO-8859-1?Q?S=F8ren_A.M=F8ller?=:
42263: 02/04/19: Re: Understanding clock routing (or not)
=?iso-8859-1?Q?St=E9phane?= Guyetant:
39762: 02/02/19: Re: "DONT TOUCH" with Xilinx XST?
40105: 02/02/27: SDRAM+FPGA
41052: 02/03/20: Re: Unused I/Os + External Clock on Virtex II
41196: 02/03/22: JTAG under Linux
42465: 02/04/24: virtex package
42615: 02/04/29: easy upgrade?
44342: 02/06/18: 5V tolerance
44361: 02/06/18: Re: 5V tolerance
44991: 02/07/09: how to keep info. in RAM during reconfiguration?
=?iso-8859-1?q?St=E9phane_Acounis?=:
67677: 04/03/17: Re: Speed of Linux vs Solaris
67679: 04/03/17: Re: Speed of Linux vs Solaris
68527: 04/04/07: Problems with Quartus 2 v4 under Linux
68566: 04/04/08: Re: Problems with Quartus 2 v4 under Linux
74344: 04/10/08: Re: Synplify on Fedora C2
=?ISO-8859-1?Q?St=E9phane_Goujet?=:
102557: 06/05/17: Re: IEEE-1394 (aka FireWire) Core
137179: 08/12/30: Digilent
137183: 08/12/30: Re: Digilent
140025: 09/04/24: Re: FPGA board with ARM9
140041: 09/04/25: Re: FPGA board with ARM9
140081: 09/04/27: Re: FPGA board with ARM9
=?iso-8859-1?q?St=E9phane_Mancini?=:
45191: 02/07/15: SOPC builder
45298: 02/07/18: NIOS programming related to ISR
=?ISO-8859-1?Q?Stefan_Brr=F6ring?=:
147216: 10/04/19: Re: Need to run old 8051 firmware
=?ISO-8859-1?Q?Stein_Kj=F8lstad?=:
45685: 02/08/01: ICAP component in Virtex-II
46361: 02/08/26: Xilinx Virtex-II : ICAP?
54923: 03/04/22: Initial values for internal RAM
55132: 03/04/28: Driving GPIO and FAST pins directly from dedicated clock input (CLKx)
=?ISO-8859-1?Q?Te=F3filo_Monteiro?=:
146397: 10/03/15: FPGA Board and a adc working between 20MHz and 100MHz
=?ISO-8859-1?Q?Tobias_M=FCller?=:
70704: 04/06/24: booting fpga and xscale
=?iso-8859-1?q?Torben_=C6gidius_Mogensen?=:
82188: 05/04/08: Re: ISA vs. patent/trademark
110194: 06/10/12: Re: Functional Languages in Hardware
=?iso-8859-1?Q?Torbj=F6rn?= Stabo:
24342: 00/08/04: Re: Verilog multiplier in Xilinx...
32729: 01/07/06: Re: Tcl/Tk VHDL Automatic Testbench Generator - tb_gen.tcl (0/1)
34676: 01/09/03: Re: Prom : Question on Configuration
=?ISO-8859-1?Q?Trygve_Laugst=F8l?=:
150486: 11/01/24: statement is not synthesizable since it does not hold its value under
150488: 11/01/24: Re: statement is not synthesizable since it does not hold its value
=?ISO-8859-1?Q?Uwe_Klo=DF?=:
146159: 10/03/07: Re: using an FPGA to emulate a vintage computer
=?ISO-8859-2?Q?Adam_G=F3rski?=:
135711: 08/10/13: Re: Lattice vs Altera (Mico32 / NIOS)....or?
135715: 08/10/13: Re: Lattice vs Altera (Mico32 / NIOS)....or?
144195: 09/11/19: Re: NIOS and ftoa()
144212: 09/11/20: Re: NIOS and ftoa()
144907: 10/01/14: Re: Virtex-5 with DDR3 running @ 50Mhz
144920: 10/01/15: Re: Virtex-5 with DDR3 running @ 50Mhz
146025: 10/03/04: Re: Laptop for FPGA design?
=?ISO-8859-2?Q?G=F3rski_Adam?=:
147340: 10/04/23: Re: confusion with ADC/DAC interface implementation
149075: 10/09/29: Re: question when using asmi_parallel ip core
149090: 10/09/30: Re: question when using asmi_parallel ip core
149205: 10/10/07: Re: question when using asmi_parallel ip core
149481: 10/10/29: Re: encrypted bitstream
151814: 11/05/20: Re: Verify failed between address 0x80000 and 0x8FFFF
151856: 11/05/25: Re: Verify failed between address 0x80000 and 0x8FFFF
<=?ISO-8859-2?Q?G=F3rski_Adam?=>:
123991: 07/09/10: LVDS pin placing on CYCLON II problem
124027: 07/09/11: Re: LVDS pin placing on CYCLON II problem
124028: 07/09/11: Re: LVDS pin placing on CYCLON II problem
=?ISO-8859-2?Q?Pawe=B3?=:
136488: 08/11/18: Quatech SPPXP-100
=?ISO-8859-2?Q?Przemys=B3aw_Elias?=:
150105: 10/12/14: ISIM simulation speed
150106: 10/12/14: Re: ISIM simulation speed
150109: 10/12/14: Re: ISIM simulation speed
ISPD-97 Organization:
4169: 96/09/21: CFP - Int. Symp. on Physical Design, Apr 14-16, CA
iss:
<istjohn@spamcop.net>:
40354: 02/03/05: Re: exceeding 2GB limits in xilinx
40405: 02/03/06: Re: share two months salary with you if you have job information
<istrolowitz@elscintcorp.co.il>:
8858: 98/02/02: Altera 5032 programming problems
Iswada Osumundli:
5533: 97/02/22: Re: Xilinx or Altera?
5534: 97/02/22: Re: Xilinx or Altera?
5535: 97/02/22: Re: Using FPGA for PCI interface
IT:
128518: 08/01/29: Re: Active-HDL 7.3 web-eval and Xilinx 9.2i.04 Smartmodel simulation?
it:
69689: 04/05/18: Micro : Bus
<it.stein@gmail.com>:
116323: 07/03/07: Where do I find CMOS image sensors and lenses?
Italian Cowboy:
16076: 99/04/30: Dynamic Reconfiguration
16324: 99/05/16: Re: High Speed Reconfigurability
16325: 99/05/16: High Speed Reconfigurability, Re:
16386: 99/05/19: R: High Speed Reconfigurability, Re:
16438: 99/05/21: R: High Speed Reconfigurability
<Itandian@gmail.com>:
129694: 08/03/03: Re: Software for FPGA-based PC scope
134162: 08/07/28: Re: Cyclone III passive serial config issue
itay:
157001: 14/08/18: calculations of logic vectors and constant
Iti:
itris:
53131: 03/03/04: xilinx HDL bencher
Itsaso Zuazua:
41743: 02/04/06: A learner of Modelsim
41790: 02/04/08: Modelsim from Altera vs Modelsim from Menthors
41854: 02/04/09: Post-synthesis simulation errors with Modelsim
41929: 02/04/11: A learner of Modelsim
42161: 02/04/17: Problems with Nios 2.0
42163: 02/04/17: Knowing the design from the compilation report
42185: 02/04/18: problems with Nios 2.0
42363: 02/04/21: Post-synthesis simulation
42884: 02/05/06: SOPC solutions applications
47700: 02/10/02: Help for Altera's FPGAs' pinout
48339: 02/10/16: HELP about signal integrity, PLEASE!
48413: 02/10/17: Re: HELP about signal integrity, PLEASE!
51264: 03/01/09: XILINX ISE + ACTIVE-HDL design flow, HELP PLEASE!!!
itsme:
47298: 02/09/23: Xilinx RAM16x1D, Write fails in functional Simulation
47895: 02/10/07: Xilinx ISE does not use Resgisters in IOB
47897: 02/10/07: Re: Xilinx ISE does not use Resgisters in IOB
47899: 02/10/07: Xilinx XST VHDL Compiler does not pack Registers in IOB
51950: 03/01/27: Xilinx ISE 5.1 SP3: XST BUG!!!
57540: 03/07/02: Why not DDR in FPGAs?
62407: 03/10/29: Xilinx Spartan3: Price
65211: 04/01/22: Xilinx Spartan3 Timing Problems - Whats about the chips
ITU Technologies:
6520: 97/05/30: Re: Need Address/Phone/Fax List of Semiconductor Companies
11564: 98/08/24: Technical Bookstore Update
ituspam@yahoo.com:
87382: 05/07/22: What a nice day for XLNX
ivan:
78454: 05/02/01: 100Mbps ethernet core
80352: 05/03/04: Re: 100Mbps ethernet core
84539: 05/05/20: How to download uClinux on Virtex4 Board.
84588: 05/05/22: Re: How to download uClinux on Virtex4 Board.
85873: 05/06/17: Error :device requires cache coherent memory for BD's
89901: 05/09/29: There is a way to instantiate 'N' VHDL components using a repetitive strutucture ?
139774: 09/04/13: Xilinx ISE bug, or?
139780: 09/04/13: Re: Xilinx ISE bug, or?
Ivan:
8518: 98/01/03: Interfacing 3.3V FPGA with ISA bus
8593: 98/01/12: Re: serial conf. PROMS
9391: 98/03/09: Problems with Atmel IDS 5.0 installation
10258: 98/05/08: Altera relative placement
16441: 99/05/22: Xilinx device readback through parallel port
58400: 03/07/22: Clock rate increase for FEC aplications
58427: 03/07/23: Re: Clock rate increase for FEC aplications
60156: 03/09/05: Re: Include design file using QuartusII
61828: 03/10/13: ByteBlasterII
69939: 04/05/25: AWGN
75098: 04/10/26: JTAG Configuration
75149: 04/10/27: JTAG Configuration
75156: 04/10/27: Re: JTAG Configuration
94691: 06/01/16: Re: How to drive 4 output ports with one combinational signal
94940: 06/01/19: Re: ISE8.1 on Linux, first impressions
97453: 06/02/22: Re: How to make Customized IP which connected with Microblaze through
97454: 06/02/22: Re: PowerPC based SoC design, getting it working from first attempt
97485: 06/02/23: Re: How to make Customized IP which connected with Microblaze through
97486: 06/02/23: Re: PowerPC based SoC design, getting it working from first attempt
97540: 06/02/23: Re: How to make Customized IP which connected with Microblaze through
97758: 06/02/27: Re: A dev board supporting partial/dynamic reconf.
97848: 06/02/28: Re: PPC Linux SoC on Virtex4 in 4 hours !?
97874: 06/03/01: Re: PPC Linux SoC on Virtex4 in 4 hours !?
97880: 06/03/01: Re: PPC Linux SoC on Virtex4 in 4 hours !?
97967: 06/03/02: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
97971: 06/03/02: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
98026: 06/03/03: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
98034: 06/03/03: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
98036: 06/03/03: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
98129: 06/03/06: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
98131: 06/03/06: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
98405: 06/03/09: Re: slice macro replace the bus macro in the virtex-4 how to do that?????
98573: 06/03/13: Re: LEON processor core
98683: 06/03/14: Re: slice macro replace the bus macro in the virtex-4 how to do that?????
99181: 06/03/21: Re: slice macro replace the bus macro in the virtex-4 how to do that?????
99265: 06/03/22: Re: slice macro replace the bus macro in the virtex-4 how to do that?????
Ivan Baggett:
16053: 99/04/30: Re: IRQ Controller
Ivan GARCIA ALFONSO:
30755: 01/04/27: XILINX ngd2vhdl tool
Ivan Godard:
156072: 13/11/22: Re: Mill: FPGA version?
156090: 13/11/22: Re: Mill: FPGA version?
156107: 13/11/23: Re: Mill: FPGA version?
156138: 13/12/08: Re: Implementing multiple interrupts
Ivan Hamer:
6597: 97/06/04: PCI how to
Ivan Jeukens:
1390: 95/06/13: Low cost FPGA system
Ivan Lee:
2109: 95/10/16: VHDL Model for XC4000 RAM Model
Ivan Leung:
26854: 00/11/01: JBits
Ivan Rossi:
6293: 97/05/09: suggestion about a pcmcia in a fpga
Ivan Tolkachev:
154494: 12/11/18: A total beginner, wondering about determining hardware specs. requirements
Ivan Vernot:
32733: 01/07/07: WTB:50 Mhz 24 CHANNEL LOGIC ANALYZER only $199
32984: 01/07/14: Re: WTB:50 Mhz 24 CHANNEL LOGIC ANALYZER only $199
Ivan Wagner:
93927: 06/01/03: Re: Coding style
ivan@gmail.com:
110798: 06/10/23: Camera link specification
110824: 06/10/24: Re: Camera link specification
Ivana Raffe:
35434: 01/10/04: input signal frequency
ivar:
30691: 01/04/23: Re: CarryLogic
30747: 01/04/26: Re: Bidirection port simulation
36082: 01/10/28: Re: 8051 timing diagrams
Ivar:
21132: 00/03/07: Re: Microprocessor architecture (6800, 4004? PA-RISC, PPC, MIPS, x86, ...?)
29782: 01/03/09: Re: Foundation RLOC - help!
30256: 01/03/29: 8279 keyboard controller in Verilog or VHDL ?
30721: 01/04/25: Re: What is wrong with Xilinx Foundation Simulator?
34388: 01/08/22: Re: Virtex-II place and route : Design doesn't route
34501: 01/08/27: Re: Defending Austin Franklin
34554: 01/08/29: Re: Defending Austin Franklin
35813: 01/10/18: Re: 8051 timing diagrams
Ivica Baran:
Ivica Hedes:
6426: 97/05/23: PLEASE, READ THIS !
ivo:
102914: 06/05/23: someone used FIFO along with the OPB-bus in FPGA ?
107682: 06/08/31: MPMC2 : npi issues
108837: 06/09/18: MPMC2 : npi issues #2
Ivor:
35171: 01/09/24: How to fix the hold time violation (clock skew>data skew) in QuartusII
Iwan Pekertia:
2782: 96/02/07: Postgraduate Research Opportunity
Iwan Santoso Oei:
16085: 99/04/30: Help me: What is FPGA?
Iwo Mergler:
26146: 00/10/05: Re: pci host
31242: 01/05/16: Re: PCI The Real Hardware
31292: 01/05/17: Re: PCI The Real Hardware
33753: 01/08/03: Re: RAM - VHDL - Altera,...
33976: 01/08/09: Re: RAM - VHDL - Altera,...
37199: 01/12/03: Re: PCI card - 2 layers versus four layers
38554: 02/01/17: Re: PCI Solution: LogiCore?
38913: 02/01/28: Re: Problem with Altera programmer
39032: 02/01/30: Re: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?)
43081: 02/05/13: Re: PCI bus software for Xilinx PCI core
43131: 02/05/14: Re: Neverending ISA bus interface drama, Spartan-II
44061: 02/06/11: Busses & permutations
44186: 02/06/13: Re: Busses & permutations
44187: 02/06/13: Re: Busses & permutations
46233: 02/08/22: Re: I2C License
46263: 02/08/23: Re: I2C License
49798: 02/11/21: Re: Programming Altera Flex10k under Linux
50190: 02/12/04: Re: ISA bus VGA
51416: 03/01/13: Re: Interfacing to a PC using EPP parallel port
52627: 03/02/17: PCMCIA + FPGA/CPLD
52656: 03/02/18: Re: PCMCIA + FPGA/CPLD
52686: 03/02/19: Re: PCMCIA + FPGA/CPLD
63154: 03/11/17: Re: Color STN LCD controller
63647: 03/11/27: Re: XC9500 design does not fit into Coolrunner
69491: 04/05/12: Compact Flash FPGA card
69535: 04/05/13: Re: Compact Flash FPGA card
69536: 04/05/13: Re: Compact Flash FPGA card
84255: 05/05/16: Re: SPI interface cpol & cpha
123862: 07/09/06: Re: ?Nios II?How Can I Find Out These Functions ?
<Iwo.mergler@soton.sc.philips.com>:
36091: 01/10/29: Re: P5Z22V10 - any left anywhere?
36217: 01/11/02: Re: High level synthesis will never work well :)
Iyad Obeid:
58990: 03/08/05: Re: model sim block ram sim
IZ5FCY Roberto:
108325: 06/09/08: NCO & DownConverter routines
109521: 06/09/27: QED files
izaak:
147965: 10/06/07: Burn to an internal prom Spartan-3an
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