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On May 3, 2:37=A0am, allen <ayho...@gmail.com> wrote: > Hey guys! > > Terasic Technologies is holding a contest to WIN the newly released > Altera DE0-Nano! Head over tohttp://www.terasic.com.tw/events/DE0_Nano_Co= ntest/ > to leave a comment and win one today!!! > > Thanks, > Allen Houng > Terasic Technologieswww.terasic.com Mr. Allen Houng, FaceBook? Really? If you were interested in the hobby market, FaceBook might be the right place. Sadly, my vision of combined FaceBook and FPGAs looks a lot like someone living in his mother's basement building geeky toys. I like to be professional with my FPGA work. RK.Article: 151676
Symon <symon_brewer@hotmail.com> wrote: >On 5/2/2011 1:42 PM, John Adair wrote: >> If you didn't see it already in our our newsletter we have a new PCIe >> devopment board based on an Altera Cyclone-IV GX. The new board keeps >> most of the mechanicals and features of our Raggedstone product range >> but extends the bandwidth capability of the product range. The >> Raggedstone3 is capabile of bandwidths exceeding 800 MBytes/s over >> it's X4 PCIe interface. >> >> Initial details of this product http://www.enterpoint.co.uk/raggedstone/raggedstone3.html. >> Anyone at ESC this week can see the board there on our stand. >> >> I am expecting this board to ship to customers in low numbers in June >> or July with a significant ramp in shipping numbers after that. >> >> John Adair >> Enterpoint Ltd. > >Hi John, > >I have a question for you (and the group) about PCIe. Let's say I build >a PCIe target in my Altera device, and let's say for the sake of >argument that it's a Ethernet MAC. My Linux single board computer (SBC) >has a software driver for this Ethernet device. As the Linux boots, it >sees the PCIe device and loads the driver. > >What happens if, without rebooting the SBC, I reconfigure the Altera >part? How does the OS react to the PCIe device vanishing from the bus >and then subsequently reappearing? With the plain old PCI the PCI core needs to be configured first (memory addresses etc). It has been too long since I worked with PCI and FPGAs but IIRC the OS should probe the card before it can be used. The proper sequence is to stop the driver, reconfigure the FPGA, force probing for hardware changes and then reload the driver. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 151677
On 5/5/2011 12:30 AM, Nico Coesel wrote: > Symon<symon_brewer@hotmail.com> wrote: > >> On 5/2/2011 1:42 PM, John Adair wrote: >>> If you didn't see it already in our our newsletter we have a new PCIe >>> devopment board based on an Altera Cyclone-IV GX. The new board keeps >>> most of the mechanicals and features of our Raggedstone product range >>> but extends the bandwidth capability of the product range. The >>> Raggedstone3 is capabile of bandwidths exceeding 800 MBytes/s over >>> it's X4 PCIe interface. >>> >>> Initial details of this product http://www.enterpoint.co.uk/raggedstone/raggedstone3.html. >>> Anyone at ESC this week can see the board there on our stand. >>> >>> I am expecting this board to ship to customers in low numbers in June >>> or July with a significant ramp in shipping numbers after that. >>> >>> John Adair >>> Enterpoint Ltd. >> >> Hi John, >> >> I have a question for you (and the group) about PCIe. Let's say I build >> a PCIe target in my Altera device, and let's say for the sake of >> argument that it's a Ethernet MAC. My Linux single board computer (SBC) >> has a software driver for this Ethernet device. As the Linux boots, it >> sees the PCIe device and loads the driver. >> >> What happens if, without rebooting the SBC, I reconfigure the Altera >> part? How does the OS react to the PCIe device vanishing from the bus >> and then subsequently reappearing? > > With the plain old PCI the PCI core needs to be configured first > (memory addresses etc). It has been too long since I worked with PCI > and FPGAs but IIRC the OS should probe the card before it can be used. > The proper sequence is to stop the driver, reconfigure the FPGA, force > probing for hardware changes and then reload the driver. > Hi Nico, So, if the OS initiates the FPGA reconfiguration, it can also reboot the driver? Thanks, SymonArticle: 151678
Symon This isn't a simple area and one of the places that the PCIe spec usually falls down. Usually if you reconfigure the device sitting the PCIe bus this is a problem because the bios and the OS don't that you are doing this. Consequently if an access is attempted during the configuration many motherboards will freeze because an answer doesn't come back. The second problem is that the enumeration and setting of the card parameters is lost. Sometimes there are work arounds to this later problem the best of which is an OS that be forced to re- enumerate the target. One way to get round the problem is to use hot plug signalling but that does depend on the motherboard and OS if that is supported. Using a partially configuration technique can sometimes work as well but again it is not a simple path. John Adair Enterpoint Ltd. On May 4, 4:43=A0pm, Symon <symon_bre...@hotmail.com> wrote: > On 5/2/2011 1:42 PM, John Adair wrote: > > > If you didn't see it already in our our newsletter we have a new PCIe > > devopment board based on an Altera Cyclone-IV GX. The new board keeps > > most of the mechanicals and features of our Raggedstone product range > > but extends the bandwidth capability of the product range. The > > Raggedstone3 is capabile of bandwidths exceeding 800 MBytes/s over > > it's X4 PCIe interface. > > > Initial details of this producthttp://www.enterpoint.co.uk/raggedstone/= raggedstone3.html. > > Anyone at ESC this week can see the board there on our stand. > > > I am expecting this board to ship to customers in low numbers in June > > or July with a significant ramp in shipping numbers after that. > > > John Adair > > Enterpoint Ltd. > > Hi John, > > I have =A0a question for you (and the group) about PCIe. Let's say I buil= d > a PCIe target in my Altera device, and let's say for the sake =A0of > argument that it's a Ethernet MAC. My Linux single board computer (SBC) > has a software driver for this Ethernet device. As the Linux boots, it > sees the PCIe device and loads the driver. > > What happens if, without rebooting the SBC, I reconfigure the Altera > part? How does the OS react to the PCIe device vanishing from the bus > and then subsequently reappearing? > > Thanks, Symon.Article: 151679
Hello, all, I'm using Xilinx Ise 10.1 on a Linux system, and ran into a crazy problem. I took a previous design and stripped out a bunch of stuff to make a skeleton of that project to test something, leaving over a bunch of pins that became unused. I then removed the unused pins from the top-level VHDL file's port list, and removed those LOC definitions from my .ucf file. Now, when I try to implement that, I get a bunch of messages that there were constraints that didn't match a signal name. I edited the .ucf file again, deleted it from the project and re-added it, but it still finds these constraints. If I open the .ucf in the text editor, they are not there, but if I open constraints in the constraint editor - port page, they do show up. Anybody know where these are coming from, or what I can do to refresh ise to get rid of this stale data? (There used to be a button to "remove implementation data" that would clear out this sort of thing, but I can't find it in 10.1.) Thanks, JonArticle: 151680
Hello all, I am a fresher in this industry..... I am working on systemverilog... I have created a model for analog to digital conversion,I have to make use of an already created model I have made the objects but while creating them (i.e initialising them) through the new operator I am getting an error as NULL POINTER DEREFERENCE....if any one can suggest something.. This error comes insidel the run task of the already created class where the interface of that model is used --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151681
Hi, How do I remove webtalk in Xilinx 13.1, I do run all the tools from a script not from GUI? I did run a trail license at first but now I have a proper flexlm license! /michaelArticle: 151682
>Hello, all, > >I'm using Xilinx Ise 10.1 on a Linux system, and ran into a crazy problem. >I took a previous design and stripped out a bunch of stuff to make a >skeleton of that project to test something, leaving over a bunch of pins >that became unused. I then removed the unused pins from the top-level VHDL >file's port list, and removed those LOC definitions from my .ucf file. > >Now, when I try to implement that, I get a bunch of messages that there were >constraints that didn't match a signal name. I edited the .ucf file again, >deleted it from the project and re-added it, but it still finds these >constraints. If I open the .ucf in the text editor, they are not there, >but if I open constraints in the constraint editor - port page, they do >show up. > >Anybody know where these are coming from, or what I can do to refresh ise to >get rid of this stale data? > >(There used to be a button to "remove implementation data" that would clear >out this sort of thing, but I can't find it in 10.1.) > >Thanks, > >Jon > Under Project menu, "Cleanup Project Files" might be what you are after. Ensure that the [name].restore file is deleted, too. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151683
Hi, On 05/05/11 07:21 AM, Jon Elson wrote: > Hello, all, > > I'm using Xilinx Ise 10.1 on a Linux system, and ran into a crazy problem. > I took a previous design and stripped out a bunch of stuff to make a > skeleton of that project to test something, leaving over a bunch of pins > that became unused. I then removed the unused pins from the top-level VHDL > file's port list, and removed those LOC definitions from my .ucf file. > > Now, when I try to implement that, I get a bunch of messages that there were > constraints that didn't match a signal name. I edited the .ucf file again, > deleted it from the project and re-added it, but it still finds these > constraints. If I open the .ucf in the text editor, they are not there, > but if I open constraints in the constraint editor - port page, they do > show up. > > Anybody know where these are coming from, or what I can do to refresh ise to > get rid of this stale data? > > (There used to be a button to "remove implementation data" that would clear > out this sort of thing, but I can't find it in 10.1.) > > Thanks, > > Jon leave the GUI and use scripts, it never causes these problems! /michaelArticle: 151684
On 5/5/2011 2:02 AM, Michael wrote: > Hi, > > How do I remove webtalk in Xilinx 13.1, I do run all the tools from a > script not from GUI? > > I did run a trail license at first but now I have a proper flexlm license! > > > /michael BOMK the latest release you cannot remove webtalk. Nothing is ever truly free. To remove webtalk you need to purchase one of the non-free version, example Logic ISE. ChrisArticle: 151685
Hi, On 05/05/11 02:52 PM, Christopher Felton wrote: > On 5/5/2011 2:02 AM, Michael wrote: >> Hi, >> >> How do I remove webtalk in Xilinx 13.1, I do run all the tools from a >> script not from GUI? >> >> I did run a trail license at first but now I have a proper flexlm >> license! >> >> >> /michael > > BOMK the latest release you cannot remove webtalk. Nothing is ever truly > free. I know, I'am also married ;) >To remove webtalk you need to purchase one of the non-free > version, example Logic ISE. > > Chris But I have a purchaed license(embedded edition) now which runs and checksout fine from the flexlm server!! So it must be possible to remove webtalk! /michaelArticle: 151686
On 5/5/2011 8:02 AM, Michael wrote: > Hi, > > On 05/05/11 02:52 PM, Christopher Felton wrote: >> On 5/5/2011 2:02 AM, Michael wrote: >>> Hi, >>> >>> How do I remove webtalk in Xilinx 13.1, I do run all the tools from a >>> script not from GUI? >>> >>> I did run a trail license at first but now I have a proper flexlm >>> license! >>> >>> >>> /michael >> >> BOMK the latest release you cannot remove webtalk. Nothing is ever truly >> free. > I know, I'am also married ;) > >> To remove webtalk you need to purchase one of the non-free >> version, example Logic ISE. >> >> Chris > But I have a purchaed license(embedded edition) now which runs and > checksout fine from the flexlm server!! > > So it must be possible to remove webtalk! Yes, agree it should be removable in that case. I don't know exactly what needs to be done. But I have had issues in the past moving from webpack to licensed or licensed to webpack. I have had to, best I could, try to start from scratch and install ISE on a clean machine. Remove the previous version and reinstall the new. ChrisArticle: 151687
On May 5, 9:11=A0am, Christopher Felton <noem...@now.com> wrote: > On 5/5/2011 8:02 AM, Michael wrote: > > > > > > > > > > > Hi, > > > On 05/05/11 02:52 PM, Christopher Felton wrote: > >> On 5/5/2011 2:02 AM, Michael wrote: > >>> Hi, > > >>> How do I remove webtalk in Xilinx 13.1, I do run all the tools from a > >>> script not from GUI? > > >>> I did run a trail license at first but now I have a proper flexlm > >>> license! > > >>> /michael > > >> BOMK the latest release you cannot remove webtalk. Nothing is ever tru= ly > >> free. > > I know, I'am also married ;) > > >> To remove webtalk you need to purchase one of the non-free > >> version, example Logic ISE. > > >> Chris > > But I have a purchaed license(embedded edition) now which runs and > > checksout fine from the flexlm server!! > > > So it must be possible to remove webtalk! > > Yes, agree it should be removable in that case. > > I don't know exactly what needs to be done. =A0But I have had issues in > the past moving from webpack to licensed or licensed to webpack. =A0I hav= e > had to, best I could, try to start from scratch and install ISE on a > clean machine. =A0Remove the previous version and reinstall the new. > > Chris Look at "Setting WebTalk Preferences" on this page to see if that helps: http://www.xilinx.com/ise/webtalk/ Regards, John McCaskill www.FasterTechnology.comArticle: 151688
Symon <symon_brewer@hotmail.com> wrote: >On 5/5/2011 12:30 AM, Nico Coesel wrote: >> Symon<symon_brewer@hotmail.com> wrote: >> >>> On 5/2/2011 1:42 PM, John Adair wrote: >>>> If you didn't see it already in our our newsletter we have a new PCIe >>>> devopment board based on an Altera Cyclone-IV GX. The new board keeps >>>> most of the mechanicals and features of our Raggedstone product range >>>> but extends the bandwidth capability of the product range. The >>>> Raggedstone3 is capabile of bandwidths exceeding 800 MBytes/s over >>>> it's X4 PCIe interface. >>>> >>>> Initial details of this product http://www.enterpoint.co.uk/raggedstone/raggedstone3.html. >>>> Anyone at ESC this week can see the board there on our stand. >>>> >>>> I am expecting this board to ship to customers in low numbers in June >>>> or July with a significant ramp in shipping numbers after that. >>>> >>>> John Adair >>>> Enterpoint Ltd. >>> >>> Hi John, >>> >>> I have a question for you (and the group) about PCIe. Let's say I build >>> a PCIe target in my Altera device, and let's say for the sake of >>> argument that it's a Ethernet MAC. My Linux single board computer (SBC) >>> has a software driver for this Ethernet device. As the Linux boots, it >>> sees the PCIe device and loads the driver. >>> >>> What happens if, without rebooting the SBC, I reconfigure the Altera >>> part? How does the OS react to the PCIe device vanishing from the bus >>> and then subsequently reappearing? >> >> With the plain old PCI the PCI core needs to be configured first >> (memory addresses etc). It has been too long since I worked with PCI >> and FPGAs but IIRC the OS should probe the card before it can be used. >> The proper sequence is to stop the driver, reconfigure the FPGA, force >> probing for hardware changes and then reload the driver. >> >Hi Nico, >So, if the OS initiates the FPGA reconfiguration, it can also reboot the >driver? Most modern OSses support run-time loading and unloading of device drivers. The only real problem is writing the PCI configuration space. The OS needs to support that but it is very similar to hotplugging which IIRC is supported by PCIe. This e-mail gives some useful pointers: http://www.spinics.net/lists/linux-pci/msg08649.html -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 151689
RCIngham wrote: > > Under Project menu, "Cleanup Project Files" might be what you are after. > Ensure that the [name].restore file is deleted, too. Great, thanks! That option was staring me in the face. All is working now. JonArticle: 151690
Hi, On 05/05/11 04:11 PM, Christopher Felton wrote: > On 5/5/2011 8:02 AM, Michael wrote: >> Hi, >> >> On 05/05/11 02:52 PM, Christopher Felton wrote: >>> On 5/5/2011 2:02 AM, Michael wrote: >>>> Hi, >>>> >>>> How do I remove webtalk in Xilinx 13.1, I do run all the tools from a >>>> script not from GUI? >>>> >>>> I did run a trail license at first but now I have a proper flexlm >>>> license! >>>> >>>> >>>> /michael >>> >>> BOMK the latest release you cannot remove webtalk. Nothing is ever truly >>> free. >> I know, I'am also married ;) >> >>> To remove webtalk you need to purchase one of the non-free >>> version, example Logic ISE. >>> >>> Chris >> But I have a purchaed license(embedded edition) now which runs and >> checksout fine from the flexlm server!! >> >> So it must be possible to remove webtalk! > > Yes, agree it should be removable in that case. > > I don't know exactly what needs to be done. But I have had issues in the > past moving from webpack to licensed or licensed to webpack. I have had > to, best I could, try to start from scratch and install ISE on a clean > machine. Remove the previous version and reinstall the new. > > Chris This is a server based install where we NFS mouting to the clients. /michaelArticle: 151691
Hi,
On 05/05/11 04:19 PM, John McCaskill wrote:
> On May 5, 9:11 am, Christopher Felton<noem...@now.com> wrote:
>> On 5/5/2011 8:02 AM, Michael wrote:
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>> Hi,
>>
>>> On 05/05/11 02:52 PM, Christopher Felton wrote:
>>>> On 5/5/2011 2:02 AM, Michael wrote:
>>>>> Hi,
>>
>>>>> How do I remove webtalk in Xilinx 13.1, I do run all the tools from a
>>>>> script not from GUI?
>>
>>>>> I did run a trail license at first but now I have a proper flexlm
>>>>> license!
>>
>>>>> /michael
>>
>>>> BOMK the latest release you cannot remove webtalk. Nothing is ever truly
>>>> free.
>>> I know, I'am also married ;)
>>
>>>> To remove webtalk you need to purchase one of the non-free
>>>> version, example Logic ISE.
>>
>>>> Chris
>>> But I have a purchaed license(embedded edition) now which runs and
>>> checksout fine from the flexlm server!!
>>
>>> So it must be possible to remove webtalk!
>>
>> Yes, agree it should be removable in that case.
>>
>> I don't know exactly what needs to be done. But I have had issues in
>> the past moving from webpack to licensed or licensed to webpack. I have
>> had to, best I could, try to start from scratch and install ISE on a
>> clean machine. Remove the previous version and reinstall the new.
>>
>> Chris
>
> Look at "Setting WebTalk Preferences" on this page to see if that
> helps: http://www.xilinx.com/ise/webtalk/
>
> Regards,
>
> John McCaskill
> www.FasterTechnology.com
Excellent
edaadm@eda06 $
/opt/eda/xilinx/ise/alliance_13.1/ISE_DS/ISE/bin/lin64/xwebtalk -help
Release 13.1 - WebTalk O.40d (lin64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Usage: xwebtalk [-user on|off] [-install on|off] [-info]
-user value Turns on or off WebTalk per user basis.
Options: "on", "off"
-user on: Turns on WebTalk per user basis.
-user off: Turns off WebTalk per user basis.
-install value Turns on or off WebTalk per install basis.
Options: "on", "off"
-install on: Turns on WebTalk per install basis.
-install off: Turns off WebTalk per install basis.
-info Checks the current status of WebTalk settings.
edaadm@eda06 $
/opt/eda/xilinx/ise/alliance_13.1/ISE_DS/ISE/bin/lin64/xwebtalk -info
Release 13.1 - WebTalk O.40d (lin64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
INFO:WebTalk:6 - WebTalk User setting is ON.
INFO:WebTalk:8 - WebTalk Install setting is ON.
NOTE: WebTalk is always enabled for WebPACK users. WebTalk ignores user and
install preference when a bitstream is generated using the WebPACK
license. If a
design is using a device contained in WebPACK and a WebPACK license is
available, the WebPACK license will always be used. To change this,
please see
Answer Record 34746.
rm ~/.Xilinx/Common/13.1/webtalk
And then xwebtalk -install off
xwebtalk -user off
edaadm@eda06 $
/opt/eda/xilinx/ise/alliance_13.1/ISE_DS/ISE/bin/lin64/xwebtalk -info
Release 13.1 - WebTalk O.40d (lin64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
INFO:WebTalk:7 - WebTalk User setting is OFF.
INFO:WebTalk:8 - WebTalk Install setting is OFF.
NOTE: WebTalk is always enabled for WebPACK users. WebTalk ignores user and
install preference when a bitstream is generated using the WebPACK
license. If a
design is using a device contained in WebPACK and a WebPACK license is
available, the WebPACK license will always be used. To change this,
please see
Answer Record 34746.
edaadm@eda06 $
Much thanks again :)
cheers
michael
Article: 151692Michael wrote: > leave the GUI and use scripts, it never causes these problems! Well, I'll have to learn how to do this. I did use a command line to run promgen, as running it from the GUI crashes. JonArticle: 151693
On May 5, 8:42=A0am, Jon Elson <el...@pico-systems.com> wrote: > Michael wrote: > > leave the GUI and use scripts, it never causes these problems! > > Well, I'll have to learn how to do this. > > I did use a command line to run promgen, as running it from the GUI crash= es. > > Jon Jon, When you read the documentation for using the command line mode, you will find that there are a number of files that are included implicitly if found. Most likely it was one of those files (<projectname>.pcf is the most likely culprit) that was causing your problem. "Real engineers don't use GUIs", RKArticle: 151694
"rittu" <rittu16@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote in news:AZCdndcTv8- 32l_QnZ2dnUVZ_oSdnZ2d@giganews.com: > Hello all, I am a fresher in this industry..... > I am working on systemverilog... > I have created a model for analog to digital conversion,I have to make use > of an already created model I have made the objects but while creating them > (i.e initialising them) through the new operator I am getting an error as > NULL POINTER DEREFERENCE....if any one can suggest something.. > This error comes insidel the run task of the already created class where > the interface of that model is used > > > --------------------------------------- > Posted through http://www.FPGARelated.com > My crystal ball says that the error occurs somewhere between the first line and the last line of your code, or perhaps in a similar location of the already created model's code. :-) I bet that if you post the code, someone can come up with a more accurate answer.Article: 151695
In a bit of a self promotional move, though probably pretty relevant to this group, I'd like to mention http://www.boldport.com which I released on Monday, and https://www.boldport.com/docs/fpgaproj for easing the migration from GUI to command-line use of FPGA tools, and more effective project/build management. The project is at an early stage, and more features will be added with time. Praise, constructive feedback, and well-mannered bashing are welcome, of course... be as honest as this group knows how to be (feel free to email me privately as well). Finally, I'm looking for early adopter projects, and offer my help with the setup. Thanks for your attention, saar.Article: 151696
On May 4, 11:48=A0am, valtih1978 <intel...@yandex.ru> wrote: > The Logic Accessible Clocks are entailed for example in =A0http://www.cis= l.columbia.edu/courses/spring-2004/ee4340/restricted_ha.... > I do not see much explanation of the concept. But, I would expect some wh= en > sys_clk_fb is registered by in-sync clk2. Sinse both clocks switch at the > same time, the setup/hold time, the basics of HW design, are violated for > sure! This was something unique to DDR SDRAM implementation in a now obsolete FPGA family to allow for a local clock in the fabric. Improvements in modern FPGA families make this technique obsolete. In this implementation the clock input does goes to the data input of a register, but the clock of this register is from a DCM 2X output and there is delay differences between the two that allows for this clock to be captured and then used as data with the logic. Ed McGettigan -- Xilinx Inc.Article: 151697
Hi,
On 05/05/11 05:42 PM, Jon Elson wrote:
> Michael wrote:
>
>
>> leave the GUI and use scripts, it never causes these problems!
> Well, I'll have to learn how to do this.
>
> I did use a command line to run promgen, as running it from the GUI crashes.
>
> Jon
To synth define PROJECT or replace with project name
xst -ifn ${PROJECT}.xst -ofn ${PROJECT}.log
You could use xflow to run the flow for P&R
xflow -p partname ${PROJECT}
There are probably even better ways that a are compatible with the GUI
ising tcl I assume but I have not digged in to that, I am to old...or
maybe not ;)
And then bitgen like you have done with promgen
You might need some config for bitgen
/michael
Article: 151698
On 05/06/2011 12:52 AM, Michael wrote:
> Hi,
>
> On 05/05/11 05:42 PM, Jon Elson wrote:
>> Michael wrote:
>>
>>
>>> leave the GUI and use scripts, it never causes these problems!
>> Well, I'll have to learn how to do this.
>>
>> I did use a command line to run promgen, as running it from the GUI
>> crashes.
>>
>> Jon
> To synth define PROJECT or replace with project name
> xst -ifn ${PROJECT}.xst -ofn ${PROJECT}.log
>
> You could use xflow to run the flow for P&R
> xflow -p partname ${PROJECT}
>
> There are probably even better ways that a are compatible with the GUI
> ising tcl I assume but I have not digged in to that, I am to old...or
> maybe not ;)
>
> And then bitgen like you have done with promgen
>
> You might need some config for bitgen
OK, well I can probably dig the syntax out of the log files. I had no
idea it was that simple!
The Windows-fashioned text editor in ise is pretty awful, I usually use
emacs.
I DO like the simulator, though. MUCH easier to hop around in the
hierarchy and bring up signals from various inner components of the
design than Modelsim. And, it automatically saves the signals on the
screen for next time.
The promgen command line I got from a Xilinx article puts out the
reverse bit ordering, so it wouldn't load. I'll have to figure out what
option sets it for the other ordering. But, after I did the cleanup,
the prom file formatter works from the gui. I need to find out what I'm
doing wrong that fouls up the management of vhdl files.
I put the files into a directory and edited them for the first cut there
before setting up an ide project and adding the files to the project.
This left several versions of files with the same name in the various
levels of the directory, and I think that is what started this mess.
I think working both outside ide and inside it is most of the cause of
the problem.
Jon
Article: 151699There have been an article in Xcell journal on how to use Xilinx tools in command-line mode, if anybody is interested: http://outputlogic.com/xcell_using_xilinx_tools/74_xperts_04.pdf Thanks, Evgeni
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