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Just a bit about the project I'm working on: Have an FPGA gathering and manipulating data, and we need a processor to run the show and to send the data over a network. At the moment we are planning on using a soft-processor. Still early stages in the project and and I'm currently deciding between Cyclone and Spartan. I haven't had any experience with either Nios II or MicroBlaze (and I believe that these are the only real options out there if you want strong community and/ or professional support). Anyway, what's really confusing me is the licensing issues. I know these questions have been asked before but I'm still confused. I understand that to use the MicroBlaze processor you either need to purchase the ISE Embedded Edition or purchase Platform Studio and the Embedded Development Kit (and use it with ISE WebPACK). However from what I can find out it says that you're free to put MicroBlaze processors on as many devices as you wish so long as they remain on site. I can't find any information about what type of license you need to include MicroBlaze in a product being sold. In the case of Nios II, you can use and develop with the Nios II with the Quartus II Web Edition because it comes with the OpenCore license that lets you use IP on an Altera FPGA so long as your development board is plugged in to the PC (I assume it doesn't matter who's hardware you use). The e variant you can use for free, but the other variants require a license to work when disconnected. The license you need is IP-NIOS, and though I can't find an official price listing anywhere I've seen $US500 being mentioned on forums... and presumably this allows you to sell as many products as you wish with Nios II processors on them? I've stated a whole bunch of assumptions here and I'd appreciate it if someone could tell me if I'm on the right track. Any advice on choosing between MicroBlaze and Nios II, or is there another option I'm missing? My company wants to spend as little as possible on licensing and/or development tools (this is their first time using an FPGA in a product), but my time is effectively free to them (I'm there under a research grant). That said, I know the free way is usually the hard way so if I can make a compelling case for them to spend money it may make my life a lot easier.Article: 151701
Hi RK and Torfinn, I'm sorry you feel that way about FaceBook. For us, it's a convenient way to reach out to customers directly by sharing content such as videos, pictures, news to everyone who is a part of our Terasic FaceBook page. It's simply a platform for expression of interest and the latest FPGA platform news, so you are right about that. As for people who abstain from using FaceBook (which I can understand completely), we are also constantly looking for ways to interact directly with FPGA designers, such as through forums, our webpage, etc. As always, if you have any suggestions, we would always certainly appreciate them. Thanks, Allen On May 5, 2:58=A0am, NeedCleverHandle <d_s_kl...@yahoo.com> wrote: > On May 3, 2:37=A0am, allen <ayho...@gmail.com> wrote: > > > Hey guys! > > > Terasic Technologies is holding a contest to WIN the newly released > > Altera DE0-Nano! Head over tohttp://www.terasic.com.tw/events/DE0_Nano_= Contest/ > > to leave a comment and win one today!!! > > > Thanks, > > Allen Houng > > Terasic Technologieswww.terasic.com > > Mr. Allen Houng, > > FaceBook? =A0Really? > > If you were interested in the hobby market, FaceBook might be the > right place. =A0Sadly, my vision of combined FaceBook and FPGAs looks a > lot like someone living in his mother's basement building geeky toys. > > I like to be professional with my FPGA work. > > RK.Article: 151702
"Alexander Kane" <ajpkane@gmail.com> wrote in message news:f1f230a8-d528-48f4-9db5-ac5700e6b2bb@17g2000prr.googlegroups.com... > I've stated a whole bunch of assumptions here and I'd appreciate it if > someone could tell me if I'm on the right track. > Any advice on choosing between MicroBlaze and Nios II, or is there > another option I'm missing? > My company wants to spend as little as possible on licensing and/or > development tools (this is their first time using an FPGA in a > product), but my time is effectively free to them (I'm there under a > research grant). That said, I know the free way is usually the hard > way so if I can make a compelling case for them to spend money it may > make my life a lot easier. 1) You will have a lot of headaches using Xilinx EDK. MicroBlaze is not a softcpu to start with. 2) You can use LatticeMico32 softcpu (which is free) on Altera or Xilinx FPGAs. E.g. check the opensource project "Milkymist", they're running LM32 softcpu on Spartan-6. 3) You can use Nios II/e (economy), which is also free, but I am not sure it could handle network speeds. Anyway, I would definitely go for Altera, but if You're interested in Xilinx devices, then go to MIlkymist page. They've developed memory controller + ethernet mac + many other cores.Article: 151703
I see it in many SDRAM controllers, e.g. ftp://ftp.xilinx.com/pub/applications/xapp/xapp608.pdf, and nobody explains WHY The extranal feedback trace must equal to CK len. Ok. This means that SDRAM will be clocked in phase with the FPGA system. How does it ensure that cmd/addr arrives to SDRAM in proper time, half cycle earlier of CK? In the more recommended xapp266 and xapp253, the external feedback is not used. Why? What is the purpose of the second, internal DLL? What should be the len of feedback in this case? In these designs, the read DQ is clocked directly by DQS. Yet, DQ is changed simultaneously with DQS. This ensures the setup/hold violation! The "HOW TO USE DDR SDRAM" says: "when controller receives read data from DDR SDRAM, it will internally delay the received strobe to the center of the received data window." I do not see any delay! ThanksArticle: 151704
On May 6, 5:11=A0pm, Alexander Kane <ajpk...@gmail.com> wrote: > Just a bit about the project I'm working on: Have an FPGA gathering > and manipulating data, and we need a processor to run the show and to > send the data over a network. =A0At the moment we are planning on using > a soft-processor. =A0Still early stages in the project and and I'm > currently deciding between Cyclone and Spartan. =A0I haven't had any > experience with either Nios II or MicroBlaze (and I believe that these > are the only real options out there if you want strong community and/ > or professional support). > > Anyway, what's really confusing me is the licensing issues. =A0I know > these questions have been asked before but I'm still confused. > > I understand that to use the MicroBlaze processor you either need to > purchase the ISE Embedded Edition or purchase Platform Studio and the > Embedded Development Kit (and use it with ISE WebPACK). =A0However from > what I can find out it says that you're free to put MicroBlaze > processors on as many devices as you wish so long as they remain on > site. =A0I can't find any information about what type of license you > need to include MicroBlaze in a product being sold. > > In the case of Nios II, you can use and develop with the Nios II with > the Quartus II Web Edition because it comes with the OpenCore license > that lets you use IP on an Altera FPGA so long as your development > board is plugged in to the PC (I assume it doesn't matter who's > hardware you use). =A0The e variant you can use for free, but the other > variants require a license to work when disconnected. =A0The license you > need is IP-NIOS, and though I can't find an official price listing > anywhere I've seen $US500 being mentioned on forums... and presumably > this allows you to sell as many products as you wish with Nios II > processors on them? > > I've stated a whole bunch of assumptions here and I'd appreciate it if > someone could tell me if I'm on the right track. > Any advice on choosing between MicroBlaze and Nios II, or is there > another option I'm missing? > My company wants to spend as little as possible on licensing and/or > development tools (this is their first time using an FPGA in a > product), but my time is effectively free to them (I'm there under a > research grant). =A0That said, I know the free way is usually the hard > way so if I can make a compelling case for them to spend money it may > make my life a lot easier. You have misunderstood what a "site license" means. This means that the software or IP can be used within the limited physical distance of the license server and not within a national or world basis for the company that purchased the license. The final bitstream can be shipped world wide. Ed McGettigan -- Xilinx Inc.Article: 151705
Hi,
On 05/06/11 11:16 PM, Jon Elson wrote:
> On 05/06/2011 12:52 AM, Michael wrote:
>> Hi,
>>
>> On 05/05/11 05:42 PM, Jon Elson wrote:
>>> Michael wrote:
>>>
>>>
>>>> leave the GUI and use scripts, it never causes these problems!
>>> Well, I'll have to learn how to do this.
>>>
>>> I did use a command line to run promgen, as running it from the GUI
>>> crashes.
>>>
>>> Jon
>> To synth define PROJECT or replace with project name
>> xst -ifn ${PROJECT}.xst -ofn ${PROJECT}.log
>>
>> You could use xflow to run the flow for P&R
>> xflow -p partname ${PROJECT}
>>
>> There are probably even better ways that a are compatible with the GUI
>> ising tcl I assume but I have not digged in to that, I am to old...or
>> maybe not ;)
>>
>> And then bitgen like you have done with promgen
>>
>> You might need some config for bitgen
> OK, well I can probably dig the syntax out of the log files. I had no
> idea it was that simple!
>
> The Windows-fashioned text editor in ise is pretty awful, I usually use
> emacs.
>
> I DO like the simulator, though. MUCH easier to hop around in the
> hierarchy and bring up signals from various inner components of the
> design than Modelsim. And, it automatically saves the signals on the
> screen for next time.
>
> The promgen command line I got from a Xilinx article puts out the
> reverse bit ordering, so it wouldn't load. I'll have to figure out what
> option sets it for the other ordering. But, after I did the cleanup, the
> prom file formatter works from the gui. I need to find out what I'm
> doing wrong that fouls up the management of vhdl files.
> I put the files into a directory and edited them for the first cut there
> before setting up an ide project and adding the files to the project.
> This left several versions of files with the same name in the various
> levels of the directory, and I think that is what started this mess.
>
> I think working both outside ide and inside it is most of the cause of
> the problem.
>
> Jon
Hi Jon, read the excelent article pointed out but outputlogic and go
scripting. Next move is go linux perhaps starting on a Virtualbox
installation on top of your Windows.
Good to hear that you use Emacs, have you installed the VHDL and Verilog
extensions to emacs?
Article: 151706You have misunderstood what a "site license" means. This means that the software or IP can be used within the limited physical distance of the license server and not within a national or world basis for the company that purchased the license. The final bitstream can be shipped world wide. ---------------------------------------------------------------------- So companies, that has HQ/support/testing in USA, but most programmers in e.g. India, can't share the same licence server? Even through VPN? It is basically possible, but out of the licence?Article: 151707
Michael wrote: > Hi Jon, read the excelent article pointed out but outputlogic and go > scripting. Next move is go linux perhaps starting on a Virtualbox > installation on top of your Windows. > > Good to hear that you use Emacs, have you installed the VHDL and Verilog > extensions to emacs? Well, that article is for 12.1, there might be a few changes to make it work with 10.1, but I do appreciate that article. I HAVE gone Linux, and am doing all new projects there, but I have some older projects to maintain, some even using classic 5V Spartan, so I can't completely abandon the ancient Windows stuff. The problem I was having was on the Linux 10.1 system, (as I even said in my subject line.) Yes, it has the VHDL language templates, but I'm not sure I really like them. Maybe I need to learn how to use them better. I use Linux native, and run Windows as a guest OS under VMware. JonArticle: 151708
> You have misunderstood what a "site license" means. This means that > the software or IP can be used within the limited physical distance of > the license server and not within a national or world basis for the > company that purchased the license. > > The final bitstream can be shipped world wide. Thanks for clearing this up for me. > 1) You will have a lot of headaches using Xilinx EDK. MicroBlaze is not a > softcpu to start with. > 2) You can use LatticeMico32 softcpu (which is free) on Altera or Xilinx > FPGAs. E.g. check the opensource project "Milkymist", they're running LM32 > softcpu on Spartan-6. > 3) You can use Nios II/e (economy), which is also free, but I am not sure it > could handle network speeds. > > Anyway, I would definitely go for Altera, but if You're interested in Xilinx > devices, then go to MIlkymist page. They've developed memory controller + > ethernet mac + many other cores. In regards to point (1) this is obviously your opinion, I was wondering if anyone else would like to comment on this. I am aware that LatticeMico32 is free, but I understand that an optimised version is available for Lattice FPGAs (so it would make sense to use it with a Lattice FPGA), whereas to use it on other FPGAs you have to deal with a Verilog dump. I'm just a little weary of learning Verilog while working on this project. Furthermore I have heard that the community support for LatticeMico32 is poor. Also is someone able to confirm about pricing for Nios II? (see first post)Article: 151709
On May 8, 3:28=A0am, "scrts" <mailsoc@[remove@here]gmail.com> wrote: > You have misunderstood what a "site license" means. This means that > the software or IP can be used within the limited physical distance of > the license server and not within a national or world basis for the > company that purchased the license. > > The final bitstream can be shipped world wide. > ---------------------------------------------------------------------- > > So companies, that has HQ/support/testing in USA, but most programmers in > e.g. India, can't share the same licence server? Even through VPN? It is > basically possible, but out of the licence? If the developers are in India then the licenses should be based in India. In most cases support and testing roles would have no need for licenses to the EDK or IP cores. This is really a conversation that is best suited for your Sales person than the internet. Ed McGettigan -- Xilinx Inc.Article: 151710
I have also reconstructed the EDK 10.1 inferred controller from example NGR file is available at https://wiki.ittc.ku.edu/rtrjvm/EDK_and_MD The circuit is http://4.bp.blogspot.com/- lbrLUp89H50/TcgOHuzzEEI/AAAAAAAAACw/j2WU_uNrxOk/s1600/feedback%2Bclocking.png I do not see it among the Xilinx Memory Interface App Notes. Is it better? Here again, commands are generated in phase with sys_clk andthe length of the internal feedbacks is the thing to know. The FB pin seems to be in phase with CLK0 at SDRAM. Why its 90 deg shifted version is used for clocking the receiving part? Since it does not account for the backward trace length from SDRAM to FPGA (the time traveled by data) but CLK and strobes must be in phase, wouldn't it be better to use one of the strobes for clocking? Instead, they use the strobe as clock enable in FIFO! Isn't it curious?Article: 151711
> > In the first app note you reference figure 8 shows the feedback for > the DCMs. This feedback allows the delay getting to the IO pins to be > calibrated out. If the feedback also includes the delay of the clock > path from the FPGA to the DIMM this delay will also be calibrated > out. I expect this is important in reading data from the DIMM. "Calibrate out" is too general term. I understand that DCM allows to have some points "in phase". I want to know why this is done in these cases. It is a XUPV2p board and the extranal feedback trace length is identical to CK.Article: 151712
> You have misunderstood what a "site license" means. This means that > the software or IP can be used within the limited physical distance of > the license server and not within a national or world basis for the > company that purchased the license. I presume this is to stop multi-national companies having _one_ license to cover wordwide development? (This isn't really a practical proposition but is the extreme case) NialArticle: 151713
Does any one know an add on card that can be used with XUPV2P?Article: 151714
On May 7, 3:02=A0pm, valtih1978 <inte...@yandex.ru> wrote: > I see it in many SDRAM controllers, e.g.ftp://ftp.xilinx.com/pub/applicat= ions/xapp/xapp608.pdf, and nobody explains > WHY > > The extranal feedback trace must equal to CK len. Ok. This means that SDR= AM > will be clocked in phase with the FPGA system. How does it ensure that > cmd/addr arrives to SDRAM in proper time, half cycle earlier of CK? > > In the more recommended xapp266 and xapp253, the external feedback is not > used. Why? What is the purpose of the second, internal DLL? What should b= e > the len of feedback in this case? > > In these designs, the read DQ is clocked directly by DQS. Yet, DQ is chan= ged > simultaneously with DQS. This ensures the setup/hold violation! The "HOW = TO > USE DDR SDRAM" says: "when controller receives read data from DDR SDRAM, = it > will internally delay the received strobe to the center of the received d= ata > window." I do not see any delay! > > Thanks In the first app note you reference figure 8 shows the feedback for the DCMs. This feedback allows the delay getting to the IO pins to be calibrated out. If the feedback also includes the delay of the clock path from the FPGA to the DIMM this delay will also be calibrated out. I expect this is important in reading data from the DIMM. But I'm a bit unclear about why the feedback does not include the delay of the read data PCB traces as well. Data going to the DIMM does not need to consider the trace delay because both clock and data see the same delay (if the board is designed that way). But the read data path delay actually consists of the clock path to the DIMM as well as the read data path back to the FPGA. Perhaps I didn't read the app note correctly. These things can be a little hard to interpret until you completely understand their terminology. RickArticle: 151715
On May 8, 10:26=A0pm, Alexander Kane <ajpk...@gmail.com> wrote: > > You have misunderstood what a "site license" means. This means that > > the software or IP can be used within the limited physical distance of > > the license server and not within a national or world basis for the > > company that purchased the license. > > > The final bitstream can be shipped world wide. > > Thanks for clearing this up for me. > > > 1) You will have a lot of headaches using Xilinx EDK. MicroBlaze is not= a > > softcpu to start with. > > 2) You can use LatticeMico32 softcpu (which is free) on Altera or Xilin= x > > FPGAs. E.g. check the opensource project "Milkymist", they're running L= M32 > > softcpu on Spartan-6. > > 3) You can use Nios II/e (economy), which is also free, but I am not su= re it > > could handle network speeds. > > > Anyway, I would definitely go for Altera, but if You're interested in X= ilinx > > devices, then go to MIlkymist page. They've developed memory controller= + > > ethernet mac + many other cores. > > In regards to point (1) this is obviously your opinion, I was > wondering if anyone else would like to comment on this. I think he may be getting MicroBlaze mixed up with PicoBlaze or even the PowerPC versions of the Vertex CPUs. To the best of my knowledge both PicoBlaze and MicroBlaze CPUs are soft cores. The MicroBlaze is fully synthesized while the PicoBlaze is structural HDL which instantiates the LUTs and FFs rather than inferring them. But that does not make the PicoBlaze CPU a hard core. > I am aware that LatticeMico32 is free, but I understand that an > optimised version is available for Lattice FPGAs (so it would make > sense to use it with a Lattice FPGA), whereas to use it on other FPGAs > you have to deal with a Verilog dump. =A0I'm just a little weary of > learning Verilog while working on this project. =A0Furthermore I have > heard that the community support for LatticeMico32 is poor. I've never dug into the details of the Lattice Micro32, but what do you mean by Verilog "dump"? Verilog is actually q > Also is someone able to confirm about pricing for Nios II? (see first > post)Article: 151716
On May 9, 1:06=A0pm, rickman <gnu...@gmail.com> wrote: > On May 8, 10:26=A0pm, Alexander Kane <ajpk...@gmail.com> wrote: > > > > > > You have misunderstood what a "site license" means. This means that > > > the software or IP can be used within the limited physical distance o= f > > > the license server and not within a national or world basis for the > > > company that purchased the license. > > > > The final bitstream can be shipped world wide. > > > Thanks for clearing this up for me. > > > > 1) You will have a lot of headaches using Xilinx EDK. MicroBlaze is n= ot a > > > softcpu to start with. > > > 2) You can use LatticeMico32 softcpu (which is free) on Altera or Xil= inx > > > FPGAs. E.g. check the opensource project "Milkymist", they're running= LM32 > > > softcpu on Spartan-6. > > > 3) You can use Nios II/e (economy), which is also free, but I am not = sure it > > > could handle network speeds. > > > > Anyway, I would definitely go for Altera, but if You're interested in= Xilinx > > > devices, then go to MIlkymist page. They've developed memory controll= er + > > > ethernet mac + many other cores. > > > In regards to point (1) this is obviously your opinion, I was > > wondering if anyone else would like to comment on this. > > I think he may be getting MicroBlaze =A0mixed up with PicoBlaze or even > the PowerPC versions of the Vertex CPUs. =A0To the best of my knowledge > both PicoBlaze and MicroBlaze CPUs are soft cores. =A0The MicroBlaze is > fully synthesized while the PicoBlaze is structural HDL which > instantiates the LUTs and FFs rather than inferring them. =A0But that > does not make the PicoBlaze CPU a hard core. > > > I am aware that LatticeMico32 is free, but I understand that an > > optimised version is available for Lattice FPGAs (so it would make > > sense to use it with a Lattice FPGA), whereas to use it on other FPGAs > > you have to deal with a Verilog dump. =A0I'm just a little weary of > > learning Verilog while working on this project. =A0Furthermore I have > > heard that the community support for LatticeMico32 is poor. > > I've never dug into the details of the Lattice Micro32, but what do > you mean by Verilog "dump"? =A0Verilog is actually q I seem to have fat fingered this post before I was done typing. Verilog is actually quite easy to pick up. If the code is already written I would not expect it to be at all hard to compile. What do you mean when you say there is an "optimized" version for Lattice devices? Do you mean they have a pre-compiled version? > > Also is someone able to confirm about pricing for Nios II? (see first > > post) Can't help you there. Wouldn't it be a good idea to talk to Altera for pricing? RickArticle: 151717
On May 9, 7:24=A0am, Manusha <manusha1...@gmail.com> wrote: > Does any one know an add on card that can be used with XUPV2P? RTFM: <http://www.xilinx.com/univ/XUPV2P/Documentation/ug069.pdf> Look for the text "for a list of expansion boards that are compatible" - it's in there.Article: 151718
Hello dear all, I have run into a problem regarding the FPGA. The FPGA output signal amplitude is 3.3, and to drive my switches, I need to increase the voltage up to 15 V. I am using TC4427(dual power mosfet driver)as a buffer after FPGA , and would like to check the possibility of my gate driver, but whenever I wanna check it, the FPGA pin is destroyed. I personally believe a resistance is required in series with the IC. Could you please give me a hand with this problem if you do not mind? I highly appreciate your prompt answer. Best Regards, BashirArticle: 151719
bashir2000 <user@compgroups.net/> wrote: > I have run into a problem regarding the FPGA. The FPGA output > signal amplitude is 3.3, and to drive my switches, I need to > increase the voltage up to 15 V. I am using TC4427(dual power > mosfet driver)as a buffer after FPGA , and would like to check > the possibility of my gate driver, but whenever I wanna check it, > the FPGA pin is destroyed. I personally believe a resistance is > required in series with the IC. My first thought is that anyone who doesn't know enough electronics to figure this out doesn't belong anywhere near and FPGA. I hope the FPGAs aren't too expensive! > Could you please give me a hand with this problem if you do not mind? > I highly appreciate your prompt answer. Well, it looks like the input to the TC4427 should be less than one microamp, and that Vih of 2.4V should be fine. Vin is allowed to go all the way up to Vdd (15V in your case), though even so it would usually be that 3.3V would be fine. I would triple check that you wired up the TC4427 right. If you do it wrong, it might put 15V into the FPGA pin, which would quickly destroy it. If speed isn't to important, a resistor should be fine on the output. With 12pF input capacitance, a resistor won't slow you down too much, and will protect the FPGA. A big enough resistor should protect you up to 15V. -- glenArticle: 151720
On May 6, 10:20=A0pm, allen <ayho...@gmail.com> wrote: > Hi RK and Torfinn, > > I'm sorry you feel that way about FaceBook. For us, it's a convenient > way to reach out to customers directly by sharing content such as > videos, pictures, news to everyone who is a part of our Terasic > FaceBook page. It's simply a platform for expression of interest and > the latest FPGA platform news, so you are right about that. > > As for people who abstain from using FaceBook (which I can understand > completely), we are also constantly looking for ways to interact > directly with FPGA designers, such as through forums, our webpage, > etc. > > As always, if you have any suggestions, we would always certainly > appreciate them. > > Thanks, > Allen > > On May 5, 2:58=A0am, NeedCleverHandle <d_s_kl...@yahoo.com> wrote: > > > > > > > > > On May 3, 2:37=A0am, allen <ayho...@gmail.com> wrote: > > > > Hey guys! > > > > Terasic Technologies is holding a contest to WIN the newly released > > > Altera DE0-Nano! Head over tohttp://www.terasic.com.tw/events/DE0_Nan= o_Contest/ > > > to leave a comment and win one today!!! > > > > Thanks, > > > Allen Houng > > > Terasic Technologieswww.terasic.com > > > Mr. Allen Houng, > > > FaceBook? =A0Really? > > > If you were interested in the hobby market, FaceBook might be the > > right place. =A0Sadly, my vision of combined FaceBook and FPGAs looks a > > lot like someone living in his mother's basement building geeky toys. > > > I like to be professional with my FPGA work. > > > RK. How about LinkedIn? It has FPGA groups (but honestly, I don't read them). Altera has a good wiki - that one I do read, and IIRC, that's how I found TerAsic in the first place. Right here - comp.arch.fpga - I feel that it's OK to have a reasonable number of product announcements here. It looks to me like Brand-X monitors this board for advertising/customer relation benefit. (No problem with that - helping people so that they buy more product is how industry is supposed to work.) And don't you have a data base of customers on your web site? Shouldn't be too hard to add potential customers. Just a couple of thoughts, RKArticle: 151721
>Hello dear all, > >I have run into a problem regarding the FPGA. The FPGA output signal amplitude is 3.3, and to drive my switches, I need to increase the voltage up to 15 V. I am using TC4427(dual power mosfet driver)as a buffer after FPGA , and would like to check the possibility of my gate driver, but whenever I wanna check it, the FPGA pin is destroyed. I personally believe a resistance is required in series with the IC. Could you please give me a hand with this problem if you do not mind? >I highly appreciate your prompt answer. > >Best Regards, >Bashir > Reading the datasheet, I would not expect that a series resistor is required, although one should not prove to be a problem (33 or 47 ohm, probably). Double check the connections. Could the MOSFET switching cause a power supply glitch to the FPGA? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151722
On May 9, 5:50=A0am, valtih1978 <inte...@yandex.ru> wrote: > > In the first app note you reference figure 8 shows the feedback for > > the DCMs. =A0This feedback allows the delay getting to the IO pins to b= e > > calibrated out. =A0If the feedback also includes the delay of the clock > > path from the FPGA to the DIMM this delay will also be calibrated > > out. =A0I expect this is important in reading data from the DIMM. > > "Calibrate out" is too general term. I understand that DCM allows to have > some points "in phase". I want to know why this is done in these cases. > > It is a XUPV2p board and the extranal feedback trace length is identical = to > CK. If you don't adjust the phase to align the clock to the timing of the return data your clock speed will be limited by the round trip delay path. That's also why they use a 90 degree phase relationship between the output clock and the input clock. That puts the sample time in the middle of the data stable time. RickArticle: 151723
> I am aware that LatticeMico32 is free, but I understand that an > optimised version is available for Lattice FPGAs (so it would make > sense to use it with a Lattice FPGA), whereas to use it on other FPGAs > you have to deal with a Verilog dump. Not true. The RTL is available and it's the same code for any FPGA (apart from the memories). Cheers, JonArticle: 151724
On May 6, 5:11=A0pm, Alexander Kane <ajpk...@gmail.com> wrote: > > I understand that to use the MicroBlaze processor you either need to > purchase the ISE Embedded Edition or purchase Platform Studio and the > Embedded Development Kit (and use it with ISE WebPACK). =A0However from > what I can find out it says that you're free to put MicroBlaze > processors on as many devices as you wish so long as they remain on > site. =A0I can't find any information about what type of license you > need to include MicroBlaze in a product being sold. > There is a version of the uBlaze that's shipped in an XAPP - you just instantiate a core, and use GCC for development. No EDK needed. My understanding is that the generated bitstream using any flavor of uBlaze is without any additional cost (provided that it's used in a Xilinx chip.) > In the case of Nios II, you can use and develop with the Nios II with > the Quartus II Web Edition because it comes with the OpenCore license > that lets you use IP on an Altera FPGA so long as your development > board is plugged in to the PC (I assume it doesn't matter who's > hardware you use). =A0The e variant you can use for free, but the other > variants require a license to work when disconnected. =A0The license you > need is IP-NIOS, and though I can't find an official price listing > anywhere I've seen $US500 being mentioned on forums... and presumably > this allows you to sell as many products as you wish with Nios II > processors on them? > There's a Free-NIOS now. It's not as "good" as the payfor-NIOS, but it works just fine. > I've stated a whole bunch of assumptions here and I'd appreciate it if > someone could tell me if I'm on the right track. > Any advice on choosing between MicroBlaze and Nios II, or is there > another option I'm missing? > My company wants to spend as little as possible on licensing and/or > development tools (this is their first time using an FPGA in a > product), but my time is effectively free to them (I'm there under a > research grant). =A0That said, I know the free way is usually the hard > way so if I can make a compelling case for them to spend money it may > make my life a lot easier. Don't ignore OpenCores. There are a couple of processors there (MIPS, OpenRISC, etc) that are portable to and supported by GCC variants. IMnsHO, the value add for NIOS and uBlaze is the ease (speed) of development - When you graduate you'll find that time goes from "free" to "priceless". RK
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