Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 151900

Article: 151900
Subject: Connecting of IP core simulated in GHDL to pseudoterminal via
From: Wojciech M. Zabolotny <wzab@ise.pw.edu.pl>
Date: Thu, 2 Jun 2011 17:45:10 +0000 (UTC)
Links: << >>  << T >>  << A >>
When working with simulated soft CPUs to be implemented in FPGA,
I often needed a possibility to connect terminal emulator
(e.g. Minicom) or my own program to serial port of the simulated
IP core.

Finally I've found a solution, which seems to be good enough
to share it with others.

I use the pseudoterminal (ptmx) found in Linux to establish
communication between GHDL simulator and my terminal program.
However GHDL does not offer functions needed to control
pseudoterminals, therefore I've prepared a small C library
(ghdl_pty.c) providing necessary functions via VPI.
Additionally I needed to provide nonblocking reading from
the pseudoterminal, to avoid stopping of simulation when no
data is available this functionality is also implemented
in ghdl_pty.c, in function ghdl_pty_read.

>From the VHDL side, my pseudo UART is visible as:

 component ghdl_uart
    port (
      data_out : out std_logic_vector(7 downto 0);
      data_in  : in  std_logic_vector(7 downto 0);
      dav      : out std_logic;         -- received data available
      ready    : out std_logic;  -- there is free space in transmit buffer
      empty    : out std_logic;         -- the transmit buffer is empty
      rd       : in  std_logic;         -- asynchronous read strobe
      wr       : in  std_logic          -- asynchronous write strobe
      );
  end component;

When new data arrives, "dav" goes high. To read the data, you should
set "rd" to '1' and the data will be visible on "data_out".
If no more data are in the input queue, "dav" goes low.

If you want to write data, you put them on "data_in", and rise "wr".
The data are transmitted to the output queue, and later transmitted
to the pseudoterminal.

Full sources, published as public domain are available on
alt.sources usenet group, in thread "Pseudo UART allowing to connect
 via pseudoterminal to GHDL simulated IP core"
( news:<slrniufi5a.d67.wzab@wzab.nasz.dom>
  http://http://groups.google.com/group/alt.sources/msg/bc8eb919101839ba )

You can find more information in the "desc.txt" file available in the
archive contained in the alt.sources message.

I hope, that the emulated UART will be useful for you.

Wojciech M. Zabolotny
wzab<at>ise.pw.edu.pl

Article: 151901
Subject: Re: J1 forth processor in FPGA - possibility of interactive work?
From: wzab <wzab01@gmail.com>
Date: Thu, 2 Jun 2011 10:56:54 -0700 (PDT)
Links: << >>  << T >>  << A >>
I have just prepared a code, allowing to connect a CPU or another SoC
simulated
in GHDL to the pseudoterminal in Linux (or similar system), and then
communicate
with it just as with real hardware connected to the
real serial port.

I think, that this solution may be useful in development of J1
(ported to VHDL, e.g. via MyHDL) as an interective or tethered
Forth system.

The announce of my solution is available in comp.arch.fpga:
http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/beef5f55376f48fd
(or look for "Connecting of IP core simulated in GHDL to
pseudoterminal via UART-like interface"
news:<slrniufj16.de4.wzab@wzab.nasz.dom>)

The sources are published as public domain on alt.sources:
http://groups.google.com/group/alt.sources/browse_thread/thread/db9232e97431c019
(or look for "Pseudo UART allowing to connect via pseudoterminal to
GHDL simulated IP core"
news:<slrniufi5a.d67.wzab@wzab.nasz.dom>)

Wojtek

Article: 151902
Subject: Re: Connecting of IP core simulated in GHDL to pseudoterminal via
From: wzab <wzab01@gmail.com>
Date: Thu, 2 Jun 2011 11:02:32 -0700 (PDT)
Links: << >>  << T >>  << A >>
Of course the link to alt.usenet message should be:
http://groups.google.com/group/alt.sources/msg/bc8eb919101839ba


Article: 151903
Subject: Re: Connecting of IP core simulated in GHDL to pseudoterminal via
From: Mike Treseler <mtreseler@gmail.com>
Date: Thu, 02 Jun 2011 11:41:51 -0700
Links: << >>  << T >>  << A >>
On 6/2/2011 10:45 AM, Wojciech M. Zabolotny wrote:
> When working with simulated soft CPUs to be implemented in FPGA,
> I often needed a possibility to connect terminal emulator
> (e.g. Minicom) or my own program to serial port of the simulated
> IP core.
>
> Finally I've found a solution, which seems to be good enough
> to share it with others.

Thanks for the interesting and useful VPI example.

 > Of course the link to alt.usenet message should be:
 > http://groups.google.com/group/alt.sources/msg/bc8eb919101839ba

Yes, that does the trick.

      -- Mike Treseler

Article: 151904
Subject: Re: Microblaze and PowerPC
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Thu, 2 Jun 2011 18:42:26 +0000 (UTC)
Links: << >>  << T >>  << A >>
Rob Gaddi <rgaddi@technologyhighland.com> wrote:
> On 6/2/2011 7:50 AM, am85 wrote:

>>     I would like to perform mathematical operations as Division and Square
>> root. From what i have read, i either need to use Microblaze or PowerPC.
>> can anyone please tell me the difference in performance between them, and
>> is it a hardware or software calculation. Does each one of these options
>> has a  dedicated FPU?
 
> Not at all true.  Either of those algorithms can be implemented, either 
> in fixed or floating point, as pure hardware.

And either pipelined or combinatorial.

-- glen

Article: 151905
Subject: Re: How could I get LUT-level netlist in Xilinx ISE?
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Thu, 2 Jun 2011 18:51:24 +0000 (UTC)
Links: << >>  << T >>  << A >>
Tim Wescott <tim@seemywebsite.com> wrote:
> On 06/02/2011 09:56 AM, chifalcon wrote:
>> Hi, I need to convert the high level design to LUT level netlist, and then
>> make corrections to it.

> Why?  Wouldn't you rather correct the high level design once, then make 
> correct LUT level netlists every time you use it?  Otherwise you're 
> doomed to hand-correcting that netlist every time you synthesize, or 
> you're stuck with that low-level netlist instead of a nice readable, 
> portable, etc., high level design.

In the XC4000 days, I had a design that used Xilinx (RPM) macros,
similar to the way people call assembly programs from a high-level
language to do things that the compiler won't do.  The way it was
done was to generate a dummy (empty) module in verilog, generate
the netlist based on that, then remove the generated netlist file
at the appropriate place just before P&R and supply the RPM to P&R.

I believe it is still possible to do something similar.
 
> The only valid reason I see to do this is if you have to hand-optimize 
> the placement of some really timing-critical piece of IP, and even there 
> it would seem that you could go far with careful use of timing 
> constraints.  But you wouldn't be doing that at the LUT level anyway, 
> would you?

Or maybe to work around a bug in the tools. 

-- glen

Article: 151906
Subject: Re: FFT using logic gates only
From: Jon Elson <jmelson@wustl.edu>
Date: Thu, 02 Jun 2011 13:58:44 -0500
Links: << >>  << T >>  << A >>
On 06/01/2011 11:00 PM, glen herrmannsfeldt wrote:
> Joel Williams<nospamwhydontyoublogaboutit@nospamgmail.com>  wrote:
>>> I intend to implement FFT using Logic gates only , by this i mean i
>>> have written verilog code of FFT for xilinx spartran III, I can
>>> visualize it in Xilinx ISE 13.1 using technology schematic. But its
>>> still high level abstraction, can someone guide me how to generate
>>> text file / other format file  that describes the whole implementation
>>> using AND OR , XOR, NAND , NOR gate only
>
>> You'll probably have to do it manually, and perhaps ask yourself why you
>> want to do it.
>
>> FPGAs aren't actually built from these primitive logic gates but rather
>> LUTs and FFs, so there's no reason for the tools to deal in any
>> constructs other than these.
>
> In any case, with the FFs in there for free, there is no reason
> not to pipeline it.  Look up systolic array processor.
CLEARLY, this is a homework question of some kind, that's the only
reason someone would do this.  And, the person who invented the question
apparently doesn't know how FPGAs are actually built or configured, as
the question seems nearly idiotic.  it would be QUITE difficult to force
the tools to avoid using any FFs.  If it really ISN'T homework, then it is
from the same camp as the guys who build digital clocks from vacuum 
tubes or computers from discrete transistors.

Jon

Article: 151907
Subject: Re: How could I get LUT-level netlist in Xilinx ISE?
From: OutputLogic <evgenist@gmail.com>
Date: Thu, 2 Jun 2011 13:31:18 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi,

What you describe looks like simulation netlist. You can generate it
using Xilinx netgen tool either in command-line mode or from ISE
(generate post-synthesis simulation model).

Thanks,
Evgeni
http://outputlogic.com

Article: 151908
Subject: Re: How could I get LUT-level netlist in Xilinx ISE?
From: "chifalcon" <eric.he@n_o_s_p_a_m.n_o_s_p_a_m.hotmail.com>
Date: Thu, 02 Jun 2011 16:19:04 -0500
Links: << >>  << T >>  << A >>

Hi, Thanks for your reply.
  I am working on the security of cryptography. Some related work cannot be
done by regular synthesize way. 
  I am generating the DRP logic (Dual Rail with Precharge logic). I need to
transform the sigle-ended circuit (normal circuit) to the complementary
dual rail circuit. 
  This cannot be directly done by the existing synthesis tool, just like
XST. BY far, the only possible way to do it is manually correcting the LUT
netlist or manually modify on FPGA editor.  

  Best,


>On 06/02/2011 09:56 AM, chifalcon wrote:
>> Hi, I need to convert the high level design to LUT level netlist, and
then
>> make corrections to it.
>>
>Why?  Wouldn't you rather correct the high level design once, then make 
>correct LUT level netlists every time you use it?  Otherwise you're 
>doomed to hand-correcting that netlist every time you synthesize, or 
>you're stuck with that low-level netlist instead of a nice readable, 
>portable, etc., high level design.
>
>The only valid reason I see to do this is if you have to hand-optimize 
>the placement of some really timing-critical piece of IP, and even there 
>it would seem that you could go far with careful use of timing 
>constraints.  But you wouldn't be doing that at the LUT level anyway, 
>would you?
>
>-- 
>
>Tim Wescott
>Wescott Design Services
>http://www.wescottdesign.com
>
>Do you need to implement control loops in software?
>"Applied Control Theory for Embedded Systems" was written for you.
>See details at http://www.wescottdesign.com/actfes/actfes.html
>	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 151909
Subject: Re: How could I get LUT-level netlist in Xilinx ISE?
From: "chifalcon" <eric.he@n_o_s_p_a_m.n_o_s_p_a_m.hotmail.com>
Date: Thu, 02 Jun 2011 16:21:43 -0500
Links: << >>  << T >>  << A >>
Hi, Thank you!
 
  It really helpful! I will try it tomorrow!

  Best,


>Hi,
>
>What you describe looks like simulation netlist. You can generate it
>using Xilinx netgen tool either in command-line mode or from ISE
>(generate post-synthesis simulation model).
>
>Thanks,
>Evgeni
>http://outputlogic.com
>	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 151910
Subject: Re: Microblaze and PowerPC
From: Martin Thompson <martin.j.thompson@trw.com>
Date: Fri, 03 Jun 2011 10:12:46 +0100
Links: << >>  << T >>  << A >>
"am85" <ammarei@n_o_s_p_a_m.hotmail.com> writes:

> Hi, 
>    I would like to perform mathematical operations as Division and Square
> root. From what i have read, i either need to use Microblaze or PowerPC.

Where did you read that?  You can perform those mathematical operations using
the FPGA fabric perfectly well.

> can anyone please tell me the difference in performance between them, and
> is it a hardware or software calculation. Does each one of these options
> has a  dedicated FPU? 
>

To directly answer the question, Microblaze has an optional FPU (made of LUTs
and flipflops).  IIRC PowerPC could have an FPU added (also made of LUTs and
FFs) so I'd expect performance on those operations to be similar(ish).

Microblaze with an FPU in a Spartan3ADSP will clock happily at tens of MHz.
Maths performance is limited - the square-root takes ~30 cycles to
complete, so you may get 2-3 Msqrts/sec.

Conversely I've written a pretty wide fixed-point square-root which runs at
about the same clock rate, but produces an answer every clock cycle (heavily
pipelined).

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware

Article: 151911
Subject: Re: How could I get LUT-level netlist in Xilinx ISE?
From: Martin Thompson <martin.j.thompson@trw.com>
Date: Fri, 03 Jun 2011 10:15:45 +0100
Links: << >>  << T >>  << A >>
"chifalcon" <eric.he@n_o_s_p_a_m.hotmail.com> writes:

> Hi, I need to convert the high level design to LUT level netlist, and then
> make corrections to it. 

XDL is a textual representation of the lowest level of FPGA that is easy to get
to (FPGA Editor level: slices, PIPs, wires...).  

You can then hack on that to your heart's content and (in theory at least) turn
it back into an NCD file and then on to a bitstream.

Cheers,
Martin
-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware

Article: 151912
Subject: Re: FFT using logic gates only
From: "RCIngham" <robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com>
Date: Fri, 03 Jun 2011 04:46:28 -0500
Links: << >>  << T >>  << A >>
>On 06/01/2011 11:00 PM, glen herrmannsfeldt wrote:
>> Joel Williams<nospamwhydontyoublogaboutit@nospamgmail.com>  wrote:
>>>> I intend to implement FFT using Logic gates only , by this i mean i
>>>> have written verilog code of FFT for xilinx spartran III, I can
>>>> visualize it in Xilinx ISE 13.1 using technology schematic. But its
>>>> still high level abstraction, can someone guide me how to generate
>>>> text file / other format file  that describes the whole
implementation
>>>> using AND OR , XOR, NAND , NOR gate only

SNIP!

>CLEARLY, this is a homework question of some kind, that's the only
>reason someone would do this.  And, the person who invented the question
>apparently doesn't know how FPGAs are actually built or configured, as
>the question seems nearly idiotic.  it would be QUITE difficult to force
>the tools to avoid using any FFs.  If it really ISN'T homework, then it
is
>from the same camp as the guys who build digital clocks from vacuum 
>tubes or computers from discrete transistors.
>
>Jon

If homework: malice; otherwise stupidity.
http://en.wikipedia.org/wiki/Hanlon%27s_razor
	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 151913
Subject: verilog task and vhdl
From: "carlob" <carlo.beccia@n_o_s_p_a_m.n_o_s_p_a_m.libero.it>
Date: Fri, 03 Jun 2011 04:54:23 -0500
Links: << >>  << T >>  << A >>
Hi all,
I've a functional model of a PHY chip in verilog with a lot of tasks to
stimualte change on signals at the interface (and not only)...
Unfortunately I'm not experienced with verilog...I would write a testbench
in vhdl and reuse the model in verilog...

How to call a verilog task inside a vhdl testbench??? Is it possible??? I
would like to don't change the verilog (that has already been tested
deeply) and reusing it as it is...

Thank you for the help
Carlo	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 151914
Subject: Re: verilog task and vhdl
From: "RCIngham" <robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com>
Date: Fri, 03 Jun 2011 05:09:55 -0500
Links: << >>  << T >>  << A >>
>Hi all,
>I've a functional model of a PHY chip in verilog with a lot of tasks to
>stimualte change on signals at the interface (and not only)...
>Unfortunately I'm not experienced with verilog...I would write a
testbench
>in vhdl and reuse the model in verilog...
>
>How to call a verilog task inside a vhdl testbench??? Is it possible??? I
>would like to don't change the verilog (that has already been tested
>deeply) and reusing it as it is...
>
>Thank you for the help
>Carlo	   
>					
>---------------------------------------		
>Posted through http://www.FPGARelated.com
>

If the Verilog task is inside a Verilog module, then you can instantiate
the module just like a VHDL component. You will need a component
declaration in VHDL that matches the Verilog module's port declaration.
	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 151915
Subject: Re: verilog task and vhdl
From: "carlob" <carlo.beccia@n_o_s_p_a_m.n_o_s_p_a_m.libero.it>
Date: Fri, 03 Jun 2011 05:24:22 -0500
Links: << >>  << T >>  << A >>

>If the Verilog task is inside a Verilog module, then you can instantiate
>the module just like a VHDL component. You will need a component
>declaration in VHDL that matches the Verilog module's port declaration.
>	   
>					
>---------------------------------------		
>Posted through http://www.FPGARelated.com
>

Thank you for the answer....
Ok...I can instantiate the module inside vhdl...but then what is the sintax
to call tasks???

For example:
in verilog I have:
module PHY{...}

and inside the module 
task pippo; ...

Inside vhdl I do a component declarartion and a port map...
component PHY 
port(...);
end component;

then 

myphy: PHY
port map(...);

..now I want to call task pippo...

myphy.pippo ???
pippo ???

Thank you for the help
Carlo	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 151916
Subject: Re: How could I get LUT-level netlist in Xilinx ISE?
From: "chifalcon" <eric.he@n_o_s_p_a_m.n_o_s_p_a_m.hotmail.com>
Date: Fri, 03 Jun 2011 09:23:10 -0500
Links: << >>  << T >>  << A >>
Yes, I was doing on XDL for a long time. But the problem is : If I work on
XDL, I have to seperate the original core and complementary core. In other
words, they are placed independently. So they are dual-core, but dual-rail
logic. 

The ideal way is to placed the dual parts together. This means each pair of
original and complementary LUT are placed in the same SLICE. In XDL, the
position for each LUT has already been located in the specific hardware
resources. There is no free neighbouring hardware to place the
complementary LUT. Therefore, I have to work on a kind of
no-hardware-specific LUT netlist.

I am still checking..

Best,

 
>"chifalcon" <eric.he@n_o_s_p_a_m.hotmail.com> writes:
>
>> Hi, I need to convert the high level design to LUT level netlist, and
then
>> make corrections to it. 
>
>XDL is a textual representation of the lowest level of FPGA that is easy
to get
>to (FPGA Editor level: slices, PIPs, wires...).  
>
>You can then hack on that to your heart's content and (in theory at least)
turn
>it back into an NCD file and then on to a bitstream.
>
>Cheers,
>Martin
>-- 
>martin.j.thompson@trw.com 
>TRW Conekt - Consultancy in Engineering, Knowledge and Technology
>http://www.conekt.co.uk/capabilities/39-electronic-hardware
>	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 151917
Subject: Re: verilog task and vhdl
From: Mike Treseler <mtreseler@gmail.com>
Date: Fri, 03 Jun 2011 11:35:54 -0700
Links: << >>  << T >>  << A >>
On 6/3/2011 3:24 AM, carlob wrote:
>> If the Verilog task is inside a Verilog module, then you can instantiate
>> the module just like a VHDL component. You will need a component
>> declaration in VHDL that matches the Verilog module's port declaration.
>> 	
>> 					
>> ---------------------------------------		
>> Posted through http://www.FPGARelated.com
>>
>
> Thank you for the answer....
> Ok...I can instantiate the module inside vhdl...but then what is the sintax
> to call tasks???
>
> For example:
> in verilog I have:
> module PHY{...}
>

I suggest a direct instance - no component,
Something like:

       phy_1 : entity work.phy
       port map (reset => reset_s,     -- [in]
                 clock => clock_s,     -- [in]
                 data  => data_s,      -- [out]
                 ready => ready_s);    -- [out]


  -- Mike Treseler

Article: 151918
Subject: Looking for bitgen Virtex7 and Kintex7 support
From: Neil Steiner <neil.steiner@isi.edu>
Date: Fri, 03 Jun 2011 14:36:16 -0400
Links: << >>  << T >>  << A >>
Hello,

It appears that bitgen in ISE 13.1 supports Virtex7 and Kintex7 
implementation up to but not including bitstream generation.  Does 
anybody know when bitgen support may be expected for those architectures?

Neil


Article: 151919
Subject: Re: Looking for bitgen Virtex7 and Kintex7 support
From: "maxascent" <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk>
Date: Fri, 03 Jun 2011 13:52:37 -0500
Links: << >>  << T >>  << A >>
>Hello,
>
>It appears that bitgen in ISE 13.1 supports Virtex7 and Kintex7 
>implementation up to but not including bitstream generation.  Does 
>anybody know when bitgen support may be expected for those architectures?
>
>Neil
>
>

Have you managed to build yourself a Virtex 7?
	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 151920
Subject: Re: Looking for bitgen Virtex7 and Kintex7 support
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Fri, 3 Jun 2011 12:26:11 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jun 3, 11:36=A0am, Neil Steiner <neil.stei...@isi.edu> wrote:
> Hello,
>
> It appears that bitgen in ISE 13.1 supports Virtex7 and Kintex7
> implementation up to but not including bitstream generation. =A0Does
> anybody know when bitgen support may be expected for those architectures?
>
> Neil

Customers that have received the initial samples have bitstream
support.  Broad based support will occur before the General ES sample
phase begins.

Ed McGettigan
--
Xilinx Inc.

Article: 151921
Subject: Re: verilog task and vhdl
From: "carlob" <carlo.beccia@n_o_s_p_a_m.n_o_s_p_a_m.libero.it>
Date: Fri, 03 Jun 2011 15:48:05 -0500
Links: << >>  << T >>  << A >>
>On 6/3/2011 3:24 AM, carlob wrote:
>>> If the Verilog task is inside a Verilog module, then you can
instantiate
>>> the module just like a VHDL component. You will need a component
>>> declaration in VHDL that matches the Verilog module's port
declaration.
>>> 	
>>> 					
>>> ---------------------------------------		
>>> Posted through http://www.FPGARelated.com
>>>
>>
>> Thank you for the answer....
>> Ok...I can instantiate the module inside vhdl...but then what is the
sintax
>> to call tasks???
>>
>> For example:
>> in verilog I have:
>> module PHY{...}
>>
>
>I suggest a direct instance - no component,
>Something like:
>
>       phy_1 : entity work.phy
>       port map (reset => reset_s,     -- [in]
>                 clock => clock_s,     -- [in]
>                 data  => data_s,      -- [out]
>                 ready => ready_s);    -- [out]
>
>
>  -- Mike Treseler
>

Thank you for your answer....
The main question is, when phy_1 is instanciated into vhdl testbench, how
to call the task defined inside the module??? 
I haven't tried till now something like this...suppose module PHY has a
task defined blabla...how can I call it???
simply blabla
or phy_1.blabla
or it is not possible....

Thank you for help...
Carlo

	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 151922
Subject: Re: verilog task and vhdl
From: Mike Treseler <mtreseler@gmail.com>
Date: Sat, 04 Jun 2011 09:43:23 -0700
Links: << >>  << T >>  << A >>

>> I suggest a direct instance - no component,
>> Something like:
>>
>>        phy_1 : entity work.phy
>>        port map (reset =>  reset_s,     -- [in]
>>                  clock =>  clock_s,     -- [in]
>>                  data  =>  data_s,      -- [out]
>>                  ready =>  ready_s);    -- [out]
>>
>>
>>   -- Mike Treseler
>>
On 6/3/2011 1:48 PM, carlob wrote:

> Thank you for your answer....
> The main question is, when phy_1 is instantiated into vhdl testbench, how
> to call the task defined inside the module???

I the instanced task can only be called from inside the module.
A test task would have to be declared in the testbench.

             -- Mike Treseler


Article: 151923
Subject: Re: verilog task and vhdl
From: "carlob" <carlo.beccia@n_o_s_p_a_m.n_o_s_p_a_m.libero.it>
Date: Sat, 04 Jun 2011 15:23:29 -0500
Links: << >>  << T >>  << A >>

>I the instanced task can only be called from inside the module.
>A test task would have to be declared in the testbench.
>
>             -- Mike Treseler
>
>

On the internet I read about writing a verilog wrapper that trigger tasks
using its input signals....then instanciate that wrapper into vhdl
testbench and move tasks by triggering signals....

Otherwise...I should write the testbench in verilog....

Another question is...I use modelsim...is there any issue related to mixed
language (vhdl-verilog) simulation that must be considered....
It should be useful to know it before starting....

Thank you for help...
Carlo	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 151924
Subject: Re: Looking for bitgen Virtex7 and Kintex7 support
From: Neil Steiner <neil.steiner@isi.edu>
Date: Sat, 04 Jun 2011 17:22:31 -0400
Links: << >>  << T >>  << A >>
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
<html>
<head>
  <meta content="text/html; charset=ISO-8859-1"
 http-equiv="Content-Type">
</head>
<body bgcolor="#ffffff" text="#000000">
<br>
<blockquote cite="mid:64udnSvExbvosHTQnZ2dnUVZ_uKdnZ2d@giganews.com"
 type="cite">
  <pre wrap="">Have you managed to build yourself a Virtex 7?
  </pre>
</blockquote>
<br>
No, I don't actually have a Virtex7!&nbsp; I'm just trying to wrap Virtex7
and Kintex7 support into <a href="http://torc.isi.edu">Torc</a> from
information in the "7 Series FPGA Configuration" guide (<a
 href="http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf">UG470</a>).&nbsp;
We develop our code primarily from the user guides, but need actual
bitstreams for sanity checks and unit tests.<br>
<br>
</body>
</html>



Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search