Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi, I have prepared a heap-sorter implementation for FPGA. The sources are licensed under the BSD license and are available at alt.sources group. Due to the fact, that I'm on my holidays, I was not able to post the standard shar archive, and instead I have finally to send the uuencoded tar.bz archive. You can find it at: http://groups.google.com/group/alt.sources/msg/ab4bda56ca52cc59?dmode=source (copy the body of the message to the file, then run "uudecode" on this file, and you'll get sorter.tar.bz2 archive). The sorter is able to sort one data record every 2 clock pulses. I was able to compile into Virtex-6 XC6VLX75T-3FF484 a sorter with capacity of 65535 records (able to sort the data stream with maximum distance between unsorted records equal to 65535) with each record containing 18 bits of time-stamp and 20 bits of payload. More information is available at the beginning of my alt.sources post. The current sources will be available (a little later) at http://www.ise.pw.edu.pl/~wzab/fpga_heapsort -- HTH & Best regards, Wojtek ZabolotnyArticle: 152126
Hi, I have prepared a heap-sorter implementation for FPGA. The sources are licensed under the BSD license and are available at alt.sources group. Due to the fact, that I'm on my holidays, I was not able to post the standard shar archive, and instead I have finally to send the uuencoded tar.bz archive. You can find it at: http://groups.google.com/group/alt.sources/msg/ab4bda56ca52cc59?dmode=source (copy the body of the message to the file, then run "uudecode" on this file, and you'll get sorter.tar.bz2 archive). The sorter is able to sort one data record every 2 clock pulses. I was able to compile into Virtex-6 XC6VLX75T-3FF484 a sorter with capacity of 65535 records (able to sort the data stream with maximum distance between unsorted records equal to 65535) with each record containing 18 bits of time-stamp and 20 bits of payload. More information is available at the beginning of my alt.sources post. The current sources will be available (a little later) at http://www.ise.pw.edu.pl/~wzab/fpga_heapsort -- HTH & Best regards, Wojtek ZabolotnyArticle: 152127
Ooops, sorry for repeated post. I have now only GPRS access to the network, and all my network related programs started to work in a crazy way :-(. -- Regards, WojtekArticle: 152128
On Jul 11, 10:22=A0am, Jon Elson <el...@pico-systems.com> wrote:
> Jon Elson wrote:
>
> Well, I changed it over to unsigned, but I still ended up with
> more or clauses than I think should be needed. =A0Anyway, it seems
> to be working correctly now.
A quadrant test can be efficient in Logic, but I'm not sure it meets
your condition of always taking the shortest path ?
If the quadrants are opposite, you could take over 128 clocks ?
So I quickly tried some unsigned maths algorithms, which leads to
firstly this in Basic Scripts (Vars are all Unsigned Bytes)
If uAp =3D uBp Then
exit Function
Else
Diff =3D uAp - uBp
if uAp > uBp Then
If Diff < 128 Then ' closer than 128, so INC uB
uBp =3D uBp+1
Else ' go the other way
uBp =3D uBp-1
End If
Else ' uAp < uBp , so Diff has wrapped
If Diff >=3D 128 Then ' Wrapped, closer than 128, so DEC uB
uBp =3D uBp-1
Else ' go the other way
uBp =3D uBp+1
End If
End If
End If
then I spotted that seems to be
If uAp =3D uBp Then
exit Function
Else
Diff =3D uAp - uBp
If Diff < 128 Then
uBp =3D uBp+1
Else
uBp =3D uBp-1
End If
End If
and tested this does seem to chose the 'right' direction, and
converge with never more than 128 calls.
So your instincts were right.
The magic of unsigned maths ;)
Article: 152129Two new FPGA coprocessor modules released today. The initial availability will be modules based on a Xilinx Spartan-6 XC6SLX150 FPGA although we may offer these products with either a XC6SLX45 or XC6SLX75 options depending on demand. Both products have a battery slot to support bitstream encryption on Spartab-6 devices that support that feature. Both products are based on our simple DIL Header format (0.1 inch 2.54mm pitch) and can be either used as add-ons to simple circuit boards or as add-on capability to many of our existing development boards. The X1 Coprocessor consists of a single XC6SLX150 with 2 independent 1Gbit DDR memories supported using the hard core memory controllers of the Spartan-6. The module has features allowing remotely controlled reconfiguration and some I/O for data passing over single ended, or LVDS, I/O. The module also has on board regulators and can operate from a sinle 3.3V supply. Picture of this product http://enterpoint.co.uk/products/spartan-6-development-boards/xc6slx150-x1-coprocessor/. The X2 differs from the X2 in not supporting DDR3. This product does offer 2x XC6SLX150 FPGAs for a variety of HPC type applications. Remotely controlled reconfiguartion again is possible as is bitstream encryption. The X2 can run from either a single 3.3V supply or a dual 5V/3.3V feed for higher power applications. Picture of this product http://enterpoint.co.uk/products/spartan-6-development-boards/xc6slx150-x2/. Both products are immediately available in low numbers with larger numbers in 1-2 months time. John Adair Enterpoint Ltd.Article: 152130
Hi John > Is the limitation to *non-programmable* hardware merely a technical > limitation, or is it a license restriction? I would say that is only a matter of engineering to interface the produced hardware by HercuLeS to programmable platforms as coprocessors. This should be the straightforward way of applying this approach to a programmable context. Currently, I haven't developed any wrappers for the produced hardware to interface e.g. to popular FPGA soft-cores. > For example, could one use it to design a microprocessor by simply > excluding the RAM from the C program, and then adding a bit of hand- > written RTL VHDL to the output to add in the programmability? Ultimately, the overall infrastructure could be used for producing an application-specific processor from scratch. This would require a "skeleton" processor to whom the added functionalities should be attached. A previous effort of mine was the ByoRISC processor which is a configurable ASIP: Demo simulator: http://www.nkavvadias.com/misc/byorisc-demo-0.0.1.zip Paper: http://www.nkavvadias.com/publications/kavvadias_vlsisoc08.pdf This approach also has some serious problems, mainly the automatic generation of complete software development toolset, especially the regarding the compiler and the libraries. Probably I wouldn't take this approach. So HercuLeS infrastructure can take account of these issues (of non- programmability) so that targeting third-party programmable platforms does not meet serious technical limitations. Best regards, Nikolaos KavvadiasArticle: 152131
On Jul 12, 5:41=A0am, Nikolaos Kavvadias <nikolaos.kavvad...@gmail.com> wrote: > Currently, I haven't developed any wrappers for the produced hardware > to interface e.g. to popular FPGA soft-cores. Ah. But that's a different question. I hadn't expected it to do _that_, because there already exists software to take VHDL or Verilog, and compile it into a program for an FPGA. My concern was for the thing described by the C code being read, and translated to VHDL, describing a programmable object instead of a non- programmable one. John SavardArticle: 152132
Hi John > My concern was for the thing described by the C code being read, and > translated to VHDL, describing a programmable object instead of a non- > programmable one. a ByoRISC is a programmable object (since it is a soft-core microprocessor), but then mapping a NAC program to its assembly is a trivial backend matter. You seem to refer to something else. Do you have anything specific in mind when you refer to a "programmable object"? Best regards, Nikolaos KavvadiasArticle: 152133
John Adair wrote: > Two new FPGA coprocessor modules released today. The initial > availability will be modules based on a Xilinx Spartan-6 XC6SLX150 > FPGA although we may offer these products with either a XC6SLX45 or > XC6SLX75 options depending on demand. Both products have a battery > slot to support bitstream encryption on Spartab-6 devices that support > that feature. Both products are based on our simple DIL Header format > (0.1 inch 2.54mm pitch) and can be either used as add-ons to simple > circuit boards or as add-on capability to many of our existing > development boards. > > The X1 Coprocessor consists of a single XC6SLX150 with 2 independent > 1Gbit DDR memories supported using the hard core memory controllers of > the Spartan-6. The module has features allowing remotely controlled > reconfiguration and some I/O for data passing over single ended, or > LVDS, I/O. The module also has on board regulators and can operate > from a sinle 3.3V supply. Picture of this product > http://enterpoint.co.uk/products/spartan-6-development-boards/xc6slx150-x1-coprocessor/. > > The X2 differs from the X2 in not supporting DDR3. This product does > offer 2x XC6SLX150 FPGAs for a variety of HPC type applications. > Remotely controlled reconfiguartion again is possible as is bitstream > encryption. The X2 can run from either a single 3.3V supply or a dual > 5V/3.3V feed for higher power applications. Picture of this product > http://enterpoint.co.uk/products/spartan-6-development-boards/xc6slx150-x2/. > > Both products are immediately available in low numbers with larger > numbers in 1-2 months time. > > John Adair > Enterpoint Ltd. Very nice... I didn't see a product brief or data sheet. Can you tell me how many I/O's are available on the DIL pins? Regards, GaborArticle: 152134
On Jul 12, 10:23=A0am, Nikolaos Kavvadias <nikolaos.kavvad...@gmail.com> wrote: > Do you have anything specific in mind when you refer to a > "programmable object"? I was wondering if, despite the limitation you cited, whether your tool might still be useful in generating VHDL for a microprocessor, since many major components of a microprocessor are not programmable in themselves. John SavardArticle: 152135
Hi quadibloc > I was wondering if, despite the limitation you cited, whether your > tool might still be useful in generating VHDL for a microprocessor, > since many major components of a microprocessor are not programmable > in themselves. In principle, yes! The hardware that is now produced follows the FSMD (Finite-State Machine with Datapath) model of computation. It is known that there is a strong relation between FSMD and implementing a microprocessor ISA. A relevant work that clearly discusses the equivalence of these two MoCs is: "A Unified Formal Model of ISA and FSMD" with direct link here: http://www.cs.york.ac.uk/rts/docs/SIGDA-Compendium-1994-2004/papers/1999/codes99/pdffiles/5_1.pdf sets this relation in a formal basis. However, the FSMD and ISA models have different structures (as also noted in the above work). For deriving an ISA (microprocessor) model from a N-Address Code program the following would be required: 1) Identify the distinct operations required to be supported by the microprocessor by static analysis of the NAC program. 2) Implement computational "states" for each one of the operations (this assumes naive, sequential scheduling of work). One could do better in terms of performance, by grouping more operations in a single state and calling this group an "instruction". 3) Map the NAC program to e.g. a microprogram store. 4) You need a skeleton microprocessor that allows modifications, e.g. removing and adding computational states and their respective functional units at design compile time. That is all that is required. AFAICS the current infrastructure would not demand extensive changes. Best regards, Nikolaos KavvadiasArticle: 152136
Hi. I'm just beginner in making fpga and i want to make MIPI CSI-2 to parallel converter in fpga. i think there are strange point. in mipi spec, there are two mode, LP and HS mode, and these are very different. how can i connect mipi p/n pins to fpga?Article: 152137
I'm looking for a FPGA OEM module for analog signal processing which contains the following: - medium size spartan 3 or spartan 6 FPGA - 2 ADCs, sampling rate > 50 MHz, at least 14 (better 16) bit resolution - 2 DACs, sampling rate > 50 MHz, 16 bit resolution - plus quite some digital I/O lines - on-board memory would be a plus, but it is not required Does such a board exist in the price range up to 500 USD? Thanks, ThomasArticle: 152138
The XC6SLX150 X1 module has 32 single ended or 16 LVDS pairs of general I/O. The rest of the pins are external programming interface and power. The XC6SLX150 X2 has 20 single ended or 10 LVDS pairs of general I/O per FPGA. The balance are programming interface, power and 8 pins that go to the control CPLD that is on-board. The later can be used for a range of options including driving the onboard JTAG chain or forcing and controlling a reconfiguration etc.. Between the FPGAs there is 38 I/O connections. If you are looking for an I/O rich solution for adding to your PCB these probably are not the best products for those applications. These are really aimed at reconfigurable computing or HPC applications and biggest use will be as add-ons to our existing development boards. Do have a look at our existing Craignell2-48 (46 I/O), Darnaw1 (219 I/O) products for the PCB add-on requirement. Not well known but we also sell our Prog4 cable board as a stand alone board offering I/O on a USB interface. It has a Spartan-3 50AN on it for simple applications. There will also be a Darnaw2 module for high I/O apps. This is based on Spartan-6 but no dates for this yet. That really depends on our highly loaded design team having some spare time just to do it. We should be adding some more information to the website in the next few days. Probably the schematic and a feature list initially but other things like CPLD source code as well for the X2 will appear in a few weeks. We have some basic builds for this already but they need to be combined properly for customer use. John Adair Enterpoint Ltd. On Jul 12, 9:32=A0pm, Gabor <ga...@szakacs.invalid> wrote: > John Adair wrote: > > Two new FPGA coprocessor modules released today. The initial > > availability will be modules based on a Xilinx Spartan-6 XC6SLX150 > > FPGA although we may offer these products with either a XC6SLX45 or > > XC6SLX75 options depending on demand. Both products have a battery > > slot to support bitstream encryption on Spartab-6 devices that support > > that feature. Both products are based on our simple DIL Header format > > (0.1 inch 2.54mm pitch) and can be either used as add-ons to simple > > circuit boards or as add-on capability to many of our existing > > development boards. > > > The X1 Coprocessor consists of a single XC6SLX150 with 2 independent > > 1Gbit DDR memories supported using the hard core memory controllers of > > the Spartan-6. The module has features allowing remotely controlled > > reconfiguration and some I/O for data passing over single ended, or > > LVDS, I/O. The module also has on board regulators and can operate > > from a sinle 3.3V supply. Picture of this product > >http://enterpoint.co.uk/products/spartan-6-development-boards/xc6slx1...= . > > > The X2 differs from the X2 in not supporting DDR3. This product does > > offer 2x XC6SLX150 FPGAs for a variety of HPC type applications. > > Remotely controlled reconfiguartion again is possible as is bitstream > > encryption. The X2 can run from either a single 3.3V supply or a dual > > 5V/3.3V feed for higher power applications. Picture of this product > >http://enterpoint.co.uk/products/spartan-6-development-boards/xc6slx1...= . > > > Both products are immediately available in low numbers with larger > > numbers in 1-2 months time. > > > John Adair > > Enterpoint Ltd. > > Very nice... =A0I didn't see a product brief or data sheet. =A0Can you te= ll > me how many I/O's are available on the DIL pins? > > Regards, > GaborArticle: 152139
Hi!
I wrote a custom IP peripheral in verilog and interfaced it to MicroBlaze,
using Harware>Co-processor option. I can see the peripheral connected on
the System Design Diagram.All compile and build is successful.
Now I can see on hyperterminal that data is being sent to FSL. But then it
gets stuck, there is no return of data from FSL.
I will paste both my Microblaze C code and Verilog code. kinldy guide me if
there is a problem in my program or a any other problem.
This is C code Test_fsl.c
#include "xparameters.h"
#include "mb_interface.h"
#include "stdio.h"
#include "xutil.h"
#include "xdmacentral.h"
#include "xdmacentral_l.h"
#include "xgpio.h"
#include "fsl.h"
#include "xbasic_types.h"
int main (void)
{
// Printing a banner on the Hyper Terminal.
print("\t#########################################\n\r");
print("\t# #\n\r");
print("\t# FSL Channel Reference Design #\n\r");
print("\t# MicroBlaze Development Board #\n\r");
print("\t# #\n\r");
print("\t#########################################\n\r");
print("\n\r\n\r");
print("-- Entering main() --\r\n");
int i;
Xuint32 arr[64];
for(i=0;i<64;i=i+1){
putfsl(i,0);
xil_printf("\t--Sent Number--%d\n\r",i);
}
for(i=0;i<64;i=i+1){
getfsl(i,0);
xil_printf("\t--Received Number--%d\n\r",i);
}
for(i=0;i<64;i=i+1)
xil_printf("\r\n 0x%x",arr[i]);
print("-- Exiting main() --\r\n");
// Printing a banner on the Hyper Terminal.
print("\t#########################################\n\r");
print("\t# #\n\r");
print("\t# FSL Channel Reference Design #\n\r");
print("\t# finished successfully #\n\r");
print("\t# #\n\r");
print("\t#########################################\n\r");
print("\n\r\n\r");
return 0;
}
My verilog custom IP perpheral code is :
//----------------------------------------------------------------------------
// video - module
//----------------------------------------------------------------------------
// IMPORTANT:
// DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
//
// SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
//
// TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
// PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
// OF THE USER_LOGIC ENTITY.
//----------------------------------------------------------------------------
//
//
***************************************************************************
// ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
**
// **
**
// ** Xilinx, Inc.
**
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
**
// ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
**
// ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
**
// ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
**
// ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
**
// ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
**
// ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
**
// ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
**
// ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
**
// ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
**
// ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
**
// ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
**
// ** FOR A PARTICULAR PURPOSE.
**
// **
**
//
***************************************************************************
//
//----------------------------------------------------------------------------
// Filename: video
// Version: 1.00.a
// Description: Example FSL core (Verilog).
// Date: Tue Jul 12 10:03:57 2011 (by Create and Import
Peripheral Wizard)
// Verilog Standard: Verilog-2001
//----------------------------------------------------------------------------
// Naming Conventions:
// active low signals: "*_n"
// clock signals: "clk", "clk_div#", "clk_#x"
// reset signals: "rst", "rst_n"
// generics: "C_*"
// user defined types: "*_TYPE"
// state machine next state: "*_ns"
// state machine current state: "*_cs"
// combinatorial signals: "*_com"
// pipelined or register delay signals: "*_d#"
// counter signals: "*cnt*"
// clock enable signals: "*_ce"
// internal version of output port: "*_i"
// device pins: "*_pin"
// ports: "- Names begin with Uppercase"
// processes: "*_PROCESS"
// component instantiations: "<ENTITY_>I_<#|FUNC>"
//----------------------------------------------------------------------------
////////////////////////////////////////////////////////////////////////////////
//
//
// Definition of Ports
// FSL_Clk : Synchronous clock
// FSL_Rst : System reset, should always come from FSL bus
// FSL_S_Clk : Slave asynchronous clock
// FSL_S_Read : Read signal, requiring next available input to be
read
// FSL_S_Data : Input data
// FSL_S_Control : Control Bit, indicating the input data are control
word
// FSL_S_Exists : Data Exist Bit, indicating data exist in the input FSL
bus
// FSL_M_Clk : Master asynchronous clock
// FSL_M_Write : Write signal, enabling writing to output FSL bus
// FSL_M_Data : Output data
// FSL_M_Control : Control Bit, indicating the output data are contol
word
// FSL_M_Full : Full Bit, indicating output FSL bus is full
//
////////////////////////////////////////////////////////////////////////////////
//----------------------------------------
// Module Section
//----------------------------------------
module video
(
// ADD USER PORTS BELOW THIS LINE
// -- USER ports added here
// ADD USER PORTS ABOVE THIS LINE
// DO NOT EDIT BELOW THIS LINE ////////////////////
// Bus protocol ports, do not add or delete.
FSL_Clk,
FSL_Rst,
FSL_S_Clk,
FSL_S_Read,
FSL_S_Data,
FSL_S_Control,
FSL_S_Exists,
FSL_M_Clk,
FSL_M_Write,
FSL_M_Data,
FSL_M_Control,
FSL_M_Full
// DO NOT EDIT ABOVE THIS LINE ////////////////////
);
// ADD USER PORTS BELOW THIS LINE
// -- USER ports added here
// ADD USER PORTS ABOVE THIS LINE
input FSL_Clk;
input FSL_Rst;
output FSL_S_Clk;
output FSL_S_Read;
input [0 : 31] FSL_S_Data;
input FSL_S_Control;
input FSL_S_Exists;
output FSL_M_Clk;
output FSL_M_Write;
output [0 : 31] FSL_M_Data;
output FSL_M_Control;
input FSL_M_Full;
// ADD USER PARAMETERS BELOW THIS LINE
// --USER parameters added here
// ADD USER PARAMETERS ABOVE THIS LINE
//----------------------------------------
// Implementation Section
//----------------------------------------
// In this section, we povide an example implementation of MODULE video
// that does the following:
//
// 1. Read all inputs
// 2. Add each input to the contents of register 'sum' which
// acts as an accumulator
// 3. After all the inputs have been read, write out the
// content of 'sum' into the output FSL bus NUMBER_OF_OUTPUT_WORDS
times
//
// You will need to modify this example for
// MODULE video to implement your coprocessor
// Total number of input data.
localparam NUMBER_OF_INPUT_WORDS = 64;
// Total number of output data
localparam NUMBER_OF_OUTPUT_WORDS = 64;
// Define the states of state machine
localparam Idle = 3'b100;
localparam Read_Inputs = 3'b010;
localparam Write_Outputs = 3'b001;
reg [0:2] state;
// Accumulator to hold sum of inputs read at any point in time
reg [0:31] sum;
// Counters to store the number inputs read & outputs written
reg [0:NUMBER_OF_INPUT_WORDS - 1] nr_of_reads;
reg [0:NUMBER_OF_OUTPUT_WORDS - 1] nr_of_writes;
// CAUTION:
// The sequence in which data are read in should be
// consistent with the sequence they are written in the
// driver's video.c file
assign FSL_S_Read = (state == Read_Inputs) ? FSL_S_Exists : 0;
assign FSL_M_Write = (state == Write_Outputs) ? ~FSL_M_Full : 0;
assign FSL_M_Data = sum;
always @(posedge FSL_Clk)
begin // process The_SW_accelerator
if (FSL_Rst) // Synchronous reset (active high)
begin
// CAUTION: make sure your reset polarity is consistent with
the
// system reset polarity
state <= Idle;
nr_of_reads <= 0;
nr_of_writes <= 0;
sum <= 0;
end
else
case (state)
Idle:
if (FSL_S_Exists == 1)
begin
state <= Read_Inputs;
nr_of_reads <= NUMBER_OF_INPUT_WORDS - 1;
sum <= 0;
end
Read_Inputs:
if (FSL_S_Exists == 1)
begin
// Coprocessor function (Adding) happens here
sum <= sum + FSL_S_Data;
if (nr_of_reads == 0)
begin
state <= Write_Outputs;
nr_of_writes <= NUMBER_OF_OUTPUT_WORDS - 1;
end
else
nr_of_reads <= nr_of_reads - 1;
end
Write_Outputs:
if (nr_of_writes == 0)
state <= Idle;
else
if (FSL_M_Full == 0) nr_of_writes <= nr_of_writes - 1;
endcase
end
endmodule
Kindly Guide.
---------------------------------------
Posted through http://www.FPGARelated.com
Article: 152140Did it work when you simulated it? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 152141
>I'm looking for a FPGA OEM module for analog signal processing .. Analog(ue) signal process normally involves a lot of Op Amps from which filters, multipliers, differentiators, integrators and similar can be constructed. No ADCs or DACs. If you want to do digital signal processing, an FPGA with a lot of MAC blocks (such as the DSP48 in Xilinx FPGAs) is what you will need. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 152142
Am 13.07.2011 08:50, schrieb Thomas Heller: > I'm looking for a FPGA OEM module for analog signal processing > which contains the following: > > - medium size spartan 3 or spartan 6 FPGA > - 2 ADCs, sampling rate > 50 MHz, at least 14 (better 16) bit resolution > - 2 DACs, sampling rate > 50 MHz, 16 bit resolution > - plus quite some digital I/O lines > - on-board memory would be a plus, but it is not required > > Does such a board exist in the price range up to 500 USD? > Am 13.07.2011 11:44, schrieb RCIngham: >> Analog(ue) signal process normally involves a lot of Op Amps from which >> filters, multipliers, differentiators, integrators and similar can be >> constructed. No ADCs or DACs. >> >> If you want to do digital signal processing, an FPGA with a lot of MAC >> blocks (such as the DSP48 in Xilinx FPGAs) is what you will need. Of course I meant digital signal processing ;-). That is the point of the ADCs and DACs connected to the FPGA.Article: 152143
Dr. Kavvadias <nikolaos.kavvadias@gmail.com> sent on July 11th, 2011: |----------------------------------------------------------| |"[..] | | | |You can [..] code your input [..] in a bit-accurate typed-| |assembly language called NAC (N-Address Code). [..] | |[..] | | | |[..]" | |----------------------------------------------------------| Ah, strongly typed assembly languages. One does not see many of those.Article: 152144
If it's a one off then probably not. But of it is anything more e.g. for an OEM manufacturing cycle we might be able to do something. We are working on a few things like this. John Adair Enterpoint Ltd. On Jul 13, 7:50=A0am, Thomas Heller <thel...@ctypes.org> wrote: > I'm looking for a FPGA OEM module for analog signal processing > which contains the following: > > - medium size spartan 3 or spartan 6 FPGA > - 2 ADCs, sampling rate > 50 MHz, at least 14 (better 16) bit resolution > - 2 DACs, sampling rate > 50 MHz, 16 bit resolution > - plus quite some digital I/O lines > - on-board memory would be a plus, but it is not required > > Does such a board exist in the price range up to 500 USD? > > Thanks, > ThomasArticle: 152145
On 07/12/2011 11:50 PM, Thomas Heller wrote: > I'm looking for a FPGA OEM module for analog signal processing > which contains the following: > > - medium size spartan 3 or spartan 6 FPGA > - 2 ADCs, sampling rate > 50 MHz, at least 14 (better 16) bit resolution > - 2 DACs, sampling rate > 50 MHz, 16 bit resolution > - plus quite some digital I/O lines > - on-board memory would be a plus, but it is not required > > Does such a board exist in the price range up to 500 USD? _Dig_ through Xilinx's and Avnet's web pages. The last time I did real FPGA design Xilinx pointed you to Avnet for a Spartan 6 board, and that board had a dock for a daughter card, and Avnet had a _bazillion_ daughter cards. A daughter card with ADC and DAC would be a no-brainer. At the speeds you're looking for, you should probably stick the keyword "video" into your search terms, look carefully at the data conversion hardware to make sure it isn't specific to some video mode, and make sure you're sitting down when you look at the price. Here: this only misses your target price by a factor of 8: http://www.xilinx.com/products/boards-and-kits/AES-V6DSP-LX240T-G.htm. This one is well within your price range, but I didn't look to see how fast the data conversion is: http://www.xilinx.com/products/boards-and-kits/HW-SPAR3A-SK-UNI-G.htm You get the idea. Good luck. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 152146
Nicholas Collin Paul de Glouceſter wrote: > Dr. Kavvadias<nikolaos.kavvadias@gmail.com> sent on July 11th, 2011: > |----------------------------------------------------------| > |"[..] | > | | > |You can [..] code your input [..] in a bit-accurate typed-| > |assembly language called NAC (N-Address Code). [..] | > |[..] | > | | > |[..]" | > |----------------------------------------------------------| > > > Ah, strongly typed assembly languages. One does not see many of > those. You do if you are assembling hardware :)Article: 152147
Hi > > Ah, strongly typed assembly languages. One does not see many of > > those. > > You do if you are assembling hardware :) Yes, bit-accurate, strongly-typed (generic) assembly languages is the way to go as an intermediate representation especially for hardware compilation. It provides some other benefits for the infrastructure in the long term. I decided to develop and extend an extremely lightweight typed- assembly language (called NAC), to keep all the infrastructure light and manageable by a single person. It certainly is manageable at the present time. Best regards, Nikolaos KavvadiasArticle: 152148
On 13 Jul., 11:44, "RCIngham" <robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > Analog(ue) signal process normally involves a lot of Op Amps from which > filters, multipliers, differentiators, integrators and similar can be > constructed. No ADCs or DACs. This is an ambiguity in english language. Analog signal processing could be: a) analog processing of a signal b) processing of an analog signal b) can be performed by digitization followed by digital processing The standard example of this language construct is the "german prisoner of war camp", where you can't tell whether the prisoners or the guards are german. KoljaArticle: 152149
You would probably be best just to buy a card with an FMC connector and develop your own daughter board. Jon --------------------------------------- Posted through http://www.FPGARelated.com
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z