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>Did it work when you simulated it? > > >--------------------------------------- >Posted through http://www.FPGARelated.com > Well i did not simulate it did not know how to. But on the hyper terminal i could see the sent number being printed after the putfsl command. But there was no return of data. ad the numbers where not getting printed as commanded after getfsl command. So it was assumed there was some problem. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 152151
>>Did it work when you simulated it? >> > >Well i did not simulate it did not know how to. But on the hyper terminal i >could see the sent number being printed after the putfsl command. But there >was no return of data. ad the numbers where not getting printed as >commanded after getfsl command. So it was assumed there was some problem. > Clearly there is a problem. It might be: (a) FPGA firmware. (b) FPGA software. (c) FPGA implementation (P&R or similar). (d) PC. (e) other... Your problem report does not eliminat any of these areas. If it works in simulation, then (a) and (b) are eliminated. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 152152
> - medium size spartan 3 or spartan 6 FPGA > - 2 ADCs, sampling rate > 50 MHz, at least 14 (better 16) bit resolution > - 2 DACs, sampling rate > 50 MHz, 16 bit resolution > - plus quite some digital I/O lines > - on-board memory would be a plus, but it is not required Check terasic: http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=73&No=278&PartNo=1 or http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=73&No=360&PartNo=1 then any development kit which You like and can afford from Altera, which has HSMC connector.Article: 152153
Kolja Sulimma <ksulimma@googlemail.com> wrote: >On 13 Jul., 11:44, "RCIngham" ><robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > >> Analog(ue) signal process normally involves a lot of Op Amps from which >> filters, multipliers, differentiators, integrators and similar can be >> constructed. No ADCs or DACs. > >This is an ambiguity in english language. Analog signal processing >could be: >a) analog processing of a signal >b) processing of an analog signal > >b) can be performed by digitization followed by digital processing > >The standard example of this language construct is the "german >prisoner of war camp", >where you can't tell whether the prisoners or the guards are german. Which is why they invented context. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 152154
On 2011-06-22, chifalcon <eric.he@n_o_s_p_a_m.n_o_s_p_a_m.hotmail.com> wrote: > Hi, > I need to modify the netlist generated from "Generate Post-map simulation > model"(i.e. netgen). > > After the netlist modifcation, can I continue the work of place&route > based on the modified simulation model netlist? As the other posters have already said, it is not really possible to do what you are asking. However, you can do something similar by modifying the post map NCD file. The key is to convert the NCD file into ASCII format in the form of an XDL netlist. You can do this using the xdl command from xilinx with the -ncd2xdl and -xdl2ncd switches. Another way of doing this is to open the mapped NCD file in the FPGA editor and create a script that does the modification. Then you can use fpga_edline to execute the script in batch mode. I wouldn't recommend this though unless you have some really good reason for doing this. The main use case I've seen so far is to merge debug tools such as a logic analyzer into the design after synthesis is complete so that you don't need to rerun synthesis every time you wish to connect different signals to your logic analyzer. (In previous versions of ISE it was actually possible to do this kind of merging after place and route, but I haven't found a good way of doing this in newer versions of ISE. [1]) regards /Andreas [1] In earlier versions you could give a partially routed NCD file to par and tell it to just route the remaining wires. This does not seem possible to do any longer unfortunately...Article: 152155
Hi! Can anyone prompt me what is potential benefit of using of auto-sequencing memory (ASM) instead of standard static RAM? The final interest is ASIC – die size and power dissipation. I’m sorry if my question is stupid, but I have no experience in FPGA and ASIC design. A bit more info: The project will include a number of memory blocks, where each block contains 1023x10 bits, one read port and one write port. All access operations (better to say - cycles) are performed consecutively and go through the whole memory block from its beginning to the end. I believe that use of auto-sequencing memory allows to save lots of resources. Am I correct? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 152156
Hi, I am using a custom board design in which i have 2 FPGAs (spartan 3 xc3s4000) and an EEPROM xcf16p daisy chained together. The chain is like this: EEPROM -> FPGA1 -> FPGA2 Now the problem is that when i try to program the FPGA using JTAG, my DONE goes high, INIT_B stays high and PROG_B stays high after config, iMPACT says program succeeded but FPGA doesn't work. If i run chipscope, it says 0 cores found. Same goes when i try to program FPGAs using EEPROM. I have tried in daisy chain and even programming the FPGAs individually by disconnecting them from the chain. Now there's another dynamic to this problem, i have a previously built .bit file, when i program the FPGAs using it, they get programmed. But if i try to program the FPGAs with any other .bit file, they don't. I am clueless now and i cannot find the problem. I need help here.. Thanks regards --------------------------------------- Posted through http://www.FPGARelated.comArticle: 152157
Am 13.07.2011 20:44, schrieb maxascent: > You would probably be best just to buy a card with an FMC connector and > develop your own daughter board. FMC, PMC, XMC, HSMC - a lot of 'standards'. However, this is one possibility. Thanks, ThomasArticle: 152158
Am 14.07.2011 14:03, schrieb scrts: >> - medium size spartan 3 or spartan 6 FPGA >> - 2 ADCs, sampling rate> 50 MHz, at least 14 (better 16) bit resolution >> - 2 DACs, sampling rate> 50 MHz, 16 bit resolution >> - plus quite some digital I/O lines >> - on-board memory would be a plus, but it is not required > > Check terasic: > http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=73&No=278&PartNo=1 > or > http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=73&No=360&PartNo=1 > > then any development kit which You like and can afford from Altera, which > has HSMC connector. > These add-on boards really look useful! Once I needed such a board several years ago, I bought an ADC evaluation board from linear technology, together with an so-called Fast DAAC evaluation kit, and modified them to support DC coupling, direct access to the build-in FPGA, and added a DAC myself as you can see in this photo (the dac in on the solder side of the board): http://starship.python.net/crew/theller/IMG_20110714_092433.jpg It was quite some work but worked fine in the end, but I would try to avoid this 'hack' in the future. I found another thing that seems exactly what I need, and it is only 3 times the price that I had in mind (I must admit that my price expectations were somewhat naive): USRP 200N from ettus research LLC: around 1500$, Spartan 3A DSP FPGA, dual 100 MS/s 14 bit ADC, dual 400 MS/s 16-bit DAC, DC coupled, 30 MHz Bandwidth, ... http://www.ettus.com/products Thanks again, ThomasArticle: 152159
It's been a while since I have said this in public but we are recruiting again for our UK office. Details on http://www.enterpoint.co.uk/careers/job14072011.html. This one covers a pile of skill bases and open to anyone with a right to work in the EEC. John Adair Enterpoint Ltd.Article: 152160
Michael S wrote: > glen herrmannsfeldt wrote: >> How about 1uHz? (or 1nHz or 1pHz?) >> ... >> For 1uHz, R=1Mohm, C=1F. That isn't easy, even with an external >> capacitor! >... >I can imagine the utility of 1mHz, may be, even 0.1 mHz in some >extreme cases where you want to take a deep thought between the >clocks. But 1uHz? Can't see how it helps debugging. Reading 1uHZ as "full stop",... A few geological ages ago, I was debugging a quite complex system based on a Z80 CPU (Fully static design) Things like an ICE or logic analyzer were luxuries not available to me, so I had to improvise. One of the things I did was to hook up a couple of logical gates and a flip-flop between the RD & WR lines and the WAIT lines, forcing the CPU into wait state each time it tried to access the bus. The address and data lines were connected to 3 x 8-bit buffers, multiplexing the 24 bits into a single 8-bit lane. That lane plus a few control lines went to a CP/M computer printer port, where an interpreted BASIC program read the data and then toggled the flip-flop allowing the Z80 to do one more memory cycle. The basic program would disassemble the current operation and, if it involved an external memory transfer show exactly what was being read/written and where Voila! With an investment of a few hours of work I had a system that allowed me to fully trace the program flow and memory access. Could have any number of breakpoints (just keep toggling the flip-flop until reaching a given address, then stop for manual control), count the number of times a branch was taken, etc. Everything in slow motion, of course, but the information I gathered was not available otherwise. I was forcing wait states, but could have accomplished the same thing gating the CPU clock. Either technique would have been impossible with chips like the 6800/6502 that would loose state if the clock was below a certain minimum frequency, and that could not be kept in wait state for more than a few microseconds. You can not do the same with a modern controller with on-chip memory, etc. but still, slowing down the processor so that you can, for example, check the state of 10 GPIO pins with your 2-channel scope, is a very valuable feature.Article: 152161
> Once I needed such a board several years ago, I bought an ADC > evaluation board from linear technology, together with an so-called > Fast DAAC evaluation kit, and modified them to support DC coupling, > direct access to the build-in FPGA, and added a DAC myself as you > can see in this photo (the dac in on the solder side of the board): > > http://starship.python.net/crew/theller/IMG_20110714_092433.jpg Maybe You're interested in software defined radio? I've got Stratix II GX devkit, so I'm also searching for good addon board with fast ADCs and DACs. That's why I've stopped at terasic site. Basically, now I am on the crossroad to buy a manufactured board or do my own. I have a hope to run four separate ADCs, each sampled from the same clock source, but +90deg phase. I am not sure if this approach would be correct. Just brainstorming now :)Article: 152162
http://wavedrom.googlecode.com WaveDrom is Free and Open Source online digital timing diagram editor that uses JavaScript?, HTML5 and SVG to render WaveJSON input text description into vector graphics. The project is in progress. Any feedback appreciated.Article: 152163
On 07/14/2011 05:01 PM, scrts wrote: >> Once I needed such a board several years ago, I bought an ADC >> evaluation board from linear technology, together with an so-called >> Fast DAAC evaluation kit, and modified them to support DC coupling, >> direct access to the build-in FPGA, and added a DAC myself as you >> can see in this photo (the dac in on the solder side of the board): >> >> http://starship.python.net/crew/theller/IMG_20110714_092433.jpg > > Maybe You're interested in software defined radio? I've got Stratix II GX > devkit, so I'm also searching for good addon board with fast ADCs and DACs. > That's why I've stopped at terasic site. Basically, now I am on the > crossroad to buy a manufactured board or do my own. I have a hope to run > four separate ADCs, each sampled from the same clock source, but +90deg > phase. I am not sure if this approach would be correct. Just brainstorming > now :) If you're looking for a way to get quadrature demodulation when you can't get a fast enough ADC, that is certainly theoretically correct. You run into problems with mismatch between the ADCs, though. With one fast ADC it's safe to assume that the sampling delay, offset, &c. of each "channel" is the same -- because it's all measured from the same ADC. You can't assume that when it's four ADCs, so you end up with offsets and phase shifts in your demodulated data. And no, I don't know how much -- run the numbers yourself!! -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 152164
On Thu, 14 Jul 2011 13:14:50 -0500, dragonfly wrote: > Hi! > > Can anyone prompt me what is potential benefit of using of > auto-sequencing memory (ASM) instead of standard static RAM? The final > interest is ASIC – die size and power dissipation. I’m sorry if my > question is stupid, but I have no experience in FPGA and ASIC design. > > A bit more info: The project will include a number of memory blocks, > where each block contains 1023x10 bits, one read port and one write > port. All access operations (better to say - cycles) are performed > consecutively and go through the whole memory block from its beginning > to the end. > > I believe that use of auto-sequencing memory allows to save lots of > resources. Am I correct? I think that would depend on the details of your ASM, including, but not limited to, whether or not your FPGA synthesis tools or ASIC foundry could implement it. It sounds like might want a good old shift register, which may well take fewer CLBs in an FPGA than the same amount of static RAM implemented the same way. But it probably wouldn't be smaller than a block of built-in RAM, which seems pretty prevalent in FPGA's today. Similarly, such a gizmo may save space in an ASIC vs. the same amount of RAM, but only if you compare apples to apples -- your ASIC vendor will have RAM blocks (both static and dynamic) that are hand-optimized. A hand-optimized ASM is probably going to be smaller than hand-optimized RAM, but if you just describe it in HDL and let the synthesizer loose on it, I doubt it'll be better than a RAM block and a sequencer. Unless your project has the market behind it to pay for that hand optimization, or unless your chip vendor has ASM blocks for you, I think pre-made RAM plus a sequencer is going to be the way to go. -- Tim Wescott Control system and signal processing consulting www.wescottdesign.comArticle: 152165
Am 15.07.2011 02:01, schrieb scrts: >> Once I needed such a board several years ago, I bought an ADC >> evaluation board from linear technology, together with an so-called >> Fast DAAC evaluation kit, and modified them to support DC coupling, >> direct access to the build-in FPGA, and added a DAC myself as you >> can see in this photo (the dac in on the solder side of the board): >> >> http://starship.python.net/crew/theller/IMG_20110714_092433.jpg > > Maybe You're interested in software defined radio? I've got Stratix II GX > devkit, so I'm also searching for good addon board with fast ADCs and DACs. > That's why I've stopped at terasic site. Basically, now I am on the > crossroad to buy a manufactured board or do my own. I have a hope to run > four separate ADCs, each sampled from the same clock source, but +90deg > phase. I am not sure if this approach would be correct. Just brainstorming > now :) > > No, I'm planning to build some kind of lock-in amplifier: Measure the amplitude and phase of a signal in the presence of lots of noise. Totally different application than software defined radio, but it seems I need the same hardware for that. ThomasArticle: 152166
On 15/07/2011 01:07, Andreas Ehliar wrote: > A long time ago there was a thread on comp.arch.fpga regarding how to > regularly print out some information about the simulation progress. > The thread was fairly short and no real progress was made to a solution > which was really satisfactory (at least not in my opinion). > > I revisited this topic today while waiting for a long simulation > and came up with a TCL script which will print out the following > info when run in Modelsim: > > *** SIMINFO: Simulator time is 272071220000 ps, real time is Thu Jul 14 11:05:57 PM CEST 2011 > *** SIMINFO: Simulation speed is about 2314451469 (simulated) ps per second > *** SIMINFO: Simulation has run for 13603561 clock cycles on /tb/clk > *** SIMINFO: Simulation is running at about 115722 (simulated) cycles per second > > This is nice when running a simulation in batch mode where it is not > possible to see the current time. I guess the script will also be > convenient when benchmarking a few different computers for use with > Modelsim since it will print out how fast the simulator is running. If you want to use it for benchmarking I would suggest to use the simstats command to extract the time rather than the Tcl wallclock which is obviously affected by other processes running on the computer. Apart from that nice :-) Hans www.ht-lab.com > > If you are interested you can download the script from my homepage: > http://www.da.isy.liu.se/~ehliar/stuff/dump_simstate.tcl > > And if you happen to notice some bug or figure out some way to > improve it, please let me know :) The script has been tested with > ModelSim SE-64 6.6 but it will hopefully work with some other > versions as well. (Let me know if it doesn't and I'll try to fix > it for at least semi-modern versions.) > > > By the way, if anyone happens to know how to ask Modelsim whether a > certain entity is a parameter I would be quite happy. > > I know how to use the examine commands to identify inputs, outputs, > inouts, and internal signals. I also know how to use the mem list > command to identify a memory. At this point I can eliminate most > other internal signals by using the find command, but this is quite > an ugly hack and there are probably other things which the find net > and find signal command will ignore besides parameters. > > regards > /AndreasArticle: 152167
Tim, thanks a lot! So, the most reliable way is to request a foundry about its RAM and ASM blocks in form of physical IP or macros (sorry my incompetence). But can you or anyone else tell me on behalf of the foundry what could be the answer? I mean, what could be approximate rate of RAM to ASM in terms of die size and so on? Just for sure - Am I correct that one logic cell (logic element) can hold 16 bits of a sequential shift register and thus to keep 1023x10 bits I need 1023*10/16=640 elemets as a margin? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 152168
> Hi, > I am using a custom board design in which i have 2 FPGAs (spartan 3 > xc3s4000) and an EEPROM xcf16p daisy chained together. The chain is like > this: > > EEPROM -> FPGA1 -> FPGA2 unless the 2 FPGAs are identical, the first problem I can see here is that XCF16P (16 MBit) is not big enough to store the configuration bits for both FPGAs (11,316,864bits) .. see page 86 of UG332Article: 152169
A long time ago there was a thread on comp.arch.fpga regarding how to regularly print out some information about the simulation progress. The thread was fairly short and no real progress was made to a solution which was really satisfactory (at least not in my opinion). I revisited this topic today while waiting for a long simulation and came up with a TCL script which will print out the following info when run in Modelsim: *** SIMINFO: Simulator time is 272071220000 ps, real time is Thu Jul 14 11:05:57 PM CEST 2011 *** SIMINFO: Simulation speed is about 2314451469 (simulated) ps per second *** SIMINFO: Simulation has run for 13603561 clock cycles on /tb/clk *** SIMINFO: Simulation is running at about 115722 (simulated) cycles per second This is nice when running a simulation in batch mode where it is not possible to see the current time. I guess the script will also be convenient when benchmarking a few different computers for use with Modelsim since it will print out how fast the simulator is running. If you are interested you can download the script from my homepage: http://www.da.isy.liu.se/~ehliar/stuff/dump_simstate.tcl And if you happen to notice some bug or figure out some way to improve it, please let me know :) The script has been tested with ModelSim SE-64 6.6 but it will hopefully work with some other versions as well. (Let me know if it doesn't and I'll try to fix it for at least semi-modern versions.) By the way, if anyone happens to know how to ask Modelsim whether a certain entity is a parameter I would be quite happy. I know how to use the examine commands to identify inputs, outputs, inouts, and internal signals. I also know how to use the mem list command to identify a memory. At this point I can eliminate most other internal signals by using the find command, but this is quite an ugly hack and there are probably other things which the find net and find signal command will ignore besides parameters. regards /AndreasArticle: 152170
In article <U4ydnRevfKpmUoLTnZ2dnUVZ_hOdnZ2d@web-ster.com>, Tim Wescott <tim@seemywebsite.com> writes: [4 channels offset by 90 degeres] >You run into problems with mismatch between the ADCs, though. With one >fast ADC it's safe to assume that the sampling delay, offset, &c. of >each "channel" is the same -- because it's all measured from the same >ADC. You can't assume that when it's four ADCs, so you end up with >offsets and phase shifts in your demodulated data. Can I correct for that by feeding in a clean signal, collecting a lot of data, and thinking about it? -- These are my opinions, not necessarily my employer's. I hate spam.Article: 152171
> If you're looking for a way to get quadrature demodulation when you can't > get a fast enough ADC, that is certainly theoretically correct. > > You run into problems with mismatch between the ADCs, though. With one > fast ADC it's safe to assume that the sampling delay, offset, &c. of each > "channel" is the same -- because it's all measured from the same ADC. You > can't assume that when it's four ADCs, so you end up with offsets and > phase shifts in your demodulated data. Well, I suppose one fast ADC would be much better, but such fast device would cost a lot. Basically, I believe that if I would use four same chips, clock as mentioned before and set the adc_start_conversion command properly, then the delay, offset, etc, would be the same for them all and as mentioned in datasheet. E.g. cheap DSOs use the same technique, but I am not sure about ADC clock there.Article: 152172
>> Hi, >> I am using a custom board design in which i have 2 FPGAs (spartan 3 >> xc3s4000) and an EEPROM xcf16p daisy chained together. The chain is like >> this: >> >> EEPROM -> FPGA1 -> FPGA2 > >unless the 2 FPGAs are identical, the first problem I can see here is >that XCF16P (16 MBit) is not big enough to store the configuration >bits for both FPGAs (11,316,864bits) .. see page 86 of UG332 > The FPGAs are identical and i am trying to configure only one FPGA at the moment using JTAG. So, EEPROM signals can be ignored for now. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 152173
Hi, I am using a customized board with 1 spartan 3 xc3s4000 FPGA and 2 Gigabit Phys. My system clock is 125Mhz and i am facing an issue which occurs after a while but since it occurs so it is a problem for me. I have no timing failures in my design, at least none reported by xilinx ISE. I also read the delay report to see if there are any of my critical signals listed under the worst delay paths,none. The design is actually a MAC so whatever we receive from one PHY is transmitted on to the other PHY. The problem i am facing is that occasionally only one byte in the packet gets corrupt.And it gets corrupt on the incoming interface i.e. at the first FF. I can't figure out why would it behave like this occasionally as it works properly otherwise. Any pointers on how i should proceed further ? PS. There are no setup/hold time violations. regards --------------------------------------- Posted through http://www.FPGARelated.comArticle: 152174
On Jul 14, 6:19=A0pm, Roberto Waltman <use...@rwaltman.com> wrote: > Michael S =A0wrote: > > glen herrmannsfeldt =A0wrote: > >> How about 1uHz? (or 1nHz or 1pHz?) > >> ... > >> For 1uHz, R=3D1Mohm, C=3D1F. =A0That isn't easy, even with an external > >> capacitor! > >... > >I can imagine the utility of 1mHz, may be, even 0.1 mHz in some > >extreme cases where you want to take a deep thought between the > >clocks. But 1uHz? Can't see how it helps debugging. > > Reading 1uHZ =A0as "full stop",... > > A few geological ages ago, I was debugging a quite complex system > based on a Z80 CPU =A0(Fully static design) > Things like an ICE or logic analyzer were luxuries not available to > me, so I had to improvise. > > One of the things I did was to hook up a couple of logical gates and a > flip-flop between the RD & WR lines and the WAIT lines, forcing the > CPU into wait state each time it tried to access the bus. > > The address and data lines were connected to 3 x 8-bit buffers, > multiplexing the 24 bits into a single 8-bit lane. > > That lane plus a few control lines went to a CP/M computer printer > port, where an interpreted BASIC program read the data and then > toggled the flip-flop allowing the Z80 to do one more memory cycle. > > The basic program would disassemble the current operation and, if it > involved an external memory transfer show exactly what was being > read/written and where > > Voila! With an investment of a few hours of work I had a system that > allowed me to fully trace the program flow and memory access. > Could have any number of breakpoints (just keep toggling the flip-flop > until reaching a given address, then stop for manual control), count > the number of times a branch was taken, etc. > Everything in slow motion, of course, but the information I gathered > was not available otherwise. > > I was forcing wait states, but could have accomplished the same thing > gating the CPU clock. > Either technique would have been impossible with chips like the > 6800/6502 that would loose state if the clock was below a certain > minimum frequency, and that could not be kept in wait state for more > than a few microseconds. > > You can not do the same with a modern controller with on-chip memory, > etc. but still, slowing down the processor so that you can, for > example, check the state of 10 GPIO pins with your 2-channel scope, is > a very valuable feature. It seems to me, some looping test programs coupled with externally syncing a scope with a 'control' signal could've been just as useful (in examining the width of a port or buffer anyway). Anyway, we used it as a poorman's logic analyzer, in the distant past. lol! I CAN see how a slow clock could be useful too. Especially with limited test equipment.
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