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jt_eaton <z3qmtr45@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: (snip) > You can't avoid 100% of all async reset flops but you can easily do the > 99.999% where sync will give you a smaller, faster design and your design > is still a black box equivalent to using the async reset. > With xilinx parts every flop with an async reset wastes 1 lut over a sync > reset. In asic design every async reset flop doubles the number of > endpoints needing timing closure from 1 to 2. I thought (at least for some) if you do a global async reset that it used the same reset as for configuration. If you reset from a LUT output, then it needs something different. I am not sure now which family that is for, though. > If you do a really lousy job > in designing your reset distribution then these async paths could become > critical paths and start taking routing resources away from your other more > important paths. -- glenArticle: 151976
Hello, I am trying to choose a new oscilloscope, but also keeping my eye on logic analyzers. I am mostly working with video stream over FPGA, so I need a scope for this purpose. I've narrowed my criteria to >350MHz BW and at least 16ch log. analyzer. Agilent offers new MSOX3*** series and also great older series as MSO6*** or MSO7***. They also have some additional modules for Altera/Xilinx FPGAs to analyze internal FPGA data. I've taken a look @ Tek scopes MSO3***/MSO4***/MSO5**** phosphor series with 350-500MHz BW, 2.5 or 5GSPS and 16ch analyzers and also some Yokogawa ones... All of these seems so similiar, that it is hard to choose which one to buy. I've worked with Hameg 350MHz scope, which is able to sample 2GSPS and is completely shit (analog and digital - both are bad). So my questions would be: 1) Which brand do You use and are You satisfied with it? Maybe You have to offer which scope would be better? 2) Do You use such additional modules like Agilent offers for FPGAs? 3) Maybe I should better take a look @ logic analyzer instead of scope? Thank You. Sincerely, Tomas D.Article: 151977
Hopefully not sparking any religious wars here, but hoping for some
advice from those-who-know :)
I switched to using Altera's software a couple of years ago, because
it felt more intuitive to me - probably a personal thing, but it just
grocked better; however, I was browsing the xilinx site just recently,
idly wondering if the -7 series that I'd heard so much about had
actually arrived yet (big surprise, it's still vapour-ware to the
likes of me), and I saw the SP605 evaluation kit had dropped to $695.
This seems to be a really great deal. You get a nice high-bandwidth-
memory card, with a PCI-e interface, and high-speed external
connections (ok, only 68/34 pins, but still), as well as a full (even
if device-locked) ISE license for both the EDK and ISE. My innate
cynicism asks "what's the catch ?"
So, I thought I'd access the wisdom of crowds ([grin] on the first
pass, that read: wisdom of crows :) and ask:
- Do you actually get a real, useful, not time-limited or anything
like that PCIe core ?
- Ditto for the DDR memory core ?
- Ditto for the Microblaze core ?
- Does "lite" mean the ethernet-lite core "only' does 10/100 rather
than 10/100/1000 ?
It seems to suggest in the docs that the answers to the above are
{yes, yes, yes, yes}, but that seems too good to be true. Over in
Altera-land I'd be paying $500 for the nios2 license, and $1000 for
the memory/ethernet cores, both on top of a board-cost... I'm halfway
through a project that uses a nios2 qsys-based system, and for the ~
$1000 difference, I'm happy to port it back to Xilinx (this is a
hobby, the cost/benefit analysis is different to most people's on here
- y'all don't have the 'WAF' (wife-approval factor) to consider, and
WAF trumps pretty much all :)
I understand that if I ever wanted to target something other than an
LX45T I'd have to re-purchase the software. Does that apply to the EDK
as well as ISE ? Or could I use the EDK that comes with the kit in
tandem with WebPack to target a smaller device ?
Cheers
Simon
Article: 151978
Simon wrote:
> Hopefully not sparking any religious wars here, but hoping for some
> advice from those-who-know :)
>
> I switched to using Altera's software a couple of years ago, because
> it felt more intuitive to me - probably a personal thing, but it just
> grocked better; however, I was browsing the xilinx site just recently,
> idly wondering if the -7 series that I'd heard so much about had
> actually arrived yet (big surprise, it's still vapour-ware to the
> likes of me), and I saw the SP605 evaluation kit had dropped to $695.
>
> This seems to be a really great deal. You get a nice high-bandwidth-
> memory card, with a PCI-e interface, and high-speed external
> connections (ok, only 68/34 pins, but still), as well as a full (even
> if device-locked) ISE license for both the EDK and ISE. My innate
> cynicism asks "what's the catch ?"
>
> So, I thought I'd access the wisdom of crowds ([grin] on the first
> pass, that read: wisdom of crows :) and ask:
>
> - Do you actually get a real, useful, not time-limited or anything
> like that PCIe core ?
> - Ditto for the DDR memory core ?
> - Ditto for the Microblaze core ?
> - Does "lite" mean the ethernet-lite core "only' does 10/100 rather
> than 10/100/1000 ?
>
> It seems to suggest in the docs that the answers to the above are
> {yes, yes, yes, yes}, but that seems too good to be true. Over in
> Altera-land I'd be paying $500 for the nios2 license, and $1000 for
> the memory/ethernet cores, both on top of a board-cost... I'm halfway
> through a project that uses a nios2 qsys-based system, and for the ~
> $1000 difference, I'm happy to port it back to Xilinx (this is a
> hobby, the cost/benefit analysis is different to most people's on here
> - y'all don't have the 'WAF' (wife-approval factor) to consider, and
> WAF trumps pretty much all :)
>
> I understand that if I ever wanted to target something other than an
> LX45T I'd have to re-purchase the software. Does that apply to the EDK
> as well as ISE ? Or could I use the EDK that comes with the kit in
> tandem with WebPack to target a smaller device ?
>
> Cheers
>
> Simon
Xilinx has a new approach to supplying software with demo boards. Read
the fine print with your board, but generally what you get is a license
to use the full EDK (Microblaze development software), which is
otherwise quite expensive. This license is good for one computer
(node-locked) *and* also locked to the particular Xilinx device on your
demo board.
There's nothing to stop you from using it on your own hardware, provided
you choose the same chip. Any other cores provided are also licensed
for use on that particular chip. I'm not familiar enough with Spartan
6 to know if you would normally pay for the PCIe license, but on the
Virtex 5 parts that have a built-in PCIe endpoint block the "wrapper"
core is free. Ditto for the ethernet MAC block wrappers. The Ethernet
TriMode soft MAC is not free.
For very simple MicroBlaze-based designs there is a "simple MicroBlaze"
pre-built core available at no charge, with very limited connectivity.
You can use this wih the SDK without the need for the EDK. However
as soon as you want to build a processor with external memory and/or
network connectivity you need to pony up for the EDK.
As far as I know, all of the Xilinx licenses are not time limited for
use, but do have a time limit for maintenance (includes upgrades to
the latest version - not always a blessing). The renewal fee for
maintenance is almost the same as a new license. You also get
webcase support while under maintenance. After that you're back to
trolling forums with the students.
-- Gabor
Article: 151979After tweaking my pipeline a bit and discovering that even after getting it down to well under 100% LUT utilization, it still utterly fails to PAR, I'm going to reassess the overall algorithm. Interesting reads from everyone though, thanks! Chris On Tue, 14 Jun 2011 23:35:33 -0700 Christopher Head <chead@is.invalid> wrote: > Lots of interesting advice here! In particular I read the Xilinx > whitepaper with interest. Unfortunately, a lot of the advice seemed to > be inapplicable to my problem. I can't look for the individual > submodule that's taking up most of the area, because my application is > a single long pipeline with a large number of very similar stages: the > area isn't taken up by any one stage, but more by the number of > stages. And because the design is a pipeline with general logic > (mostly bitwise, plus a small bit of basic arithmetic) between > registers, I don't really see any opportunities for special > primitives like SRLs, DSPs, or the like that would reduce area. I can > probably solve my problem by building a smaller pipeline and reusing > it; I preferred not to do that as it will decrease system performance > but it looks like I don't have much choice now. > > Thanks anyway! > ChrisArticle: 151980
On Thu, 16 Jun 2011 23:58:16 -0700, Christopher Head wrote: > After tweaking my pipeline a bit and discovering that even after getting > it down to well under 100% LUT utilization, it still utterly fails to > PAR, I'm going to reassess the overall algorithm. > > Interesting reads from everyone though, thanks! Chris At this point, try to PAR with a ridiculously slow target clock. If that works, increase the clock until it fails, and let the timing report tell you which part of the pipeline is failing. Re-engineer that, and repeat... - BrianArticle: 151981
Hi,
On 06/16/11 11:38 PM, Gabor wrote:
> Simon wrote:
>> Hopefully not sparking any religious wars here, but hoping for some
>> advice from those-who-know :)
>>
>> I switched to using Altera's software a couple of years ago, because
>> it felt more intuitive to me - probably a personal thing, but it just
>> grocked better; however, I was browsing the xilinx site just recently,
>> idly wondering if the -7 series that I'd heard so much about had
>> actually arrived yet (big surprise, it's still vapour-ware to the
>> likes of me), and I saw the SP605 evaluation kit had dropped to $695.
>>
>> This seems to be a really great deal. You get a nice high-bandwidth-
>> memory card, with a PCI-e interface, and high-speed external
>> connections (ok, only 68/34 pins, but still), as well as a full (even
>> if device-locked) ISE license for both the EDK and ISE. My innate
>> cynicism asks "what's the catch ?"
>>
>> So, I thought I'd access the wisdom of crowds ([grin] on the first
>> pass, that read: wisdom of crows :) and ask:
>>
>> - Do you actually get a real, useful, not time-limited or anything
>> like that PCIe core ?
>> - Ditto for the DDR memory core ?
>> - Ditto for the Microblaze core ?
>> - Does "lite" mean the ethernet-lite core "only' does 10/100 rather
>> than 10/100/1000 ?
>>
>> It seems to suggest in the docs that the answers to the above are
>> {yes, yes, yes, yes}, but that seems too good to be true. Over in
>> Altera-land I'd be paying $500 for the nios2 license, and $1000 for
>> the memory/ethernet cores, both on top of a board-cost... I'm halfway
>> through a project that uses a nios2 qsys-based system, and for the ~
>> $1000 difference, I'm happy to port it back to Xilinx (this is a
>> hobby, the cost/benefit analysis is different to most people's on here
>> - y'all don't have the 'WAF' (wife-approval factor) to consider, and
>> WAF trumps pretty much all :)
>>
>> I understand that if I ever wanted to target something other than an
>> LX45T I'd have to re-purchase the software. Does that apply to the EDK
>> as well as ISE ? Or could I use the EDK that comes with the kit in
>> tandem with WebPack to target a smaller device ?
>>
>> Cheers
>>
>> Simon
>
> Xilinx has a new approach to supplying software with demo boards. Read
> the fine print with your board, but generally what you get is a license
> to use the full EDK (Microblaze development software), which is
> otherwise quite expensive. This license is good for one computer
> (node-locked) *and* also locked to the particular Xilinx device on your
> demo board.
>
> There's nothing to stop you from using it on your own hardware, provided
> you choose the same chip. Any other cores provided are also licensed
> for use on that particular chip. I'm not familiar enough with Spartan
> 6 to know if you would normally pay for the PCIe license, but on the
> Virtex 5 parts that have a built-in PCIe endpoint block the "wrapper"
> core is free. Ditto for the ethernet MAC block wrappers. The Ethernet
> TriMode soft MAC is not free.
>
> For very simple MicroBlaze-based designs there is a "simple MicroBlaze"
> pre-built core available at no charge, with very limited connectivity.
> You can use this wih the SDK without the need for the EDK. However
> as soon as you want to build a processor with external memory and/or
> network connectivity you need to pony up for the EDK.
>
> As far as I know, all of the Xilinx licenses are not time limited for
> use, but do have a time limit for maintenance (includes upgrades to
> the latest version - not always a blessing). The renewal fee for
> maintenance is almost the same as a new license. You also get
> webcase support while under maintenance. After that you're back to
> trolling forums with the students.
>
> -- Gabor
I have not check this up now but IIRC, Xilinx license is for new designs
for one year but after one year you need to purchase a new license for
new designs but you can maintain
old designs for a unlimited time.
Article: 151982
On Jun 16, 2:38=A0pm, Gabor <ga...@szakacs.invalid> wrote:
> Simon wrote:
> > Hopefully not sparking any religious wars here, but hoping for some
> > advice from those-who-know :)
>
> > I switched to using Altera's software a couple of years ago, because
> > it felt more intuitive to me - probably a personal thing, but it just
> > grocked better; however, I was browsing the xilinx site just recently,
> > idly wondering if the -7 series that I'd heard so much about had
> > actually arrived yet (big surprise, it's still vapour-ware to the
> > likes of me), and I saw the SP605 evaluation kit had dropped to $695.
>
> > This seems to be a really great deal. You get a nice high-bandwidth-
> > memory card, with a PCI-e interface, and high-speed external
> > connections (ok, only 68/34 pins, but still), as well as a full (even
> > if device-locked) ISE license for both the EDK and ISE. My innate
> > cynicism asks "what's the catch ?"
>
> > So, I thought I'd access the wisdom of crowds ([grin] on the first
> > pass, that read: wisdom of crows :) and ask:
>
> > =A0- Do you actually get a real, useful, not time-limited or anything
> > like that PCIe core ?
> > =A0- Ditto for the DDR memory core ?
> > =A0- Ditto for the Microblaze core ?
> > =A0- Does "lite" mean the ethernet-lite core "only' does 10/100 rather
> > than 10/100/1000 ?
>
> > It seems to suggest in the docs that the answers to the above are
> > {yes, yes, yes, yes}, but that seems too good to be true. Over in
> > Altera-land I'd be paying $500 for the nios2 license, and $1000 for
> > the memory/ethernet cores, both on top of a board-cost... I'm halfway
> > through a project that uses a nios2 qsys-based system, and for the ~
> > $1000 difference, I'm happy to port it back to Xilinx (this is a
> > hobby, the cost/benefit analysis is different to most people's on here
> > - y'all don't have the 'WAF' (wife-approval factor) to consider, and
> > WAF trumps pretty much all :)
>
> > I understand that if I ever wanted to target something other than an
> > LX45T I'd have to re-purchase the software. Does that apply to the EDK
> > as well as ISE ? Or could I use the EDK that comes with the kit in
> > tandem with WebPack to target a smaller device ?
>
> > Cheers
>
> > Simon
>
> Xilinx has a new approach to supplying software with demo boards. =A0Read
> the fine print with your board, but generally what you get is a license
> to use the full EDK (Microblaze development software), which is
> otherwise quite expensive. =A0This license is good for one computer
> (node-locked) *and* also locked to the particular Xilinx device on your
> demo board.
>
> There's nothing to stop you from using it on your own hardware, provided
> you choose the same chip. =A0Any other cores provided are also licensed
> for use on that particular chip. =A0I'm not familiar enough with Spartan
> 6 to know if you would normally pay for the PCIe license, but on the
> Virtex 5 parts that have a built-in PCIe endpoint block the "wrapper"
> core is free. =A0Ditto for the ethernet MAC block wrappers. =A0The Ethern=
et
> TriMode soft MAC is not free.
>
> For very simple MicroBlaze-based designs there is a "simple MicroBlaze"
> pre-built core available at no charge, with very limited connectivity.
> You can use this wih the SDK without the need for the EDK. =A0However
> as soon as you want to build a processor with external memory and/or
> network connectivity you need to pony up for the EDK.
>
> As far as I know, all of the Xilinx licenses are not time limited for
> use, but do have a time limit for maintenance (includes upgrades to
> the latest version - not always a blessing). =A0The renewal fee for
> maintenance is almost the same as a new license. =A0You also get
> webcase support while under maintenance. =A0After that you're back to
> trolling forums with the students.
>
> -- Gabor- Hide quoted text -
>
> - Show quoted text -
> I'm not familiar enough with Spartan 6 to know if you would normally
> pay for the PCIe license, but on the Virtex 5 parts that have a built-in
> PCIe endpoint block the "wrapper" core is free
Spartan-6 devices also include an integrated PCIe block so there is no
extra license cost.
Ed McGettigan
--
Xilinx Inc.
Article: 151983Jon Elson wrote: > CLEARLY, this is a homework question of some kind, that's the only > reason someone would do this. And, the person who invented the question > apparently doesn't know how FPGAs are actually built or configured, as > the question seems nearly idiotic. it would be QUITE difficult to force > the tools to avoid using any FFs. If it really ISN'T homework, then it is > from the same camp as the guys who build digital clocks from vacuum > tubes or computers from discrete transistors. > > Jon Any what exactly is wrong with vacuum tube digital clocks, or discrete transistor computers, if that is what one considers fun or interesting? Rather than suspect a homework problem, or feeling the need to insult the OP's question, I wonder if it's just the curiosity factor of a person new to electronics, who has put together the ideas of "FFT=interesting" and "logic gates = makes stuff happen" and wondered "how can you make an FFT using logic gates?" This sort of questioning should be encouraged, with the answer consisting of both what the drawbacks would be of attempting such an approach, as well as suggesting a look at how modern implementations of the FFT in hardware are done. -- _____________________ Mr.CRC crobcBOGUS@REMOVETHISsbcglobal.net SuSE 10.3 Linux 2.6.22.17Article: 151984
scrts wrote: > Hello, > I am trying to choose a new oscilloscope, but also keeping my eye on logic > analyzers. I am mostly working with video stream over FPGA, so I need a > scope for this purpose. I've narrowed my criteria to >350MHz BW and at least > 16ch log. analyzer. Agilent offers new MSOX3*** series and also great older > series as MSO6*** or MSO7***. They also have some additional modules for > Altera/Xilinx FPGAs to analyze internal FPGA data. I've taken a look @ Tek > scopes MSO3***/MSO4***/MSO5**** phosphor series with 350-500MHz BW, 2.5 or > 5GSPS and 16ch analyzers and also some Yokogawa ones... All of these seems > so similiar, that it is hard to choose which one to buy. I've worked with > Hameg 350MHz scope, which is able to sample 2GSPS and is completely shit > (analog and digital - both are bad). > So my questions would be: > 1) Which brand do You use and are You satisfied with it? Maybe You have to > offer which scope would be better? > 2) Do You use such additional modules like Agilent offers for FPGAs? > 3) Maybe I should better take a look @ logic analyzer instead of scope? > > Thank You. > > Sincerely, > Tomas D. Tomas, I use Agilent 7000B and 3000X primarily for electronic design/troubleshooting primarily because they have fast waveform update rates, even when using the logic channels and decoding serial busses, etc. I have little experience with video, unfortunately. My least favorite scope that I acquired recently is the Tek MSO4000. It is painfully slow to acquire when using the full memory, or when logic channels are turned on. Agilent doesn't have this problem. I am very interested in trying a Yokogawa next time I'm in the market. I also have a LeCroy, but it has the worst waveform update rate. I wouldn't think of using it for troubleshooting. Where it shines is built-in data analysis. In this aspect it simply steamrolls over the others. Agilent: waveform update rate for glitch/anomaly finding--superb! LeCroy: superior built-in data analysis! Tek: I haven't much use for them anymore Yokogawa: on my hot list to evaluate next time. -- _____________________ Mr.CRC crobcBOGUS@REMOVETHISsbcglobal.net SuSE 10.3 Linux 2.6.22.17Article: 151985
On 6/16/2011 11:47 AM, scrts wrote: > Hello, > I am trying to choose a new oscilloscope, but also keeping my eye on logic > analyzers. I am mostly working with video stream over FPGA, so I need a > scope for this purpose. I've narrowed my criteria to>350MHz BW and at least > 16ch log. analyzer. Agilent offers new MSOX3*** series and also great older > series as MSO6*** or MSO7***. They also have some additional modules for > Altera/Xilinx FPGAs to analyze internal FPGA data. I've taken a look @ Tek > scopes MSO3***/MSO4***/MSO5**** phosphor series with 350-500MHz BW, 2.5 or > 5GSPS and 16ch analyzers and also some Yokogawa ones... All of these seems > so similiar, that it is hard to choose which one to buy. I've worked with > Hameg 350MHz scope, which is able to sample 2GSPS and is completely shit > (analog and digital - both are bad). > So my questions would be: > 1) Which brand do You use and are You satisfied with it? Maybe You have to > offer which scope would be better? > 2) Do You use such additional modules like Agilent offers for FPGAs? > 3) Maybe I should better take a look @ logic analyzer instead of scope? > > Thank You. > > Sincerely, > Tomas D. > > Dear Tomas, Please buy a simulator instead. LTspice does your analog stuff for free. HTH, Symon.Article: 151986
On Jun 15, 8:40=A0pm, "jt_eaton" <z3qmtr45@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > >As to the philosophical avoidance of async resets, I can't say I share > >that belief. =A0As you point out, there is one async reset on the chip > >that you can't eliminate, the PROGRAM pin. =A0Even if it doesn't reset > >the FFs, it will stop the design from working and reload all the LUTs > >and memory. > > >Rick > > You can't avoid 100% of all async reset flops =A0but you can easily do th= e > 99.999% where sync will give you a smaller, faster design and your design > is still a =A0black box equivalent to using the async reset. > > With xilinx parts every flop with an async reset wastes 1 lut over a sync > reset. In asic design every async reset flop =A0doubles the number of > endpoints needing timing closure from 1 to 2. If you do a really lousy jo= b > in designing your reset distribution then these async paths could become > critical paths and start taking routing resources away from your other mo= re > important paths. > > Async resets on flops are nothing but trouble. > > John > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com Actually you miss the point. There is no 99.999% issue. When you hit the PROGRAM pin, it is an async input and your entire design stops while the chips reconfigures. So any "analog" issues you may have with async reset inputs applies to the PROGRAM pin. Not much you can do but tie it off hard, but according to your description of the problems an async input has this won't address your concerns. Also, your analysis of the LUT utilization is flawed. There is only a LUT savings in some cases where using the set and/or reset inputs to the FF as sync inputs will save you a LUT. There are plenty of logic cases where this is not true. Heck, there are plenty of cases where no LUTs are used with a FF. So how can you save a LUT then? RickArticle: 151987
On Jun 17, 7:33=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
> On Jun 16, 2:38=A0pm, Gabor <ga...@szakacs.invalid> wrote:
>
>
>
>
>
> > Simon wrote:
> > > Hopefully not sparking any religious wars here, but hoping for some
> > > advice from those-who-know :)
>
> > > I switched to using Altera's software a couple of years ago, because
> > > it felt more intuitive to me - probably a personal thing, but it just
> > > grocked better; however, I was browsing the xilinx site just recently=
,
> > > idly wondering if the -7 series that I'd heard so much about had
> > > actually arrived yet (big surprise, it's still vapour-ware to the
> > > likes of me), and I saw the SP605 evaluation kit had dropped to $695.
>
> > > This seems to be a really great deal. You get a nice high-bandwidth-
> > > memory card, with a PCI-e interface, and high-speed external
> > > connections (ok, only 68/34 pins, but still), as well as a full (even
> > > if device-locked) ISE license for both the EDK and ISE. My innate
> > > cynicism asks "what's the catch ?"
>
> > > So, I thought I'd access the wisdom of crowds ([grin] on the first
> > > pass, that read: wisdom of crows :) and ask:
>
> > > =A0- Do you actually get a real, useful, not time-limited or anything
> > > like that PCIe core ?
> > > =A0- Ditto for the DDR memory core ?
> > > =A0- Ditto for the Microblaze core ?
> > > =A0- Does "lite" mean the ethernet-lite core "only' does 10/100 rathe=
r
> > > than 10/100/1000 ?
>
> > > It seems to suggest in the docs that the answers to the above are
> > > {yes, yes, yes, yes}, but that seems too good to be true. Over in
> > > Altera-land I'd be paying $500 for the nios2 license, and $1000 for
> > > the memory/ethernet cores, both on top of a board-cost... I'm halfway
> > > through a project that uses a nios2 qsys-based system, and for the ~
> > > $1000 difference, I'm happy to port it back to Xilinx (this is a
> > > hobby, the cost/benefit analysis is different to most people's on her=
e
> > > - y'all don't have the 'WAF' (wife-approval factor) to consider, and
> > > WAF trumps pretty much all :)
>
> > > I understand that if I ever wanted to target something other than an
> > > LX45T I'd have to re-purchase the software. Does that apply to the ED=
K
> > > as well as ISE ? Or could I use the EDK that comes with the kit in
> > > tandem with WebPack to target a smaller device ?
>
> > > Cheers
>
> > > Simon
>
> > Xilinx has a new approach to supplying software with demo boards. =A0Re=
ad
> > the fine print with your board, but generally what you get is a license
> > to use the full EDK (Microblaze development software), which is
> > otherwise quite expensive. =A0This license is good for one computer
> > (node-locked) *and* also locked to the particular Xilinx device on your
> > demo board.
>
> > There's nothing to stop you from using it on your own hardware, provide=
d
> > you choose the same chip. =A0Any other cores provided are also licensed
> > for use on that particular chip. =A0I'm not familiar enough with Sparta=
n
> > 6 to know if you would normally pay for the PCIe license, but on the
> > Virtex 5 parts that have a built-in PCIe endpoint block the "wrapper"
> > core is free. =A0Ditto for the ethernet MAC block wrappers. =A0The Ethe=
rnet
> > TriMode soft MAC is not free.
>
> > For very simple MicroBlaze-based designs there is a "simple MicroBlaze"
> > pre-built core available at no charge, with very limited connectivity.
> > You can use this wih the SDK without the need for the EDK. =A0However
> > as soon as you want to build a processor with external memory and/or
> > network connectivity you need to pony up for the EDK.
>
> > As far as I know, all of the Xilinx licenses are not time limited for
> > use, but do have a time limit for maintenance (includes upgrades to
> > the latest version - not always a blessing). =A0The renewal fee for
> > maintenance is almost the same as a new license. =A0You also get
> > webcase support while under maintenance. =A0After that you're back to
> > trolling forums with the students.
>
> > -- Gabor- Hide quoted text -
>
> > - Show quoted text -
> > I'm not familiar enough with Spartan 6 to know if you would normally
> > pay for the PCIe license, but on the Virtex 5 parts that have a built-i=
n
> > PCIe endpoint block the "wrapper" core is free
>
> Spartan-6 devices also include an integrated PCIe block so there is no
> extra license cost.
>
> Ed McGettigan
> --
> Xilinx Inc.
Thanks Ed, (and everyone else). Looks like I'll be getting one of the
embedded kits then. Everyone wins, because as soon as I actually pay
for it, the Zynq or -7 series will immediately be available... That's
just the way it goes :)
Cheers
Simon
Article: 151988> Agilent: waveform update rate for glitch/anomaly finding--superb! > > LeCroy: superior built-in data analysis! > > Tek: I haven't much use for them anymore > > Yokogawa: on my hot list to evaluate next time. Hello, thanks for Your opinion. I haven't taken a look @ LeCroy, I'll check what do they offer, but I suppose it has the best serial/parallel data analysis tools available on the market? I am not talking about UART/SPI/I2C, which are available on every scope, but do they support more complex protocols like PCI-e, USB, MII/GMII/RGMII, etc on default configuration scopes?Article: 151989
> Dear Tomas, > Please buy a simulator instead. LTspice does your analog stuff for free. > HTH, Symon. Hello, I have to work with FPGAs mostly, but using ModelSim + SignalTap very often. Now when I've faced problems with DDR interfaces (DDR memory and RGMII bus), which SignalTap can't show, so I am considering buying a scope. Thought, this would be the best place to ask, since most of people here work with FPGAs and I am a bit off the market now, using an old Agilent scope, which isn't capable of showing me any more, than 50MHz square signals.Article: 151990
Simon,
I have been through a similar exercise recently -
Avnet has the EK-S6-SP605-G listed as in stock at $495....rather than
$695...
However, I ended up purchasing an EBV DB4CGX15 Altera Cyclone IV pcie
development board, online from www.devboards.de , for 133 euros (around
$190) - this provides similar functionality with a similar deal to the
SP605. Maybe worth a look...although a lot depends on the detail of what
you want to do with the card..
Regards,
Tom C.
"Simon" <google@gornall.net> wrote in message
news:7beafd0e-b915-4e67-9b4c-3fe7c8bb741c@k15g2000pri.googlegroups.com...
> Hopefully not sparking any religious wars here, but hoping for some
> advice from those-who-know :)
>
> I switched to using Altera's software a couple of years ago, because
> it felt more intuitive to me - probably a personal thing, but it just
> grocked better; however, I was browsing the xilinx site just recently,
> idly wondering if the -7 series that I'd heard so much about had
> actually arrived yet (big surprise, it's still vapour-ware to the
> likes of me), and I saw the SP605 evaluation kit had dropped to $695.
>
> This seems to be a really great deal. You get a nice high-bandwidth-
> memory card, with a PCI-e interface, and high-speed external
> connections (ok, only 68/34 pins, but still), as well as a full (even
> if device-locked) ISE license for both the EDK and ISE. My innate
> cynicism asks "what's the catch ?"
>
> So, I thought I'd access the wisdom of crowds ([grin] on the first
> pass, that read: wisdom of crows :) and ask:
>
> - Do you actually get a real, useful, not time-limited or anything
> like that PCIe core ?
> - Ditto for the DDR memory core ?
> - Ditto for the Microblaze core ?
> - Does "lite" mean the ethernet-lite core "only' does 10/100 rather
> than 10/100/1000 ?
>
> It seems to suggest in the docs that the answers to the above are
> {yes, yes, yes, yes}, but that seems too good to be true. Over in
> Altera-land I'd be paying $500 for the nios2 license, and $1000 for
> the memory/ethernet cores, both on top of a board-cost... I'm halfway
> through a project that uses a nios2 qsys-based system, and for the ~
> $1000 difference, I'm happy to port it back to Xilinx (this is a
> hobby, the cost/benefit analysis is different to most people's on here
> - y'all don't have the 'WAF' (wife-approval factor) to consider, and
> WAF trumps pretty much all :)
>
> I understand that if I ever wanted to target something other than an
> LX45T I'd have to re-purchase the software. Does that apply to the EDK
> as well as ISE ? Or could I use the EDK that comes with the kit in
> tandem with WebPack to target a smaller device ?
>
> Cheers
>
> Simon
Article: 151991> However, I ended up purchasing an EBV DB4CGX15 Altera Cyclone IV pcie > development board, online from www.devboards.de , for 133 euros (around > $190) - this provides similar functionality with a similar deal to the > SP605. Maybe worth a look...although a lot depends on the detail of what > you want to do with the card.. Did they fix the RAM address bug? Afaik 256mb memory was actually smaller - 32mb, because they did not connect last address pins.Article: 151992
Hello all, I struggle with an issue I can't understand the root cause. When simulating my back annoted design with modelsim, I get unexpected behavior when using a simulation step of 1ns, but no errors when using a step of 1ps. My design is running at 1MHz (so I expect a simulation step of 1ns to be highly sufficient). The part that is causing trouble is a wrapper around an SRAM instance (it is an actel RAM512x18 component on an actel proasic3 FPGA). I've got the exact same component instanciated in the exact same wrapper simulating fine on an actel igloo FPGA. I am aware that place and route may have produce significantly different results between the two FPGAs and that having the design running smoothly on one FPGA don't prove anything. Still I can't figure out why modelsim would not simulate identically using a 1ns or 1ps step. Last but not least, I've got no warning from modelsim (no glitch found). If any of you have an idea of what could be happening there I would be glad to ear it. RegardsArticle: 151993
On 20 Jun., 12:12, JB <jb.dubois....@gmail.com> wrote: > When simulating my back annoted design with modelsim, I get unexpected > behavior when using a simulation step of 1ns, but no errors when using > a step of 1ps. > > My design is running at 1MHz (so I expect a simulation step of 1ns to > be highly sufficient). > The part that is causing trouble is a wrapper around an SRAM instance > (it is an actel RAM512x18 component on an actel proasic3 FPGA). The selected technology knows delays below 1 ns, your clock frequency is not everything to take into account. Consider you have in clock tree between two register 2 buffer difference with 100 ps delay each leading to a skew of 200 ps between those registers and in datapath 1 cell with 500 ps delay. Using 1ns resolution would lead to 2 ns skew vs 1 ns data which ends up with 1 ns data before clock violation against 300 ps clock before data when using 1 ps resolution. regards ThomasArticle: 151994
On 20 juin, 14:21, Thomas Stanka <usenet_nospam_va...@stanka-web.de> wrote: > On 20 Jun., 12:12, JB <jb.dubois....@gmail.com> wrote: > > > When simulating my back annoted design with modelsim, I get unexpected > > behavior when using a simulation step of 1ns, but no errors when using > > a step of 1ps. > > > My design is running at 1MHz (so I expect a simulation step of 1ns to > > be highly sufficient). > > The part that is causing trouble is a wrapper around an SRAM instance > > (it is an actel RAM512x18 component on an actel proasic3 FPGA). > > The selected technology knows delays below 1 ns, your clock frequency > is not everything to take into account. > Consider you have in clock tree between two register 2 buffer > difference with 100 ps delay each leading to a skew of 200 ps between > those registers and in datapath 1 cell with 500 ps delay. > Using 1ns resolution would lead to 2 ns skew vs 1 ns data which ends > up with 1 ns data before clock violation against 300 ps clock before > data when using 1 ps resolution. > > regards Thomas Thanks I will use 1ps resolution then. I still find weird that modelsim (or VITAL libraries) does not warn in such cases. RegardsArticle: 151995
On Jun 19, 12:59=A0pm, "Chopper" <Chop...@gymrat.force9.co.uk> wrote: > Simon, > > I have been through a similar exercise recently - > > Avnet has the EK-S6-SP605-G listed as in stock at $495....rather than > $695... Yep, but thats the 'Evaluation kit' not the 'Embedded evaluation kit'. You get the EDK for $200 if you go for the embedded version. > However, I ended up purchasing an EBV DB4CGX15 Altera Cyclone IV pcie > development board, online fromwww.devboards.de, =A0for 133 euros (around > $190) - this provides similar functionality with a similar deal to the > SP605. =A0Maybe worth a look...although a lot depends on the detail of wh= at > you want to do with the card.. I saw it, and it's tempting for the price, but there weren't enough I/ O pins for what I need :( I did consider using a CPLD as a port- expander-type-of-thing, but in the end I think the 605 will be a lot easier... Cheers SimonArticle: 151996
On Jun 20, 8:52=A0am, JB <jb.dubois....@gmail.com> wrote: > > Thanks I will use 1ps resolution then. > I still find weird that modelsim (or VITAL libraries) does not warn in > such cases. > Recheck the transcript right at the start before running for the following type of message: The minimum time resolution limit (1ps) in the Verilog source is smaller than the one chosen for SystemC or VHDL units in the design. Use the vsim -t option to specify the desired resolution. KJArticle: 151997
The RAM size is still 32Mb. Devboards committed most of the FPGA outputs to a user accessible header (and didn't have the nous to make two additional bits jumper selectable, so they could be used either for RAM address or for header pin use. That's not a major problem in my immediate application, as I am using the board simply as a pcie I/O test bed, part of a larger design, and am relaying the circuit, together with other devices, as part of a larger PCB, now that I am happy with the pcie sustained transfer rates (under busmaster DMA) and the SERDES throughput the Cyclone IV can sustain through the pcie port. "scrts" <hidden@email.com> wrote in message news:itmlah$icb$1@dont-email.me... >> However, I ended up purchasing an EBV DB4CGX15 Altera Cyclone IV pcie >> development board, online from www.devboards.de , for 133 euros (around >> $190) - this provides similar functionality with a similar deal to the >> SP605. Maybe worth a look...although a lot depends on the detail of what >> you want to do with the card.. > > > Did they fix the RAM address bug? Afaik 256mb memory was actually > smaller - 32mb, because they did not connect last address pins. >Article: 151998
I saw it, and it's tempting for the price, but there weren't enough I/ O pins for what I need :( I did consider using a CPLD as a port- expander-type-of-thing, but in the end I think the 605 will be a lot easier... Maybe You're interested in other manufacturers? E.g. Lattice offers ECP3 FPGA devkit with transceivers and PCI-e connection, plus 1Gb DDR3 memory and two gigabit network transceivers for 99$. http://www.latticesemi.com/products/developmenthardware/developmentkits/ecp3versadevelopmentkit/index.cfm Afaik software tools are also OK from Lattice, since they use Synplify for synthesis. Anyway, check it out, seems like very good price for such board.Article: 151999
On Jun 20, 6:12=A0am, JB <jb.dubois....@gmail.com> wrote: > Hello all, > > I struggle with an issue I can't understand the root cause. > > When simulating my back annoted design with modelsim, I get unexpected > behavior when using a simulation step of 1ns, but no errors when using > a step of 1ps. > > My design is running at 1MHz (so I expect a simulation step of 1ns to > be highly sufficient). > The part that is causing trouble is a wrapper around an SRAM instance > (it is an actel RAM512x18 component on an actel proasic3 FPGA). > > I've got the exact same component instanciated in the exact same > wrapper simulating fine on an actel igloo FPGA. I am aware that place > and route may have produce significantly different results between the > two FPGAs and that having the design running smoothly on one FPGA > don't prove anything. > > Still I can't figure out why modelsim would not simulate identically > using a 1ns or 1ps step. > > Last but not least, I've got no warning from modelsim (no glitch > found). > > If any of you have an idea of what could be happening there I would be > glad to ear it. > > Regards I don't see evidence that this is your problem, but a classic "back- annotated sim time resolution problem" that often arises is the mixing of your testbench environment made up only of idealistic delays (i.e. delays are only based on the temporal ordering assignments made by your simulator) with your back-annotated "real world" worst case delays. For instance, if you attempt to clock a signal from a simple clocked assignment statement into a back-annotated reg with a real setup time assigned to it, it will always be one cycle behind. A typical fix for this is to add an artificial delay to your testbench assignment statements that interact directly with the back-annotated code to satisfy the setup times. - John
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