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Threads Starting Jul 1995
1496: 95/07/01: Scott Taylor: Xilinx PROMs with Altera FPGAs
1497: 95/07/03: Scott Taylor: Xilinx PROM, Altera FPGA
1498: 95/07/03: Alexander B. Taubin: Async96 CALL FOR PAPERS
1499: 95/07/03: comp-arch-fpga-owner: Comp.Arch.FPGA Reflector V1 #268
1501: 95/07/03: Joseph J. Kubicky: Who makes low-power 22v10-type PLDs?
1503: 95/07/04: Erik Blake: Re: Who makes low-power 22v10-type PLDs?
1506: 95/07/05: John Ragnvald Walliker: Re: Who makes low-power 22v10-type PLDs?
1504: 95/07/04: kayvon irani: Help with Viewlogic II
1505: 95/07/05: <granville@decus.org.nz>: Re: Low Power 22V10, market needs...
1507: 95/07/05: Neal Becker: AHDL reference?
1516: 95/07/06: Russell Petersen: Re: AHDL reference?
1530: 95/07/10: Ken Goldman: Re: AHDL reference?
1508: 95/07/05: Hans Jörg Lebert: Curious behaviour of Synopsys Simulator V3.3a
1509: 95/07/05: Bushy: JEDEC File format
1513: 95/07/06: Richard Vireday: Re: JEDEC File format
1514: 95/07/06: Adrian Godwin: Re: JEDEC File format
1510: 95/07/05: Jason Gomez: FPGA modules compatible with 6u VME
1511: 95/07/05: Jason Gomez: FPGA modules compatible with 6u VME
1533: 95/07/10: Jason Gomez: FPGA modules compatible with 6u VME ???
1512: 95/07/06: r. bansal: VHDL/FPGAs/PLDs help
1610: 95/07/28: <harrah1@ibm.net>: Re: VHDL/FPGAs/PLDs help
1611: 95/07/28: Ashley Stevens: Re: VHDL/FPGAs/PLDs help
1654: 95/08/11: John Cooley: Re: VHDL/FPGAs/PLDs help
1656: 95/08/11: John Walton: Re: VHDL/FPGAs/PLDs help
1657: 95/08/11: Dan Simpkins: Re: VHDL/FPGAs/PLDs help
1659: 95/08/11: Nelson Soria: Re: VHDL/FPGAs/PLDs help
1515: 95/07/06: Tony Stansfield TEMP: Job Advert: Hw/Sw Prototyping (Bristol, UK)
1517: 95/07/06: <GCAT@dorval.mpbtech.qc.ca>: re: 'romance' adds
1518: 95/07/06: <course@garnet.berkeley.edu>: Berkeley Announces 2 Short Courses
1519: 95/07/06: <course@garnet.berkeley.edu>: Packaging/Test Courses from Berkeley
1521: 95/07/06: Jeffrey M. Arnold: anonymous postings
1522: 95/07/07: Joerg Wittenberger: Q: Need help with MAX+plus reading EDIF
1527: 95/07/09: Alex Koegel: Re: Q: Need help with MAX+plus reading EDIF
1523: 95/07/07: Herbert Larbie: Abel and connectedt tri-state outputs
1536: 95/07/11: Alex Koegel: Re: Abel and connectedt tri-state outputs
1524: 95/07/07: Sandra Hillel: ** Computer Buying Guide **
1526: 95/07/08: Rolande Kendal: Please recommend good EDA program
1528: 95/07/09: The Right Reverend <name withheld by request>: QLogic FAS246 info?
1529: 95/07/09: Joseph J. Kubicky: Alternative to low-power 22v10...
1531: 95/07/10: John Forrest: Xilinx 5200 Software
1535: 95/07/11: <randraka@ids.net>: RE: Xilinx 5200 Software
1532: 95/07/10: Rolande Kendal: FPGA as LCD controller
1534: 95/07/10: <course@garnet.berkeley.edu>: BGAs, Flip Chip, COB, SMT, MCMs-courses this summer
1537: 95/07/11: Saul Cozens: FPGAs for video coding
1538: 95/07/11: Jon Saul: JOB AD (UK): Research at Oxford University in Computing
1539: 95/07/11: Amar A. Kapadia: [Q] Comments on Synario
1540: 95/07/11: Evgeny V. Vlasov: I want to work in expert system. Help!
1541: 95/07/11: Wout Klaren: EP330 driver for APLUS
1542: 95/07/12: avider: info
1543: 95/07/12: Mike Reynolds: Exemplar users in Australia (or elsewhere)?
1544: 95/07/12: Ed Musall: Flex 8000: Locking down pins
1550: 95/07/13: Steve Holmes: Re: Flex 8000: Locking down pins
1552: 95/07/13: Hing-Fai Lee: Re: Flex 8000: Locking down pins
1553: 95/07/13: John Phillips: Re: Flex 8000: Locking down pins
1545: 95/07/12: Jarek Lis: Intel FLEXLogic
1546: 95/07/12: David Van den Bout: Re: Intel FLEXLogic
1575: 95/07/20: Richard Steven Walz: Re: Intel FLEXLogic
1547: 95/07/13: John Cooley: Dog Food Drive For Joe Costello
1585: 95/07/21: John Cooley: Re: Dog Food Drive For Joe Costello
1598: 95/07/25: John Cooley: Re: Dog Food Drive For Joe Costello
1614: 95/07/31: ldallara: Re: Dog Food Drive For Joe Costello
1548: 95/07/13: Gary Cook: AT&T FPGAs - Opinions needed
1551: 95/07/13: Don Husby: Re: AT&T FPGAs - Opinions needed
1563: 95/07/17: celia clause: Re: AT&T FPGAs - Opinions needed
1566: 95/07/18: Dave Howarter: Re: AT&T FPGAs - Opinions needed
1549: 95/07/13: Andreas Kugel: Synopsys timing simulation of two XC3000 chips
1556: 95/07/14: Martin Radetzki: Re: Synopsys timing simulation of two XC3000 chips
1554: 95/07/14: Sven Haarhoff: LIVE, INTERACTIVE ESDA BROADCAST
1555: 95/07/14: Markus Wannemacher: Q: New XILINX XC6200-FPGA
1558: 95/07/14: Andreas Kugel: Re: Q: New XILINX XC6200-FPGA
1559: 95/07/14: Jouni Siirtola: Has anyone programmed the Lattice in-system-programmable ispLSI2032?
1560: 95/07/15: <course@garnet.berkeley.edu>: Surface Mount/Fine Pitch course in San Francisco
1561: 95/07/16: <course@garnet.berkeley.edu>: SMT Short course August 8-9 in San Francisco
1562: 95/07/17: Andrew Shelley: ROM synthesis
1570: 95/07/19: Hans Jörg Lebert: Re: ROM synthesis
1564: 95/07/17: zalc: RFI: wavelet
1565: 95/07/17: Rod Zimmerman: Subscription
1567: 95/07/18: K. P. Wang: benchmarks and PD program for channel routing
1568: 95/07/18: Hans Jörg Lebert: HELP!! Xilinx V5.0 doesn't work correctly with Synopsys
1577: 95/07/20: Vincent Rowley: Re: HELP!! Xilinx V5.0 doesn't work correctly with Synopsys
1569: 95/07/18: VLSI: ACTEL PLACE AND ROUTE
1572: 95/07/19: Paul T. Shultz: Re: ACTEL PLACE AND ROUTE
1574: 95/07/19: Eric Pearson: Re: ACTEL PLACE AND ROUTE
1602: 95/07/25: Mike Forster: Re: ACTEL PLACE AND ROUTE
1571: 95/07/19: Marco Schmidt: routing
1573: 95/07/19: James H. Grandt: FPGA Software...
1576: 95/07/20: <Cooper@interpath.net>: Re: FPGA Software...
1578: 95/07/20: Keith D. Brown: Lattice isp programming adapters
1597: 95/07/25: Jeffrey L. Hutchings: Re: Lattice isp programming adapters
1579: 95/07/20: Chuck Gollnick x196: "Circuit Loops" in NeoCad??
1592: 95/07/23: f.j.koons: Re: "Circuit Loops" in NeoCad??
1580: 95/07/21: <romance@in.the.former.USSR.ua>: letter from Olga! =) (Unverified)
1582: 95/07/21: Philip Freidin: Re: letter from Olga! =)
1591: 95/07/23: Victor A. Holen: Re: letter from Olga! =)
1581: 95/07/21: zalc: PREP data
1593: 95/07/24: Trevor Hall: Re: PREP data
1594: 95/07/24: Markus Wannemacher: Re: PREP data
1583: 95/07/21: q: Xilinx XACT Ver 6.0
1584: 95/07/21: Navneet S Yadav: Altera Software on DEC Alpha
1586: 95/07/21: Ross Yu: Help on Altera FLEX 8000 programming
1596: 95/07/24: Ken Goldman: Re: Help on Altera FLEX 8000 programming
1587: 95/07/21: Ross Yu: Help on Altera FLEX 8000 programming
1595: 95/07/24: Qian Zhang: Re: Help on Altera FLEX 8000 programming
1588: 95/07/22: Peter Fenn: Xilinx EPLD's
1590: 95/07/22: <jothi@singnet.com.sg>: Re: Xilinx EPLD's
1609: 95/07/28: Craig Jackson: Re: Xilinx EPLD's
1589: 95/07/22: Jozsef Ludvig: Are the Mach210/230 programming algoritms?
1599: 95/07/25: Uwe Kremmin: Re: Are the Mach210/230 programming algoritms?
1600: 95/07/25: Rick Filipkiewicz: Re:FLEX8000 programming
1601: 95/07/25: Qian Zhang: Re: FLEX8000 programming
1603: 95/07/25: Jeff Wetch: Actel Place and Route response
1604: 95/07/25: Jeff Wetch: Actel Place and Route response
1608: 95/07/27: Chuck Gollnick x196: Re: Actel Place and Route response
1631: 95/08/08: John Eaton: Re: Actel Place and Route response
1605: 95/07/26: Jim Bock: Lattice:pds+/Viewlogic Comments please
1606: 95/07/26: Bill Banzhof: Re: Lattice:pds+/Viewlogic Comments please
1607: 95/07/26: Walt Manaker: Re: "Circuit Loops" in NeoCad??
1612: 95/07/28: David Albert: CUPL Expert?
1613: 95/07/29: Russ Vreeland: Re: Dog Food Drive For Joe Costello
1636: 95/08/09: John Cooley: Re: Dog Food Drive For Joe Costello
1615: 95/07/31: <granville@decus.org.nz>: PLD's with Hystersis ?
1616: 95/07/31: Santiago Felici Castell: HW VIDEO ALGORITHMS
1618: 95/08/02: John McCluskey: Re: HW VIDEO ALGORITHMS
1822: 95/09/07: 0000-Admin(0000): Re: HW VIDEO ALGORITHMS
1836: 95/09/07: 0000-Admin(0000): Re: HW VIDEO ALGORITHMS (Dyslexia Strikes Again!)
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
