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There are at least two tools that I can recommend, depending on how much you are willing to spend: Exemplar Logic CORE logic synthesis package is moderately priced and available on PC and workstation. Synopsys Design Compiler and FPGA Compiler is more expensive and only available on workstation. In either case, you will still need FPGA tools as well. I'd recommend contacting both companies directly. Synopsys: -------- Synopsys has a Web site at http://www.synopsys.com Exemplar Logic: -------------- Contact Exemplar at http:/www.edac.org/EDAC/Companies/Exemplar.html -- Steve Knapp Corporate Applications Manager Xilinx, Inc.Article: 1826
The package offered by DigiKey is equivalent to the Xilinx VIEWlogic BASE development system. It includes: - VIEWdraw and VIEWsim Unified libraries and interface for - XC2000, XC3000A, XC3100A, and XC4000 FPGAs - XC7200A and XC7300 EPLDs - Xilinx core implementation software for FPGAs and EPLDs, including device support for - All XC2000 FPGAs - XC3000A, XC3100A FPGAs up to XC3x42A (4,200 gates) - XC4000 up to XC4003 (3,000 gates) - All XC7200A and XC7300 EPLDs - FPGA demonstration board and parallel download cable - Configuration program generator for both FPGAs and EPLDs NOTE: This package does not include VIEWlogic schematic capture or simulation tools but does include the interface to these tools. These must be purchase separately and are also available in a US$2,500 package. -- Steve Knapp Corporate Applications Manager Xilinx, Inc.Article: 1827
I can recommend two books on the subject: PCI SYSTEM ARCHITECTURE ======================= by Tom Shanley and Don Anderson published by Mindshare Inc. 2202 Buttercup Dr. Richardson, TX 75082 USA 1-214-231-2216 (TEL) 1-214-783-4715 (FAX) Distributed by Computer Literacy Bookshops E-mail: 'info@clbooks.com' ISBN 1-881609-08-1 PCI HARDWARE AND SOFTWARE (Architecture & Design) ================================================= by Edward Solari and George Willse published by Annabooks 11848 Bernardo Plaza Court, Suite 110 San Diego, CA 92128 USA 1-619-673-0870 (TEL) ISBN 0-929392-19-1 The second is a _lot_ more detailed while the first provides a solid, general approach. Also, if you are doing a PCI design with programmable logic, check out the Xilinx webLINX site for additional information at http://www.xilinx.com/products/appsweb.htm#PCI There are two application notes there in Adobe Acrobat format describing how to build a PCI Target in a Xilinx XC3164A-2 FPGA or an XC7300 EPLD. A PCI Initiator design is coming later this year based on Xilinx XC4000E FPGAs. Alternatively, you can receive a compressed, uuencoded Postscript file of these application notes. For the PCI Target interface using FPGA, send an E-mail to 'xdocs@xilinx.com' with 'send 80006' in the Subject header. Also, if you have general PCI questions about programmable logic, you can contact our applications staff directly at 'pci@xilinx.com'. -- Steve Knapp Corporate Applications Manager Xilinx, Inc.Article: 1828
We have an application note that may be of interest titled "A Zero Wait State Synchronous DRAM Controller for the Pentium Microprocessor" It describes how to build a 66 MHz Pentium interface and how to interface to 3.3 volt synchronous DRAMs. You can find an Adobe Acrobat copy on the Xilinx webLINX page at http://www.xilinx.com/products/appsweb.htm#EPLD Alternatively, we can send you one by SnailMail if you provide your mailing address to 'pci@xilinx.com'. -- Steve Knapp Corporate Applications Manager Xilinx, Inc.Article: 1829
I am a computer engineering student who need help on how to use verilog language. I need to know how does this language work and how it is excuted. I don't understand the syntax of the language. I have experience in C language and Pascal but that did not help. I am looking for a good book for this subject or a source that can help me using the language. Also I need refrences that can help me determine and understand propegational delays in gates. Thank you for your help. Please e-mail me your responce at c608476@missou1.missouri.edu because I don't usually have access to the internet. Thank you againArticle: 1830
Has anybody out there tried to use the MAX+plusII development tool from Altera under Windows '95 and may tell me his/her experiences ? We have version 5.41 of the software. Thanks. -- ----------------------------------------------------------------------- Andre' Klindworth Universitaet Hamburg, FB Informatik klindwor@informatik.uni-hamburg.de Vogt-Koelln-Str.30, D-22527 Hamburg Phone: +49 40 54715-501, Fax: -397 GermanyArticle: 1831
Just out of curiosity, I looked at www.att.com, and followed the employment links to AT&T MicroElectronics. At least a couple of pages of listings. Too bad I don't need a new job yet. -- Gerry Belanger, WA1HOZ wa1hoz@a3bbak.nai.net Newtown, CT g.belanger@ieee.orgArticle: 1832
> In article <tompkins.810316022@appliedmicro.ns.ca>, tompkins@appliedmicro.ns.ca (Jim Tompkins) writes: > |> Does anyone have experience with FPGA (e.g. xilinx) to masked > |> gate array conversions? I know that a company called Orbit > |> Semiconductor offers this service. Has anyone used it? > |> Does anyone know of any other companies offering a similar > |> service? > Xilinx has Hardwire. > Chrysalis Research offers FPGA => ASIC conversion services, we also offer multiple FPGA => (Single) ASIC services, something Orbit and the FPGA foundries do not. K. -- _______________________________________________________________________ Kevin McCluskey Chrysalis Research 52 Domino Drive, Concord, MA 01742 (508) 371-9115, kevinm@chrysal.com or info@chrysal.com CHRYSALIS RESEARCH specializes in hardware design consulting services including: VHDL/Verilog, ASIC, FPGA design, EMI and Emissions control. _______________________________________________________________________Article: 1833
The University of California, Berkeley, announces two intensive short courses in San Francisco/Burlingame: I. "CHEMICAL VAPOR DEPOSITION (CVD) FOR SILICON INTEGRATED CIRCUITS", September 11-13, 1995 at the San Francisco Airport, Burlingame, California This course is intended to give you a fundamental, practical understanding of CVD as it applies to IC fabrication. It also serves as an update for process Engineers with a background in CVD. Topics covered: Fundamentals of CVD; Mathematical Modeling of CVD Processes; Thermal CVD---Epitaxial Silicon and Polysilicon Films; Thermal CVD---Polysilicon and Dielectric Films; Thermal CVD---Conducting Films; Thermal CVD--- Selective Deposition of Conducting Films, Barrier Films; Plasma-Enhanced CVD; CVD Reactors---Atmospheric and Low Pressure Systems; CVD Reactors---Single-Wafer and Multichamber Systems. INSTRUCTORS: Dennis W. Hess, Ph.D., Professor and Chairman of the Chemical Engineering Dept., Lehigh University, Bethlehem, PA Ted Kamins, Ph.D., Project Leader at Hewlett-Packard, Palo Alto, CA Arthur Sherman, Ph.D., Consultant in CVD, Palo Alto, CA FEE: $995 ----------------------------------------------------------- II. "ELECTROSTATIC DISCHARGE (ESD) IN INTEGRATED CIRCUITS" October 9-10, 1995, at the San Francisco Airport, Burlingame, California This course is for circuit designers, process development engineers and product/reliability engineers. While most protection techniques presented emphasize CMOS technology, the material is applicable to engineers working on other technologies. Topics covered: ESD in ICs; Testing for ESD; Basics of ESD Protection; Failure Modes and Characterization; CMOS ESD Input Protection; Transmission Line Pulsing; Wafer Level Monitor; Device Physics; CMOS Output Protection; Process Effects; Internal Protection; CDM Phenomena and Protection; Bipolar/BiCMOS Protection; Failure Analysis Tools; Device and Circuit Simulations; Electrical Overstress; Case Studies. INSTRUCTORS: Ajith Amerasekera, Ph.D., Senior Member of Technical Staff, Texas Instruments, Dallas, TX Charvaka Duvvury (course organizer), Ph.D., Senior Member of the Technical Staff, Texas Instruments, Dallas, TX Gadi Krieger, Ph.D., President of QualiTau, Inc., Sunnyvale, CA Timothy J. Maloney, Ph.D., Senior Staff Engineer, Intel Corporation, Santa Clara Tom Polgreen, Ph.D., Staff Modeling Engineer, Dallas Semiconductor, Dallas, TX. UC Berkeley Faculty Advisor: Chenming Hu, Professor of Electrical Engineering and Computer Sciences, UC Berkeley -------------------------------------------------------- FURTHER INFORMATION: Reply with your POSTAL ADDRESS and we will send you a descriptive brochure. In your message, please mention "CVD/ESD courses".Article: 1834
!!! "It's not a BUG, jcooley@world.std.com /o o\ / it's a FEATURE!" (508) 429-4357 ( > ) \ - / _] [_ "Jury Verdict + Test Benches" Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222 Fish out your Sept. copy of "Integrated System Design" (which was delivered in mid-August) and turn to pg. 58 if you want to find out what 273 engineers thought about the accidental Verilog/VHDL design contest. Three weeks of sorting through 317 letters led to some interesting insights (along with a few rather surprizing individual letters. Check it out!) Since I'd like my name associated with getting the hard data (as opposed to propagating all the propaganda the Verilog and VHDL bigots have been known to sling) I tried to report as many numbers as possible (including raw numbers & percentages) in that write-up. After reading it, tell me what you think. :^) - John Cooley part-time EDA Consumer Advocate P.S. Enclosed you'll find the original 4 Verilog and 5 VHDL test bench files used in the design contest. Place each one in its own separate file as named. The only modifications done were to make it universally e-mailable (i.e. all TAB's were removed and no line is longer than 78 characters.) --------------------------- VERILOG sample_counter.v --------------------- // sample_counter.v - Sample Counter design for SNUG'95 Design Contest module counter (data_in, up, down, clock, count_out, carry_out, borrow_out, parity_out); output [8:0] count_out; output carry_out, borrow_out, parity_out; input [8:0] data_in; input clock, up, down; reg [8:0] count_out; reg carry_out, borrow_out, parity_out; // insert your design here, contestant!!!!! endmodule --------------------------- VERILOG stimulus_response --------------------- 00111111101111111101000 10000000000000000000100 00111111110111111110000 10xxxxxxxxx000000001101 00111111111111111111001 10000000000000000010101 00000000101000000101000 01111111111000000000000 00000000100000000100001 01010101010111111111011 00000000011000000011000 01101010101111111110010 00000000010000000010001 01000000010111111101010 00000000001000000001001 01000000000111111100011 00000000000000000000000 01xxxxxxxxx111111011010 ---------------------------- VERILOG testbench.v -------------------------- // This testbench verifies the functionality of the counter using // a minimal set of test vectors, counting once with each vector. // The vector set is not exhaustive. module driver (data_in, up, down, clock, count_out, carry_out, borrow_out, parity_out); output [8:0] data_in; output up, down; output clock; input [8:0] count_out; input carry_out, borrow_out, parity_out; reg [8:0] data_in, count; reg up, down, clock, carry, borrow, parity; reg [22:0] stimulus_count[17:0]; reg [3:0] temp_in, temp_out; integer i, err_cnt; // CLOCK Definition initial #1 clock = 0; always #25 clock = ~clock; // Main loop initial begin seva_banner; $readmemb("stimulus_response", stimulus_count); err_cnt = 0; @(negedge clock); for ( i = 0; i < 18; i = i + 1) begin {up,down,data_in,count,carry,borrow,parity} = stimulus_count[i]; @(negedge clock); temp_in = {count,carry,borrow,parity}; temp_out = {count_out,carry_out,borrow_out,parity_out}; if (temp_in !== temp_out) begin $display("The Results don't match the expected response"); $display("\texpected response\n"); $display("\t\tcount %b\n",count); $display("\t\tcarry %b\n\t\tborrow %b\n\t\tparity %b\n\n", carry,borrow,parity); $display("\tactual response\n"); $display("\t\tcount_out %b\n",count_out); $display("\t\tcarry_out %b\n\t\tborrow_out %b\n\t\tparity_out %b\n\n", carry_out,borrow_out,parity_out); err_cnt = err_cnt + 1; end else begin $display("The Results match the expected response"); $display("\texpected response\n"); $display("\t\tcount %b",count); $display("\t\tcarry %b\n\t\tborrow %b\n\t\tparity %b\n\n", carry,borrow,parity); $display("\tactual response\n"); $display("\t\tcount_out %b",count_out); $display("\t\tcarry_out %b\n\t\tborrow_out %b\n\t\tparity_out %b\n\n", carry_out,borrow_out,parity_out); end end if (err_cnt == 0) $display("\nBingo!! You are one of the sure entries to win $1000.\n\n"); else $display("Huh??!! And you call yourself an expert??\n"); #10 $finish; end // Print Seva Banner task seva_banner ; begin $display("\n\tWelcome to SNUG Design Contest 1995\n") ; $display("This testbench is provided courtesy of SEVA Technologies.") ; $display("Fremont, CA (510) 249-9085 {trivedi,lfs}@seva.com") ; $display("\n;-)\tYour friendly HDL Bug consultants\t;-)\n\n") ; end endtask endmodule ---------------------------- VERILOG top.v -------------------------------- // top.v - top level verilog model that instantiates the counter model // and the testbench module test; wire [8:0] count_out, data_in; wire up, down; wire carry_out, borrow_out, parity_out; wire clock; counter inst1 (data_in,up,down,clock,count_out,carry_out, borrow_out, parity_out); driver inst2 (data_in,up,down,clock,count_out,carry_out, borrow_out,parity_out); endmodule **************************** VHDL sample_counter.vhd *********************** -- sample_counter.vhd - sample design for SNUG'95 Design Contest library ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; entity counter is port (data_in : in std_logic_vector(8 downto 0); up : in std_logic; down : in std_logic; clock : in std_logic; count_out : inout std_logic_vector(8 downto 0); carry_out : out std_logic; borrow_out : out std_logic; parity_out : out std_logic ); end counter; architecture example of counter is begin -- insert your design here, contestant!!!!! end example; **************************** VHDL test.vec ********************************* 00111111101111111101000 10000000000000000000100 00111111110111111110000 10xxxxxxxxx000000001101 00111111111111111111001 10000000000000000010101 00000000101000000101000 01111111111000000000000 00000000100000000100001 01010101010111111111011 00000000011000000011000 01101010101111111110010 00000000010000000010001 01000000010111111101010 00000000001000000001001 01000000000111111100011 00000000000000000000000 01xxxxxxxxx111111011010 **************************** VHDL testbench.vhd **************************** -- This testbench verifies the functionality of the counter using -- a minimal set of test vectors, counting once with each vector. -- The vector set is not exhaustive. library ieee,std; use std.textio.all; use ieee.std_logic_1164.all; entity testbench is port (data_in : out std_logic_vector(8 downto 0); up : out std_logic; down : out std_logic; clock : inout std_logic; count_out : in std_logic_vector(8 downto 0); carry_out : in std_logic; borrow_out : in std_logic; parity_out : in std_logic ); end testbench; architecture test of testbench is -- FUNCTIONS AND PROCEDURES function str_to_stdvec ( inp : string) return std_logic_vector is variable temp : std_logic_vector(inp'range):= (others => 'X') ; begin for i in inp'range loop if ( inp(i) = '1' ) then temp(i) := '1' ; elsif ( inp(i) = '0' ) then temp(i) := '0' ; end if ; end loop ; return temp ; end ; function stdvec_to_str ( inp : std_logic_vector) return string is variable temp : string(inp'left+1 downto 1) := (others => 'X') ; begin for i in inp'reverse_range loop if ( inp(i) = '1' ) then temp(i+1) := '1' ; elsif ( inp(i) = '0' ) then temp(i+1) := '0' ; end if ; end loop ; return temp ; end ; function std_to_str ( inp : std_logic) return string is variable temp : string(1 to 1) := (others => 'X'); begin if ( inp = '1') then temp(1) := '1'; elsif (inp = '0') then temp(1) := '0'; end if; return temp; end ; -- PROCEDURE SEVA BANNER procedure seva_banner is begin assert false report "Welcome to SNUG Design Contest 1995" & lf & "This testbench is provided courtesy of SEVA Technologies. " & lf & "Fremont, CA (510) 249-9085 {trivedi,lfs}@seva.com" & lf & "Your friendly HDL Bug consultants" & lf severity note ; end ; --ARCHITECTURE BODY signal done : std_logic := '0'; begin clk : process constant half_period : time := 25 ns; begin while ( done = '0') loop clock <= '1'; wait for half_period; clock <= '0'; wait for half_period; end loop; wait; end process; main : process file vec_file: text is in "./test.vec"; variable stimulus_in: std_logic_vector(22 downto 0); variable str_stimulus_in: string(23 downto 1); variable count : std_logic_vector(8 downto 0); variable carry : std_logic; variable borrow : std_logic; variable parity : std_logic; variable err_cnt : integer := 0; variable file_line : line ; variable temp_in : std_logic_vector(11 downto 0); variable temp_out : std_logic_vector(11 downto 0); begin seva_banner; wait until clock = '0' and clock'event; while (not endfile(vec_file)) loop readline (vec_file,file_line); read (file_line,str_stimulus_in) ; stimulus_in := str_to_stdvec (str_stimulus_in) ; up <= stimulus_in(22); down <= stimulus_in(21); data_in <= stimulus_in(20 downto 12); count := stimulus_in(11 downto 3); carry := stimulus_in(2); borrow := stimulus_in(1); parity := stimulus_in(0); wait until clock = '0' and clock'event; temp_in := count & carry & borrow & parity; temp_out := count_out & carry_out & borrow_out & parity_out; if (temp_in = temp_out) then assert false report "RESULTS match the expected response" & lf & "expected response" & lf & "count " & stdvec_to_str(count) & lf & "carry " & std_to_str(carry) & lf & "borrow " & std_to_str(borrow) & lf & "parity " & std_to_str(parity) & lf severity note; assert false report "actual response" & lf & "count_out " & stdvec_to_str(count_out) & lf & "carry_out " & std_to_str(carry_out) & lf & "borrow_out " & std_to_str(borrow_out) & lf & "parity_out " & std_to_str(parity_out) & lf severity note; else err_cnt := err_cnt + 1; assert false report "Results mismatch" & lf & "expected response" & lf & "count " & stdvec_to_str(count) & lf & "carry " & std_to_str(carry) & lf & "borrow " & std_to_str(borrow) & lf & "parity " & std_to_str(parity) & lf severity note; assert false report "actual response" & lf & "count_out " & stdvec_to_str(count_out) & lf & "carry_out " & std_to_str(carry_out) & lf & "borrow_out " & std_to_str(borrow_out) & lf & "parity_out " & std_to_str(parity_out) & lf severity note; end if; end loop; done <= '1'; if (err_cnt = 0) then assert false report "Bingo!! You are one of the sure entries to win $1000." & lf & lf severity note; else assert false report "Huh?!! And you call yourself an expert??" & lf severity note; end if; wait; end process; end test; **************************** VHDL top.vhd ********************************** -- top.vhd - top level verilog model that instantiates the counter model -- and the testbench. library ieee; use ieee.std_logic_1164.all; entity top is end top; architecture top of top is --COMPONENT DECLARATION component counter port ( data_in : in std_logic_vector(8 downto 0); up : in std_logic; down : in std_logic; clock : in std_logic; count_out : inout std_logic_vector(8 downto 0); carry_out : out std_logic; borrow_out : out std_logic; parity_out : out std_logic ); end component; component testbench port ( data_in : out std_logic_vector(8 downto 0); up : out std_logic; down : out std_logic; clock : inout std_logic; count_out : in std_logic_vector(8 downto 0); carry_out : in std_logic; borrow_out : in std_logic; parity_out : in std_logic ); end component; --SIGNAL DECLARATIONS signal data_in, count_out : std_logic_vector(8 downto 0); signal carry_out, borrow_out : std_logic; signal parity_out : std_logic; signal up, down : std_logic; signal clock : std_logic; begin --COMPONENT INSTANTIATION u1: counter port map(data_in => data_in, up => up, down => down, clock => clock, count_out => count_out, carry_out => carry_out, borrow_out => borrow_out, parity_out => parity_out ); u2: testbench port map(data_in => data_in, up => up, down => down, clock => clock, count_out => count_out, carry_out => carry_out, borrow_out => borrow_out, parity_out => parity_out ); end top; **************************** VHDL cfg.vhd ********************************** -- placeholder for configuration file. Depending on which brand of VHDL -- simulator you're using, you may or may not need (or be able) to use a -- configuration file with it. Synopsys synthesis doesn't use config files. =========================================================================== Trapped trying to figure out a Synopsys bug? Want to hear how 3713 other users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)! !!! "It's not a BUG, jcooley@world.std.com /o o\ / it's a FEATURE!" (508) 429-4357 ( > ) \ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys, _] [_ Verilog, VHDL and numerous Design Methodologies. Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222 Legal Disclaimer: "As always, anything said here is only opinion."Article: 1835
Doesn't have to be latest version, just want to (economically) find out if i like it. MikeArticle: 1836
My apologies on my previous posting. I have the table table description wrong. The correct values should be XC4000E-3 FIR FILTER PERFORMANCE Implementation Method CLBs Data Rate Device ========================== ====== =========== ========== Fully-Parallel (best speed) 432 55 MHz XC4013E-3 (auto layout) 389 48 MHz XC4010E-3 Distrubted Arithmetic 68 8.1 MHz XC4003E-3 (bit-serial) Many thanks to Brad Hutchings at BYU for pointing this out. Note that we also updated the performance of the DA approach. We retimed the values using the -3 speed grade. As before, if you are interested in additional information, look at http:/www.xilinx.com/products/appsweb.htm#DSP or please contact us at 'dsp@xilinx.com'. -- Steve Knapp Corporate Applications Manager Xilinx, Inc.Article: 1837
VHDL International Home Page Available at http://www.e2w3.com/vi/ VHDL International (VI) is an organization dedicated to cooperatively and proactively promoting the Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) as a standard worldwide language for the design and description of electronic systems. Index to key elements of the WWW Site: o Membership Information: A list of VI corporate members, linked to their home pages, and application forms for corporate and individual memberships. o Links to the VHDL International Internet Services (which is available at http://www.vhdl.org/ and gopher://vhdl.org/) o Brochure: Fall VIUF (Oct 15-18 Boston) Text: http://vhdl.org/~merryb/viuf-fall95-brochure.txt HTML: http://www.e2w3.com/vi/fallviuf/ o Recent Press Release and Announcements from VI o VI Contacts o VHDL TIMES Newsletter (http://www.e2w3.com/vi/vltimes/) VHDL TIMES - The Information Source for VHDL (published Quarterly) Volume 4, Number 3 (Third Quarter, 1995) + Executive Director's Message by Mahendra Jain + VHDL Designer by Charles Shelor + VITAL Moves Toward IEEE Standardization by Victor Berman + VHDL Language Mathematical Packages by Jose A. Torres + Rapid Design & Exploration of Signal Processing Systems Using a VHDL Generator Paradigm by Scott R. Powell and Thomas M. Cesear Volume 4, Number 2 (Second Quarter, 1995) + Executive Director's Message by Mahendra Jain + Your VITAL News Source by Steven Schulz + The VHDL International Test Suite by Stan Krolikoski + Ask Dr. VHDL by Dr. VHDL + VHDL in Sweden by Dennis Soderberg + VHDL Designer: by Charles Shelor + VIUF Conference/Expo: Call for Papers, Panels, Workshops & Tutorials Volume 4, Number 1 (First Quarter, 1995) + Ask Dr. VHDL by Dr. VHDL + Success Story: VHDL to Chip by Ronald Meadows + VHDL Designer by Charles Shelor Subscription Form for the Paper Version of VHDL Times Comment/Question/Sugggestion Form for VI WWW Site Note: This site is under continuous construction (to borrow a phrase from Steve Waterbury, webmaster for the EE Virtual Library on the WWW at http://epims1.gsfc.nasa.gov/engineering/ee.html, who said it first and said it best). However, all of the links and content listed in this announcement is debugged and availalble now. ______________________________________________________________________________ Sean Murphy, President, Leader-Murphy, Inc. (skmurphy@netcom.com 408 252-9676) WWW-Enabled Applications and Methodology Consulting: "Knowledge, Refined from Information Derived from Data, is the Fundamental Asset of the Enterprise" URL: http://www.l-m.com/l-m/ & http://www.e2w3.com/ ______________________________________________________________________________Article: 1838
Why not ACEO? They are the only company offer tools for ASIC protoyping using FPGAs Ravi "0000-Admin(0000)" <stevek> wrote: >There are at least two tools that I can recommend, depending on how much you >are willing to spend: >Exemplar Logic CORE logic synthesis package is moderately priced and available >on PC and workstation. >Synopsys Design Compiler and FPGA Compiler is more expensive and only available >on workstation. >In either case, you will still need FPGA tools as well. I'd recommend >contacting both companies directly. >Synopsys: >-------- >Synopsys has a Web site at >http://www.synopsys.com >Exemplar Logic: >-------------- >Contact Exemplar at >http:/www.edac.org/EDAC/Companies/Exemplar.html >-- Steve Knapp > Corporate Applications Manager > Xilinx, Inc.Article: 1839
- does anyone know of a book written by Sherwani on Routing MCM's in the Third Dimension (not the exact title but close)? It is a fairly new book and I need to know (if any) who the other authors are. Thanx. jc -- -------------------------------------------------------------------------------- Jared Colflesh | "But then again, all good things Graduate Student | must come to an end." University of Virginia Computer Science | e-mail: colflesh@virginia.edu | - Q, "All Good Things ..." WWW: http://www.cs.virginia.edu/~jlc5a/ | Star Trek: The Next Generation --------------------------------------------------------------------------------Article: 1840
John, I'd Like to have a go at this little problem for my own benefit. Were the contestants a) provided with a functional requirements spec for the counter, and b) were they given a time limit to solve the problem. If they answer to either of the above is true would you be kind enough to post the details as I dont have a copy of the magazine you mentioned. Regards -- ----------------------------------------------------------- Jason Flood email: jflood@gec-rl-hrc.co.uk GMMT Hirst Division, Tel: +44 181 732 0638 Borehamwood, Fax: +44 181 732 0099 Herts, UK. Orange: +44 973 178526 -----------------------------------------------------------Article: 1841
Article: 1842
Hi. Can someone email me, or repost the call for papers for the '96 FPGA conference? Thanks, Bill Cox cox@qlogic.comArticle: 1843
Does anyone have experience with the Aptix MP3 card used for emulation of ASICs? Pros - cons? -- Vince Dugar <>< | >>>> "I am, therefore I think." <<<< Boulder, Colorado | All comments here are mine -- they are Vince_Dugar@stortek.com | not representative of my employer.Article: 1844
Does anyone get QuickLogic SpDE 5.0 ? We paid for the maintence charge to upgrade from 4.0 for a long time but still don't get 5.0 yet. Frankie Chung R & D Manager Onmate Technology LtdArticle: 1845
Has anyone got PROTEL for WINDOWS SCHEMATIC library components for the XC2000 and XC3000 series chips that treat the entire chip as a component. ie: I don't want the library,s for creating XNF files, but rather to display the chip as a whole on the schematic dwg. I also want the PCB components for 132 pin PQFP to PTH sockets, (AMP brand) for PROTEL for WINDOWS Thanks in advance, Bill Keenan.Article: 1846
Has anyone got PROTEL for WINDOWS SCHEMATIC library components for the XC2000 and XC3000 series chips that treat the entire chip as a component. ie: I don't want the library,s for creating XNF files, but rather to display the chip as a whole on the schematic dwg. I also want the PCB components for 132 pin PQFP to PTH sockets, (AMP brand) for PROTEL for WINDOWS Thanks in advance, Bill Keenan.Article: 1847
Has anyone got PROTEL for WINDOWS SCHEMATIC library components for the XC2000 and XC3000 series chips that treat the entire chip as a component. ie: I don't want the library,s for creating XNF files, but rather to display the chip as a whole on the schematic dwg. I also want the PCB components for 132 pin PQFP to PTH sockets, (AMP brand) for PROTEL for> Thanks in advance, Bill Keenan.Article: 1848
Has anyone got PROTEL for WINDOWS SCHEMATIC library components for the XC2000 and XC3000 series chips that treat the entire chip as a component. ie: I don't want the library,s for creating XNF files, but rather to display the chip as a whole on the schematic dwg. I also want the PCB components for 132 pin PQFP to PTH sockets, (AMP brand) for PROTEL for> Thanks in advance, Bill Keenan.Article: 1849
Has anyone got PROTEL for WINDOWS SCHEMATIC library components for the XC2000 and XC3000 series chips that treat the entire chip as a component. ie: I don't want the library,s for creating XNF files, but rather to display the chip as a whole on the schematic dwg. I also want the PCB components for 132 pin PQFP to PTH sockets, (AMP brand) for PROTEL for> Thanks in advance, Bill Keenan.
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