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Authors (U)
U. Hernandez:
56749: 03/06/13: Power consumed in a non configured FPGA?
56792: 03/06/16: Re: Power consumed in a non configured FPGA?
56795: 03/06/16: Re: Power consumed in a non configured FPGA?
56796: 03/06/16: Re: XILINX Error Message
<u1000393@email.sjsu.edu>:
76624: 04/12/07: Re: Verilog Book Recommendation
u1061771156:
45269: 02/07/17: Re: JTAG Analyzer with HP16510
<u644866943@spawnkill.ip-mobilphone.net>:
31312: 01/05/18: Xilinx PCI macro problems
<u687591552@spawnkill.ip-mobilphone.net>:
31072: 01/05/10: fpga tutorials
<u722534179@spawnkill.ip-mobilphone.net>:
73175: 04/09/15: I/O state of max7000s during power-up?
<u8011620@cc.nctu.edu.tw>:
723: 95/02/17: PLA? PAL? PLD? GAL?
<u880939@alumni.nthu.edu.tw>:
98912: 06/03/17: bvci protocol for fpga
<u9200386@bournemouth.ac.uk>:
6060: 97/04/08: bidirectional buses in xilinx 3000 fpgas
[u]Joe Dalton:
121: 94/08/17: Re: Sizeable symbols using Actel/Concept?
u_stadler@yahoo.de:
88054: 05/08/08: ModelSim Error
88176: 05/08/11: rom
88180: 05/08/11: Re: rom
89549: 05/09/19: modelsim
93673: 05/12/28: ISE WebPack Clock Signals
93883: 06/01/03: Clock generation
93932: 06/01/03: XST error Xst:2035
93943: 06/01/03: Re: XST error Xst:2035
93970: 06/01/04: DCM and buffers
108337: 06/09/08: microblaze programm doesn't fit into bram...
108600: 06/09/13: Spartan3E availability
108704: 06/09/15: microblaze lwip
108716: 06/09/15: Re: microblaze lwip
108726: 06/09/15: Re: microblaze lwip
108774: 06/09/16: Re: microblaze lwip
108776: 06/09/16: lwip xilinx
108841: 06/09/18: lwip Out of semaphore resources
109297: 06/09/23: edk 8.2 user needed
109302: 06/09/23: Re: edk 8.2 user needed
109464: 06/09/27: lwip
109534: 06/09/28: Re: lwip
109538: 06/09/28: Re: lwip
109738: 06/10/04: Re: FPGA power-up and code relocation (basics)
109939: 06/10/08: 75Mhz Spartan3e microblaze
109962: 06/10/09: Re: 75Mhz Spartan3e microblaze
110076: 06/10/10: EDK Bug
110078: 06/10/10: Re: EDK Bug
110145: 06/10/11: Re: EDK Bug
110147: 06/10/11: Re: EDK Bug
110154: 06/10/11: Re: Release Status of Spartan3E
110385: 06/10/14: Re: 75Mhz Spartan3e microblaze
110486: 06/10/16: lwip xilinx
111148: 06/10/30: xilkernel cache
112281: 06/11/19: Re: spartan-3e starter kit and ethernet
112975: 06/12/03: EDk and DCM
112984: 06/12/04: Re: EDk and DCM
112986: 06/12/04: Re: EDk and DCM
112990: 06/12/04: Re: EDk and DCM
112993: 06/12/04: Re: EDk and DCM
120001: 07/05/30: Re: Xilinx Seminars in Wiesbaden, Berlin, Hannover
122938: 07/08/11: ucf editor edk
123003: 07/08/13: edk + spi
123051: 07/08/15: Re: edk + spi
124046: 07/09/11: hydraxc
125866: 07/11/07: did i miss edk 9.2
126185: 07/11/16: simulating xilinx block ram with modelsim
126210: 07/11/16: Re: simulating xilinx block ram with modelsim
126220: 07/11/16: Re: simulating xilinx block ram with modelsim
126258: 07/11/18: Re: simulating xilinx block ram with modelsim
126304: 07/11/19: Re: simulating xilinx block ram with modelsim
126367: 07/11/20: Re: simulating xilinx block ram with modelsim
126739: 07/11/30: ise timing analysis + different clock domains
126867: 07/12/05: Re: ise timing analysis + different clock domains
126871: 07/12/05: BUFGCE
126883: 07/12/05: Re: BUFGCE
126924: 07/12/06: Re: BUFGCE
127359: 07/12/19: Xilinx EDK PPC405+FSL
128608: 08/01/31: question about fsl and microblaze
128640: 08/02/01: Re: question about fsl and microblaze
129994: 08/03/12: infer block ram with mismatched port width
130243: 08/03/18: vhdl type conversions
130265: 08/03/19: Re: vhdl type conversions
130336: 08/03/20: timing and timing reports (again)
130348: 08/03/20: Re: timing and timing reports (again)
130350: 08/03/20: Re: timing and timing reports (again)
130367: 08/03/21: chip scope
130378: 08/03/21: Re: chip scope
131132: 08/04/11: Virtex4 FX PPC and Fsl
131286: 08/04/17: Re: attached a 2nd peripheral to FSL bus. how to use it in software?
131521: 08/04/24: HydraXC + EDK
131561: 08/04/25: Re: HydraXC + EDK
131708: 08/04/29: PPC + APU + FSL + Xilkernel Problem
131709: 08/04/29: Re: HydraXC + EDK
<uab@info.novsu.ac.ru>:
9876: 98/04/10: Tools for Xillinx 6200 ?
<UAeji029@aol.com>:
Ubaid R. Khan:
897: 95/03/23: Need some Data on FPGA Gate/Pin Counts
<ubxtni@my.com>:
ucfchuck:
144743: 09/12/30: ACE file programming of Virtex 4
144748: 09/12/30: Re: ACE file programming of Virtex 4
144750: 09/12/30: Re: ACE file programming of Virtex 4
146909: 10/04/01: XSVF player that writes V4 key
uche:
131683: 08/04/29: parallel port using XSA-50
132089: 08/05/12: xsa-50 issues
132212: 08/05/18: XSA-50 implementation
132351: 08/05/22: globals
141400: 09/06/22: UART testbench debug
143786: 09/10/25: SPR
uckingcu:
99729: 06/03/28: xst and fpga express
<ucy193@gmail.com>:
160171: 17/07/20: IP core LCD controller for Zynq-7000 famiy
uday:
141988: 09/07/20: Re: FM radio with Spartan3A kit, demo
Uday Godbole:
15083: 99/03/05: Re: Looking for advice on CPLD's
16367: 99/05/19: Is schmitt trigger possible with Xilinx 9536?
18764: 99/11/13: WHERE can I find xc9536_v2.bsd??!
98440: 06/03/10: Re: ISE 8.1: simulation modelsm & tbw generated in Verilog instead of VHDL?!
Uday Hegde:
37957: 01/12/27: Re: Look for FPGA Starterkit
Udayan:
57856: 03/07/08: clock management on SPARTAN2
57905: 03/07/09: Re: clock management on SPARTAN2
57915: 03/07/09: Re: clock management on SPARTAN2
Udesh:
155124: 13/04/23: FPGA implementation of Interpolation controller for a Timing Recovery Loop
Udi Finkelstein:
2314: 95/11/19: Re: NeoCAD and AT&T vs. Xilinx
2498: 95/12/18: Synplicity vs. Exemplar for ORCA - Which is better?
2723: 96/01/30: HELP WANTED - PC-UPROG device programmer
2924: 96/03/01: Re: Atmel Serial Configuration E2PROMs
6660: 97/06/10: Re: ATMEL 17Cxxx ISP function
8589: 98/01/11: Re: SDRAM model
12195: 98/10/03: ANNOUNCE: A new logic simulation library with PCI models
Udo:
80076: 05/03/01: Re: Platform Cable USB
89460: 05/09/15: Small (OEM-)Memory Modules (SRAM/FLASH/DRAM)
89589: 05/09/20: Re: Small (OEM-)Memory Modules (SRAM/FLASH/DRAM)
91085: 05/10/28: Virtex-4 DSP48 - special features (Peter Alfke?)
91088: 05/10/28: Virtex-4: SLICEM and SLICEL, why? (Peter Alfke?)
91090: 05/10/28: Re: Virtex-4: SLICEM and SLICEL, why? (Peter Alfke?)
91291: 05/11/02: Re: newbie question
91476: 05/11/07: XILINX ISE 7.1 Symbol Editor
91557: 05/11/08: ERROR:Pack:1564: ML403 & Xilinx Platform Studio 7.1.02i
91607: 05/11/09: Xilinx Block RAM - initializing with Intel Hex-File
91763: 05/11/11: ModelSim XE III: Arrow disapears during single-stepping
99507: 06/03/25: Nios II - VHDL Source Code, Licensing
99508: 06/03/25: Nios II - Branch Prediction
118318: 07/04/23: I/O-Standards: HSTL vs. SSTL and others...
118370: 07/04/25: Virtex-5 FX when ? (II)
118806: 07/05/03: Tcl slash backslash
119064: 07/05/10: Xilinx ISE Simulator 9.1.03i: A bunch of problems (Block Memory Gen.)
119684: 07/05/24: ModelSim Memory Content import from Intel Hex
119761: 07/05/25: ISE 9.1 and ModelSim XE III/Starter 6.2c: Distributed memory behaviorial simulation
126252: 07/11/18: Xilinx WebPack 9.2i: Download not possible, wrong links
129936: 08/03/11: Virtex-5 FX when ? (III)
Udo Weik:
46369: 02/08/27: Virtex-IIpro Demo-Boards
46394: 02/08/28: Re: Virtex-IIpro Demo-Boards
UETIAN:
131895: 08/05/06: Re: Xilinx xilfatfs and systemACE speed issue
Uffe Toft:
12681: 98/10/23: Re: I2C Core
ug:
39165: 02/02/02: odd divider
<ugcydt@hotmail.com>:
Ui (daniel) Han:
98475: 06/03/10: (no subject)
<uiznvw@my.com>:
<uj101@my-deja.com>:
19312: 99/12/13: Re: Silicon instead of FPGA for Ethernet-to-Ethernet MAC Switch?
ujjwal:
121651: 07/07/10: Type Conversion in VHDL
UK Gary:
42194: 02/04/18: 1000 I/O Pins -- What is cheapest FPGA?
42202: 02/04/18: Re: 1000 I/O Pins -- What is cheapest FPGA?
Ukkdl:
37627: 01/12/18: Re: newbie Xilinx Foundation ISE4.1 questions
<ukrspezmash@euro.ru>:
ulegat:
143967: 09/11/05: BRAM reconfiguration problem using OPB_HWICAP on Virtex 4
143990: 09/11/06: BRAM reconfiguration problem using OPB_HWICAP on Virtex 4
Ulf Andersson:
15022: 99/03/03: Re: Selt-Timed circuit
66318: 04/02/17: Re: using fpga for sampling audio
Ulf Ochsenfahrt:
80697: 05/03/10: Spontaneous Board Reset
80709: 05/03/10: Re: Spontaneous Board Reset
80711: 05/03/10: Re: Spontaneous Board Reset
80806: 05/03/11: Re: Spontaneous Board Reset
Ulf Samuelsson:
17077: 99/06/29: Re: Read/Writes to memories/register files for PIC core
17673: 99/08/23: Re: Smallest Configurator for Xilinx
18108: 99/09/30: Re: Need help programming Spartan FPGA with Atmel serial EEPROM
18157: 99/10/04: Re: microcontroller vs FPGA
18328: 99/10/15: Re: Xilinx FPGA Programmer
18329: 99/10/15: SRAM FPGA with hardwired 40 MHz AVR RISC processor, memory and peripherals
18346: 99/10/17: Re: SRAM FPGA with hardwired 40 MHz AVR RISC processor, memory and peripherals
19820: 00/01/13: Re: fastest 32 bit RISC
19852: 00/01/14: Re: fastest 32 bit RISC
19853: 00/01/14: Re: fastest 32 bit RISC
20892: 00/02/25: Re: Spartan-II Pricing - What gives?
20986: 00/03/02: Re: Comment on Atmel AT40K ?
21343: 00/03/17: SV: Atmel censors web access
22586: 00/05/12: Re: Do you know xilinx FPGAs well?
22587: 00/05/12: Re: Future of FPGAs?
22589: 00/05/12: Re: asic vs fpga
22725: 00/05/19: Re: FPGA emultaion of a microprocessor
23349: 00/06/23: Re: Looking for 'FREE' FPGA software
24471: 00/08/10: FPSLIC Software availability
24783: 00/08/18: Re: Permanently programming FPGAs
25322: 00/09/06: Re: Mealy vs Moore FSM model
25339: 00/09/07: Re: Mealy vs Moore FSM model
25639: 00/09/16: Re: hardware compatibility and patent infringement
25640: 00/09/16: Re: Guide to useing Atmel FPGA (at40k)
25704: 00/09/18: Re: Good FPGA prototyping boards?
25703: 00/09/18: Re: hardware compatibility and patent infringement
25751: 00/09/19: Re: hardware compatibility and patent infringement
25889: 00/09/25: Re: FPGA for PCM coded DTMF transmission?
25986: 00/09/29: Re: FPGA development on the cheap?
25988: 00/09/29: Re: FPGA development on the cheap?
25987: 00/09/29: Re: FPGA development on the cheap?
25989: 00/09/29: Re: FPGA development on the cheap?
25990: 00/09/29: Re: atmel verses altera
26423: 00/10/16: Re: Sinusoidal PWM on Xilinx FPGA
26570: 00/10/20: Re: How safe is the algorithm implemented with FPGA?
26579: 00/10/20: Re: How safe is the algorithm implemented with FPGA?
26636: 00/10/23: Atmel FPGA tools (was Re: Cheapy FPGA sw)
26715: 00/10/25: Re: log2 function in VHDL
26716: 00/10/25: Re: implementing a memory
27276: 00/11/16: Re: Microprocessor Verilog/VHDL Models
27552: 00/11/28: Re: hard or soft core for FPGA?
27640: 00/12/01: Re: Xilinx Coolrunner going on last time buy?
28483: 01/01/15: Re: IDS 6.0 - FPGA Compiler Problem
28564: 01/01/17: Re: Rconfiguration of FPSLIC
28642: 01/01/19: Re: spartanII chip availability
28716: 01/01/22: Re: FPGAs with a partial reconfiguration
29320: 01/02/14: Re: Integrated Conf.EPROM / smaller Footprints?
31526: 01/05/29: Re: Xilinx Coolrunner 100% routable - but the tools aren't
31541: 01/05/29: Re: Peripheral for Microcontroller
31645: 01/06/01: Re: My80-- i8080A instruction compatible processor core
31749: 01/06/05: Re: Which Tools Work with ATMEL FPSLIC?
31928: 01/06/08: Re: Studentlab with Xilinx tools
32024: 01/06/11: Re: Triscend A5: can it reconfigure itself?
32186: 01/06/18: Re: Flexlm license and windows 2000
32784: 01/07/09: Re: WTB:50 Mhz 24 CHANNEL LOGIC ANALYZER only $199
33822: 01/08/06: Re: Slightly off topic - PCs for running FPGA tools
34733: 01/09/05: Re: Special counter for scheduling
35191: 01/09/25: Re: FPGA with embedded Memory
35281: 01/09/27: Re: Programming flash connected to CPLD via JTAG
36040: 01/10/26: Re: Cloning someone else's IP core
37280: 01/12/06: Re: Triscend E5 vs Atmel FPSLIC
38051: 02/01/03: Re: Atmel FPSLIC - Problem with concurrent statements
38091: 02/01/04: Re: Configuration Times of FPGAs
38146: 02/01/07: Re: Suitability of Atmel for project?
38182: 02/01/08: Re: Suitability of Atmel for project?
38677: 02/01/21: Re: Atmel FPGA configuration memory?!
38705: 02/01/22: Re: Atmel FPGA configuration memory?!
38976: 02/01/29: Re: FPGA or Micro-controller in Lowpower designs?
39096: 02/01/31: Re: FPGA or Micro-controller in Lowpower designs?
39134: 02/02/01: Re: FPGA or Micro-controller in Lowpower designs?
39680: 02/02/15: Re: FPGA choices and questions
39845: 02/02/21: Re: Need largest CPLD devices?
39846: 02/02/21: Re: FPGA choices and questions
41182: 02/03/22: Re: which is the fastest FPGA ?
41532: 02/04/01: Re: Where to get MAX7000S
41533: 02/04/01: Re: FPGA config without boot PROM???
41800: 02/04/08: Re: Distributed ram
41900: 02/04/10: Re: Low-cost FPGA + processor board?
42249: 02/04/19: Re: 8051 Core for Motor Electronics
42520: 02/04/26: Re: Hack an bitstream file for AT40Kxx
42610: 02/04/29: Re: Hack an bitstream file for AT40Kxx
43505: 02/05/22: Re: Time for a new computer. Suggestions?
43593: 02/05/25: Re: Small FIFOs in Spartan
43594: 02/05/25: Re: Time for a new computer. Suggestions?
43792: 02/06/03: Re: Small FIFOs in Spartan
44123: 02/06/12: Re: Digital FM demodulator in FPGA-continue
45379: 02/07/21: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
48049: 02/10/10: Re: Booting a FPGA via USB
48210: 02/10/14: Re: Worlds lowest cost FPGA
48586: 02/10/21: Re: ASIC/CPLD Tradeoff
48588: 02/10/21: Re: low power embedded FPGA
61315: 03/10/02: Re: USB Core (Japanese Version)
61317: 03/10/02: Re: USB Core (Japanese Version)
61318: 03/10/02: Re: USB Core (Japanese Version)
61320: 03/10/02: Re: Counting ones
61047: 03/09/26: Re: Graphics rendering
63360: 03/11/20: Re: State Machines....
63380: 03/11/20: Re: 400 Mb/s ADC
63382: 03/11/20: Re: Small PLD choices
63440: 03/11/21: Re: 400 Mb/s ADC
63546: 03/11/25: Re: Slightly unmatched UART frequencies
64188: 03/12/19: Re: From ASIC to FPGA these days
64456: 04/01/05: Re: Hyperthreading vs. Dual proc
65629: 04/02/03: Re: 4 bit divisor with flip-flop ?
65690: 04/02/05: Re: Dual clock FIFO with Atmel FPGA ??
67550: 04/03/14: Re: copy protection on FPGA using embedded serial number
67552: 04/03/14: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
67598: 04/03/15: Re: copy protection on FPGA using embedded serial number
69126: 04/04/28: Re: Looking for a USB-enabled flash-based microcontroller with CPLD/FPGA
69766: 04/05/19: Re: Atmel Zigbee solutions
69767: 04/05/19: Re: How to replace Triscend - Xilinx plans for the future
69855: 04/05/22: Re: Atmel Zigbee solutions
70100: 04/06/02: Re: FPGA + A/D converter
71875: 04/08/03: Re: FPGA Selection--
74062: 04/10/03: Re: Open-Source MicroBlaze IP-Core working in FPGA :)
74521: 04/10/13: Re: low cost MPEG4 codec (from Atmel )
76831: 04/12/14: Re: FPGA as host for a USB peripheral
77296: 05/01/04: Re: USB JTAG programmers?
77333: 05/01/04: Re: USB JTAG programmers?
77336: 05/01/04: Re: USB JTAG programmers?
77710: 05/01/15: Re: I2C --> SPI or Parallel Port Concentrator
77793: 05/01/17: Re: USB Host
77795: 05/01/17: Re: HardCopy cost
77846: 05/01/18: Re: USB Host
77847: 05/01/18: Re: Programming and copyright
77896: 05/01/20: Re: Comparison of LEON2, Microblaze and Openrisc processors
77926: 05/01/20: Re: Comparison of LEON2, Microblaze and Openrisc processors
78325: 05/01/29: Re: Is Atmel producing Altera EPCS memories???
78345: 05/01/30: Re: Is Atmel producing Altera EPCS memories???
78526: 05/02/02: Re: Is Atmel producing Altera EPCS memories???
78571: 05/02/03: Re: Is Atmel producing Altera EPCS memories???
79144: 05/02/15: Re: SimmStick FPGA module
80068: 05/03/01: Re: FPGA interface to an asynchronous microcontroller memory bus
80209: 05/03/02: Re: Hardcopy Vs ASIC
80212: 05/03/02: Re: Hardcopy Vs ASIC
80316: 05/03/03: Re: How to get 1.8432 MHz out of 24 MHz with Sparten-3?
80317: 05/03/03: Re: programming ATF750 in ABEL
80818: 05/03/11: Re: State Machine Coding?
80837: 05/03/12: Re: low speed FIR filter in FPGA
80868: 05/03/13: Re: (Stupid/Newbie) Question on UART
80889: 05/03/14: Re: (Stupid/Newbie) Question on UART
80939: 05/03/15: Re: (Stupid/Newbie) Question on UART
81044: 05/03/17: Re: Potential Uses of Atmel FPSLIC Devices?
81045: 05/03/17: Re: Potential Uses of Atmel FPSLIC Devices?
82021: 05/04/05: Re: ISA vs. patent/trademark
82037: 05/04/06: Re: ISA vs. patent/trademark
82651: 05/04/15: Re: ISA vs. patent/trademark
86339: 05/06/25: Re: damage Atmel AT40k/AT94k with wrong bitstream?
91065: 05/10/28: Re: 24 to 32 8-bit PWM outputs
97869: 06/03/01: Re: How do I make dual-port RAM from single port RAM?
100498: 06/04/10: Re: C-Compiler for free VHDL controller core ?
101381: 06/04/30: Re: Spartan 3 documentation confusing...
102273: 06/05/13: Re: Programming the JTAG flash in circuit
104055: 06/06/17: Re: ARM cores in FPGA ?
109261: 06/09/22: Re: Dell Laptop for Embedded Work
109327: 06/09/24: Re: Dell Laptop for Embedded Work
130280: 08/03/19: Re: A Challenge for serialized processor design and implementation
130558: 08/03/27: Re: A Challenge for serialized processor design and implementation
149088: 10/09/30: Re: SDRAM for specific use - performance and timing questions
149226: 10/10/09: Re: Actel bought by Microsemi
149227: 10/10/09: Re: Why did Microsemi buy Actel?
149323: 10/10/16: Re: Actel bought by Microsemi
153032: 11/11/18: Re: Production Programming of Flash for FPGAs and MCUs
154983: 13/03/15: Re: full tcp offload solution with tcp session setup/teardown support
155093: 13/04/11: Re: IP for SDIO serial port
Ulises Hernandez:
29346: 01/02/15: Bubble tristate
29602: 01/02/28: Re: UNISIM
29867: 01/03/14: Re: bonding information
32088: 01/06/13: From EDF to VHDL?
32107: 01/06/14: Re: From EDF to VHDL?
32130: 01/06/15: Re: From EDF to VHDL?
34821: 01/09/10: Re: Clock division in Xilinx Vertex-E.
35552: 01/10/10: 155MHz to a DLL in Spartan II
35580: 01/10/11: Re: 155MHz to DLL in Spartan II
43700: 02/05/30: Can we edit an RBT Configuration file for a Xilinx FPGA?
43852: 02/06/04: Re: Can we edit an RBT Configuration file for a Xilinx FPGA?
44487: 02/06/21: StrongARM - 110 Model request
45972: 02/08/13: RBT versus BIT file
46860: 02/09/10: PowerTheatre for FPGAs?
46927: 02/09/12: Re: Saving results with modelsim
46928: 02/09/12: Re: Saving results with modelsim
47628: 02/10/01: Re: Search help about architecture of STARTUP?
47689: 02/10/02: Re: Configuration:Startup
47739: 02/10/03: Re: Configuration:Startup
47747: 02/10/03: Re: Low power design
47788: 02/10/04: Re: Configuration:Startup
47789: 02/10/04: Re: FPGA with an EPROM on it?
47797: 02/10/04: Re: Low power design
47806: 02/10/04: Re: FPGA with an EPROM on it?
47893: 02/10/07: Re: Low power design
47946: 02/10/08: Re: DDS in PLD?
47991: 02/10/09: Re: Simple Counters in Xilinx Spartan II
48001: 02/10/09: Re: Cosimulation of VHDL and Verilog Files in ISE?
48058: 02/10/10: Re: how do initialised signals really get set in Xilinx slices?
48111: 02/10/11: Re: How do i Know, which service pack i am using?
48229: 02/10/14: Re: VHDL & OBUFE8
48489: 02/10/18: Re: Cyclic Redundancy Check generator
48491: 02/10/18: Re: Cyclic Redundancy Check generator
48629: 02/10/22: Re: FPGA XC4005E
48728: 02/10/23: Re: ngdbuild - command line in xilinx' ISE tools
48784: 02/10/24: Re: ngdbuild - command line in xilinx' ISE tools
49378: 02/11/11: Re: Back annotation initialization problem
<ulkjhlk@poikj.com>:
6850: 97/07/02: !800 SERVICE AT 7.9 CENTS PER MINUTE!!!!!!
Ulrich Bangert:
88528: 05/08/22: Symmetric clocks with ALTERA Quartus
88533: 05/08/22: Re: Symmetric clocks with ALTERA Quartus
89387: 05/09/14: Re: Tree Representation of Logic Circuits
94900: 06/01/19: Re: clock generation with DOPPLER shift
101952: 06/05/09: Re: Putting the Ring into Ring oscillators
109749: 06/10/05: Re: JTAG cable @ 2.5 V - where?
110646: 06/10/19: Re: 64 bit division compensate NCO
113998: 07/01/02: Strange JTAG TCK problems with Spartan XC3S400
116382: 07/03/08: Re: Introducing picosecond delay between two output signals
121206: 07/06/28: Analogue like signal interaction within cpld possible ????
121215: 07/06/28: Re: Analogue like signal interaction within cpld possible ????
121256: 07/06/29: Re: Analogue like signal interaction within cpld possible ????
121345: 07/07/03: Re: Analogue like signal interaction within cpld possible ????
121433: 07/07/04: Re: Analogue like signal interaction within cpld possible ????
121507: 07/07/06: Re: SOLVED: Spartan-3e JTAG no device id
122273: 07/07/25: Re: tiny Spartan 3 module?
Ulrich Hack:
1433: 95/06/22: Re: Low cost CPLD/FPGA tools
Ulrich Kloidt:
70705: 04/06/24: Re: Asteroids Deluxe in an FPGA
80545: 05/03/08: Re: spartan3 development board in Europe?
80696: 05/03/10: Re: spartan3 development board in Europe?
Ulrich Langenbach:
143180: 09/09/24: Re: Virtex 4 configruation frame internal details
148861: 10/09/04: Re: debit source code
Ulrich Nageldinger [Inf.]:
8612: 98/01/13: Call for Papers: FPL-98
10900: 98/06/29: Advance Program.: 8th WS on Field-Programmable Logic FPL'98
Ulrich Seidl:
22940: 00/06/05: Virtex: How to Map 2 Functions to one Slice
Ulrich Stauss:
20042: 00/01/25: Re: FPGA to manage serial DAQ?
Ulsk:
116764: 07/03/17: Systemverilog preprocessor allow "..."?
116765: 07/03/17: Xilinx XST 9.1, Verilog 2-D arrays, always @*
116777: 07/03/17: Re: Xilinx XST 9.1, Verilog 2-D arrays, always @*
Ultimate Bob:
35412: 01/10/03: error from BUFGMUX in ModelSim??
Umair Siddiqui:
81721: 05/03/30: PID Controller implemented on FPGA
umerdarazawan:
149529: 10/11/02: EDK problem
Umesh Chandra Gowda:
8154: 97/11/21: Re: Q: HDLC packet size in V5.2
20926: 00/02/28: Re: Galois Coefficients g0,g1,...
Umesh Gowda:
9175: 98/02/27: Re: Xilinx Info.
9176: 98/02/27: Re: Xilinx Info.
Umesh Nair:
5518: 97/02/21: help!newbie question!
6321: 97/05/14: Wide edged decoders in Xilinx XC4000 series!
7222: 97/08/15: MaxPlusII from Altera.
8217: 97/11/29: Altera vs Xilinx
<umeshmgowda@gmail.com>:
112531: 06/11/24: jtag loader for picoblaze
Unbeliever:
84248: 05/05/16: Re: SPI interface cpol & cpha
84254: 05/05/16: Re: SPI interface cpol & cpha
84326: 05/05/17: Re: delays
85498: 05/06/10: Re: X-Fest devkit order leadtimes & software silliness....
85588: 05/06/11: Re: FPGAFLASH
85872: 05/06/17: Re: comp.arch.fpga.<mfr>
86690: 05/07/05: Re: Xilinx: XST synchronous FIFO using BRAMs
87107: 05/07/15: Re: Xilinx: Clock speeds 420MHz+ tested in Spartan-3
87196: 05/07/19: Re: Lattice MachXO is LAUNCHED NOW!
87204: 05/07/19: Re: Lattice MachXO is LAUNCHED NOW!
Uncle Noah:
47420: 02/09/25: Re: C\C++ to VHDL Converter
48649: 02/10/22: Re: mif /hex files for lpm models
50280: 02/12/07: Re: memory in VHDL
50649: 02/12/15: Re: EDIF LPM Support in Synthesis
51222: 03/01/07: Re: Co-simulation of Spice and Vhdl
69934: 04/05/25: Re: Nios II = Microblaze
73881: 04/09/30: Re: MicroBlaze is no available as Open-Source!! (from independant 3rd party)
93687: 05/12/28: Re: DigitalRadioMondiale
96656: 06/02/08: Re: Open Verification Libiary Free Download
102920: 06/05/23: Re: Superscalar Out-of-Order Processor on an FPGA
110173: 06/10/11: Re: Xilinx MicroBlaze 4.00.a source codes released by Xilinx !?
111214: 06/10/31: Re: FFT help
111238: 06/10/31: Re: FFT help
114599: 07/01/20: Re: SPARC V7 CORE
116593: 07/03/13: WTF? - Spartan-3E starter kit with no printed board manual?
116611: 07/03/13: Re: WTF? - Spartan-3E starter kit with no printed board manual?
120737: 07/06/15: Re: c code to initialize a peripheral
121661: 07/07/11: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121667: 07/07/11: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121670: 07/07/11: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121715: 07/07/11: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121743: 07/07/12: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
123377: 07/08/25: Overriding a VHDL generic for command-line driven synthesis with ISE
124247: 07/09/16: [ANNOUNCE] YARDstick - custom processor development toolset
124248: 07/09/16: Re: YARDstick - custom processor development toolset
124254: 07/09/16: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
124290: 07/09/17: Re: YARDstick - custom processor development toolset
124378: 07/09/19: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
124474: 07/09/23: ANNOUNCE: Embedded hw/sw developer freebies by Nikolaos Kavvadias
124517: 07/09/25: Re: Own soft-processor
124557: 07/09/26: YARDstick custom processor design tool homepage updates
124578: 07/09/26: Re: Basic questions about the Nios II.
124582: 07/09/26: Re: Basic questions about the Nios II.
124583: 07/09/26: Re: Basic questions about the Nios II.
124585: 07/09/26: Re: Basic questions about the Nios II.
125104: 07/10/16: Re: FPGA to FPGA Bus
127107: 07/12/11: Re: Craignell and Darnaw1 Website Updates
127456: 07/12/27: Xilinx XST questions
127460: 07/12/27: Re: Xilinx XST questions
127461: 07/12/27: Re: Xilinx XST questions
127478: 07/12/27: Re: Xilinx XST questions
127479: 07/12/27: Re: Xilinx XST questions
127480: 07/12/27: Re: Xilinx XST questions
128170: 08/01/17: Re: CynApps Cynlib
128986: 08/02/12: Re: XiRisc softcore processor
128987: 08/02/12: Re: XiRisc softcore processor
128988: 08/02/12: Re: XiRisc softcore processor
129035: 08/02/13: Re: XiRisc softcore processor
130640: 08/03/29: Re: Sorry to Those Who Deem This to be Spam: Employment or
unforgiven:
72059: 04/08/06: Error Using Block Ram in model sim XE 5.7
unfrostedpoptart:
77206: 04/12/29: Re: SATA/SAS designs with FPGA
88415: 05/08/17: Re: Modelsim on a remote display
90773: 05/10/20: Re: "Cannot synthesize logic..." ERROR
90899: 05/10/24: Re: Xilinx ISERDES
101102: 06/04/25: Re: clock multiplication
102262: 06/05/12: Re: ISE 7.1 synthesis problems
149812: 10/11/24: Re: System Verilog 2D input port?
Unit Manager:
39743: 02/02/18: Book Recommendation for Designing Complex System using HDL.
41467: 02/03/29: Q: Any Virtex II pro development board on market?
unknown:
136003: 08/10/27: Re: linux usb-drivers: Cable connection failed.
136135: 08/11/03: Re: blockram init file in spartan 3E
136152: 08/11/04: Re: blockram init file in spartan 3E
unknown@aol.com:
111847: 06/11/11: Re: Stratix-III announced
112558: 06/11/24: Re: Altera configuration with microcontroller
<unlogic@o2.pl>:
95588: 06/01/24: Newbie: xilinx vs arm
95745: 06/01/25: Re: Newbie: xilinx vs arm
UNO:
untergangsprophet:
142321: 09/08/04: Re: AES encryption of bitstream - is my design secure?
144052: 09/11/09: Re: Sinewave generation
144082: 09/11/10: Re: Analog power supplies to FPGAs
144808: 10/01/05: Re: How to protect my Virtex5 design without battery?
145099: 10/01/27: Re: Achronix FPGA
145126: 10/01/28: Re: DPA vs FPGA Security?
145207: 10/02/01: Re: DPA vs FPGA Security?
Uolricus:
144367: 09/12/01: Re: Going mad trying to solve PLL setup/hold timing violation issues in Quartus
7Up:
104976: 06/07/11: wrapper file error : ports not on the entity
upforever:
96936: 06/02/13: microblaze with FSL
97069: 06/02/15: Re: microblaze with FSL
97070: 06/02/15: system generator : interrupt with FSL
99346: 06/03/23: asynchronization FIFO in HDL co-simulation
<upsidedown@downunder.com>:
150485: 11/01/24: Re: Xilinx news
<uraniumore238@gmail.com>:
135332: 08/09/26: maximum clock rating
135726: 08/10/13: sensitive fpga
135733: 08/10/13: Re: sensitive fpga
136226: 08/11/07: led programming
136472: 08/11/18: spartan specifications
136697: 08/12/02: reading registers
137344: 09/01/09: spartan 3an usb connection issue
137394: 09/01/13: ttl compatible
137409: 09/01/14: Re: ttl compatible
137411: 09/01/14: Re: ttl compatible
137638: 09/01/25: picoblaze q's
137891: 09/02/02: spartan 3an lcd application doesn't work
137994: 09/02/03: Re: picoblaze q's
138193: 09/02/09: pulser problem
138205: 09/02/09: Re: pulser problem
138242: 09/02/10: Re: pulser problem
138250: 09/02/10: Re: pulser problem
138251: 09/02/10: Re: pulser problem
138255: 09/02/10: Re: pulser problem
Urban Stadler:
74283: 04/10/07: spartan 3 starter kit
74548: 04/10/13: Tristate
urielka:
96402: 06/02/03: FPGA ogg Vorbis/Theora player
urock:
141466: 09/06/25: SRAM vs Flash based FPGA one more time
Usama:
145429: 10/02/09: Running BMD design on a 64 bit machine
146850: 10/03/30: MSI for BMD design
146851: 10/03/30: MSI for BMD design
146900: 10/03/31: Multiple Interrupts Handling
147432: 10/04/27: Fpga Board detection on INTEL motherboard S5000XVN and S3210SHLC
147463: 10/04/27: Re: Fpga Board detection on INTEL motherboard S5000XVN and S3210SHLC
147465: 10/04/27: Re: Fpga Board detection on INTEL motherboard S5000XVN and S3210SHLC
147475: 10/04/28: Re: Fpga Board detection on INTEL motherboard S5000XVN and S3210SHLC
148013: 10/06/14: Power Management for PCIe
<'use_real_email'>:
138533: 09/02/26: Re: Fm digital baseband demodulation
138574: 09/02/28: Re: Fm digital baseband demodulation
138749: 09/03/07: Re: Want to buy: FPGA T-Shirt $$
138916: 09/03/14: Digital division scale
138917: 09/03/14: Re: Digital division scale
139290: 09/03/25: Re: Help Needed Regarding VPR
139929: 09/04/19: Help me I am a new techie on FPGA
139984: 09/04/22: problem with high speed data transfer
140000: 09/04/23: Re: problem with high speed data transfer
140005: 09/04/23: (Actel)Want Clock on Global Network , but input is normal I/O
140014: 09/04/23: Re: (Actel)Want Clock on Global Network , but input is normal I/O
140380: 09/05/12: Re: Which alternative prog to use for hdl handling ?
140414: 09/05/13: Re: [newbie asking] I don't like Xilinx
140516: 09/05/15: Re: Open source processors
140519: 09/05/15: Info on the JBC file
140528: 09/05/15: sdio lab testing help needed
140531: 09/05/15: Net-List Conversion
140545: 09/05/16: Re: sdio lab testing help needed
140582: 09/05/18: Re: i2c Start and stop detection
Usenet Admin:
6785: 97/06/27: Help!!
<usenet+5@ladybug.xs4all.nl>:
76763: 04/12/10: Re: Trying to get 4 LUTs, MUXF5, MUXF6 in Spartan-3
<usenet201@hotmail.com>:
20847: 00/02/24: Interfacing Xilinx PCI32 Logicore with external Dual-Port sync. SRAM?
21116: 00/03/07: setup and hold times for data during configuration (Xilinx Virtex 4000E select-map)
<usenet@zevv.nl>:
88268: 05/08/13: Re: Troubles when mapping registers into microblaze address space
<usenet_10@stanka-web.de>:
84590: 05/05/22: Re: Coloring by clock?
87611: 05/07/27: Re: Conversion of ASIC RTL to FPGA RTL
87873: 05/08/03: Re: Porting Actel code
87999: 05/08/05: Re: System Engineering in the R/D World
88087: 05/08/09: Re: sequence detection using shift register approach
88088: 05/08/09: Re: Hiding data inside a FPGA
92535: 05/12/01: Re: systemC vs VHDL
<UsenetCentralControl_comp@nacxtttol.gov>:
19866: 00/01/14: ..,,.. Warning To @Home Users - Your ISP Is SPAM CENTRAL ...,,
User:
85781: 05/06/15: Re: Availability of Spartan3
85822: 05/06/16: Re: Availability of Spartan3
user:
18023: 99/09/24: Re: F 1.5
<user@domain.invalid>:
59460: 03/08/19: Re: Which software from Xilinx
60139: 03/09/05: Re: EDK problem!
65385: 04/01/27: Re: How do I fix this type of errors?
66541: 04/02/21: Re: GZIP algorithm in FPGA
66604: 04/02/23: Re: Floating point calculation in Microblaze
67237: 04/03/09: Re: Release asynchrounous resets synchronously
67238: 04/03/09: Re: Quartus II 4.0 Web Edition Software & Documentation - Available
67271: 04/03/09: Re: Release asynchrounous resets synchronously
68967: 04/04/23: Re: SDRAM's dqm
69042: 04/04/26: Re: SDRAM's dqm
69137: 04/04/28: Re: SDRAM's dqm
69138: 04/04/28: Re: SDRAM's dqm
70376: 04/06/15: >Math Skills = >Engineer ?
73573: 04/09/24: bin hot gray jedi encoding in ISE
104429: 06/06/27: Once synthesized RAMs are vanishing in WebPACK 8.1i03
104431: 06/06/27: Re: Once synthesized RAMs are vanishing in WebPACK 8.1i03
117743: 07/04/09: Re: How do I use the Xilinx USB download cable for testing?
118424: 07/04/26: WebPACK 9.1i still makes errors with synthesis of BRAMS
118425: 07/04/26: Re: WebPACK 9.1i still makes errors with synthesis of BRAMS
119046: 07/05/10: Re: ISE 8.1.03: Bizarre MAP removes almost everything of my design!!!
119764: 07/05/25: Re: PC to JTAG
<userkan@gmail.com>:
154099: 12/08/07: Re: Burn to an internal prom Spartan-3an
154103: 12/08/08: Re: Burn to an internal prom Spartan-3an
<username@dso.org.sg>:
16298: 99/05/14: How to physically implement the fuse map of a PLA
16473: 99/05/25: LUT implementation in XC3000
16544: 99/05/27: CFI (CAD Framework Initiative) webpage - DR documentation
16615: 99/05/31: ANy good recommendations for Books on FPGA
usman yousaf:
75316: 04/11/02: FPGA : configuration
usmgn:
76241: 04/11/29: two I/O markers on the same wire
76260: 04/11/29: Re: two I/O markers on the same wire
77620: 05/01/12: Re: Looking for low-cost protoboards.
80384: 05/03/04: Re: Newby Getting started with FPGA
80812: 05/03/11: Re: FPGA tech enhancement idea for sale at ebay any takers?
<usrdr@yahoo.co.uk>:
76539: 04/12/06: xess boards
78247: 05/01/27: Pin Sort
78288: 05/01/28: Re: Pin Sort
78543: 05/02/03: Re: MP3 Player Project
78804: 05/02/08: Microblaze and Picoblaze
80422: 05/03/05: simulation and real world
80423: 05/03/05: for debugging
<UstuiosimaHuslova>:
81591: 05/03/29: C++ code to FPGA
Usuario Invitado:
5296: 97/02/05: Re: What Does ASIC Stand For?
Utente Occasionale:
5973: 97/04/01: 8051 core for XC40xx
=?UTF-8?B?44OQ44K144Ot?=:
153266: 12/01/22: MicroBlaze MCS Error.
=?utf-8?B?66eI7Ims?=:
108431: 06/09/11: What would be the best evaluation board for machin vision algo?
=?UTF-8?B?7J6E7IOB7KeE?=:
159837: 17/04/07: How to download ISPLSI 1032 and how to program it?
=?UTF-8?B?QmVuamFtaW4gTWVua8O8Yw==?=:
82219: 05/04/08: Re: Getting started with Virtex-II Pro LC Dev Board
82231: 05/04/09: Re: Getting started with Virtex-II Pro LC Dev Board
=?UTF-8?B?QWRhbSBHw7Nyc2tp?=:
155792: 13/09/05: Altera EP3CLS70U484C8N
156591: 14/05/06: Re: The USB FPGA?
156610: 14/05/13: Re: need coding
156612: 14/05/13: Re: need coding
157648: 15/01/19: Re: Altera Cyclone II
=?UTF-8?B?QWxlxaEgU3ZldGVr?=:
151313: 11/03/22: Re: SRL as a synchroniser
=?utf-8?B?R2FMYUt0SWtVc+KEog==?=:
112363: 06/11/21: Spartan-3E Starter Kit and programmable pre-Amplifier
112454: 06/11/22: Re: Virtex 4 Internal Tristate (BUFT)?
113415: 06/12/13: Energy consumption estimation of Virtex-4
117098: 07/03/22: URGENT HELP NEEDED: LVDS
117102: 07/03/22: Re: URGENT HELP NEEDED: LVDS
117164: 07/03/25: Re: URGENT HELP NEEDED: LVDS
117233: 07/03/26: Where is MIG 1.7???
117360: 07/03/29: Re: Where is MIG 1.7???
117469: 07/04/01: DCM_STANDBY macro in Virtex-4
117485: 07/04/02: Re: DCM_STANDBY macro in Virtex-4
117511: 07/04/02: Re: DCM_STANDBY macro in Virtex-4
117558: 07/04/04: MIG under Linux
117770: 07/04/10: VIrtex-4 FIFO16
118674: 07/05/01: DCIRESET in Virtex-4
120112: 07/06/01: Virtex-4 troubles after configuration
124193: 07/09/14: Is post-place and route simulation useful?
125237: 07/10/18: Dynamic Reconfiguration books
=?UTF-8?B?R8O2cmFuIEJpbHNraQ==?=:
89357: 05/09/13: Re: Microblaze & Memory DMA operation
89390: 05/09/14: Re: Microblaze & Memory DMA operation
=?UTF-8?B?R8OzcnNraSBBZGFt?=:
147740: 10/05/21: Re: Debugging SDRAM interfaces
147744: 10/05/21: Re: Debugging SDRAM interfaces
149604: 10/11/10: Altera JTAG problem
<=?UTF-8?B?R8OzcnNraSBBZGFt?=>:
105849: 06/08/02: Re: Programmable pulse generator
105868: 06/08/02: Re: Minimum frequency at which ddr can operate
105884: 06/08/02: Re: Minimum frequency at which ddr can operate
=?UTF-8?B?SGVpbnotSsO8cmdlbg==?= Oertel:
140488: 09/05/14: SGMII to MII
=?UTF-8?B?SsO8cmdlbiBCw7ZobQ==?=:
126703: 07/11/29: Re: CPU design uses too many slices
144332: 09/11/26: Re: Development boards for CPU development ?
=?UTF-8?B?THVkd2lnIEjDvGdlbHNjaMOkZmVy?=:
154325: 12/09/28: JTAG access from user design in Altera FPGAs
154331: 12/10/01: Re: JTAG access from user design in Altera FPGAs
=?UTF-8?B?TWljaGFlbCBTY2jDtmJlcmw=?=:
98296: 06/03/08: Re: The IDE interface
103594: 06/06/06: Re: Xlinix ML403 evaluation board
=?UTF-8?B?UGFsaW5kcuKYu21l?=:
108036: 06/09/04: Re: Please help me with (insert task here)
108050: 06/09/04: Re: Please help me with (insert task here)
108055: 06/09/04: Re: Please help me with (insert task here)
=?UTF-8?B?VHJ5Z3ZlIExhdWdzdMO4bA==?=:
150491: 11/01/24: Re: statement is not synthesizable since it does not hold its value
=?UTF-8?Q?Adam_G=c3=b3rski?=:
159825: 17/03/24: Re: Master Xilinx FPGA like Jtag bridge.
160481: 18/02/05: Re: Interface on board ADC to Spartan 3E startkit
160484: 18/02/08: Re: Interface on board ADC to Spartan 3E startkit
160515: 18/03/12: Re: How to handle a data packet while calculating CRC.
160522: 18/03/15: Re: How to handle a data packet while calculating CRC.
160530: 18/03/16: Re: How to handle a data packet while calculating CRC.
161050: 19/01/25: Re: Altera Cyclone replacement
=?utf-8?Q?G=C3=B6ran_Bilski?=:
124730: 07/10/02: Re: Count Leading Zero (CLZ) possible by MicroBlaze??
=?UTF-8?Q?Jan_Marjanovi=C4=8D?=:
158636: 16/02/21: Re: Where is a code example on how to use a floating multiplier on
159316: 16/10/05: Re: C to FPGA
=?UTF-8?Q?Nicholas_Collin_Paul_de_Glouce=C5=BFter?=:
152143: 11/07/13: Re: [ANN] HercuLeS high-level synthesis tool
=?UTF-8?Q?Piotr_B=C5=82achnio?=:
157076: 14/09/23: Re: Some newbe questions.
157084: 14/10/01: Re: Some newbe questions.
=?UTF-8?Q?Przemys=C5=82aw_Elias?=:
150111: 10/12/14: Re: ISIM simulation speed
utilisateur:
17761: 99/09/01: Re: Virtex BRAM Initialization
17833: 99/09/09: Re: DPRAM in Xilinx XC4000 with leonardo?
17878: 99/09/15: Re: some help required on Virtex configuration
Utku Ozcan:
6953: 97/07/15: UTOPIA?
7163: 97/08/08: PLL in Synergy?
9137: 98/02/24: Galois field
10239: 98/05/06: Re: help:DfII netlist from extracted
10968: 98/07/07: question on combinational logic synthesis for FPGA
12974: 98/11/09: placement&routing problems
13108: 98/11/16: Re: placement&routing problems
13109: 98/11/16: Re: Looking for a good documentation on FPGA
13177: 98/11/18: XNF issue
13230: 98/11/20: Re: XNF issue
14234: 99/01/21: Re: Ratings for Synplicity Synplify
14285: 99/01/23: Re: Ratings for Synplicity Synplify
14286: 99/01/23: small correction
14705: 99/02/12: Very Long Write Enable in Xilinx Dual Port RAMs
14741: 99/02/14: Re: Synplify resource usage report for Virtex devices
14829: 99/02/19: multiple clock domain problem
14854: 99/02/20: Re: multiple clock domain problem
14855: 99/02/20: Re: multiple clock domain problem
14857: 99/02/20: Re: multiple clock domain problem
15935: 99/04/22: xc40110xv data into xc40150xv
16860: 99/06/15: Xilinx DP RAM SPO Output
16902: 99/06/16: Re: Xilinx DP RAM SPO Output
17014: 99/06/24: Re: Xilinx DP RAM SPO Output
17209: 99/07/09: how to choose only a set of pins
17213: 99/07/09: Re: how to choose only a set of pins
17217: 99/07/09: Re: how to choose only a set of pins
17541: 99/08/09: Xilinx w/ClearCase
17626: 99/08/16: input offset constraint to Xilinx IOB's
17841: 99/09/11: Re: synthesis comparion between Synplify and FPGA express
17942: 99/09/18: Re: speeding up place and route
17968: 99/09/20: FF to PAD constraint in Xilinx
18190: 99/10/06: Re: Xilinx post route simulation
18238: 99/10/09: Re: RAM in xilinx FPGAs.
18239: 99/10/09: Re: RAM in xilinx FPGAs.
18424: 99/10/23: Re: Foundation 1.5i Map fatal error
18451: 99/10/25: unknown in real life
18458: 99/10/25: Re: Problem solved?
18459: 99/10/25: Re: Problem solved?
18831: 99/11/18: How to use multiple resets?
19050: 99/11/25: Re: Non-dedicated clock
18782: 99/11/15: Xilinx m2.1i Service Pack #2 installation problems
19244: 99/12/08: Re: Is there two-read one-write asynchronous SRAM in FPGA?
19247: 99/12/08: constraints between clock domains: can't advance
19294: 99/12/10: Re: constraints between clock domains: can't advance
21018: 00/03/03: Re: SpartanXL route and place
21125: 00/03/07: Re: SpartanXL route and place
21144: 00/03/08: Re: SpartanXL route and place
21187: 00/03/09: Re: I need parallel processor SIMULATOR
21882: 00/04/05: PCI Bridge to Xilinx XCV*E
21922: 00/04/07: Re: PCI Bridge to Xilinx XCV*E
21928: 00/04/07: multiprocessor support of IC design tools
21932: 00/04/07: Re: multiprocessor support of IC design tools
21954: 00/04/09: Re: multiprocessor support of IC design tools
22228: 00/05/02: Re: VDHL and ASIC people
22343: 00/05/05: Re: edif
22457: 00/05/09: Re: Nets or regs
22567: 00/05/12: Re: FPGA emulators?
22742: 00/05/22: Re: verilog modules into viewlogic designs
22773: 00/05/23: Re: Xilinx Virtex E
22821: 00/05/25: Re: Verilog assignment
22822: 00/05/25: Re: Xilinx Virtex E
22828: 00/05/25: Re: Fire Wire
23083: 00/06/13: Re: Virtex questions
23165: 00/06/16: Re: 3.1i
23625: 00/07/03: addition
23624: 00/07/03: Virtex DLL deskew of board clock with a clock/2
23704: 00/07/06: Re: Virtex DLL deskew of board clock with a clock/2
23796: 00/07/10: Re: Clock Buffer
26304: 00/10/11: Re: Computer Architecture emulator on a Xilinx chip
27204: 00/11/15: BUFT conflict with LOC
27205: 00/11/15: Re: BUFT conflict with LOC
27239: 00/11/16: Re: BUFT conflict with LOC
27244: 00/11/16: Re: BUFT conflict with LOC
27275: 00/11/17: Re: BUFT conflict with LOC
27539: 00/11/28: floorplan thru UCF fail in M2.1i
27685: 00/12/02: Re: Routing constraints & A2.1i
28405: 01/01/11: Re: grey code counters
28524: 01/01/16: Re: Xilinx UCF/ngdbuild problem
28527: 01/01/16: Re: Xilinx UCF/ngdbuild problem
28528: 01/01/16: Synplicity newsgroup?
28529: 01/01/16: Re: How to implement a 5-variable function in a CLB?
28559: 01/01/17: Re: How to implement a 5-variable function in a CLB?
28721: 01/01/22: Verilog model of Xilinx macro in VHDL Testbench fails
28741: 01/01/23: Re: Verilog model of Xilinx macro in VHDL Testbench fails
28777: 01/01/24: Re: Verilog model of Xilinx macro in VHDL Testbench fails
28787: 01/01/24: Re: Verilog model of Xilinx macro in VHDL Testbench fails
28790: 01/01/24: Re: fpga: regarding startup virtex
28934: 01/01/30: Re: Is it a timing constraint problem?
29068: 01/02/05: Re: interior timing constraints - Xilinx F1.5
29129: 01/02/07: Re: interior timing constraints - Xilinx F1.5
29458: 01/02/22: Re: clock divider by 1.5
29492: 01/02/23: Re: UCF mode for Emacs?
29750: 01/03/07: Re: SRAM fpga cell
29823: 01/03/12: Re: SRAM fpga cell
30396: 01/04/06: Re: Modlesim5.5
30476: 01/04/10: Re: Modlesim5.5
30592: 01/04/18: Re: PAR single pass vs multi-pass differences
30593: 01/04/18: Re: PAR single pass vs multi-pass differences
30607: 01/04/19: Re: PAR single pass vs multi-pass differences
30621: 01/04/19: Re: PAR single pass vs multi-pass differences
30662: 01/04/22: Re: what does it mean in fe.log?
31012: 01/05/09: Re: floorplaning and layout
31059: 01/05/10: Re: Waveforms painting
31239: 01/05/16: Re: Bizarre PAR phenomenon
31285: 01/05/17: Synplify: warnings for Verilog blackbox in VHDL
31310: 01/05/18: Re: Synplify: warnings for Verilog blackbox in VHDL
31373: 01/05/21: Synplicity newsgroup?
31396: 01/05/22: Re: Synplicity newsgroup?
31600: 01/05/31: Re: PowerPC?
32943: 01/07/12: *.SDC - *.UCF conversion table?
34053: 01/08/13: Re: Use of lpm in Xilinx Foundation 2.1i
35540: 01/10/10: Re: Who knows the news server of synplicity?
35776: 01/10/17: Re: High level synthesis will never work well :)
35874: 01/10/22: Re: About BLIF
35880: 01/10/22: Re: Verilog vs. VHDL
35969: 01/10/25: SpartanXL: DOUT or GCK6?
36143: 01/10/31: one SPROM for 2 XCS30XLs?
36798: 01/11/20: Altera: diff betw. MAX3000 and MAX7000?
37185: 01/12/03: XC17S00A programmable as XC17S00 for 2 XC2Ss?
37286: 01/12/06: Re: Timing Constraints Spartan, divided Clk
37448: 01/12/11: Re: i want "RAMB4_S1_S16.VHD"
37485: 01/12/12: Re: Constraints Some basics
37510: 01/12/13: Re: Initialization of RAM
37701: 01/12/19: Re: How to initialize the block ram of xilinx SpartanII FPGA?(Verilog)
37948: 01/12/27: vector reversed in netlist of XC9572XL
37952: 01/12/27: Re: vector reversed in netlist of XC9572XL
38141: 02/01/07: Re: simprims_ver/xilinxcorelib_ver /unisims_ver
38142: 02/01/07: Re: WARNING
38143: 02/01/07: Re: WARNING
38224: 02/01/09: Re: ADPCM?
39350: 02/02/07: toolbox.xilinx.com
39603: 02/02/14: Re: inconsistent results after place and route on xilinx XC2V3000
39643: 02/02/15: Re: par and carry chains not allowing manual floorplanning
40550: 02/03/09: Re: Xilinx ISE 4.1
40551: 02/03/09: Re: Xilinx ISE 4.1
40559: 02/03/10: Re: How can I install Xilinx ISE 4.1i under Linux?
40572: 02/03/11: promgen: unused area in with different values produce same checksum
40921: 02/03/18: Re: How do I simulate two separate designs simutaneously in ModelSim XE?
41519: 02/04/01: Re: powerpc in virtex2pro
42806: 02/05/03: Re: Modelsim 5.6 problem
43164: 02/05/15: Re: Please help me figure out serial prom problem
43346: 02/05/20: Re: Slice Usage Per Module
43564: 02/05/24: Re: Small FIFOs in Spartan
43618: 02/05/27: Re: static vs gate-level timing analysis
43656: 02/05/29: Re: Timing Analyzer lockups
43677: 02/05/29: Re: place and route simulation time
43946: 02/06/07: Re: Xilinx ise software?
44088: 02/06/11: Re: OFFSET constraint for internal clock
45212: 02/07/16: Re: Spartan PROMs...
46370: 02/08/27: Re: Export from ModelSim to Excel?
46608: 02/09/04: Synplify and FPGA Express translates clock from normal I/O differently
47089: 02/09/17: Re: Viewing internal signals during Post route simulation.
47799: 02/10/04: Re: Finding nets in hierarchy
47814: 02/10/04: Re: ANN: Embedded processor for Tcl language
47894: 02/10/07: Re: writing STAMP file for Synplify Synthesis
47939: 02/10/08: Re: STAMP Model for Coregen Outputs
47940: 02/10/08: Re: Academic FPGA Cad Tools
49058: 02/10/31: Re: From NCD to Bitstream (Xilinx FPGA)
49170: 02/11/04: Re: Learner ? - Open Collector in Verilog
49294: 02/11/08: Re: LU-decomposition
49486: 02/11/13: Re: Feedback from a 200 MHz Virtex2 design
53369: 03/03/12: unsupported switches of PAR
53389: 03/03/12: TEMPERATURE constraint in UCF
53666: 03/03/19: Re: TEMPERATURE constraint in UCF
53667: 03/03/19: Re: unsupported switches of PAR
56271: 03/06/02: Re: SONET/SDH chipset on FPGA
76660: 04/12/08: Re: Modelsim Directory
<utkudenizal@gmail.com>:
161200: 19/03/13: Green/Red detector and button controlled car (BASYS3/VHDL)
161214: 19/03/18: Color sensor with BASYS3 VHDL
161308: 19/03/26: TCS34725 Basys3 VHDL
uttam singh:
38718: 02/01/23: Internal tri state buffer..
Utthaman:
78248: 05/01/27: CFP: International Conference on Computational Intelligence and Multimedia Applications 2005-ICCIMA'05
78249: 05/01/27: CfP: Int. Conf. on Systems Engineering'05 - August 16-18, 2005 - ICSEng'05
uuyu:
87361: 05/07/22: (x86 linux) SSE2 usage by simulation applications?
uvbaz:
111200: 06/10/30: How to configuration 2 FPGAs mit one cable?
111207: 06/10/31: Re: How to configuration 2 FPGAs mit one cable?
111228: 06/10/31: Re: How to configuration 2 FPGAs mit one cable?
111576: 06/11/06: Global Clocks in Xilinx Virtex-4
111589: 06/11/06: surprised output of Xilinx Virtex-4
111598: 06/11/06: Re: surprised output of Xilinx Virtex-4
111599: 06/11/06: Re: surprised output of Xilinx Virtex-4
111633: 06/11/07: Re: surprised output of Xilinx Virtex-4
111654: 06/11/07: confused result in Logic Analyser, being crazy...
111655: 06/11/07: Re: How to generate a PROM file and then burn it on FPGA
111736: 06/11/09: Re: confused result in Logic Analyser, being crazy...
111920: 06/11/13: How to control the running of NC-Sim and Xilinx ISE under Unix?
111924: 06/11/13: Re: How to control the running of NC-Sim and Xilinx ISE under Unix?
111951: 06/11/13: Compile error by Cadence NC-Sim
111953: 06/11/13: Re: Xilinx USB cable - can't install driver
111977: 06/11/14: Re: Compile error by Cadence NC-Sim
111989: 06/11/14: Re: How to control the running of NC-Sim and Xilinx ISE under Unix?
111990: 06/11/14: Re: Compile error by Cadence NC-Sim
111992: 06/11/14: xilinx_device_details.xml <= which program create it?
112033: 06/11/15: Re: How to control the running of NC-Sim and Xilinx ISE under Unix?
112150: 06/11/17: How to use "ON NBC 12429" as clock resource of Virtex-4
116626: 07/03/14: Xilinx FPGA, OFFSET OUT AFTER
116726: 07/03/16: Re: Xilinx FPGA, OFFSET OUT AFTER
116731: 07/03/16: XILINX ISE: How to define a Internal clock and use it in OFFSET command?
119001: 07/05/09: XILINX ISE 9.1i: DELAYCHAIN by input data
Uwe:
26364: 00/10/13: How to functionally simulate Xilinx Cores in my design ?
26384: 00/10/13: Re: 5V compatible Virtex
26720: 00/10/26: Re: timing simulation with Xilinx and Fusion/SpeedWave
Uwe Bonnes:
1773: 95/08/30: Re: AMD MACH eval package ?
2272: 95/11/16: [Q] FPGA Software for Linux
3342: 96/05/16: Re: Looking for free FPGA softw./Xilinx
4152: 96/09/19: Re: Are there any FPGA Starter Kits?
4683: 96/11/29: Re: Free Evaluation VHDL Editor
4994: 97/01/09: Re: Linux & EDA at Usenix 97
5033: 97/01/14: Re: ASIC/FPGA Synthesis for LINUX... It's HERE!
5352: 97/02/10: Re: Anyone for Linux ?
5730: 97/03/11: Re: Introducing Renoir
7318: 97/08/26: Re: ANNOUNCE: VHDL Synthesis for $495
7377: 97/09/04: Re: ANNOUNCE: VHDL Synthesis for $495
9500: 98/03/19: Re: Linux and Xchecker
10197: 98/05/03: Re: Xilinx Foundation and Linux
10218: 98/05/05: Re: Xilinx Foundation and Linux
10235: 98/05/05: Re: Xilinx Foundation and Linux
11273: 98/07/31: Re: Altera tools on Linux
15111: 99/03/07: Re: Current State of FPGA-based PCI Interfaces?
17818: 99/09/07: Re: QuickLogic FPGAs
18479: 99/10/26: Re: Announcing Free VHDL Simulator for Windows
18483: 99/10/27: Re: Announcing Free VHDL Simulator for Windows
20244: 00/02/02: Re: Announcement: Xilinx on Linux HowTo
20347: 00/02/07: Re: Xilinx "WebCD" gripes
20836: 00/02/23: Re: Noise to RAM
21129: 00/03/07: Re: antifuse fpga's replacing xilinx
22226: 00/05/02: Re: Why are there no "cheap" FPGAs?
22411: 00/05/08: Non-BGA High Pin Count FPGA/CPLD
26856: 00/11/01: Re: Alliance under Linux?
28562: 01/01/17: Re: Oscillator for FPGA - low cost
31028: 01/05/09: Synplicity/Quicklogic choosing high drive input
31051: 01/05/10: Re: Synplicity/Quicklogic choosing high drive input
34664: 01/09/02: Re: DSP in OTP
35073: 01/09/20: Quicklogic Eclipse Pinout needed
35706: 01/10/14: Re: I need free PCI-Core (vhdl)!!
36349: 01/11/07: Re: FPGA suppliers for hobbyists?
39936: 02/02/22: Re: Linux tools
40098: 02/02/27: Re: Need comments on QuickWorks 9.1.
41047: 02/03/20: Re: Announce: Commercial/Non-Commercial Verilog simulator
44430: 02/06/19: Re: ATMEL CPLD
44431: 02/06/19: Re: uart code using vhdl
44527: 02/06/22: Re: Xilinx's 4.1i's Lastest webpack
44691: 02/06/27: Re: blank CPLD
44877: 02/07/03: Xilinix Webpack ChipViewer very slow
44919: 02/07/05: Setting individual slewrate on Xilinx Coolrunner II
45170: 02/07/14: Re: EDIF netlist from XST
45171: 02/07/14: Re: Webpack under Linux ?
45154: 02/07/13: Re: Webpack under Linux ?
45223: 02/07/16: Re: LVDS interface cable recommendation sought
45426: 02/07/23: Re: xilinx v ti
45460: 02/07/24: Re: Field Programmable SoC's
45477: 02/07/24: Re: 8bit Magnitude Comparator
45493: 02/07/24: Re: 8bit Magnitude Comparator
45497: 02/07/24: Re: 8bit Magnitude Comparator
45743: 02/08/03: Re: Silicon Area for Xilinx FPGAs
46452: 02/08/30: Availability of Xilinx Coolrunner II
46812: 02/09/09: Re: XCR3384XL availability
46863: 02/09/10: Xilinx Parallell Cable IV and Wine
47060: 02/09/16: Virtex II packaging, why no QFP?
47070: 02/09/16: Re: Virtex II packaging, why no QFP?
47227: 02/09/20: Re: Xilinx ISE5.1 and Windows NT
47247: 02/09/21: Re: Xilinx ISE5.1 and Windows NT
47249: 02/09/21: Re: Silicon lifetime
47253: 02/09/21: Re: Xilinx ISE5.1 and Windows NT
47254: 02/09/21: Re: Cheap development package for beginner?
47275: 02/09/22: Re: Cheap development package for beginner?
47938: 02/10/08: Re: Academic FPGA Cad Tools
48024: 02/10/09: Re: Why can Xilinx sw be as good as Altera's sw?
48289: 02/10/15: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
48508: 02/10/18: Re: Webpack4.2
48531: 02/10/19: Re: Webpack4.2
48609: 02/10/21: Re: Buy Small quantities
48809: 02/10/24: Re: Silly Virtex 2 Pro question...
48929: 02/10/27: How to interpret Xilinx synthesis report
48934: 02/10/27: Re: How to interpret Xilinx synthesis report
49050: 02/10/30: Re: Concepts: What is "Clock Edge"?
49064: 02/10/31: Re: XST Constraint
49141: 02/11/01: Re: Asynchronous clock enable with stable data
49215: 02/11/05: Re: WebPACK 5.1 SP2
49216: 02/11/05: Decoupling requirements on VREF pins (Xilinx)
49231: 02/11/05: Re: WebPACK 5.1 SP2
49234: 02/11/05: ISE for Linux: How is programming done
49235: 02/11/05: Re: Decoupling requirements on VREF pins (Xilinx)
49287: 02/11/07: Re: WebPACK 5.1 SP2
49358: 02/11/10: Re: functional test for Xilinx virtex II Pro
49592: 02/11/16: Re: Global clock routing
49789: 02/11/21: Re: XCS-05-3PC84 and XCS10-3PC84 Question
49874: 02/11/23: Re: BGA footprints
50033: 02/11/29: Re: Spartan-II 2S200 PCI Board
50037: 02/11/29: Re: Coolrunner II Voltage levels
50176: 02/12/04: [POLL] What JTAG/Configuration connector to use
50244: 02/12/06: Re: meaning of system gates vs. logic gates?
50245: 02/12/06: Re: map error:FATAL_ERROR:MapLib:basmmngm.c
50337: 02/12/09: Re: FPGA/PCI on low budget
50396: 02/12/10: Re: ISA bus VGA
50399: 02/12/10: Re: Tiny Forth Processors
50429: 02/12/10: Re: Tiny Forth Processors
50501: 02/12/11: Re: Power consumption question
50506: 02/12/11: Re: Power consumption question
50546: 02/12/12: Using smaller configuration device possible with Xilinx
50553: 02/12/12: Re: what makes an implementation a patent?
50581: 02/12/13: Re: Using smaller configuration device possible with Xilinx
50584: 02/12/13: Re: RPM Using ISE5.1i FloorPlanner
50743: 02/12/18: Re: What's the easy way to port an ISE project
50818: 02/12/20: Re: Hi xilinx
50873: 02/12/21: Re: Hi xilinx
50953: 02/12/24: Re: Combinatorial clock source question
51405: 03/01/13: Re: DLL/PLL with global clock net
51458: 03/01/14: Re: fpga versus cpld
51737: 03/01/20: Re: Problem with XST libraries.
51834: 03/01/23: Using unbonded CPLD IO Pads?
51838: 03/01/23: Re: Xilinx Impact on a SUN/Solaris
51854: 03/01/23: Re: Xilinx/Altera pricing
51953: 03/01/27: Re: Xilinx ISE 5.1 SP3: XST BUG!!!
52036: 03/01/29: Re: Random number generator
52047: 03/01/29: Re: JTAG
52071: 03/01/30: Re: JTAG
52149: 03/02/03: Re: difference between pci2.1 and pci2.2
52192: 03/02/04: Re: Difference between : CPLD , FPGA , ASICS
52409: 03/02/08: Re: Overclock Xilinx Coolrunner 2 ?
52533: 03/02/12: Re: Coolrunner II I/O speeds?
52609: 03/02/16: Re: Help wanted on Installing Xilinx on Win NT
52616: 03/02/16: Re: Help wanted on Installing Xilinx on Win NT
52797: 03/02/22: Re: spartan III what is it?
52809: 03/02/23: Re: Lpm equivalent for Xilinx devices
52851: 03/02/24: Re: Xilinx FPGA on PCI board
52852: 03/02/24: Re: Connect USB device to Spartan 2e FPGA
52877: 03/02/25: Re: config SlewRate for PCI-pads in Xilinx WebPack ??
52891: 03/02/25: Re: Licencing for downloadable FPGA tools
52903: 03/02/25: Re: Licencing for downloadable FPGA tools
52935: 03/02/26: Re: Spartan II PCB, I/O pins consederations
52967: 03/02/27: Re: xc9500 Low power mode
53003: 03/02/28: Re: 10 MHz Clock out of 30 MHz
53073: 03/03/03: Re: Spartan II PCB, bypass Capacitors
53114: 03/03/04: Re: rudimentary way to program CPLD
53238: 03/03/07: Re: Cyclone power up problem
53243: 03/03/07: Re: Xilinx ISP Header
53286: 03/03/10: Re: Time constraint of bit-stream file
53807: 03/03/24: Re: Xilinx FPGAs available?
53994: 03/03/30: Re: How can I fix module inputs
54017: 03/03/31: Re: connecting 2 FPGAs
54066: 03/04/01: Re: XC9572XL Macrocell power
54086: 03/04/02: Re: XC9572XL Macrocell power
54112: 03/04/02: Re: XC9572XL Macrocell power
54274: 03/04/07: Re: Xilinx announces 90nm sampling today!
54275: 03/04/07: Re: Xilinx V2.1i Licensing
54277: 03/04/07: Re: Spartan-3 in docsan Webpack release notes... a joke???
54292: 03/04/07: Re: price of fpga chips
54300: 03/04/07: Re: Spartan-3 in docsan Webpack release notes... a joke???
54310: 03/04/07: Re: Spartan-3 in docsan Webpack release notes... a joke???
54435: 03/04/10: Re: Webpack 5.2 and Win98se
54441: 03/04/10: Re: Webpack 5.2 and Win98se
54467: 03/04/11: Re: Xilinx IOB flip flop mapping
54468: 03/04/11: Re: Webpack 5.2 and Win98se
54562: 03/04/14: Re: ISE WebPack under Linux (use of command line tools)
54569: 03/04/14: Re: Spartan-3 in docsan Webpack release notes... a joke???
54587: 03/04/14: Re: Spartan 3, Vccaux?
54609: 03/04/14: Re: Xilinx has released SpartanIII
54715: 03/04/16: Re: ISE WebPack under Linux (use of command line tools)
54741: 03/04/17: Re: spartan2e vs cyclone
54797: 03/04/18: Re: spartan2e vs cyclone
54896: 03/04/21: Re: ISE WebPack under Linux (use of command line tools)
55011: 03/04/24: Re: Xilinx Virtex-E and PROM devices for Eagle
55031: 03/04/24: Re: bidirectional bus
55047: 03/04/25: Re: Xilinx has released SpartanIII
55068: 03/04/25: Xilinx XCF Configuration parts
55095: 03/04/26: Re: Dynamic Reconfigurable FPGAs
55160: 03/04/29: Re: general: vhdl
55199: 03/04/30: Re: Xilinx XCF Configuration parts
55234: 03/05/01: Re: mcs files
55241: 03/05/01: Re: mcs files
55398: 03/05/06: Re: I want a 800 k gates FPGA in 40 pin DIL
55409: 03/05/07: Re: spartan 3 development board
55559: 03/05/12: Re: OK I am pissed off with Xilinx webpack.
55604: 03/05/13: Re: Spartan3 DLL?
55613: 03/05/14: Re: EDK under linux/wine - xflow problem
55657: 03/05/15: Re: EDK under linux/wine - xflow problem
55686: 03/05/15: Re: CollRunner-II EVB problems
55749: 03/05/18: Re: Mini solder masks - was Re: I want a 800 k gates FPGA in 40 pin DIL
55779: 03/05/19: Re: smallest embedded cpu....and the most pain?
55970: 03/05/25: Re: Why is there a large gulf between CPLD and FPGA?
55972: 03/05/25: Re: Newbie CPLD question
55989: 03/05/26: Re: Why is there a large gulf between CPLD and FPGA?
56013: 03/05/27: Re: Xilinx Spartan download with Parallel III cable
56099: 03/05/28: Re: 5v TTL to 3.3v 2.5v 1.8v 1.2v LVTTL solution
56134: 03/05/29: Re: need help on sending 500Mbit/s data through 100 feet of cable, Giga-Ethernet?
56388: 03/06/04: Re: spartan2e vs cyclone
56413: 03/06/04: Re: spartan2e vs cyclone
56547: 03/06/09: Re: Info on Spartan-II PCI Development Kit
56557: 03/06/09: Re: Controlling FPGA speed with VCCINT
56565: 03/06/09: Re: Fixed point divider cores?
56599: 03/06/10: Re: Orcad 2 Quartus
56705: 03/06/11: Re: DVI with a Virtex-II - summary
56730: 03/06/12: Re: Analog signals connected to xilinx spartan2
56921: 03/06/19: Re: Spartan3 in WebPack
56940: 03/06/19: Re: PC-104 dev Boards
57056: 03/06/22: Re: Xilinx --> WARNING:DesignRules:372
57098: 03/06/23: Re: Programmable Delay (not clock driven)
57134: 03/06/24: Re: Xilinx ISE Webpack on Linux?
57389: 03/06/29: Re: memory
57469: 03/07/01: Re: Cyclone vs Spartan-3
57501: 03/07/01: Re: Cyclone vs Spartan-3
57529: 03/07/02: Re: VHDL variable setup and propogations
57639: 03/07/03: Re: Regarding NRZ
57641: 03/07/03: Re: XPLA3 vs. MAX3000A
57658: 03/07/03: Re: XPLA3 vs. MAX3000A
57685: 03/07/03: Re: Xilinx ISE drops support for more parts
57686: 03/07/03: Re: Xilinx ISE drops support for more parts
57714: 03/07/04: Re: Spartan-3 availability
57759: 03/07/06: Re: Spartan2E + PCI
57802: 03/07/07: Re: create JAM-File for Xilinx device
57812: 03/07/07: Re: GSR
57859: 03/07/08: Re: clock management on SPARTAN2
57906: 03/07/09: Re: clock management on SPARTAN2
58216: 03/07/17: Re: Xilinx ECS Schematic Entry
58334: 03/07/21: Re: processing `ifdef in Xilinx ISE 5.2i
58385: 03/07/22: Re: Xilinx WebPack support "dual edge clock" ??
58425: 03/07/23: Re: Floorplanner "features"
58929: 03/08/04: Re: 5 volt tolerant Xilinx parts
58939: 03/08/04: Re: 5 volt tolerant Xilinx parts
59259: 03/08/13: Re: Datasheet for National PAL20L10
59260: 03/08/13: Re: Xilinx Platform flash prom price
59647: 03/08/25: Re: What is the context switching time
59833: 03/08/29: Re: pricing, cyclone or spartan
59834: 03/08/29: Re: Selecting between two clock signals
59887: 03/08/31: Re: Parallel Cable III Problems
60193: 03/09/07: Re: Spartan 2 xc2s150
60194: 03/09/07: Re: Spartan3 multiplier
60253: 03/09/09: Re: Programming Xilinx CPLD under linux
60297: 03/09/10: Re: Spartan-3 3S50 in Web ISE 5.2i = no block RAM, no multiplier?
60580: 03/09/16: Re: USB transceiver for FPGA
60624: 03/09/17: Re: Webpack Vs. ISE
60626: 03/09/17: Re: 'RSVD' pin on V2/V2P
61080: 03/09/27: Re: Free WebPack 6.1i Download Available Now for Spartan-3
61125: 03/09/29: Re: Counting ones
61138: 03/09/29: Re: Counting ones
61141: 03/09/29: Re: Spartan 2e implementation
61283: 03/10/01: Re: Parameterized Multiplier in Xilinx FPGA
61309: 03/10/01: Re: USB Core (Japanese Version)
61342: 03/10/02: Re: Parameterized Multiplier in Xilinx FPGA
61416: 03/10/03: Re: OT: spam poll
61441: 03/10/03: Re: LVDS_25_DCI : Top Ten List
61842: 03/10/14: Re: How to select a FPGA
61891: 03/10/14: Re: SpartanXL
62105: 03/10/19: Re: ISE5.2 to ISE6.1
62437: 03/10/29: Re: Xilinx Spartan3: Price
62504: 03/10/31: Re: How to protect fpga based design against cloning?
62676: 03/11/04: Re: I/O on current FPGAs - deserialise first ??
62776: 03/11/07: Re: Shannon Entropy for Black Holes
62913: 03/11/11: Re: Implementing a very fast counterin VirtexII
63040: 03/11/13: Re: Xilinx Virtex2 tristate support
63108: 03/11/15: Re: XILINX Foundation Series 3_1i Problem with installation...
63111: 03/11/15: Re: XILINX Foundation Series 3_1i Problem with installation...
63214: 03/11/18: Re: Xilinx Design entry via Schematic Capture - What tool to use ?
63237: 03/11/18: Re: PCI interface with attached PLD
63421: 03/11/21: Re: XC9500 design does not fit into Coolrunner
63454: 03/11/21: Re: PCI interface with attached PLD
63455: 03/11/21: Re: Xilinx WebPack and Linux/WINE
63457: 03/11/21: Re: PCI interface with attached PLD
63537: 03/11/25: Re: XC9500 design does not fit into Coolrunner
63902: 03/12/08: Re: USB basic doubts
64186: 03/12/19: Re: Spartan3 availability
64211: 03/12/20: Re: Parallel Cable 4 & Linux
64225: 03/12/21: Re: Spartan3 availability
64344: 03/12/29: Re: [Spartan-IIE] Exeeding max. input rise/fall time of signals ??
64466: 04/01/05: Re: p160 connector
64505: 04/01/06: Re: Spartan3 availability
64562: 04/01/07: Re: Synthesis in VHDL vs. Verilog
64580: 04/01/08: Re: spartan 3 sample
64602: 04/01/08: Re: Large/Fast static RAM
64611: 04/01/08: Re: Large/Fast static RAM
64764: 04/01/13: Re: How to generate a CSA tree?
64812: 04/01/14: Re: Send Ethernet traffic from an FPGA
64862: 04/01/15: Re: Which version of ISE Webpack has FPGA Editor on it?
64870: 04/01/15: Re: yo, Mr. FPGA Engineer
65093: 04/01/20: Re: Which version of ISE Webpack has FPGA Editor on it?
65279: 04/01/23: Re: Spirit on Mars
65356: 04/01/26: Re: Tristate buffer
65397: 04/01/27: Re: Xilinx JTAG download under Linux (urgent)
65413: 04/01/28: Re: Spirit on Mars, upsets on Earth -- does your vendor know? How?
65420: 04/01/28: Re: Asking about FPGA-SPARTAN error in synthizer
65474: 04/01/30: Re: Where to get FPGA devices for testing?
65486: 04/01/30: Re: Where to get FPGA devices for testing?
65512: 04/01/31: Re: New USB chip for fast FPGA bitstream download
65517: 04/01/31: Re: Xilinx JTAG download under Linux (urgent)
65537: 04/02/01: Re: Differences between Xilinx ISE and Altera Quartus software
65552: 04/02/02: Re: Xilinx JTAG download under Linux (urgent)
65553: 04/02/02: Re: Differences between Xilinx ISE and Altera Quartus software
65598: 04/02/03: Re: Altera programming
65655: 04/02/04: Spartan 3 Availability again
65665: 04/02/04: Re: Spartan 3 Availability again
65674: 04/02/04: Re: Design Flow: PCI or any other high-speed PC interface ?
65704: 04/02/05: Re: Spartan 3 Availability again
65711: 04/02/05: Re: The fastest interface between FPGA's
65924: 04/02/10: Re: VHDL:Dividing a real number by two??
66039: 04/02/11: Re: Spartan-3 shipping, or perhaps not!
66067: 04/02/12: Re: How many PCB layers ?
66085: 04/02/12: Re: How many PCB layers ?
66363: 04/02/18: Re: GSR in Spartan3 ?
66369: 04/02/18: Re: GSR in Spartan3 ?
66375: 04/02/18: Re: GSR in Spartan3 ?
66383: 04/02/18: Re: GSR in Spartan3 ?
66439: 04/02/19: Re: Can FPGA bootstrap itself?
66635: 04/02/24: Re: Spartan 2 XC2S400E and XC2S600E availabillity
67460: 04/03/12: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
67604: 04/03/15: Re: low power Oscillator for Xilinx CoolrunnerII
67608: 04/03/15: Re: low power Oscillator for Xilinx CoolrunnerII
67678: 04/03/17: Re: Speed of Linux vs Solaris
67791: 04/03/19: Re: Spartan III availability ROTFL
67991: 04/03/24: Re: Fried a XC2S200!
68022: 04/03/24: Re: Time measurement with Xilinx Spartan-3 - Help
68526: 04/04/07: Re: Quartus for linux
68675: 04/04/13: Re: VirtexII : XC2V2000 Design
68688: 04/04/14: Re: Price of a Virtex-2 6000 chip...
68713: 04/04/15: Re: VirtexII : XC2V2000 Design
69066: 04/04/26: Re: OT - Generating a 20MHz clock that can be adjusted by +- 2%
69067: 04/04/26: Re: Quartus for linux
69096: 04/04/27: Re: transport applications
70184: 04/06/08: Re: Virtex-4 availability?
70398: 04/06/15: Re: >Math Skills = >Engineer ?
70470: 04/06/17: Re: Xilinx ParallelCable IV vs. Linux
70518: 04/06/18: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
70637: 04/06/22: Re: Altera Quartus II on Linux
70669: 04/06/23: Re: Family Photo Album
70749: 04/06/26: Re: 5V board in a 3.3V PCI slot
70778: 04/06/28: Re: How to add clock delay in CPLD?
70789: 04/06/28: Re: How to add clock delay in CPLD?
70876: 04/06/30: Re: Xilinx $99 Spartan-3 kit
70880: 04/06/30: Re: Xilinx $99 Spartan-3 kit
70890: 04/07/01: Re: *RANT* Ridiculous EDA software "user license agreements"?
71012: 04/07/05: Re: Linux.
71198: 04/07/12: Re: FPGA to PCI Bus Interface
71285: 04/07/13: Re: new Lattice FPGAs vs Cyclone and SpartanIII
71430: 04/07/18: Re: Xilinx 6.2i ISE WebPACK running under wine?
71510: 04/07/20: Re: Xilinx 6.2i ISE WebPACK running under wine?
71530: 04/07/21: Re: Xilinx 6.2i ISE WebPACK running under wine?
71537: 04/07/21: Re: Xilinx 6.2i ISE WebPACK running under wine?
71812: 04/07/31: Re: 1GHz FPGA counters
72527: 04/08/23: Re: Announcing JOLT - Yet Another Xilinx Programming Tool
72582: 04/08/25: Re: Any experience with Actel Flash-FPGAs ?
72594: 04/08/26: Re: ring oscillator calibration
72636: 04/08/27: Re: ring oscillator calibration
72668: 04/08/27: Re: Announcing JOLT - Yet Another Xilinx Programming Tool
72738: 04/08/31: Re: Installing Xilinx ISEWebPack under Wine
72789: 04/09/01: Re: Spartan 3 Starter Kit and ISE WebPACK
73728: 04/09/28: Re: Spartan-3 VCCIO ramp up time
73818: 04/09/29: Re: Pricing info for Synplify Pro Xilinx...
73884: 04/09/30: Re: Spartan-3 VCCIO ramp up time
73885: 04/09/30: Re: FPGA vs ASIC area
72816: 04/09/03: Re: Spartan 3 Starter Kit and ISE WebPACK
73324: 04/09/19: Re: Where are the Cyclones2
73327: 04/09/19: Re: Where are the Cyclones2
73387: 04/09/21: Re: USER RESET in XILINX FPGA
73401: 04/09/21: Re: bad nph file
73411: 04/09/21: Understanding output width in signed multipliers
73415: 04/09/21: Re: Understanding output width in signed multipliers
73461: 04/09/22: Re: USER RESET in XILINX FPGA
73462: 04/09/22: Re: Virtex 4 integrated A/Ds? Yes it does.
73486: 04/09/22: Re: spartan-3 sram
73568: 04/09/24: Re: Webpack 6.3 and Spartan3-1000/1500?
73622: 04/09/26: Re: XILINX FIX UP THE WEBPACK 6.3 DOWNLOAD !!!
73692: 04/09/28: Re: fast adder and equal
75313: 04/11/02: Re: "frying" FPGAs
75326: 04/11/02: Re: XST - Memory Problems
74161: 04/10/05: Re: XILINX FIX UP THE WEBPACK 6.3 DOWNLOAD !!!
74304: 04/10/07: Re: XILINX SHIPS ONE MILLION SPARTAN-3 FPGAS
74470: 04/10/12: Re: Actel Fusefile Reverse Engineering
74519: 04/10/13: Re: EP1C12 or XC3S400?
74726: 04/10/17: Re: which xilinx CPLD to select?
75919: 04/11/19: Re: Suggestion for Xilinx parallel port cable replacement.
75951: 04/11/20: Re: 5V PCI interface using Spartan3
76034: 04/11/23: Re: Spartan 3 output voltage level
76036: 04/11/23: Re: Spartan 3 output voltage level
76215: 04/11/29: Re: CPLD + CAN bus
76221: 04/11/29: Re: CPLD + CAN bus
76222: 04/11/29: Re: CPLD + CAN bus
77277: 05/01/03: Re: USB JTAG programmers?
77302: 05/01/04: Re: USB JTAG programmers?
77499: 05/01/08: Re: Xilinx CPLD configuration under Linux ?
77507: 05/01/08: Re: Xilinx CPLD configuration under Linux ?
77535: 05/01/10: Re: Starting with xilinix and Linux
77604: 05/01/12: Re: Starting with xilinix and Linux
77619: 05/01/12: Re: Starting with xilinix and Linux
77644: 05/01/13: Re: Starting with xilinix and Linux
77645: 05/01/13: Re: Starting with xilinix and Linux
77647: 05/01/13: Re: Starting with xilinix and Linux
77659: 05/01/13: Re: Starting with xilinix and Linux
77667: 05/01/13: Re: Starting with xilinix and Linux
77727: 05/01/15: Re: I2C --> SPI or Parallel Port Concentrator
77728: 05/01/15: Re: XST vs. Verilog Libraries
77778: 05/01/17: Re: USB Host
78505: 05/02/02: Re: See Peter's High-Wire Act next Tuesday
78586: 05/02/03: Re: LVDS without termination
79072: 05/02/13: Re: Fast counting in Spartan 3
79855: 05/02/25: Re: Altera available from Digikey
79935: 05/02/26: Re: spartan 3 vs virtex 2
79943: 05/02/26: Re: spartan 3 vs virtex 2
79944: 05/02/26: Re: spartan 3 vs virtex 2
80018: 05/02/28: Re: spartan 3 vs virtex 2
80152: 05/03/02: Re: Spartan3E
80154: 05/03/02: Xilinx ISE7.1
80156: 05/03/02: Re: Xilinx ISE history?
80160: 05/03/02: Re: Xilinx ISE history?
80557: 05/03/08: Re: Good, affordable verilog simulator
80671: 05/03/10: Re: Xilinx ISE 7.1 WebPack first impressions
80894: 05/03/14: Re: Xilinx ISE7.1
81649: 05/03/29: Re: some +. for Altera
82044: 05/04/06: Re: ISE 7.1 unisims and cver simulation
82304: 05/04/10: Re: XST -vlgincdir
82716: 05/04/16: Re: Xilinx tools from the commandline
82718: 05/04/16: Re: Xilinx tools from the commandline
82787: 05/04/18: Re: Xilinx tools on Linux
82821: 05/04/18: Re: Xilinx tools unusable on Linux
82833: 05/04/18: Re: Xilinx tools on Linux
82834: 05/04/18: Re: Xilinx tools on Linux
82843: 05/04/18: Re: source control and Xilinx ISE 6 and 7
82870: 05/04/19: Re: Xilinx tools on Linux
82922: 05/04/19: Re: Linux, ISE 7.1, problems, problems, problems ....
83027: 05/04/21: Re: Xilinx Impact in Linux 2.6.x
83379: 05/04/28: Re: Xilinx Webpack 7.1 under Wine(and libQt_Qt.dll)
83551: 05/05/02: Re: JTAG without parallel port
84148: 05/05/13: Re: Xilinx "Free ISE WebPACK 7.1i" under Fedora core 3 ?
84206: 05/05/14: Re: Xilinx "Free ISE WebPACK 7.1i" under Fedora core 3 ?
84568: 05/05/21: Re: Xilinx "Free ISE WebPACK 7.1i" under Fedora core 3 ?
84607: 05/05/23: Re: Xilinx "Free ISE WebPACK 7.1i" under Fedora core 3 ?
84857: 05/05/31: Re: Magical Mystery Tour of ISE environment variables
85220: 05/06/06: Re: Spartan 3 Starter kit group formed
85221: 05/06/06: Re: Pissed off with Xilinx - Spartan 3
86079: 05/06/21: Re: dru files for eagle ?
86292: 05/06/24: Re: Xilinx webshop
86331: 05/06/25: Re: Xilinx webshop
88354: 05/08/16: Re: Peter Alfke's SPDT Switch Debouncer
88372: 05/08/16: Re: Peter Alfke's SPDT Switch Debouncer
91342: 05/11/03: Re: Spartan-3E starter kit
91390: 05/11/04: Re: icarus verilog
91447: 05/11/07: Re: icarus verilog
91605: 05/11/09: Re: looking for FPGA pin header board
91723: 05/11/11: Re: fastest possible USB
92513: 05/11/30: Re: Supplier of Xilinx XC2V1000 or 2V250?
92887: 05/12/08: Re: How to connect 2 FPGA?
93774: 05/12/30: Re: XILINX I2C controller core in FPGA and multisource problem.
94031: 06/01/04: Re: Schematic Entry, Xilinx or Altera?
94136: 06/01/06: Re: Schematic Entry, Xilinx or Altera?
94357: 06/01/10: Re: ISE 8.1i WebPack available
94427: 06/01/11: Re: Xilinx Spartan3E Sample Pack 3rd party programing support now available
94428: 06/01/11: Re: Xilinx Spartan3E Sample Pack 3rd party programing support now available
94431: 06/01/11: Re: Webpack 8.1 device support
94442: 06/01/11: Re: Webpack 8.1 device support
94731: 06/01/17: Re: Migrating Project from Xilinx ISE 4.1 to 8.1?
94824: 06/01/18: Re: Migrating Project from Xilinx ISE 4.1 to 8.1?
95521: 06/01/23: Re: LVDS Input buffer in VHDL (ISE)
96160: 06/01/31: Re: Impact 8.1 problems=> uClinux rules on MicroBlaze !!!
96401: 06/02/03: Re: BGA central ground matrix
96904: 06/02/13: Re: [ANN] MicroBlaze uClinux FPGA module (with microwindows) at Embedded
97067: 06/02/15: Re: News from Embedded World in Nurnber
97192: 06/02/18: Re: Maxim anounce MAX3421E SPI-USB Host/Peri
97222: 06/02/19: Re: What is the best price you have gotten on for these FPGAs?
97592: 06/02/24: Re: USB 2.0 OTG in FPGA
97969: 06/03/02: Re: Help wanted
98601: 06/03/13: Re: Soldering SMT/BGA
98742: 06/03/15: Re: CSV files available for Xilinx FPGA parts pinouts?
98805: 06/03/16: Re: spartan-3e starter kit
98809: 06/03/16: Re: spartan-3e starter kit
98850: 06/03/17: Re: spartan-3e starter kit
98940: 06/03/17: Re: spartan-3e starter kit
99267: 06/03/22: Re: Xilinx programming cable; Linux notebook w/o parallel port; Am I doomed?
99497: 06/03/25: Re: Spartan-3E 500 and PCI 33/66 design
100780: 06/04/18: Re: Petition about the xilinx online store ?
101124: 06/04/26: Re: Async FPGA ~2GHz
101159: 06/04/26: Re: ISE 8.1i for Linux ?
101612: 06/05/03: Re: Interfacing Spartan 3 board to PC parallel port??
102093: 06/05/10: Re: Quartus II 6.0 available
102293: 06/05/14: Re: Spartan 3E
102297: 06/05/14: Re: Spartan 3E
102385: 06/05/15: Re: Virtex 5 announced and sampling ... and real!
102484: 06/05/16: Re: Spartan 3E
102507: 06/05/17: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
102520: 06/05/17: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
102567: 06/05/17: Re: getting good deals on small qty?
102623: 06/05/18: Re: getting good deals on small qty?
102968: 06/05/24: Re: getting good deals on small qty?
103504: 06/06/04: Re: FPGA board for USB experiments?
103567: 06/06/06: Re: Webpack larger than CDs
103668: 06/06/07: Re: IOBDELAY's delay value
103840: 06/06/13: Re: xc3sprog -- any updates?
104287: 06/06/22: Re: Spartan 3E Starter Kit - diff b/t rev. C and D?
104336: 06/06/24: Re: xc3sprog -- any updates?
104414: 06/06/27: Re: ISE WebPack 8.2
104415: 06/06/27: XC3SE available
104421: 06/06/27: Re: Number of bonded IOB's
104520: 06/06/29: Xilinx BUFGMUX Setup Time requirement clarification needed
105777: 06/07/31: Re: 100m JTAG cable
105787: 06/07/31: Re: 100m JTAG cable
105790: 06/07/31: Re: Lattice Blogs
105822: 06/08/01: Re: 100m JTAG cable
105841: 06/08/01: Re: 100m JTAG cable
105863: 06/08/02: Re: 100m JTAG cable
105908: 06/08/02: Re: generating sine-like waveforms
105958: 06/08/03: Re: generating sine-like waveforms
106077: 06/08/07: XC3SPROG, was: Re: 100m JTAG cable
106122: 06/08/08: Re: Open source Xilinx JTAG programmer with Digilent USB support
106972: 06/08/23: Re: Open source Xilinx JTAG Programmer released on sourceforge.net
107105: 06/08/24: Re: QuickLogic
107135: 06/08/24: Re: Digilent USB support from Xilinx Impact (Programmer cable SDK for Impact)
107177: 06/08/25: Re: Digilent USB support from Xilinx Impact (Programmer cable SDK for Impact)
107400: 06/08/28: Re: placing addiional caps across existing caps to reduce noise
107404: 06/08/28: Re: placing addiional caps across existing caps to reduce noise
107408: 06/08/28: Re: Spartan-4 ?
107414: 06/08/28: Re: Spartan-4 ?
108154: 06/09/06: Re: Open-source CableServer for Impact (no more need for Jungo driver on Linux)
108156: 06/09/06: Re: Open-source CableServer for Impact on sourceforge.net
108181: 06/09/06: Re: Open-source CableServer for Impact on sourceforge.net
108199: 06/09/06: Re: Open-source CableServer for Impact on sourceforge.net
108206: 06/09/06: Re: Open-source CableServer for Impact on sourceforge.net
108261: 06/09/07: Re: Open-source CableServer for Impact on sourceforge.net
108601: 06/09/13: Re: Spartan3E availability
108659: 06/09/14: Re: Spartan3: Multiplier Madness
108767: 06/09/16: Re: Spartan3 driving mosfets
108768: 06/09/16: Re: http://www.srisc.com ?
108769: 06/09/16: Re: simplyrisc-s1 free core
108771: 06/09/16: How to handle UCF file
109188: 06/09/21: Re: Dell Laptop for Embedded Work
110117: 06/10/11: Release Status of Spartan3E
110131: 06/10/11: Re: Release Status of Spartan3E
111244: 06/10/31: Re: Need just a few 5V Spartan
111260: 06/10/31: Re: Need just a few 5V Spartan
111302: 06/11/01: Re: Need just a few 5V Spartan
111344: 06/11/01: Re: Need just a few 5V Spartan
111419: 06/11/02: Re: Need just a few 5V Spartan
111788: 06/11/10: Re: Need just a few 5V Spartan
111880: 06/11/12: Re: Xilinx XC9500 Jtag instructions?
111895: 06/11/12: Re: Xilinx XC9500 Jtag instructions?
112160: 06/11/17: Re: combinatorical divide by 2 in FPGA
112162: 06/11/17: Re: Spartan 3/3E to Standard TTL/Low power devices
112414: 06/11/21: Re: Spartan 3E-Kit
112546: 06/11/24: Re: types of FPGA
113021: 06/12/05: Re: Spartan-3A launched
113025: 06/12/05: Re: Spartan-3A launched
113170: 06/12/07: Re: FPGA+Ethernet
113709: 06/12/19: Re: Slightly OT: Need a USB-to-LPT adapter for Xilinx Parallel IV Cable
114482: 07/01/17: Re: Ethernet Interface
115017: 07/01/29: Installing Webpack 9.1 on "low-memory" machine (SUSE-10.2)
115026: 07/01/29: Re: Installing Webpack 9.1 on "low-memory" machine (SUSE-10.2)
115027: 07/01/29: Re: Installing Webpack 9.1 on "low-memory" machine (SUSE-10.2)
115088: 07/01/30: Re: Differential pairs per Bank
115106: 07/01/31: Re: Differential pairs per Bank
115114: 07/01/31: Re: cpld version?
115424: 07/02/09: Re: ISE 9.1 Installation crash SuSE 10.2
115617: 07/02/15: Re: picoblaze assembler : kcpsm3.exe and wine/linux
115658: 07/02/16: Re: Do you like Virtex-5 ?
115927: 07/02/26: XC3S400 and XC3S500E in PQ208
115978: 07/02/27: Re: Spartan-3AN
115979: 07/02/27: Re: spartan 3E USB port... use for i/o instead of programming
115980: 07/02/27: Re: XC3S400 and XC3S500E in PQ208
116009: 07/02/27: Re: Spartan-3AN
116120: 07/03/01: Re: XC3S400 and XC3S500E in PQ208
116125: 07/03/01: Re: XC3S400 and XC3S500E in PQ208
116387: 07/03/08: Re: Query regarding Project.Plz help very urgent
116502: 07/03/11: Re: Design report does not show BRAM usage
116518: 07/03/12: Re: Design report does not show BRAM usage
116536: 07/03/12: Re: Design report does not show BRAM usage
116545: 07/03/12: Re: Initialization of arrays in Verilog
116851: 07/03/19: Re: Altera introduces Cyclone III devices, ships 65nm
117080: 07/03/22: Re: Xilinx Platform cable USB and impact on linux without windrvr
117374: 07/03/29: Re: Problems with Xilinx Parallel III Cable
117375: 07/03/29: Webpack 9.1 Service Pack 3
117502: 07/04/02: Re: Does the XC3S250E-VQ100 exist?
117594: 07/04/04: Re: Does the XC3S250E-VQ100 exist?
117893: 07/04/12: Re: CPLD + µC with reasonably-priced tools?
117980: 07/04/15: Pin Count requirements with MICO32
117993: 07/04/16: Re: Pin Count requirements with MICO32
118012: 07/04/16: Re: Running Xilinx 9.1 GUIs on FC6
118030: 07/04/16: Re: License Key based on WLAN/Bluetooth MAC
119101: 07/05/11: Re: Xilinx software quality - how low can it go ?!
119157: 07/05/14: Re: Xilinx software quality - how low can it go ?!
119158: 07/05/14: Re: Spartan-3A StarterKit, DDR2, WebServer EVERYTHING WORKS, tested ;)
119355: 07/05/17: Re: An Open-Source suggestion for Xilinx
119484: 07/05/21: Re: Cyclone FPGAs in Switzerland
120100: 07/06/01: Re: accesing JTAG ports on GPIOs
120239: 07/06/04: Re: Lattice XP2 finally announced
120257: 07/06/04: Re: Lattice XP2 finally announced
120267: 07/06/04: Re: xilinx parallel cable troubles
120298: 07/06/05: Re: Lattice XP2 finally announced
120912: 07/06/20: DFS to generate Frequencies slightly apart
121030: 07/06/22: Xilinx DFS woes
121039: 07/06/23: Re: Xilinx DFS woes
121043: 07/06/23: Re: Xilinx DFS woes
121046: 07/06/23: Re: Xilinx DFS woes
121057: 07/06/24: Multidimensional Register in Modul Port List
121124: 07/06/26: Re: How to choose FPGA for a huge computation?
121190: 07/06/27: Re: Bidirectional LVDS
121216: 07/06/28: How to write constraints with a clock enable?
121282: 07/06/30: Re: Bidirectional LVDS
121284: 07/06/30: Re: Xilinx programmer, many unknown devices...
121350: 07/07/03: Re: high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
121356: 07/07/03: Re: high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
121454: 07/07/04: Re: Unbuffered jtag programmer?
121915: 07/07/15: Re: spartan-3e idcode
122021: 07/07/17: Re: XC9572XL bus hold - Cant be disabled
122249: 07/07/24: Re: 3 input adder in Spartan 3E
122275: 07/07/25: Re: VCD file doesn't show anything in GtkWave
122277: 07/07/25: Re: tiny Spartan 3 module?
123340: 07/08/24: Re: Annoying
123591: 07/08/30: Re: Die size, pitch size?
123621: 07/08/31: Re: Spartan 3E - Readback via JTAG
123730: 07/09/03: Re: Spartan 3E - Readback via JTAG
123912: 07/09/06: Re: ANNC: New Boundary-Scan Software
124286: 07/09/17: Re: Altera / Lattice / Xilinx CPLDs ?
124298: 07/09/18: Re: Altera / Lattice / Xilinx CPLDs ?
124364: 07/09/19: Re: FPGA history
124471: 07/09/23: Re: Gated Clock Problems
124541: 07/09/26: Re: Never buy Altera!!!!
124864: 07/10/09: Re: JTAG interconnect testing, prototypes
124998: 07/10/15: Re: Quartus II 7.2 web edition - Linux or not?
125183: 07/10/17: Re: FPGA quiz 1&2, we have the answers and winners
125287: 07/10/19: Re: FPGA input level conversion
125295: 07/10/19: Re: FPGA input level conversion
125306: 07/10/19: Re: FPGA input level conversion
125581: 07/10/29: Re: 2 FPGAs /w programming FLASH in one JTAG chain
125884: 07/11/08: Re: Non-volatile FPGA in a small package
126271: 07/11/19: Re: Altera webpack for Linux?
126399: 07/11/21: Re: FPGA Editor (9.2.03i) under Linux x86_64
127597: 08/01/03: Re: WebPack on GNU/Linux
127630: 08/01/04: Re: Ethernet on recent FPGAs
127753: 08/01/07: Re: Processor in CPLD
127911: 08/01/10: Re: Multiple UCF support in Xilinx ISE
128257: 08/01/19: Re: Source of accurate frequency
128307: 08/01/21: Re: Fuzzy Fixed Point Calculating
128318: 08/01/22: Re: FPGA decoupling calculation
128326: 08/01/22: Re: FPGA decoupling calculation
128407: 08/01/24: Re: Virtex-4 driving a 5V CMOS
128562: 08/01/30: Re: PC requirements for ISE webpack
128598: 08/01/31: Re: PC requirements for ISE webpack
128600: 08/01/31: Re: PC requirements for ISE webpack
128895: 08/02/08: Re: impact bug or wrong interpretation of xsvf layout?
129218: 08/02/19: Re: Efficient division algorithm?
129853: 08/03/07: Spartan-3A DSP Starter: JX Connector Part number
129861: 08/03/07: Re: Spartan-3A DSP Starter: JX Connector Part number
129918: 08/03/10: Re: opencores down ?
130063: 08/03/14: Re: Xilinx S3DSP + EDK Board, too good to be true?
130076: 08/03/14: Re: Xilinx S3DSP + EDK Board, too good to be true?
130081: 08/03/14: Re: Xilinx S3DSP + EDK Board, too good to be true?
130082: 08/03/14: Re: Xilinx S3DSP + EDK Board, too good to be true?
130118: 08/03/15: Re: DDR3 speed, Altera vs Xilinx
130138: 08/03/17: Wondering about "LatticeMico32 Open Source Licensing"
130164: 08/03/17: Re: Wondering about "LatticeMico32 Open Source Licensing"
130168: 08/03/17: Re: total cost for virtex II pro FPGA
130185: 08/03/17: Re: Wondering about "LatticeMico32 Open Source Licensing"
130285: 08/03/19: Re: ISE 10.0 finally with multi-threading and SV support ?
130466: 08/03/25: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
130816: 08/04/02: Re: Xilinx ISE 10.1 Ubuntu Linux Installation - Driver Installation ?Problem
130976: 08/04/07: Re: counterfeit Xilinx ?
130984: 08/04/07: Re: system level language: why all this fuss about
131043: 08/04/08: Re: Modify POF with new ESB (ROM) content?
131044: 08/04/08: Re: 32 bit multiplier
131047: 08/04/08: Re: Disable optimisation - Ring oscillator
131054: 08/04/09: Re: Disable optimisation - Ring oscillator
131072: 08/04/09: Re: Xilinx CPLD programming tool under Linux
131088: 08/04/10: Re: Xilinx CPLD programming tool under Linux
131540: 08/04/24: Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860
132283: 08/05/20: Re: my Spartan-4 wishlist
132398: 08/05/26: Re: FPGA Programing file
132756: 08/06/06: Re: xilinx and jtag
133019: 08/06/14: Re: CPLD beginner questions
133091: 08/06/18: Re: Xilinx Webpack
133794: 08/07/15: Re: Xilinx tools in Windows or Linux - Suggestions
133795: 08/07/15: Re: Xilinx tools in Windows or Linux - Suggestions
135606: 08/10/09: Mismatch between XST and trce delay estimation
135624: 08/10/10: Re: Mismatch between XST and trce delay estimation
135979: 08/10/24: Re: Hollybush2 - Soft Core Processor Board
136322: 08/11/11: Re: How to handle the problem "timing constraint not met"?
136328: 08/11/11: How to constrain time-multiplexed pathes
136331: 08/11/11: Re: How to constrain time-multiplexed pathes
136332: 08/11/11: Re: How to handle the problem "timing constraint not met"?
136458: 08/11/17: Re: Aligned PLL clocks in RTL simulation
136633: 08/11/27: Re: Infer Dual Port Block ROM for Xilinx FPGA
136725: 08/12/03: Re: Dynamical alteration of signal path
136948: 08/12/15: Re: JTAG / IMPACT / VIRTEX
137138: 08/12/27: Re: JTAG USB interface
137600: 09/01/23: Re: Spartan-6
137632: 09/01/24: Re: Xilinx web broken again?
137899: 09/02/02: Re: Selecting a starter FPGA board
137901: 09/02/02: Re: Selecting a starter FPGA board
137918: 09/02/02: Re: Spartan-6
138221: 09/02/09: Re: Recommended Xilinx USB JTAG cable?
138224: 09/02/09: Re: Recommended Xilinx USB JTAG cable?
138498: 09/02/25: Re: Opencores DDR controller
138534: 09/02/26: Re: Send data from FPGA to PC via USB
138575: 09/02/28: Re: Where can a cheap programmer for Xilinx Virtex II XC2V1500 be ?found?
138580: 09/02/28: Re: Where can a cheap programmer for Xilinx Virtex II XC2V1500 be ??found?
138759: 09/03/09: Re: Spartan 6 3.3V (was Re: Virtex6 Virtex4 FPGA compatibility)
139537: 09/04/02: Re: Programming Digilent Nexys 2 from Linux
139544: 09/04/02: Re: Programming Digilent Nexys 2 from Linux
140091: 09/04/28: ISE 11.1 Webpack: How to install for Suse 64 Bits?
140092: 09/04/28: Re: ISE 11.1 Webpack: How to install for Suse 64 Bits?
140121: 09/04/29: Re: ISE 11.1 Webpack: How to install for Suse 64 Bits?
140785: 09/05/26: Re: 11.1 & USB cable drivers
140792: 09/05/26: Re: 11.1 & USB cable drivers
140797: 09/05/26: Re: 11.1 & USB cable drivers
141105: 09/06/05: Re: 11.1 & USB cable drivers
141328: 09/06/18: Re: ISC_DNA over JTAG in Spartan3A-DSP?
141423: 09/06/24: Re: 11.1 & USB cable drivers
141459: 09/06/24: Re: Virtex-6 shipping?
141469: 09/06/25: Re: Virtex-6 shipping?
141517: 09/06/26: Re: SPARTAN-3AN open-drain at vccio1.8V
141524: 09/06/26: Re: Using Xilinx tools with ft2232 based programming cable.
141555: 09/06/27: Re: Xilinx USB CABLE SCHEMATIC NOW OFFICIALLY PUBLISED !!!! ::) yippii ?yee
141924: 09/07/17: Re: FPGA to PC connection
141941: 09/07/18: Re: FPGA to PC connection
141949: 09/07/18: Re: FPGA editor in Fedora 11 x86_64
142023: 09/07/22: Re: building a card reader into a virtex 2 or 5 based FPGA device.
142069: 09/07/23: Re: FPGA development tools for FreeBSD?
142089: 09/07/24: Re: FPGA development tools for FreeBSD?
142090: 09/07/24: Re: FPGA development tools for FreeBSD?
142110: 09/07/25: Re: FPGA development tools for FreeBSD?
142115: 09/07/25: Re: FPGA development tools for FreeBSD?
142160: 09/07/27: Re: ISE 11 and symbolic links with linux - just a tip
142244: 09/07/30: Re: Antti-Brain, should I keep going?
142357: 09/08/05: Re: how to sign extend or round?
142463: 09/08/12: Re: Spartan-6 Boards - Your Wish List
142822: 09/09/02: Re: xc3sprog support for Altera Byteblaster
142823: 09/09/02: Re: program spartan3 under linux
142863: 09/09/04: Re: Spartan-6 boards now REALLY in online shops
142914: 09/09/08: Re: Spartan-6 boards now REALLY in online shops
142917: 09/09/08: Re: IMPACT-Xilinx Platform Cable USB II
142918: 09/09/08: Re: Spartan 3E current usage
142920: 09/09/08: Re: IMPACT-Xilinx Platform Cable USB II
142990: 09/09/13: Re: Spartan-6 - Pre-release Information on Drigmorn3.
143035: 09/09/15: Re: 8 phase clock output
143049: 09/09/17: Re: Xilinx Spartan6: ISERDES2 and BUFIO2 (xc6slx45-2csg324)
143100: 09/09/20: Re: xc3sprog
143101: 09/09/20: Re: xc3sprog
143228: 09/09/27: Re: USB programmable Open Source Hardware
143230: 09/09/27: Re: USB programmable Open Source Hardware
143242: 09/09/28: Re: USB programmable Open Source Hardware
143270: 09/09/29: SP601 HDL source files available?
143375: 09/10/07: Re: SP601 HDL source files available?
143388: 09/10/08: xc3sprog service release
143390: 09/10/08: Re: xilinx ISE 11.1 and linux (Mint) - USB drivers problems with IMPACT
143394: 09/10/09: Re: xilinx ISE 11.1 and linux (Mint) - USB drivers problems with ?IMPACT
143396: 09/10/09: Re: xilinx ISE 11.1 and linux (Mint) - USB drivers problems with ??IMPACT
143412: 09/10/10: Re: xilinx ISE 11.1 and linux (Mint) - USB drivers problems with ???IMPACT
143413: 09/10/10: Re: MCS -> BIT
143424: 09/10/11: Re: Development boards for CPU development ?
143432: 09/10/11: Re: Development boards for CPU development ?
143461: 09/10/12: Re: FPGA ruined (?)
143717: 09/10/22: Re: Time stability of clock on FPGA board
143719: 09/10/22: Re: CPLD/FPGA with Linux
143741: 09/10/23: Re: CPLD/FPGA with Linux
143920: 09/11/03: Re: SP601 HDL source files available?
143965: 09/11/05: Re: Cyclone IV announced
144071: 09/11/10: Re: XPLA3 coolrunner programming tool?
144072: 09/11/10: Re: NIOS II/e is FULLY FREE NOW !!!!
144261: 09/11/23: Re: Goal to make $30-40 Open Source Logic Analyzer with Spartan 3E.
144475: 09/12/09: Re: Cheapest way to get a chipscope compatible cable?
144489: 09/12/10: Re: Cheapest way to get a chipscope compatible cable?
144500: 09/12/11: Re: Cheapest way to get a chipscope compatible cable?
144547: 09/12/14: Re: Cheapest way to get a chipscope compatible cable?
144652: 09/12/21: Re: Please help, Xilinx FIFO problem!
144838: 10/01/07: Re: Difference among Virtex Families, FPGA Books
144942: 10/01/16: Re: CPLD programming sequence XC9500
145194: 10/02/01: Constraining minimum hold times (Xilinx)
145264: 10/02/04: Re: Constraining minimum hold times (Xilinx)
145265: 10/02/04: Re: Constraining minimum hold times (Xilinx)
145268: 10/02/04: Re: Board layout for FPGA
145332: 10/02/05: Re: Constraining minimum hold times (Xilinx)
145359: 10/02/06: Re: Constraining minimum hold times (Xilinx)
145439: 10/02/09: Spartan-3E Starter Kit reconfiguration problems
145453: 10/02/10: Re: Spartan-3E Starter Kit reconfiguration problems
145864: 10/02/26: Re: Frustration with Vendors!
146358: 10/03/14: Re: Tier Logic introduces the world's first 3D FPGA
146635: 10/03/24: Re: PROM for Spartan 6 FPGA
146649: 10/03/25: Re: PROM for Spartan 6 FPGA
146745: 10/03/27: Re: PROM for Spartan 6 FPGA
147114: 10/04/14: Re: A few LatticeMico32 questions
147692: 10/05/17: Re: Spartan 6 schedule
147726: 10/05/19: Re: Spartan 6 schedule
147771: 10/05/23: Re: Last Xilinx Webpack that was big-brother free?
147784: 10/05/24: Re: About CLB inter-slice communication in Virtex
147873: 10/05/28: Re: Anyone else need bigger parts in small (low pin count) packages
147915: 10/06/02: Re: Graphical User Interface project on Spartan-3 FPGA
148063: 10/06/17: Re: Programming the Actel Smartfusion Eval Kit in Linux
148070: 10/06/18: Re: Asynchronous FIFO in Spartan6
148101: 10/06/21: Re: Xilinx BULLSHITIX-8, when?
148140: 10/06/23: Re: Programming the Actel Smartfusion Eval Kit in Linux
148141: 10/06/23: Re: Xilinx BULLSHITIX-8, when?
148144: 10/06/23: Re: altshift_taps for Xilinx?
148147: 10/06/23: Re: Spartan-3E starter kit USB schematics ? (again)
148171: 10/06/25: Re: fooling the compiler
148182: 10/06/25: Re: Binary integer to ASCII string in HDL?
148282: 10/07/04: Re: xilinx leadtimes
148324: 10/07/07: Re: xilinx leadtimes
148450: 10/07/24: Re: Parallel Cable IV under Ubuntu Linux 10.04
148466: 10/07/26: Re: sdram stable clock
148927: 10/09/11: Re: Question about OC PCI Cores
149041: 10/09/23: Re: Virtex6 quote
149044: 10/09/23: Re: Virtex6 quote
149062: 10/09/27: Re: FPGA For Image Processing[Economical]
149167: 10/10/05: Re: Xilinx Artix 7 - When?
149171: 10/10/05: Re: Xilinx Artix 7 - When?
149178: 10/10/06: Re: Xilinx Artix 7 - When?
149574: 10/11/05: Re: PCI Parallel port detection in XILINX
149650: 10/11/13: Re: Spartan3 bidirectional 3.3V 5V level shifter
149680: 10/11/17: Re: Spartan3 bidirectional 3.3V 5V level shifter
149701: 10/11/18: Re: Does anyone have die sizes for Xilinx Virtex V devices
149713: 10/11/20: Re: Spartan3 device with long availability
149714: 10/11/20: Re: Spartan3 device with long availability
149734: 10/11/21: Re: Spartan3 device with long availability
149753: 10/11/22: Re: Spartan3 device with long availability
149785: 10/11/24: Re: Spartan3 device with long availability
150366: 11/01/12: Re: spartan 3 xc3s1000 not getting programmed
150598: 11/01/27: Re: Interfacing with a 5v micro controller
151400: 11/04/02: Re: Ideal FPGA Development Kit
151496: 11/04/13: Re: Desperately looking for XC5VFX30T-3FFG665
151499: 11/04/14: Re: Desperately looking for XC5VFX30T-3FFG665
151846: 11/05/24: Re: Fall Times and Pullup
152378: 11/08/17: Re: 5V FCT TO Cyclone II
152395: 11/08/18: Re: extracting D from 1 / D*D
152396: 11/08/18: Re: Spartan6 PCB debugging: how badly do you have to screw up for JTAG to not shift?
152532: 11/09/06: Re: interfacing Xilinx platform usb jtag with other vendor devices
152543: 11/09/09: Re: interfacing Xilinx platform usb jtag with other vendor devices
152558: 11/09/14: Re: Xilinx Tin Whiskers ?
153288: 12/01/26: Re: Open source cable server for Xilinx - for remote running of tools like Chipscope with unsopported target
153348: 12/02/04: Re: Xilinx Artix-7 availability
153548: 12/03/27: Re: FPGA communication with a PC (Windows)
153565: 12/03/28: Re: FPGA communication with a PC (Windows)
153567: 12/03/28: Re: FPGA communication with a PC (Windows)
153584: 12/04/02: Re: Ball-park price of Xilinx Virtex 7 FPGA?
153589: 12/04/03: Re: Ball-park price of Xilinx Virtex 7 FPGA?
154051: 12/07/22: Re: Interface Xilinx KC705 to BeagleBone?
155343: 13/06/24: Re: FPGA Exchange
155733: 13/08/24: Re: Lattice Announces EOL for XP and EC/P Product Lines
155798: 13/09/07: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
156215: 14/01/17: Re: my first microZed board
156335: 14/03/11: Re: Ball-park price of Xilinx Virtex 7 FPGA?
156573: 14/05/03: Re: Free alternatives to Xilinx iMPACT?
157006: 14/08/23: Re: xc3sprog
157352: 14/11/26: Re: Low-end FPGA mezzanine standard
159828: 17/03/28: Re: Divide clock frequency by 1.5: output duty cycle is not 50%
Uwe Hercksen:
115536: 07/02/13: Re: Building Coaxial transmission line on PCB?
115537: 07/02/13: Re: Building Coaxial transmission line on PCB?
115591: 07/02/14: Re: Building Coaxial transmission line on PCB?
115626: 07/02/15: Re: Building Coaxial transmission line on PCB?
115627: 07/02/15: Re: Loss Diagram
Uwe Kremmin:
1419: 95/06/20: Re: Low cost CPLD/FPGA tools
1599: 95/07/25: Re: Are the Mach210/230 programming algoritms?
3162: 96/04/17: Germany: FPGA/CPLD Developers Forum
3164: 96/04/17: Germany: FPGA/CPLD Developers Forum
Uwe Mattheyer:
76987: 04/12/18: GAL/PAL - Read the UES/AND-Array with burned Security Fuse???
<uwoief@finaledgedev.com>:
<uwuh@my-deja.com>:
25334: 00/09/06: bga->dip?
uxello:
84036: 05/05/11: Re: Any Virtex 4 development/prototyping boards out there???
86385: 05/06/27: Poor PCI performance during read accesses (in master mode)
86392: 05/06/27: Re: Poor PCI performance during read accesses (in master mode)
86409: 05/06/27: Re: Poor PCI performance during read accesses (in master mode)
87578: 05/07/26: [JTAG] How to force a FPGA to reprogram itself from a prom with JTAG
87580: 05/07/26: Re: Free 8 bit micro for fpga
87581: 05/07/26: Re: [JTAG] How to force a FPGA to reprogram itself from a prom with
<uynfdq@thecardigans.net>:
18478: 99/10/26: I Am LOSING MY FAVORITE GAME
Uzma:
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