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Update on the Technologic Systems, TS-7800 This looks like a wonderful system. But it is NOT an FPGA development board with an on-board ARM. It is a single board ARM-based computer. One of the FPGAs that they used in their design has some spare capacity. They have a way to make this available to the user. This would be great for some ... no doubt. But I'm really looking for an FPGA development board with an ARM9. The other options already mentioned are more appropriate for me. Cheers, Gil PS. They have a TS-7300 that may be a better fit, but I think the FPGA capacity may be too low for me.Article: 140076
Sorry, I forgot one more. I don't remember how I found this one. http://www.knjn.com/?pg=info&src=FPGA-FX2 The Xylo-L or Xylo-LM might also fit the bill.Article: 140077
No more Virtex-2Pro! Well there GUI is getting nicer. 6/6 Support comes in 11.2 targeted for release in june Antti Brain Issue 9/April released http://groups.google.com/group/antti-brain/files?hl=enArticle: 140078
On Apr 27, 6:39=A0am, "xdsd98123" <xdsd98...@163.com> wrote: > Hi, > > Many thanks for your time. > > I'm looking for a board to pre-process the video signal from camera. > > The followings are the features of the camera I will use: > -- The camera is of RGB type and has three separate CCD sensors. > -- The interface of 3CCD camera is not limited, can be Camera link, GigE, > 1394 or analog RGB (three channels), it depends on which kind of > development board I can use. > -- The frame rate of this camera is about 30f/s, and resolution about > 1024*768, 8/10bit. > > The followings are the features of the board I am looking for: > -- Proper interface to receive data from 3CCD camera. > -- FPGA or combination of FPGA and DSP. Combination of boards, e.g., a DS= P > kit and a plug-in FPGA board can also work. > -- Big memory and high performance. > -- Proper interface to transmit the processing result to PC: Ethernet or > USB or=85 But not PCI or PCI express. > > I didn=92t find a board with Camera link interface. And I am a litter > confused by the interface and format of camera. > -- What is the difference between composite and VGA? > --Does RGB output mean 3 analog channels corresponding to R/G/B, and each > channel has the same format with black-white camera video output and has > sync information included in each channel? > --What kind of chip do I need to transform RGB output to raw data that > FPGA can process? > > In my application, about 30 images will be received per second and I want > to use 30 images to produce an averaged image. After 30 images add togeth= er > and form one image, the board transmits it to computer online. Any > suggestions? > > I really appreciate your help. > > Danny Matrox makes some nifty frame grabber boards with on-board FPGAs which you can use for whatever you like. You can get boards with Camera Link, GigE and analog inputs. But they use PCI or PCIe to attach to the computer. USB will not keep up with your sensors if you are running at Camera Link speeds. -aArticle: 140079
>>A while ago i did some research related to capacitive touch sensing, and was really surprised to see that this function is offered by Altera as ready made solution. Hi Antti - Altera recently released a webcast on capacitive touch sensing that may be useful for your project: http://www.altera.com/education/webcasts/all/wc-2009-max-ii-z-multi-touch-screen.html It talks about upgrading resistive touch screens to multi-touch screens, using MAX IIZ CPLDs and IP functions. KatiArticle: 140080
> I need that for spartan 3, i think floorplanner doesn't support S3 > chips .. I can hardly imagine that to be the case. /MikhailArticle: 140081
gil@radix20.com a écrit : > Sorry, I forgot one more. I don't remember how I found this one. I gave it to you :-) > http://www.knjn.com/?pg=info&src=FPGA-FX2 > The Xylo-L or Xylo-LM might also fit the bill. But it is not an ARM9. Goodbye, Stéphane.Article: 140082
On Apr 27, 10:13=A0am, lolita.tang...@gmail.com wrote: > Thanks for answer. > For the ngc file, I=92m assured it=92s in the project directory and it > matches the module name from the source code (benchmark.ngc). > For the mc8051_ramx i synthesize a description VHDL and not a black > box and I don=92t know why matches its as black box. > The description when I have my problem is: > > library IEEE; > use IEEE.std_logic_1164.all; > use IEEE.std_logic_arith.all; > use IEEE.std_logic_textio.all; > =A0 --synopsys synthesis_off > library STD; > use STD.textio.all; > =A0 --synopsys synthesis_on > ------------------------ ENTITY DECLARATION ------------------------- > entity mc8051_ramx is > =A0 --synopsys synthesis_off > -- =A0generic (c_init_file : string :=3D "../DfM/test_program.dua"); > =A0 =A0 --synopsys synthesis_on > > =A0 port (clk =A0 =A0 =A0 =A0: in =A0std_logic; =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0-- clock signal > =A0 =A0 =A0 =A0 reset =A0 =A0 =A0: in =A0std_logic; =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0-- reset signal > =A0 =A0 =A0 =A0 ram_data_i : in =A0std_logic_vector(7 downto 0); =A0 -- d= ata input > =A0 =A0 =A0 =A0 ram_data_o : out std_logic_vector(7 downto 0); > =A0 =A0 =A0 =A0 ram_adr_i =A0: in =A0std_logic_vector(15 downto 0); =A0--= adresses > =A0 =A0 =A0 =A0 ram_wr_i =A0 : in =A0std_logic; =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0-- read=3D0, > write=3D1 > =A0 =A0 =A0 =A0 Bypass_TM =A0: in =A0std_logic); > end mc8051_ramx; > > architecture sim of mc8051_ramx is > --synopsys synthesis_off > =A0 type ram_type is array (65535 downto 0) of bit_vector(7 downto 0); > =A0 signal s_init : boolean :=3D false; > --synopsys synthesis_on > begin > --synopsys synthesis_off > -------------------------------------------------------------------------= ------ > -- ram_read_write > -------------------------------------------------------------------------= ------ > =A0 p_readwrite : process (clk, reset) > =A0 =A0 variable gpram =A0: ram_type; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0= -- general purpose > RAM > =A0 =A0 variable v_loop : integer; > =A0 =A0 variable v_line : line; > -- =A0 =A0file f_initfile : text is in c_init_file; tolto MG 19 Sep 06 > =A0 begin > =A0 =A0 if reset =3D '1' then > =A0 =A0 =A0 ram_data_o <=3D "00000000"; > =A0 =A0 =A0 =A0 =A0 else > =A0 =A0 =A0 if Rising_Edge(clk) then > =A0 =A0 =A0 =A0 ram_data_o <=3D to_stdlogicvector(gpram(conv_integer(unsi= gned > (ram_adr_i)))); > =A0 =A0 =A0 =A0 if ram_wr_i =3D '1' then > =A0 =A0 =A0 =A0 =A0 =A0 gpram(conv_integer(unsigned(ram_adr_i))) :=3D to_= bitvector > (ram_data_i); > =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 end if; > =A0 =A0 end if; > =A0 end process p_readwrite; > =A0 --synopsys synthesis_on > end sim; > > configuration mc8051_ramx_sim_cfg of mc8051_ramx is > =A0 =A0 for sim > =A0 =A0 end for; > end mc8051_ramx_sim_cfg; > > Regards, > lolita Remove everything in your code between "--synopsys synthesis_off" and "--synopsys synthesis_on" and you will have all of the code that will be synthesized. If there is nothing there, you end up with a "black box", i.e. the synthesis tool assumes your architecture is described some other way (EDIF or NGC). Are you trying to synthesize a simulation model? Regards, GaborArticle: 140083
On Apr 27, 1:12=A0pm, Andy Peters <goo...@latke.net> wrote: > On Apr 27, 6:39=A0am, "xdsd98123" <xdsd98...@163.com> wrote: > > > > > Hi, > > > Many thanks for your time. > > > I'm looking for a board to pre-process the video signal from camera. > > > The followings are the features of the camera I will use: > > -- The camera is of RGB type and has three separate CCD sensors. > > -- The interface of 3CCD camera is not limited, can be Camera link, Gig= E, > > 1394 or analog RGB (three channels), it depends on which kind of > > development board I can use. > > -- The frame rate of this camera is about 30f/s, and resolution about > > 1024*768, 8/10bit. > > > The followings are the features of the board I am looking for: > > -- Proper interface to receive data from 3CCD camera. > > -- FPGA or combination of FPGA and DSP. Combination of boards, e.g., a = DSP > > kit and a plug-in FPGA board can also work. > > -- Big memory and high performance. > > -- Proper interface to transmit the processing result to PC: Ethernet o= r > > USB or=85 But not PCI or PCI express. > > > I didn=92t find a board with Camera link interface. And I am a litter > > confused by the interface and format of camera. > > -- What is the difference between composite and VGA? > > --Does RGB output mean 3 analog channels corresponding to R/G/B, and ea= ch > > channel has the same format with black-white camera video output and ha= s > > sync information included in each channel? > > --What kind of chip do I need to transform RGB output to raw data that > > FPGA can process? > > > In my application, about 30 images will be received per second and I wa= nt > > to use 30 images to produce an averaged image. After 30 images add toge= ther > > and form one image, the board transmits it to computer online. Any > > suggestions? > > > I really appreciate your help. > > > Danny > > Matrox makes some nifty frame grabber boards with on-board FPGAs which > you can use for whatever you like. You can get boards with Camera > Link, GigE and analog inputs. > > But they use PCI or PCIe to attach to the computer. USB will not keep > up with your sensors if you are running at Camera Link speeds. > > -a USB might be good enough for one averaged frame every second. Alacron makes framegrabbers with all kinds of interfaces. If you really wanted an FPGA development board, however you may want to look at the boards and kits offerings on the Xilinx site. Framegrabber manufacturers aren't in the business of supporting FPGA development in general. Niche manufacturers like Alacron may be interested in doing the whole job for you if it involves using their hardware in your product. Regards, GaborArticle: 140084
On Apr 27, 12:06=A0pm, Antti <Antti.Luk...@googlemail.com> wrote: > No more Virtex-2Pro! > > Well there GUI is getting nicer. > 6/6 Support comes in 11.2 targeted for release in june > > Antti > Brain Issue 9/April releasedhttp://groups.google.com/group/antti-brain/fi= les?hl=3Den So now we get to keep 10.1 as another "classic" version for previous device support...Article: 140085
On Apr 27, 6:06=A0pm, Antti <Antti.Luk...@googlemail.com> wrote: > No more Virtex-2Pro! > > Well there GUI is getting nicer. > 6/6 Support comes in 11.2 targeted for release in june > > Antti > Brain Issue 9/April releasedhttp://groups.google.com/group/antti-brain/fi= les?hl=3Den With 6/6 you probably mean Spartan6 and Virtex6? June? That is not much time. AlesArticle: 140086
On Apr 27, 9:44=A0pm, gabor <ga...@alacron.com> wrote: > On Apr 27, 1:12=A0pm, Andy Peters <goo...@latke.net> wrote: > > > > > On Apr 27, 6:39=A0am, "xdsd98123" <xdsd98...@163.com> wrote: > > > > Hi, > > > > Many thanks for your time. > > > > I'm looking for a board to pre-process the video signal from camera. > > > > The followings are the features of the camera I will use: > > > -- The camera is of RGB type and has three separate CCD sensors. > > > -- The interface of 3CCD camera is not limited, can be Camera link, G= igE, > > > 1394 or analog RGB (three channels), it depends on which kind of > > > development board I can use. > > > -- The frame rate of this camera is about 30f/s, and resolution about > > > 1024*768, 8/10bit. > > > > The followings are the features of the board I am looking for: > > > -- Proper interface to receive data from 3CCD camera. > > > -- FPGA or combination of FPGA and DSP. Combination of boards, e.g., = a DSP > > > kit and a plug-in FPGA board can also work. > > > -- Big memory and high performance. > > > -- Proper interface to transmit the processing result to PC: Ethernet= or > > > USB or=85 But not PCI or PCI express. > > > > I didn=92t find a board with Camera link interface. And I am a litter > > > confused by the interface and format of camera. > > > -- What is the difference between composite and VGA? > > > --Does RGB output mean 3 analog channels corresponding to R/G/B, and = each > > > channel has the same format with black-white camera video output and = has > > > sync information included in each channel? > > > --What kind of chip do I need to transform RGB output to raw data tha= t > > > FPGA can process? > > > > In my application, about 30 images will be received per second and I = want > > > to use 30 images to produce an averaged image. After 30 images add to= gether > > > and form one image, the board transmits it to computer online. Any > > > suggestions? > > > > I really appreciate your help. > > > > Danny > > > Matrox makes some nifty frame grabber boards with on-board FPGAs which > > you can use for whatever you like. You can get boards with Camera > > Link, GigE and analog inputs. > > > But they use PCI or PCIe to attach to the computer. USB will not keep > > up with your sensors if you are running at Camera Link speeds. > > > -a > > USB might be good enough for one averaged frame every second. > Alacron makes framegrabbers with all kinds of interfaces. =A0If > you really wanted an FPGA development board, however you may > want to look at the boards and kits offerings on the Xilinx > site. =A0Framegrabber manufacturers aren't in the business of > supporting FPGA development in general. =A0Niche manufacturers > like Alacron may be interested in doing the whole job for > you if it involves using their hardware in your product. > > Regards, > Gabor Hi, Well, my Cameleon can be general purpose USB FPGA camera with full source code (VHDL, C) at an attractive price. And some new models are already on the drawing board. http://www.optomotive.si/ AlesArticle: 140087
Try checking out Gidel Inc. They make some StratixII cards with Cameralink, 2-4 GB memory etc. The one I'm using is based on PCIe. Their development tools are pretty good but pricey. CTW. "xdsd98123" <xdsd98123@163.com> wrote in message news:UrWdnReISb8cKGjUnZ2dnUVZ_gKdnZ2d@giganews.com... > Hi, > > Many thanks for your time. > > I'm looking for a board to pre-process the video signal from camera. > > The followings are the features of the camera I will use: > -- The camera is of RGB type and has three separate CCD sensors. > -- The interface of 3CCD camera is not limited, can be Camera link, GigE, > 1394 or analog RGB (three channels), it depends on which kind of > development board I can use. > -- The frame rate of this camera is about 30f/s, and resolution about > 1024*768, 8/10bit. > > The followings are the features of the board I am looking for: > -- Proper interface to receive data from 3CCD camera. > -- FPGA or combination of FPGA and DSP. Combination of boards, e.g., a DSP > kit and a plug-in FPGA board can also work. > -- Big memory and high performance. > -- Proper interface to transmit the processing result to PC: Ethernet or > USB or. But not PCI or PCI express. > > I didn't find a board with Camera link interface. And I am a litter > confused by the interface and format of camera. > -- What is the difference between composite and VGA? > --Does RGB output mean 3 analog channels corresponding to R/G/B, and each > channel has the same format with black-white camera video output and has > sync information included in each channel? > --What kind of chip do I need to transform RGB output to raw data that > FPGA can process? > > In my application, about 30 images will be received per second and I want > to use 30 images to produce an averaged image. After 30 images add > together > and form one image, the board transmits it to computer online. Any > suggestions? > > I really appreciate your help. > > Danny > > >Article: 140088
On Apr 27, 10:46=A0pm, gabor <ga...@alacron.com> wrote: > On Apr 27, 12:06=A0pm, Antti <Antti.Luk...@googlemail.com> wrote: > > > No more Virtex-2Pro! > > > Well there GUI is getting nicer. > > 6/6 Support comes in 11.2 targeted for release in june > > > Antti > > Brain Issue 9/April releasedhttp://groups.google.com/group/antti-brain/= files?hl=3Den > > So now we get to keep 10.1 as another "classic" version for > previous device support... yes, can so say. 10.1 is now member of the "ISE Classics"... AnttiArticle: 140089
On Apr 27, 6:06=A0pm, Antti <Antti.Luk...@googlemail.com> wrote: > No more Virtex-2Pro! > > Well there GUI is getting nicer. > 6/6 Support comes in 11.2 targeted for release in june > > Antti > Brain Issue 9/April releasedhttp://groups.google.com/group/antti-brain/fi= les?hl=3Den Well, isn't that nice? I opened a case two weeks ago, the guy said wait for the 11.1 release, its been fixed there. Great, but I need Spartan 2, not 666Article: 140090
On Apr 28, 10:21=A0am, aleksa <aleks...@gmail.com> wrote: > On Apr 27, 6:06=A0pm, Antti <Antti.Luk...@googlemail.com> wrote: > > > No more Virtex-2Pro! > > > Well there GUI is getting nicer. > > 6/6 Support comes in 11.2 targeted for release in june > > > Antti > > Brain Issue 9/April releasedhttp://groups.google.com/group/antti-brain/= files?hl=3Den > > Well, isn't that nice? > > I opened a case two weeks ago, the guy said wait for the 11.1 release, > its been fixed there. Great, but I need Spartan 2, not 666 be happy! it is FIXED, no supported, not an issue! for Xilinx... it is huge cost savings (for Xilinx) to drop S2/V2 support.. so it is understandable the move i wonder if the "Everything changes" means that 11.2 drops support for 3,4,5 and has only 6/6? that would be even more savings in support cost AnttiArticle: 140091
Software_matrix.pdf for Xilinx ISE 11.1 lists "SUSE Linux Enterprise 10* 64-bit" supported for webpack. Downloading the whole file Xilinx_11.1_WebPack_SFD.tar, untarring and running ./xsetup gives "Product is not supported on "Linux x86_64" platform" as with 10.1, and there is no bin/lin64 as required by xsetup. What counts? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 140092
Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote: > Software_matrix.pdf for Xilinx ISE 11.1 lists "SUSE Linux Enterprise 10* > 64-bit" supported for webpack. Downloading the whole file > Xilinx_11.1_WebPack_SFD.tar, untarring and running ./xsetup gives > "Product is not supported on "Linux x86_64" platform" as with 10.1, and there > is no bin/lin64 as required by xsetup. > What counts? http://www.xilinx.com/ise/ossupport/index.htm Argh: Differing information on the same subject... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 140093
On Apr 28, 2:19=A0pm, Uwe Bonnes <b...@elektron.ikp.physik.tu- darmstadt.de> wrote: > Uwe Bonnes <b...@elektron.ikp.physik.tu-darmstadt.de> wrote: > > Software_matrix.pdf for Xilinx ISE 11.1 lists "SUSE Linux Enterprise 10= * > > 64-bit" supported for webpack. =A0Downloading the whole file > > Xilinx_11.1_WebPack_SFD.tar, untarring and running ./xsetup gives > > "Product is not supported on "Linux x86_64" platform" as with 10.1, and= there > > is no bin/lin64 as required by xsetup. > > What counts? > > http://www.xilinx.com/ise/ossupport/index.htm > > Argh: Differing information on the same subject... > -- > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-dar= mstadt.de > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- why should web pack user need 64 bit O/S ?? (is what xilinx marketing thinks...) AnttiArticle: 140094
Andy Peters <google@latke.net> writes: > Matrox makes some nifty frame grabber boards with on-board FPGAs which > you can use for whatever you like. You can get boards with Camera > Link, GigE and analog inputs. Interesting. Is this the Vio? Do you know if it can handle 1080p/60? What kind of FPGA? Does it have a digital input (HDMI) as well? > But they use PCI or PCIe to attach to the computer. USB will not keep > up with your sensors if you are running at Camera Link speeds. Even better. I'm looking for something which can be used as a frame grabber to store uncompressed frames on harddisk, but presumably at least 1080p/60fps. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 140095
On Apr 28, 12:27=A0am, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > On Apr 28, 10:21=A0am, aleksa <aleks...@gmail.com> wrote: > > > On Apr 27, 6:06=A0pm, Antti <Antti.Luk...@googlemail.com> wrote: > > > > No more Virtex-2Pro! > > > > Well there GUI is getting nicer. > > > 6/6 Support comes in 11.2 targeted for release in june > > > > Antti > > > Brain Issue 9/April releasedhttp://groups.google.com/group/antti-brai= n/files?hl=3Den > > > Well, isn't that nice? > > > I opened a case two weeks ago, the guy said wait for the 11.1 release, > > its been fixed there. Great, but I need Spartan 2, not 666 > > be happy! it is FIXED, no supported, not an issue! > for Xilinx... > > it is huge cost savings (for Xilinx) to drop S2/V2 support.. > so it is understandable the move > > i wonder if the "Everything changes" means that 11.2 drops support for > 3,4,5 and has only 6/6? > that would be even more savings in support cost > > Antti Does anyone actually care about Spartan 6? Where's the non-volatile version? We like the Spartan 3AN, but it does suck big-time that each device has its own package and you can't go from 200 to 400 and stay in the same footprint. Oh, and FlexLM? thanks for making your customers HATE you, Xilinx. -aArticle: 140096
On Apr 28, 7:11=A0am, Petter Gustad <newsmailco...@gustad.com> wrote: > Andy Peters <goo...@latke.net> writes: > > Matrox makes some nifty frame grabber boards with on-board FPGAs which > > you can use for whatever you like. You can get boards with Camera > > Link, GigE and analog inputs. > > Interesting. Is this the Vio? Do you know if it can handle 1080p/60? I have a Solios eCL (digital Camera Link) in my development machine and we use both Solios and Helios cards. Medium CL supports up to 85 MHz pixel clock with a variety of pixel formats. There's not enough bandwidth for 1080p/60 but it can do 30 no problem. > What kind of FPGA? Does it have a digital input (HDMI) as well? The Processing FPGA is an Altera Stratix. No support for HDMI, as far as I know. Do any cameras have HDMI outputs? (If so, why?) -aArticle: 140097
On Apr 28, 8:25=A0pm, Andy Peters <goo...@latke.net> wrote: > On Apr 28, 12:27=A0am, "Antti.Luk...@googlemail.com" > > > > <Antti.Luk...@googlemail.com> wrote: > > On Apr 28, 10:21=A0am, aleksa <aleks...@gmail.com> wrote: > > > > On Apr 27, 6:06=A0pm, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > No more Virtex-2Pro! > > > > > Well there GUI is getting nicer. > > > > 6/6 Support comes in 11.2 targeted for release in june > > > > > Antti > > > > Brain Issue 9/April releasedhttp://groups.google.com/group/antti-br= ain/files?hl=3Den > > > > Well, isn't that nice? > > > > I opened a case two weeks ago, the guy said wait for the 11.1 release= , > > > its been fixed there. Great, but I need Spartan 2, not 666 > > > be happy! it is FIXED, no supported, not an issue! > > for Xilinx... > > > it is huge cost savings (for Xilinx) to drop S2/V2 support.. > > so it is understandable the move > > > i wonder if the "Everything changes" means that 11.2 drops support for > > 3,4,5 and has only 6/6? > > that would be even more savings in support cost > > > Antti > > Does anyone actually care about Spartan 6? Where's the non-volatile > version? We like the Spartan 3AN, but it does suck big-time that each > device has its own package and you can't go from 200 to 400 and stay > in the same footprint. > > Oh, and FlexLM? thanks for making your customers HATE you, Xilinx. > > -a oh, yes, I forgot the FlexLM, this is what customers REALLY do HATE what I did not like with Altera was their licensing, but recenty they changed their policy and Quartus web edition can be downloaded and installed without any license request or registration at all. This is so cool. Spartan-3A is was the first almost nice Xilinx FPGA, but the 3 family is too clustered, while each of them has some good features, and each of them lucks some, making it impossible to choose the right device as you need features from different sub families.. what is major problem with S-6 is the security, that is no security - design cloning is a problem, specially for the lower end, this has been recognized by other vendors offering key encryption in the low cost families. Xilinx is the only one with no such features offered. the Device DNA really isnt an option. AnttiArticle: 140098
Antti.Lukats@googlemail.com <Antti.Lukats@googlemail.com> wrote: >> Uwe Bonnes <b...@elektron.ikp.physik.tu-darmstadt.de> wrote: >> > Software_matrix.pdf for Xilinx ISE 11.1 lists "SUSE Linux Enterprise 10* >> > 64-bit" supported for webpack. ?Downloading the whole file >> > Xilinx_11.1_WebPack_SFD.tar, untarring and running ./xsetup gives >> > "Product is not supported on "Linux x86_64" platform" as with 10.1, >> > and there is no bin/lin64 as required by xsetup. I have 9.2 running on Scientific Linux 5.2 x86_64. In the end, I installed it on an IA32 machine then copied the files over. Other than the install script test, I believe the problem is related to selinux (security system). After copying over the installed version I got selinux messages. It seems that the problem is related to self relocation (as in self-modifying code) of DLLs. That violates some of the security tests. In the case of the installer, it doesn't run at all. In the case of installed ISE it starts up, but gives errors when some other programs are called. There is a fix, which turns off the security test for those DLLs. I haven't tried 11.1 yet, but I suspect the same problem. > why should web pack user need 64 bit O/S ?? > (is what xilinx marketing thinks...) That is what I thought, too. As 64 bit hardware is very affordable, and 64 bit linux is the same price, unless one is dedicating hardware to ISE, it is likely that one will want to run the IA32 version on x86_64 systems. The linux web pages indicate that the problem should be fixed by the vendor. I haven't found the right person to ask yet. -- glenArticle: 140099
Ok, my electrical non-background is showing. So I've got some pins that I'm driving and all is well on a Spartan3e. looking at the pins on the scope, they sit at 0 volts for a '0' and looks like 3.3v on a '1' Now the only inputs I use are on pins 11 and 12, and the UCF looks like this: NET "BUTTON_1" LOC = "F12" | PULLUP ; #"FPGA_IO17" pin 11 NET "BUTTON_2" LOC = "F14" | PULLUP ; #"FPGA_IO18" pin 12 NET "PIN13_LED" LOC = "F2"; #"FPGA_IO19" driven output. Now the way the buttons work is on the scope they show 3.3 volts, and I have them hooked up to a normally open momentary switch that will attach this signal to ground when closed. When I push the button (viz "pull to ground"????) the button, the VHDL program recognizes the signal as a switch from 0 to 1 (give or take a debounce) Now when I put a scope on my input pin, I see it is up at 3.3 volts, and when the button is pushed, it drops to 0. It seems to me this is not a good setup for using one of my output pins attached to one of my inputs. At some point both pins have 3.3 volts on them, and those two wires are attached. My question is if I want to take my driven output and run it around as an input signal, how do I do that? Thanks, Jon
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