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"Niv (KP)" <kev.parsons@mbda-systems.com> wrote in message
news:58b23b74-8594-4a6b-b4da-d14c69ad697c@j18g2000yql.googlegroups.com...
> On 11 Apr, 15:32, Rob <noth...@nowhere.com> wrote:
>> sorry for the multiple posts--a quirk with my system..
>>
>>
>>
>> Niv (KP) wrote:
>> > My stratix3 design simulates OK at RTL & gate-level.
>>
>> > On the PCB however, an internal module fails to read some M9K RAMS
>> > properly all the time
>> > when I connect an input signal to the chip, but which has nothing to
>> > do with the failing module.
>>
>> > Are there any crosstalk/noise issues with Strarix3 devices that anyone
>> > has encountered?
>>
>> > Basically, the s/w guys are testing the system and getting a lot of
>> > errors on reading this particular RAM,
>> > but removing this un-related signal (relative o the RAMs in question)
>> > reduces the error count a lot. (but not totally, apparently, possibly
>> > another signal also affecting?).
>>
>> > I have not floorplanned the design, but let Quartus do whatever it
>> > wanted routing wise to meet timing and pin-out.
>>
>> > Regards, Kev P.- Hide quoted text -
>>
>> - Show quoted text -
>
> It would seem a bug was in the VHDL code, a simple mistake and easy to
> overlook.
> eg;
> IF address = ("000" OR "101") THEN
> -- do something.
>
> Should have been;
>
> IF (address = "000") OR (address = "101") THEN
> -- do something.
>
> Not my code, but I was one of 3 reviewers, and we all missed it!!
ahhhh the ease, speed, accuracy and visibility of designing with words!
Article: 140051whygee wrote: > russ wrote: >> Thanks for the response, but that choice isn't there. > sorry, i'm too lazy to turn the viscrap computer on and take screenshots. > The dialog has maybe changed with the newer version of libero... > But I found the trick, I believe that others can too ? > > maybe antti will help ? /o\ > >> BTW, I did the counter tutorial from Actel and got 8 warnings. It >> doesn't seem to have much practical impact, but the process says no >> errors no warnings. Is there something that is expected to be in the >> top file? > The "top" file defines all the I/O that will be tied to the physical > pins of the FPGA. It is important because that is where the synthesizer, > place&route tools will pick the pins and assign the functions (clock, > global resets etc) according to the available resources in the chosen chip. > > It took me about a month or two to get used to this software, > with its limitations and quirks, but it works for my needs > and it was worth the efforts and expense. I wish the same to you too. > > yg > Interesting. The tutorial seems to hint that the file must be named top.vhd. Is that correct?Article: 140052
On 25 Apr, 12:40, "KJ" <kkjenni...@sbcglobal.net> wrote: > > It would seem a bug was in the VHDL code, a simple mistake and easy to > > overlook. > > That's why simulation is an important step > > > Not my code, but I was one of 3 reviewers, and we all missed it!! > > That's why reviews are less important than good simulation practices. > > KJ It worked in the simulation environment, that's why it was hard to find.Article: 140053
"Niv (KP)" <kev.parsons@mbda-systems.com> wrote in message
news:7278fbcb-3358-4de5-b3c7-4f6f589ceff5@m19g2000yqk.googlegroups.com...
> On 25 Apr, 12:40, "KJ" <kkjenni...@sbcglobal.net> wrote:
>> > It would seem a bug was in the VHDL code, a simple mistake and easy to
>> > overlook.
>>
>> That's why simulation is an important step
>>
>> > Not my code, but I was one of 3 reviewers, and we all missed it!!
>>
>> That's why reviews are less important than good simulation practices.
>>
>> KJ
>
> It worked in the simulation environment, that's why it was hard to
> find.
So you're saying you actually tested the condition where address is set to
"000" and it worked in simulation?
If a simulator didn't catch the difference between this
IF address = ("000" OR "101") THEN
and this...
IF (address = "000") OR (address = "101") THEN
It's because
- You didn't actually simulate the condition where address is set to "000"
- The 'if' statement is in a non-clocked process with an incorrect
sensitivity list
- Your simulator isn't working, get a new one
I'd suggest getting to the root cause of why this didn't get caught in
simulation to figure out what is lacking in your design process that let the
design error get through.
KJ
Article: 140054On Apr 25, 3:11=A0pm, russ <lytt...@gmail.com> wrote: > whygee wrote: > > russ wrote: > >> Thanks for the response, but that choice isn't there. > > sorry, i'm too lazy to turn the viscrap computer on and take screenshot= s. > > The dialog has maybe changed with the newer version of libero... > > But I found the trick, I believe that others can too ? > > > maybe antti will help ? /o\ > > >> BTW, I did the counter tutorial from Actel and got 8 warnings. It > >> doesn't seem to have much practical impact, but the process says no > >> errors no warnings. Is there something that is expected to be in the > >> top file? > > The "top" file defines all the I/O that will be tied to the physical > > pins of the FPGA. It is important because that is where the synthesizer= , > > place&route tools will pick the pins and assign the functions (clock, > > global resets etc) according to the available resources in the chosen c= hip. > > > It took me about a month or two to get used to this software, > > with its limitations and quirks, but it works for my needs > > and it was worth the efforts and expense. I wish the same to you too. > > > yg > > Interesting. The tutorial seems to hint that the file must be named > top.vhd. Is that correct? doesnt really matter, it USUALLY auto detect the top level entity unless you do something that prevents the auto detect to work and then you need to specify by hand AnttiArticle: 140055
russ a utilisé son clavier pour écrire : > I'm learning Actel and started a simple 4-bit adder project. I get the > following on the Synthesis step : > > @W: BN246 |Failed to find top level module 'work.adder' as specified in > project file > This a dummy warning from Synplify, just ignore it. If you want to take a tour of the tools, I've made available a nice Tutorial covering most of the Design Flow steps with example files (abnd even how to get & install the design software). See : http://www.alse-fr.com/Actel/igloo.html and http://www.alse-fr.com/Actel/ALSE_Igloo_nano.exe BertArticle: 140056
I have been trying to simulate a direct interface to Actel's Soft FIFO Controller, and so far no luck. The FIFO Empty/Full signals, outputs, and memory contents are undefined, and Modelsim gives me a bunch of warnings: BLKA and BLKB unknown, and illegal addresses on the RAM ports. Anyone had any success in simulating the Soft FIFO? Cheers, SteveArticle: 140057
Steve, You don't give us much to think about & help you. - Libero Version 8.5 sp1 ? (& msim ae 6.4c?) - Which target (device family) ? - Which language : Verilog, SystemVerilog, VHDL ? - Which Smartgen macro ? - was it properly reset with a pulse ? - which simulation ? RTL ? postmap ? post-layout ? - what is your test bench ? As the tech supports usually ask, it's best to provide a simple test case... hard to guess otherwise. Bert CuzeauArticle: 140058
A while ago i did some research related to capacitive touch sensing, and was really surprised to see that this function is offered by Altera as ready made solution. today i was looking at ambient light measurement solutions. and on the first google search page i found this http://www.altera.com/literature/wp/wp-01076-led-driver-reduces-power-adjusting-intensity-ambient-light.pdf cool. really... no need to think, just look at stuff altera has prepared for its customers. hm.. maybe i should make some cool stuff with Altera ICs? and.. OI I have been so stupid.. with my two last FPGA designs, me idiot -- i did connect the on board LED one side to the GND!! it could have been possible i did even think about it, hm maybe i did, but did not implement it. Well the routing was complicated so connecting to gnd was easier never again, when adding a LED to the FPGA board will always connect it between 2 IO's then the same LED can be used as input or output device :) using a LED as sensor when polarity can not be changed doesnt work at all, or well, i tried once the pin oscillator without changing polarity and got no light sensing (or almost none) AnttiArticle: 140059
On Apr 26, 6:37=A0pm, Bert_Paris <do_not_spam_@me> wrote: > Steve, > You don't give us much to think about & help you. > - Libero Version 8.5 sp1 ? (& msim ae 6.4c?) > - Which target (device family) ? > - Which language : Verilog, SystemVerilog, VHDL ? > - Which Smartgen macro ? > - was it properly reset with a pulse ? > - which simulation ? RTL ? postmap ? post-layout ? > - what is your test bench ? > > As the tech supports usually ask, it's best to provide a simple test > case... hard to guess otherwise. > > Bert Cuzeau Bert, Thanks for getting back to me, and sorry that I didn't provide more information.. this is my first time using Actel tools opposed to Xilinx. - Libero 8.5, haven't bothered with any service packs... ModelSim 6.4a - Target is ProAsic3 - Language VHDL - Smartgen Macro: SoftFIFOControllerWithMemory - My testbench is just a shared read/write clock with an incrementing value on the write input port, and read/write enables tied to active - I've tried both pre and post-synthesis simulations. Of what you asked, here's the suspicious one, which I just realized a few minutes ago when looking at the docs for the cores: -Was it properly reset with a pulse? The SmartGen cores documentation reads: "When power is first applied to the FIFO, the FIFO must be initialized with an asynchronous clear cycle to reset the internal address pointers." This seems to have helped. Thanks! SteveArticle: 140060
Antti wrote: > never again, when adding a LED to the FPGA board will always connect it between > 2 IO's then the same LED can be used as input or output device :) > using a LED as sensor when polarity can not be changed doesnt work at all, > or well, i tried once the pin oscillator without changing polarity and got no > light sensing (or almost none) hmmm cool, it gives me new ideas :-) > Antti yg -- http://ygdes.com / http://yasep.orgArticle: 140061
hi ! sbattazz@yahoo.co.jp wrote: > - Libero 8.5, haven't bothered with any service packs... ModelSim 6.4a > - Target is ProAsic3 > - Language VHDL > - Smartgen Macro: SoftFIFOControllerWithMemory Your message subject says "Soft FIFO Controller" but the A3P family has hardware FIFO : use them, don't bother with FIFO softcore (particularly if you're not a specialist). It's faster, safer, and smaller. > The SmartGen cores documentation reads: > "When power is first applied to the FIFO, the FIFO must be initialized > with an asynchronous clear cycle to reset the internal address > pointers." > This seems to have helped. hmmmm it should :-) > Thanks! good luck, > Steve yg -- http://ygdes.com / http://yasep.orgArticle: 140062
On Apr 27, 3:09=A0am, whygee <why...@yg.yg> wrote: > Antti wrote: > > never again, when adding a LED to the FPGA board will always connect it= between > > 2 IO's then the same LED can be used as input or output device :) > > using a LED as sensor when polarity can not be changed doesnt work at a= ll, > > or well, i tried once the pin oscillator without changing polarity and = got no > > light sensing (or almost none) > > hmmm cool, it gives me new ideas :-) > > > Antti > > yg > > --http://ygdes.com/http://yasep.org didi or altera? I have tried both methods with FPGA, but not used in products yet AnttiArticle: 140063
whygee wrote : > > Your message subject says "Soft FIFO Controller" but the A3P family has > hardware FIFO : use them, don't bother with FIFO softcore (particularly > if you're not a specialist). It's faster, safer, and smaller. > mmm... I'm not sure I would give the same advice. As far as I remember, these hard macros have a somewhat unusual behavior and I wonder if it's not safer/easier to wrap them in the Soft macro... Anyway, simulation is the key as always, and the OP seems to be doing this, so I guess it wont be an issue. BertArticle: 140064
On 18 Apr., 02:29, mng <michael.jh...@gmail.com> wrote: > On Apr 17, 5:44=A0am, olliH <oliver.hofh...@googlemail.com> wrote: > > > > > On 17 Apr., 00:20, mng <michael.jh...@gmail.com> wrote: > > > > On Apr 16, 4:24=A0am, "oliver.hofh...@googlemail.com" > > > > <oliver.hofh...@googlemail.com> wrote: > > > > Hi everybody, > > > > > in my design i have a timing problem with an ADC. I have this probl= em > > > > since my design has become more dense: > > > > [...] > > > > How do i now define the relationship between the CLK-output and the > > > > SCLK-input for example? In the datasheet are the timing- > > > > specifications. > > > > CLK to SCLK varies from 100 to 300 ns. Your clock has a period of > > > 10ns, so I am not sure what you want to accomplish with timing > > > constraints. How do you communicate with the ADC? > > > > -Mike > > > Hi, the ADC is directly connected to the FPGA-Pins. The communication > > is realized with a state machine that runs in the fpga. > > The ADC CLK is ~2 MHz or less, and your FPGA runs at 100 MHz. In this > situation I would simply sample SCLK for rising edges -- timing > constraints aren't useful here. If you are trying to do it a different > way, I have no idea what it is, and you will have to provide more > details. > > -Mike Hi Mike, thank you for your answer. I just wasn't sure if timing constraints are necessary or not. OlliArticle: 140065
On 24 avr, 22:21, "MM" <mb...@yahoo.com> wrote: > <barm...@gmail.com> wrote in message > > news:1310f073-5bb1-41fb-9317-42c0cca10836@u10g2000vbd.googlegroups.com... > > > Any other way ? > > Have you considered using floorplanner? > > /Mikhail I need that for spartan 3, i think floorplanner doesn't support S3 chips .. Best regards, barme2iArticle: 140066
Bert_Paris wrote: > whygee wrote : >> >> Your message subject says "Soft FIFO Controller" but the A3P family has >> hardware FIFO : use them, don't bother with FIFO softcore (particularly >> if you're not a specialist). It's faster, safer, and smaller. > mmm... I'm not sure I would give the same advice. > As far as I remember, these hard macros have a somewhat > unusual behavior Can you elaborate on that last point ? > and I wonder if it's not safer/easier to > wrap them in the Soft macro... > Anyway, simulation is the key as always, and the OP seems to > be doing this, so I guess it wont be an issue. well, right, as long as one knows what to simulate and how, what are the particular quirks of the simulator, and the eternal difference between synthesisable code and testbench code... I've been caught when simulating PA3 SRAM blocks so I'm cautious too :-) > Bert yg (not far from where you work) -- http://ygdes.com / http://yasep.orgArticle: 140067
Hi everybody. I need the help. I implanted a description of a SoC in Spartan 3. I was able to synthetize it, but when I wanted to implant I had the following error: NgdBuild:604 - logical block 'i_mem_BISTed/imc8051_ramx' with type 'mc8051_ramx' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'mc8051_ramx' is not supported in target 'spartan3'. I verified all files and I=92m assured i don't have any misspelling, and I have the ngc file in the project directory. When I synthetize i have the following message: WARNING:Xst:2211 - "//bison/damri/ISE_Projects/DFM_1500_benchmarks (new)/test_mem/core.vhd" line 266: Instantiating black box module <mc8051_ramx>. Entity <CORE_RAM_MICRO> analyzed. Unit <CORE_RAM_MICRO> generated. The mc8051_ramx is declared automatically as a black box. I don=92t know what the black box is. I don't found soultion which can correct this error and I don't know how to make. pls help regards.Article: 140068
hi every body, I have some doubts in verilog. Please clear my doubts. 1. How to declare arrays with each element in the array is a vector. 2. Can input and output ports can be real, integer etc., If yes, How? If no, then how can we pass floating point values to a module. 3. what are the default of value of REAL and INTEGER variables. Thanks 'n' regards PrashArticle: 140069
PrAsHaNtH@IIT <prashaenator@gmail.com> wrote: > I have some doubts in verilog. Please clear my doubts. > 1. How to declare arrays with each element in the array is a vector. > 2. Can input and output ports can be real, integer etc., If yes, How? > If no, then how can we pass floating point values to a module. > 3. what are the default of value of REAL and INTEGER variables. I have some doubts, too. It may or may not be that you can do those, but why do you want to? Verilog is not a programming language. It is extremely rare that you want to pass a floating point value to a module. You can pass bits that happen to represent the value of a floating point value. There are no variables in verilog, there are wires and regs. Yes wires and regs can hold a floating point value, and that is likely to happen more and more often as FPGAs get bigger. -- glenArticle: 140070
On Apr 27, 5:24=A0am, lolita.tang...@gmail.com wrote: > Hi everybody. > I need the help. > I implanted a description of a SoC in Spartan 3. > I was able to synthetize it, but when I wanted to implant I had the > following error: > > NgdBuild:604 - logical block 'i_mem_BISTed/imc8051_ramx' with type > 'mc8051_ramx' could not be resolved. A pin name misspelling can cause > this, a > missing edif or ngc file, or the misspelling of a type name. Symbol > 'mc8051_ramx' is not supported in target 'spartan3'. > > I verified all files and I=92m assured i don't have any misspelling, and > I have the ngc file in the project directory. > > =A0When I synthetize i have the following message: > > =A0 WARNING:Xst:2211 - "//bison/damri/ISE_Projects/DFM_1500_benchmarks > (new)/test_mem/core.vhd" line 266: Instantiating black box module > <mc8051_ramx>. > Entity <CORE_RAM_MICRO> analyzed. Unit <CORE_RAM_MICRO> generated. > > =A0The mc8051_ramx is declared automatically as a black box. > > I don=92t know what the black box is. > > I don't found soultion which can correct this error and I don't know > how to make. > pls help > regards. Make sure that the file name of your .ngc matches the module name from the source code. If you are running UNIX or LINUX the case should also match. i.e. you should have a file called mc8051_ramx.ngc (not MC8051_RAMX.ngc) in your project directory, not a subdirectory. The source for this module may be in another location. If your problem had been with pin name misspelling, I would have expected an error during synthesis, however it may be that the black box declaration, used for synthesis, does not match the pin names in the .ngc file. You may want to regenerate cores to make sure everything is up to date. Regards, GaborArticle: 140071
Hi everyone, does anyone know my questions,thanks: 1) How many control signals(The one that control mux,not show in the software named ISE) for one slice in one CLB of virtex 4(XV4VLX80)? 2) How the control signals configu one slice to a 16X1s,give me a example for the control signals? 3) How the control signals control the slice,use a decorder ? or some other ? thanks! <Qigang Ying.Article: 140072
Hi, Many thanks for your time. I'm looking for a board to pre-process the video signal from camera. The followings are the features of the camera I will use: -- The camera is of RGB type and has three separate CCD sensors. -- The interface of 3CCD camera is not limited, can be Camera link, GigE, 1394 or analog RGB (three channels), it depends on which kind of development board I can use. -- The frame rate of this camera is about 30f/s, and resolution about 1024*768, 8/10bit. The followings are the features of the board I am looking for: -- Proper interface to receive data from 3CCD camera. -- FPGA or combination of FPGA and DSP. Combination of boards, e.g., a DSP kit and a plug-in FPGA board can also work. -- Big memory and high performance. -- Proper interface to transmit the processing result to PC: Ethernet or USB or… But not PCI or PCI express. I didn’t find a board with Camera link interface. And I am a litter confused by the interface and format of camera. -- What is the difference between composite and VGA? --Does RGB output mean 3 analog channels corresponding to R/G/B, and each channel has the same format with black-white camera video output and has sync information included in each channel? --What kind of chip do I need to transform RGB output to raw data that FPGA can process? In my application, about 30 images will be received per second and I want to use 30 images to produce an averaged image. After 30 images add together and form one image, the board transmits it to computer online. Any suggestions? I really appreciate your help. DannyArticle: 140073
Thanks for answer.
For the ngc file, I=92m assured it=92s in the project directory and it
matches the module name from the source code (benchmark.ngc).
For the mc8051_ramx i synthesize a description VHDL and not a black
box and I don=92t know why matches its as black box.
The description when I have my problem is:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
--synopsys synthesis_off
library STD;
use STD.textio.all;
--synopsys synthesis_on
------------------------ ENTITY DECLARATION -------------------------
entity mc8051_ramx is
--synopsys synthesis_off
-- generic (c_init_file : string :=3D "../DfM/test_program.dua");
--synopsys synthesis_on
port (clk : in std_logic; -- clock signal
reset : in std_logic; -- reset signal
ram_data_i : in std_logic_vector(7 downto 0); -- data input
ram_data_o : out std_logic_vector(7 downto 0);
ram_adr_i : in std_logic_vector(15 downto 0); -- adresses
ram_wr_i : in std_logic; -- read=3D0,
write=3D1
Bypass_TM : in std_logic);
end mc8051_ramx;
architecture sim of mc8051_ramx is
--synopsys synthesis_off
type ram_type is array (65535 downto 0) of bit_vector(7 downto 0);
signal s_init : boolean :=3D false;
--synopsys synthesis_on
begin
--synopsys synthesis_off
---------------------------------------------------------------------------=
----
-- ram_read_write
---------------------------------------------------------------------------=
----
p_readwrite : process (clk, reset)
variable gpram : ram_type; -- general purpose
RAM
variable v_loop : integer;
variable v_line : line;
-- file f_initfile : text is in c_init_file; tolto MG 19 Sep 06
begin
if reset =3D '1' then
ram_data_o <=3D "00000000";
else
if Rising_Edge(clk) then
ram_data_o <=3D to_stdlogicvector(gpram(conv_integer(unsigned
(ram_adr_i))));
if ram_wr_i =3D '1' then
gpram(conv_integer(unsigned(ram_adr_i))) :=3D to_bitvector
(ram_data_i);
end if;
end if;
end if;
end process p_readwrite;
--synopsys synthesis_on
end sim;
configuration mc8051_ramx_sim_cfg of mc8051_ramx is
for sim
end for;
end mc8051_ramx_sim_cfg;
Regards,
lolita
Article: 140074I'm making a hardmacro usinx Xilinx 9.1.03i Fpga Editor. My implementation will be on Spartan 3 200. I am trying to connect resets of the Slices and make only one reset input for my macro in the top module of my hdl. Likely, I am trying to connect clocks of the Slices and make only one clock input for my macro in the top module of my hdl. Is it not possible? I connected the resets of the Slices. I tried to auto route but it does not auto route. Should I just connect them ignore the errors and hope that the tool will take care when I combine the macro in the top module or am I doint something wrong. If I dont connect all of them but make external macro pins for each of them seperately, I can not give the same name to the resets or clocks. I do not want to make 16 resets or clocks (and connect each of them to real reset and clock using VHDL/Verilog on my top module.)
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