Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 140025

Article: 140025
Subject: Re: FPGA board with ARM9
From: =?ISO-8859-1?Q?St=E9phane_Goujet?= <stephane@news.ci.invalid>
Date: Fri, 24 Apr 2009 10:56:28 +0200
Links: << >>  << T >>  << A >>
gil@radix20.com a écrit :

> I'm looking for a development board with an on-board ARM9.
> [...]
> But I have to assume that there are already boards out there with an
> FPGA plus an ARM9.  Xilinx would be nice since I already have the
> tools and a rough familiarity.  But any FPGA vendor is probably ok.

i.MX27 (ARM926) + Spartan 3A (50k or 200k) :
<http://www.armadeus.com/>

With an ARM7 (not 9) + Spartan 3E (500k):
<http://www.knjn.com/?pg=info&src=FPGA-FX2>

Goodbye,
  Stéphane.

Article: 140026
Subject: Re: FPGA board with ARM9
From: Lars <noreply.larthe@gmail.com>
Date: Fri, 24 Apr 2009 02:39:22 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi!
Prevas has this module among its products:
http://www.prevas.com/module_hm20_product_development.html

- 200 MHz ARM9
- Xilinx Spartan3E, 250k -1.2 mill gates
- Up to 256+256 MB SDRAM
- 4-32 MB flash
- Linux OS
- Windows CE
- 64 FPGA I/O (100+ MHz) + 32 GPIO

No idea about the price, but it seems to fit your requirements quite
nicely. The support people are in Sweden but the development is done
in Denmark. There are some other similar modules as well.

Regards,
/Lars

P.S. Remove the obvious to email me directly.

Article: 140027
Subject: Modelsim GTP_DUAL not recognized
From: Ruzica <ruleevropa@yahoo.co.uk>
Date: Fri, 24 Apr 2009 04:09:51 -0700 (PDT)
Links: << >>  << T >>  << A >>
  Hello all,

 I am using Modelsim 6.3 and ISE 10.1 and have a gtp_dual in my
design. When I try to simulate it, Modelsim reports the following
error:

 (vcom-1141) Identifier "gtp_dual" does not identify a component
declaration.

I have all the libraries with smartmodels installed in Modelsim, in
fact I can see the component gtp_dual in Unisim and Simprim libraries
in Modelsim workspace. However, it seems that it does not recognize
this option.
Does someone know what could be the problem?
Many thanks.

Ruzica

Article: 140028
Subject: Re: Modelsim GTP_DUAL not recognized
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Fri, 24 Apr 2009 12:26:34 +0100
Links: << >>  << T >>  << A >>
On Fri, 24 Apr 2009 04:09:51 -0700 (PDT), Ruzica wrote:

> I am using Modelsim 6.3 and ISE 10.1 and have a gtp_dual in my
>design. When I try to simulate it, Modelsim reports the following
>error:
>
> (vcom-1141) Identifier "gtp_dual" does not identify a component
>declaration.
>
>I have all the libraries with smartmodels installed in Modelsim, in
>fact I can see the component gtp_dual in Unisim and Simprim libraries
>in Modelsim workspace. However, it seems that it does not recognize
>this option.
>Does someone know what could be the problem?


Errrm, it sounds like there's no component declaration :-)

The fact that an entity/architecture exists in a library
does not allow the VHDL compiler to know about it by magic.
You probably forgot a use clause, for the package containing
the gtp_dual component declaration.  And the synthesis tool
(ISE?) probably cheats, and assumes it knows all about the
Xilinx primitives already.

I can't find the gtp_dual component anywhere in my Xilinx
simulation library sources; what am I missing?
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Article: 140029
Subject: FPGA evaluation board for SD/SDHC Host controller
From: muthusnv@gmail.com
Date: Fri, 24 Apr 2009 05:37:49 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hello,

I am planning to evaluate a SD/SDHC Host Controller. Do Xilinx has any
suitable evaluation boards? From the Websearch, I couldn't find any
Xilinx board with SD/SDHC card interface.


Best regards,
Muthu

Article: 140030
Subject: Re: Modelsim GTP_DUAL not recognized
From: Ruzica <ruleevropa@yahoo.co.uk>
Date: Fri, 24 Apr 2009 05:53:04 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 24, 1:26=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On Fri, 24 Apr 2009 04:09:51 -0700 (PDT), Ruzica wrote:
> > I am using Modelsim 6.3 and ISE 10.1 and have a gtp_dual in my
> >design. When I try to simulate it, Modelsim reports the following
> >error:
>
> > (vcom-1141) Identifier "gtp_dual" does not identify a component
> >declaration.
>
> >I have all the libraries with smartmodels installed in Modelsim, in
> >fact I can see the component gtp_dual in Unisim and Simprim libraries
> >in Modelsim workspace. However, it seems that it does not recognize
> >this option.
> >Does someone know what could be the problem?
>
> Errrm, it sounds like there's no component declaration :-)
>
> The fact that an entity/architecture exists in a library
> does not allow the VHDL compiler to know about it by magic.
> You probably forgot a use clause, for the package containing
> the gtp_dual component declaration. =A0And the synthesis tool
> (ISE?) probably cheats, and assumes it knows all about the
> Xilinx primitives already.
>
Hi Jonathan,

Thanks for your answer. I just saw that the component GTP_DUAL is not
inside the package unisim.vcomponents. Instead it is instantiated as
an entity in another file. How can I tell Modelsim where to search for
this component instantiation?

> I can't find the gtp_dual component anywhere in my Xilinx
> simulation library sources; what am I missing?
> --
It should be defined in the folder where ISE has been installed in the
path Xilinx\10.1\ISE\vhdl\src\unisims. You should follow the
guidelines in http://www.xilinx.com/support/answers/24800.htm
in order to install it in Modelsim.



Article: 140031
Subject: Re: Modelsim GTP_DUAL not recognized
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Fri, 24 Apr 2009 14:35:04 +0100
Links: << >>  << T >>  << A >>
On Fri, 24 Apr 2009 05:53:04 -0700 (PDT), Ruzica wrote:

>Thanks for your answer. I just saw that the component GTP_DUAL is not
>inside the package unisim.vcomponents. Instead it is instantiated as
>an entity in another file. How can I tell Modelsim where to search for
>this component instantiation?

Probably the easiest fix is to use direct instantiation.
Where you currently have

  some_instance_name: GTP_DUAL 
                        generic map (whatever)
                        port map (whatever);

you could instead write

  some_instance_name: entity THE_LIB.GTP_DUAL
                        generic map (whatever)
                        port map (whatever);

where THE_LIB is the name of the library into which GTP_DUAL
has already been compiled.  Using direct instantiation
in this way, there is no need for a component declaration.

>> I can't find the gtp_dual component anywhere in my Xilinx
>> simulation library sources; what am I missing?
>> --
>It should be defined in the folder where ISE has been installed in the
>path Xilinx\10.1\ISE\vhdl\src\unisims. You should follow the
>guidelines in http://www.xilinx.com/support/answers/24800.htm
>in order to install it in Modelsim.

Yes.  I think I was just being stupid, and looking at my 
WebPack installation which perhaps lacks those components.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Article: 140032
Subject: Re: Modelsim GTP_DUAL not recognized
From: "HT-Lab" <hans64@ht-lab.com>
Date: Fri, 24 Apr 2009 14:50:52 +0100
Links: << >>  << T >>  << A >>

"Ruzica" <ruleevropa@yahoo.co.uk> wrote in message 
news:28fbcf44-7560-446a-aef2-c93922f67c8c@k8g2000yqn.googlegroups.com...
>  Hello all,
>
> I am using Modelsim 6.3 and ISE 10.1 and have a gtp_dual in my
> design. When I try to simulate it, Modelsim reports the following
> error:
>
> (vcom-1141) Identifier "gtp_dual" does not identify a component
> declaration.
>
> I have all the libraries with smartmodels installed in Modelsim, in
> fact I can see the component gtp_dual in Unisim and Simprim libraries
> in Modelsim workspace. However, it seems that it does not recognize
> this option.
> Does someone know what could be the problem?
> Many thanks.
>
> Ruzica

This might help you out:

http://www.xilinx.com/support/answers/31125.htm

Hans
www.ht-lab.com



Article: 140033
Subject: Re: Modelsim GTP_DUAL not recognized
From: Ruzica <ruleevropa@yahoo.co.uk>
Date: Fri, 24 Apr 2009 06:56:15 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 24, 3:35=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On Fri, 24 Apr 2009 05:53:04 -0700 (PDT), Ruzica wrote:
> >Thanks for your answer. I just saw that the component GTP_DUAL is not
> >inside the package unisim.vcomponents. Instead it is instantiated as
> >an entity in another file. How can I tell Modelsim where to search for
> >this component instantiation?
>
> Probably the easiest fix is to use direct instantiation.
> Where you currently have
>
> =A0 some_instance_name: GTP_DUAL
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 generic map (whatever)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 port map (whatever);
>
> you could instead write
>
> =A0 some_instance_name: entity THE_LIB.GTP_DUAL
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 generic map (whatever)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 port map (whatever);
>
> where THE_LIB is the name of the library into which GTP_DUAL
> has already been compiled. =A0Using direct instantiation
> in this way, there is no need for a component declaration.
>
> >> I can't find the gtp_dual component anywhere in my Xilinx
> >> simulation library sources; what am I missing?
> >> --
> >It should be defined in the folder where ISE has been installed in the
> >path Xilinx\10.1\ISE\vhdl\src\unisims. You should follow the
> >guidelines inhttp://www.xilinx.com/support/answers/24800.htm
> >in order to install it in Modelsim.
>
> Yes. =A0I think I was just being stupid, and looking at my
> WebPack installation which perhaps lacks those components.
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.

Thanks a lot. This works!
It's not so handy as when I use gtp for implementation in ISE, as I
can define only the signals that I am using, and the tool deals with
the rest of them. Now I have to say what happens to each of the
component ports, but I wouldn't call that a problem :-)

Cheers,
Ruzica

Article: 140034
Subject: Re: FPGA evaluation board for SD/SDHC Host controller
From: LittleAlex <alex.louie@email.com>
Date: Fri, 24 Apr 2009 12:22:45 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 24, 5:37 am, muthu...@gmail.com wrote:
> Hello,
>
> I am planning to evaluate a SD/SDHC Host Controller. Do Xilinx has any
> suitable evaluation boards? From the Websearch, I couldn't find any
> Xilinx board with SD/SDHC card interface.
>
> Best regards,
> Muthu

It doesn't look like you tried very hard to find one:
<http://www.hitechglobal.com/Boards/Spartan3-MMC.htm>

Article: 140035
Subject: Re: FPGA evaluation board for SD/SDHC Host controller
From: Dave Pollum <vze24h5m@verizon.net>
Date: Fri, 24 Apr 2009 12:57:19 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 24, 8:37=A0am, muthu...@gmail.com wrote:
> Hello,
>
> I am planning to evaluate a SD/SDHC Host Controller. Do Xilinx has any
> suitable evaluation boards? From the Websearch, I couldn't find any
> Xilinx board with SD/SDHC card interface.
>
> Best regards,
> Muthu

Digilent has a SD card module that works with their Spartan-3/3E FPGA
boards.
http://www.digilentinc.com/Products/Detail.cfm?Prod=3DPMOD-SD&NavTop=3D2&Na=
vSub=3D513&DetailType=3D
HTH
-Dave Pollum


Article: 140036
Subject: Re: How to put area routing constraints in a xilinx flow
From: "MM" <mbmsv@yahoo.com>
Date: Fri, 24 Apr 2009 16:21:00 -0400
Links: << >>  << T >>  << A >>
<barme2i@gmail.com> wrote in message 
news:1310f073-5bb1-41fb-9317-42c0cca10836@u10g2000vbd.googlegroups.com...
> Any other way ?

Have you considered using floorplanner?


/Mikhail



Article: 140037
Subject: Re: FPGA board with ARM9
From: gil@radix20.com
Date: Fri, 24 Apr 2009 13:21:53 -0700 (PDT)
Links: << >>  << T >>  << A >>
Stephane and Lars, thank you both for the excellent pointers.  In
addition I should also update the other possible solutions that I have
found.

Technologic Systems, TS-7800
http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/f9731810437ceda0
Has a Lattice FPGA.... probably too small for my application.

The Armadeus board mentioned by Stephane also has a 400K option for
the FPGA.  This might be ok for me, but I'd feel more comfortable with
at least a million FPGA gates.

The Cortex-M1 seems to be a synthesizable ARM for Altera... this could
work maybe.

So far the Prevas board with the 1.2M gates looks pretty good.

Thank you again.

Article: 140038
Subject: Re: FPGA board with ARM9
From: gil@radix20.com
Date: Fri, 24 Apr 2009 13:26:03 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 24, 1:21=A0pm, g...@radix20.com wrote:

Corrected link.

> Technologic Systems, TS-7800h
http://www.embeddedarm.com/products/board-detail.php?product=3DTS-7800

Article: 140039
Subject: actel libero
From: russ <lyttlec@gmail.com>
Date: Fri, 24 Apr 2009 17:19:53 -0400
Links: << >>  << T >>  << A >>
I'm learning Actel and started a simple 4-bit adder project. I get the 
following on the Synthesis step :

@W: BN246 |Failed to find top level module 'work.adder' as specified in 
project file

Also the logs have a message that top-level file is not set.

The top level of the design is adder.vhd. How do I make it the top-level 
  file and create the top-level module?

Article: 140040
Subject: Re: actel libero
From: whygee <whygee@yg.yg>
Date: Sat, 25 Apr 2009 00:10:17 +0200
Links: << >>  << T >>  << A >>
russ wrote:
> I'm learning Actel and started a simple 4-bit adder project. I get the 
> following on the Synthesis step :
> 
> @W: BN246 |Failed to find top level module 'work.adder' as specified in 
> project file
> 
> Also the logs have a message that top-level file is not set.
> 
> The top level of the design is adder.vhd. How do I make it the top-level 
>  file and create the top-level module?

(from memory :)
look at the graphic interface, where the list of the source files appear.
IIRC, right-click on you .vhdl file and "set as top level".
Note : this should also be in sync with the synthesizer
(more or less the same should be done with synplify if you play
too much with the toolsuite).

Not a big problem, but "get used to it" :-/

good luck,
yg

-- 
http://ygdes.com / http://yasep.org

Article: 140041
Subject: Re: FPGA board with ARM9
From: =?ISO-8859-1?Q?St=E9phane_Goujet?= <stephane@news.ci.invalid>
Date: Sat, 25 Apr 2009 00:29:54 +0200
Links: << >>  << T >>  << A >>
gil@radix20.com a écrit :

> Technologic Systems, TS-7800
> Has a Lattice FPGA.... probably too small for my application.

  It must be a ECP2-12, it looks roughly equivalent to a 200k spartan,
indeed.

> The Armadeus board mentioned by Stephane also has a 400K option for
> the FPGA. 

  Yes, but last time I checked, only 200k and perhaps 50k were available
for buying.

Goodbye,
  Stéphane.

Article: 140042
Subject: Re: actel libero
From: russ <lyttlec@gmail.com>
Date: Fri, 24 Apr 2009 20:21:29 -0400
Links: << >>  << T >>  << A >>
whygee wrote:
> russ wrote:
>> I'm learning Actel and started a simple 4-bit adder project. I get the 
>> following on the Synthesis step :
>>
>> @W: BN246 |Failed to find top level module 'work.adder' as specified 
>> in project file
>>
>> Also the logs have a message that top-level file is not set.
>>
>> The top level of the design is adder.vhd. How do I make it the 
>> top-level  file and create the top-level module?
> 
> (from memory :)
> look at the graphic interface, where the list of the source files appear.
> IIRC, right-click on you .vhdl file and "set as top level".
> Note : this should also be in sync with the synthesizer
> (more or less the same should be done with synplify if you play
> too much with the toolsuite).
> 
> Not a big problem, but "get used to it" :-/
> 
> good luck,
> yg
> 
Thanks for the response, but that choice isn't there. BTW, I did the 
counter tutorial from Actel and got 8 warnings. It doesn't seem to have 
much practical impact, but the process says no errors no warnings. Is 
there something that is expected to be in the top file?

Article: 140043
Subject: Re: actel libero
From: whygee <whygee@yg.yg>
Date: Sat, 25 Apr 2009 03:02:23 +0200
Links: << >>  << T >>  << A >>
russ wrote:
> Thanks for the response, but that choice isn't there.
sorry, i'm too lazy to turn the viscrap computer on and take screenshots.
The dialog has maybe changed with the newer version of libero...
But I found the trick, I believe that others can too ?

maybe antti will help ? /o\

> BTW, I did the 
> counter tutorial from Actel and got 8 warnings. It doesn't seem to have 
> much practical impact, but the process says no errors no warnings. Is 
> there something that is expected to be in the top file?
The "top" file defines all the I/O that will be tied to the physical
pins of the FPGA. It is important because that is where the synthesizer,
place&route tools will pick the pins and assign the functions (clock,
global resets etc) according to the available resources in the chosen chip.

It took me about a month or two to get used to this software,
with its limitations and quirks, but it works for my needs
and it was worth the efforts and expense. I wish the same to you too.

yg

-- 
http://ygdes.com / http://yasep.org

Article: 140044
Subject: About those TIEOFF primitives ...
From: Neil Steiner <neil.steiner@east.isi.edu>
Date: Fri, 24 Apr 2009 21:59:22 -0400
Links: << >>  << T >>  << A >>
I'm embarrassed to say I can't tell what the KEEP1 output of the Virtex4 
TIEOFF primitive does.  HARD1 and HARD0 are pretty obvious, but since 
there are no tristatable wires inside the device, I'm less certain about 
the purpose of KEEP1.

Did Austin perhaps suggest the answer in the "What is TIEOFF_X0Y31" 
thread from 2008 (http://www.fpga-faq.org/archives/133475.html#133487)? 
  If I read between the lines, I might conclude that KEEP1 is the 
implicit "weak keeper" that drives slice inputs when nothing else is 
connected to them.  Any firmer answers?

Article: 140045
Subject: Re: About those TIEOFF primitives ...
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Sat, 25 Apr 2009 03:29:22 +0000 (UTC)
Links: << >>  << T >>  << A >>
Neil Steiner <neil.steiner@east.isi.edu> wrote:

> I'm embarrassed to say I can't tell what the KEEP1 output of the Virtex4 
> TIEOFF primitive does.  HARD1 and HARD0 are pretty obvious, but since 
> there are no tristatable wires inside the device, I'm less certain about 
> the purpose of KEEP1.

I don't know specifically for Virtex4, but internal tristates are
now usually implemented as MUXes.  (Actually, I believe AND/OR logic.)

It would seem easy to set the default (with no active drivers)
to high or low.  Not so easy to generate KEEP logic.

-- glen

Article: 140046
Subject: Error in Verilog Code
From: "PrAsHaNtH@IIT" <prashaenator@gmail.com>
Date: Fri, 24 Apr 2009 21:58:51 -0700 (PDT)
Links: << >>  << T >>  << A >>
I am new to verilog HDL. I have written code for one algorithm. While
simulating, it is giving some errors. Could any body tell how to
remove this error

The code is as shown in below.

module two_pt_FFT(YR,YI,XR,XI
    );
output reg [31:0] YR [0:1];
output reg [31:0] YI [0:1];
input [31:0] XR [0:1];
input [31:0] XI [0:1];

always @(XR or XI)
begin
YR[0] = XR[0]+XR[1];
YI[0] = XI[0]+XI[1];
YR[1] = (XR[0]-XR[1]);
YI[1] = (XI[0]-XI[1]);
end

endmodule


The test bench program is as shown below

module two_pt_fft_dif_tbw;

	// Inputs
	wire YR;
	wire YI;
	reg [31:0] XR;
	reg [31:0] XI;

	// Instantiate the Unit Under Test (UUT)
	two_pt_FFT uut (
		.YR(YR),
		.YI(YI),
		.XR(XR),
		.XI(XI)
	);

	initial begin
		// Initialize Inputs

		XR[0] = 32'd0;
		XR[1] = 32'd0;
		XI[0] = 32'd0;
		XI[1] = 32'd0;

		// Wait 100 ns for global reset to finish
		#100;

		// Add stimulus here
		#10 XR[0] = 32'd1;
		 XI[0] = 32'd1;
			XR[1] = 32'd5;
			XI[1]=32'd1;

	end

endmodule




Errors & Warnings are as shown below


WARNING:HDLCompiler:991 - "two_pt_FFT.v" Line 31. Event expressions
must result in a singular type
Analyzing Verilog file two_pt_FFT.v
Analyzing Verilog file two_pt_fft_dif_tbw.v
Analyzing Verilog file C:/Xilinx/10.1/ISE/verilog/src/glbl.v
Saving Verilog parse-tree work.two_pt_FFT into i:/fft/isim/work/
two_pt_@f@f@t.sdb
Saving Verilog parse-tree work.two_pt_fft_dif_tbw into i:/fft/isim/
work/two_pt_fft_dif_tbw.sdb
Saving Verilog parse-tree work.glbl into i:/fft/isim/work/glbl.sdb
Starting static elaboration
ERROR:HDLCompiler:252 - "two_pt_fft_dif_tbw.v" Line 35. Cannot assign
an unpacked type to a packed type
ERROR:HDLCompiler:252 - "two_pt_fft_dif_tbw.v" Line 36. Cannot assign
an unpacked type to a packed type
ERROR:HDLCompiler:252 - "two_pt_fft_dif_tbw.v" Line 37. Cannot assign
a packed type to an unpacked type
ERROR:HDLCompiler:252 - "two_pt_fft_dif_tbw.v" Line 38. Cannot assign
a packed type to an unpacked type
WARNING:HDLCompiler:189 - "two_pt_fft_dif_tbw.v" Line 35. Actual bit
length 1 differs from formal bit length 64 for port YR
WARNING:HDLCompiler:189 - "two_pt_fft_dif_tbw.v" Line 36. Actual bit
length 1 differs from formal bit length 64 for port YI
WARNING:HDLCompiler:189 - "two_pt_fft_dif_tbw.v" Line 37. Actual bit
length 32 differs from formal bit length 64 for port XR
WARNING:HDLCompiler:189 - "two_pt_fft_dif_tbw.v" Line 38. Actual bit
length 32 differs from formal bit length 64 for port XI
ERROR:Simulator:778 - Static elaboration of top level Verilog design
unit(s) in library work failed



1. Tell me how to remove this error. How to declare a packed data type
and unpacked data type in test bench program.

2. Whre can I find these error codes.

Please reply

thnx 'n' regards
Prash

Article: 140047
Subject: Re: Error in Verilog Code
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Sat, 25 Apr 2009 10:18:36 +0100
Links: << >>  << T >>  << A >>
On Fri, 24 Apr 2009 21:58:51 -0700 (PDT), "PrAsHaNtH@IIT"
<prashaenator@gmail.com> wrote:

>I am new to verilog HDL. I have written code for one algorithm. While
>simulating, it is giving some errors. Could any body tell how to
>remove this error

(1) You can't put 2-d arrays in a sensitivity list.

>input [31:0] XR [0:1];
>input [31:0] XI [0:1];
>
>always @(XR or XI)

It's better to do this with a continuous assignment:

 assign YR[0] = XR[0]+XR[1];

(then, of course, YR must be a net).


(2) You've connected a single 32-bit vector to the
2x32-bit inputs of your design.  Indeed, you can only
have array ports because you're using a SystemVerilog
compiler.  In regular Verilog you would need to 
flatten the 2x32-bit inputs to be 64-bit vectors.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Article: 140048
Subject: Re: Noise in Stratix3?
From: "Niv (KP)" <kev.parsons@mbda-systems.com>
Date: Sat, 25 Apr 2009 04:02:48 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 11 Apr, 15:32, Rob <noth...@nowhere.com> wrote:
> sorry for the multiple posts--a quirk with my system..
>
>
>
> Niv (KP) wrote:
> > My stratix3 design simulates OK at RTL & gate-level.
>
> > On the PCB however, an internal module fails to read some M9K RAMS
> > properly all the time
> > when I connect an input signal to the chip, but which has nothing to
> > do with the failing module.
>
> > Are there any crosstalk/noise issues with Strarix3 devices that anyone
> > has encountered?
>
> > Basically, the s/w guys are testing the system and getting a lot of
> > errors on reading this particular RAM,
> > but removing this un-related signal (relative o the RAMs in question)
> > reduces the error count a lot. (but not totally, apparently, possibly
> > another signal also affecting?).
>
> > I have not floorplanned the design, but let Quartus do whatever it
> > wanted routing wise to meet timing and pin-out.
>
> > Regards, Kev P.- Hide quoted text -
>
> - Show quoted text -

It would seem a bug was in the VHDL code, a simple mistake and easy to
overlook.
eg;
    IF address = ("000" OR "101") THEN
       -- do something.

Should have been;

    IF (address = "000") OR (address = "101") THEN
       -- do something.

Not my code, but I was one of 3 reviewers, and we all missed it!!

Article: 140049
Subject: Re: Noise in Stratix3?
From: "KJ" <kkjennings@sbcglobal.net>
Date: Sat, 25 Apr 2009 07:40:02 -0400
Links: << >>  << T >>  << A >>

>
> It would seem a bug was in the VHDL code, a simple mistake and easy to
> overlook.

That's why simulation is an important step

> Not my code, but I was one of 3 reviewers, and we all missed it!!

That's why reviews are less important than good simulation practices.

KJ 





Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search