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Gabor Thank you for the reply.I'm sorry I didn't describe it clearly. --What about data from B to A? No data should be transferred from B to A. --If not can you use LVDS for the interconnect? Yes,I use LVDS for the interconnect . If Virtex2 is the source, you can use DDR flops to drive the interface. I will have a look at DDR flops. --What makes you think the problem is crosstalk? Do you have adequate --grounding on the cables? I just think it should be crosstalk,because 8 links work at the high speed at the same time.The cables are network cables,which are not grounded. --Are you using DCI or series resistors at the driver to reduce overshoot? No,I didn't use any DCI or resistros.Can ou get a single link to work reliably? I just did the test in only B board,which means B sends and B receives it back. For one link,it workes reliably. But for more than one link,it doesn't work,the received data is wrong.when I do post simulation in questasim,more than one links receiver have unknown state.even if I reduce the speed to 100 MHZ,I don't know why. -- mingyuexin ------------------------------------------------------------------------ mingyuexin's Profile: http://www.fpgacentral.com/group/member.php?userid=72 View this thread: http://www.fpgacentral.com/group/showthread.php?t=89596Article: 140001
I have a question about the calculation of MAX_STEPS when using variable phase shift in a DCM_SP of a Spartan 3E. The formula is: =B1[INTEGER(20 =95(TCLKIN =96 3))] I use a clock frequency of 62.5 MHz (16 ns period time). If I use the formula it will give me a result of =B1 59.99 for MAX_STEPS. Is this correct? Should I use 0.000000016 for the clock period or 16? If I use 16, the result will be out range of the =B1255 for the PHASE_SHIFT attribute. However, if I look in an application note of Xilinx (XAPP977, v1.1, page 16), the example uses the clock period in ns (instead of seconds). It's a bit confusing to me.Article: 140002
On Apr 23, 3:31 am, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > On Apr 23, 3:22 am, jleslie48 <j...@jonathanleslie.com> wrote: > > > > > On Apr 21, 8:24 pm, Brian Davis <brimda...@aol.com> wrote: > > > > jleslie48 wrote: > > > > > So it appears that driving PIN15 is not an issue at all when the > > > > program loads from the SP flash, and I'm leaning to the conclusion > > > > that the CRC error is a function of the impact 10.1 having an issue, > > > > making higgley-piggley out of my program and locking up the FPGA. > > > > >Xilinx has no documentation of any of this, and their support, well > > > >let's just leave it as leaves a lot to be desired. > > > > The conflict between SPI-mode configuration and JTAG configuration > > > in various Spartan-3's is well known and documented in several places > > > by Xilinx (see below), as well as being a fairly regular topic here. > > > > The only workarounds I know of are to either erase the flash > > > (as Antti suggested), disconnect/disable the flash, or to set > > > the configuration mode on the chip to JTAG when programming > > > the FPGA directly. > > > > After a quick look at the Drigmorn1 board schematic, it does not > > > appear that the configuration mode can be changed, as the mode pins > > > are hardwired to VCC/ground; the erase-the-flash-before-JTAG-download > > > method is probably your best bet if you want to program the FPGA > > > directly without loading up the SPI flash. > > > > Brian > > > > Xilinx Documentation: > > > > XAPP951 v1.2 Configuring Xilinx FPGAs with SPI Serial Flashhttp://www.xilinx.com/support/documentation/application_notes/xapp951... > > > figure3, footnote 6 : > > > " > > > " 6. For dual configuration mode usage, it is recommended to have the > > > " option to hold the M2 signal High for JTAG configuration mode. > > > " > > > > Answer Records: > > > >http://www.xilinx.com/support/answers/9013.htmhttp://www.xilinx.com/s... > > > Brian, > > > Thank you very much. It wasn't untll the end that I connected the > > JTAG load problem with my previous SPI load, mostly because after I > > loaded the SPI, I successfully changed the code using the JTAG to FPGA > > without any issue. It was only when I added signals to pins did the > > error message pop up. > > > One would think Xilinx would have that listed in the possible causes > > of the 2217 error and that a search of Xilinx for "iMpact:2217 crc > > error bit not 0" (the actual error message that pops up) would be > > acknowledged. > > > For the amount of money I paid for this development suite and support > > I cannot believe the level and frequency of bugs in the software and > > lack of support I get from these folks.- Hide quoted text - > > > - Show quoted text - > > impact s**** > always has... > > there are things to KNOW > JTAG configuration mode does OVERRIDE other modes > but it not always works with impact > > this may depend 2 bitfiles bit difference you are trying to load > or the speed of the PC, or the type of cable you use.. > > so while it should be ALWAYS be possible to configure > over jtag without concern of the MODE pins settings > with impact this isnt true > > i once designed a workaround that used boundary scan > to place the SPI flash into deep powerdown mode > to allow the configuration to be done properly.. > > Antti The thing that really burns my, err kiester, is that here the iMPACT tool not only generates an error, but a full blown pop up window: "WARNING:iMPACT:2217 - Error shows in the status register, CRC Error bit is NOT 0. " that I have to click an [OK] button to get around. first off, its not a warning it totally KILLS the fpga. that's not a warning thats a FATAL ERROR. secondly and more importantly, How in god's name can it be that if I search Xilinx for that exact error I don't get a connection to the links that Brian so nicely provided? Here the problem is a known issue for 2 years, yet its most glaring symptom, a big pop up window with an error code, can't be cross referenced against what caused the error. That is pathetic. Meantime Webcase support is 3 days into looking at the issue, and all they can tell me is do I have the unit powered up... This I pay $600 a year for. This forum should be getting the $600... Thanks everyone. - JonArticle: 140003
On Apr 23, 2:56=A0pm, jleslie48 <j...@jonathanleslie.com> wrote: > On Apr 23, 3:31 am, "Antti.Luk...@googlemail.com" > > > > > > <Antti.Luk...@googlemail.com> wrote: > > On Apr 23, 3:22 am, jleslie48 <j...@jonathanleslie.com> wrote: > > > > On Apr 21, 8:24 pm, Brian Davis <brimda...@aol.com> wrote: > > > > > jleslie48 wrote: > > > > > > So it appears that driving PIN15 is not an issue at all when the > > > > > program loads from the SP flash, and I'm leaning to the conclusio= n > > > > > that the CRC error is a function of the impact 10.1 having an iss= ue, > > > > > making higgley-piggley out of my program and locking up the FPGA. > > > > > >Xilinx has no documentation of any of this, and their support, wel= l > > > > >let's just leave it as leaves a lot to be desired. > > > > > =A0The conflict between SPI-mode configuration and JTAG configurati= on > > > > in various Spartan-3's is well known and documented in several plac= es > > > > by Xilinx (see below), as well as being a fairly regular topic here= . > > > > > =A0The only workarounds I know of are to either erase the flash > > > > (as Antti suggested), disconnect/disable the flash, or to set > > > > the configuration mode on the chip to JTAG when programming > > > > the FPGA directly. > > > > > After a quick look at the Drigmorn1 board schematic, it does not > > > > appear that the configuration mode can be changed, as the mode pins > > > > are hardwired to VCC/ground; the erase-the-flash-before-JTAG-downlo= ad > > > > method is probably your best bet if you want to program the FPGA > > > > directly without loading up the SPI flash. > > > > > Brian > > > > > Xilinx Documentation: > > > > > XAPP951 v1.2 Configuring Xilinx FPGAs with SPI Serial Flashhttp://w= ww.xilinx.com/support/documentation/application_notes/xapp951... > > > > figure3, footnote 6 : > > > > " > > > > " 6. For dual configuration mode usage, it is recommended to have t= he > > > > " option to hold the M2 signal High for JTAG configuration mode. > > > > " > > > > > Answer Records: > > > > >http://www.xilinx.com/support/answers/9013.htmhttp://www.xilinx.com/= s... > > > > Brian, > > > > Thank you very much. =A0It wasn't untll the end that I connected the > > > JTAG load problem with my previous SPI load, mostly because after I > > > loaded the SPI, I successfully changed the code using the JTAG to FPG= A > > > without any issue. =A0It was only when I added signals to pins did th= e > > > error message pop up. > > > > One would think Xilinx would have that listed in the possible causes > > > of the 2217 error and that a search of Xilinx for "iMpact:2217 crc > > > error bit not 0" (the actual error message that pops up) would be > > > acknowledged. > > > > For the amount of money I paid for this development suite and support > > > I cannot believe the level and frequency of bugs in the software and > > > lack of support I get from these folks.- Hide quoted text - > > > > - Show quoted text - > > > impact s**** > > always has... > > > there are things to KNOW > > JTAG configuration mode does OVERRIDE other modes > > but it not always works with impact > > > this may depend 2 bitfiles bit difference you are trying to load > > or the speed of the PC, or the type of cable you use.. > > > so while it should be ALWAYS be possible to configure > > over jtag without concern of the MODE pins settings > > with impact this isnt true > > > i once designed a workaround that used boundary scan > > to place the SPI flash into deep powerdown mode > > to allow the configuration to be done properly.. > > > Antti > > The thing that really burns my, err kiester, is that here the iMPACT > tool not only generates an error, but a full blown pop up window: > > "WARNING:iMPACT:2217 - Error shows in the status register, CRC Error > bit is NOT 0. " > > that I have to click an [OK] button to get around. > > first off, its not a warning it totally KILLS the fpga. =A0that's not a > warning thats a FATAL ERROR. > > secondly and more importantly, How in god's name can it be that if I > search Xilinx for that exact error I don't get a connection to the > links that Brian so nicely provided? =A0Here the problem is a known > issue for 2 years, yet its most glaring symptom, a big pop up window > with an error code, can't be cross referenced against what caused the > error. =A0That is pathetic. > > Meantime Webcase support is 3 days into looking at the issue, and all > they can tell me is do I have the unit powered up... > > This I pay $600 a year for. =A0This forum should be getting the $600... > > Thanks everyone. > > - Jon- Hide quoted text - > > - Show quoted text - HA HA HA I talked with my wife once about xilinx "Answer Record" system saying, you know they have special AR database, there are 30K+ here she interrupted me: "Ah this is the place where you DO NOT GET ANSWERS!" I said, yes this is the place. If you dont know the AR number, you would not find it. but not only you, Xilinx employees and webcase personel are equally unable to find them as well. At least it happens.. AnttiArticle: 140004
On Apr 23, 2:56=A0pm, jleslie48 <j...@jonathanleslie.com> wrote: > On Apr 23, 3:31 am, "Antti.Luk...@googlemail.com" > > > > > > <Antti.Luk...@googlemail.com> wrote: > > On Apr 23, 3:22 am, jleslie48 <j...@jonathanleslie.com> wrote: > > > > On Apr 21, 8:24 pm, Brian Davis <brimda...@aol.com> wrote: > > > > > jleslie48 wrote: > > > > > > So it appears that driving PIN15 is not an issue at all when the > > > > > program loads from the SP flash, and I'm leaning to the conclusio= n > > > > > that the CRC error is a function of the impact 10.1 having an iss= ue, > > > > > making higgley-piggley out of my program and locking up the FPGA. > > > > > >Xilinx has no documentation of any of this, and their support, wel= l > > > > >let's just leave it as leaves a lot to be desired. > > > > > =A0The conflict between SPI-mode configuration and JTAG configurati= on > > > > in various Spartan-3's is well known and documented in several plac= es > > > > by Xilinx (see below), as well as being a fairly regular topic here= . > > > > > =A0The only workarounds I know of are to either erase the flash > > > > (as Antti suggested), disconnect/disable the flash, or to set > > > > the configuration mode on the chip to JTAG when programming > > > > the FPGA directly. > > > > > After a quick look at the Drigmorn1 board schematic, it does not > > > > appear that the configuration mode can be changed, as the mode pins > > > > are hardwired to VCC/ground; the erase-the-flash-before-JTAG-downlo= ad > > > > method is probably your best bet if you want to program the FPGA > > > > directly without loading up the SPI flash. > > > > > Brian > > > > > Xilinx Documentation: > > > > > XAPP951 v1.2 Configuring Xilinx FPGAs with SPI Serial Flashhttp://w= ww.xilinx.com/support/documentation/application_notes/xapp951... > > > > figure3, footnote 6 : > > > > " > > > > " 6. For dual configuration mode usage, it is recommended to have t= he > > > > " option to hold the M2 signal High for JTAG configuration mode. > > > > " > > > > > Answer Records: > > > > >http://www.xilinx.com/support/answers/9013.htmhttp://www.xilinx.com/= s... > > > > Brian, > > > > Thank you very much. =A0It wasn't untll the end that I connected the > > > JTAG load problem with my previous SPI load, mostly because after I > > > loaded the SPI, I successfully changed the code using the JTAG to FPG= A > > > without any issue. =A0It was only when I added signals to pins did th= e > > > error message pop up. > > > > One would think Xilinx would have that listed in the possible causes > > > of the 2217 error and that a search of Xilinx for "iMpact:2217 crc > > > error bit not 0" (the actual error message that pops up) would be > > > acknowledged. > > > > For the amount of money I paid for this development suite and support > > > I cannot believe the level and frequency of bugs in the software and > > > lack of support I get from these folks.- Hide quoted text - > > > > - Show quoted text - > > > impact s**** > > always has... > > > there are things to KNOW > > JTAG configuration mode does OVERRIDE other modes > > but it not always works with impact > > > this may depend 2 bitfiles bit difference you are trying to load > > or the speed of the PC, or the type of cable you use.. > > > so while it should be ALWAYS be possible to configure > > over jtag without concern of the MODE pins settings > > with impact this isnt true > > > i once designed a workaround that used boundary scan > > to place the SPI flash into deep powerdown mode > > to allow the configuration to be done properly.. > > > Antti > > The thing that really burns my, err kiester, is that here the iMPACT > tool not only generates an error, but a full blown pop up window: > > "WARNING:iMPACT:2217 - Error shows in the status register, CRC Error > bit is NOT 0. " > > that I have to click an [OK] button to get around. > > first off, its not a warning it totally KILLS the fpga. =A0that's not a > warning thats a FATAL ERROR. > > secondly and more importantly, How in god's name can it be that if I > search Xilinx for that exact error I don't get a connection to the > links that Brian so nicely provided? =A0Here the problem is a known > issue for 2 years, yet its most glaring symptom, a big pop up window > with an error code, can't be cross referenced against what caused the > error. =A0That is pathetic. > > Meantime Webcase support is 3 days into looking at the issue, and all > they can tell me is do I have the unit powered up... > > This I pay $600 a year for. =A0This forum should be getting the $600... > > Thanks everyone. > > - Jon- Hide quoted text - > > - Show quoted text - Jon, I forgot... your problem is you are paying too little !!! there is "Xilinx Platinum support" option they promise that clients will speed up time to market by 6 months if they use Platinum support. 6 month TTM is more then 6 man-manths, I wonder how much Xilinx takes for this service. But I can see how those 6 months are posssible to save.. (you need sick software, and sick documents and support - this opens the window for the platinum guys todo miracle in saving customer frustration) everybody can milder the above saying to their liking.. its not that bad always, even xilinx software is getting better (in some ways at least) AnttiArticle: 140005
Hi, i am using a Actel ProAsic3 Device (A3P015 QN68) , i have completed the design and now layout is been done.Now i found out that Clock and Reset is given to a normal I/O pin instead of global pins . My question is, can we use CLKBUF macro( or any other) on this inputed clock via normal I/o to connect to FPGA global network. Can any help, or have to alter the layout board and thats costly?? Regards Manish -- manishsingh1981 ------------------------------------------------------------------------ manishsingh1981's Profile: http://www.fpgacentral.com/group/member.php?userid=73 View this thread: http://www.fpgacentral.com/group/showthread.php?t=89615Article: 140006
On Apr 23, 4:04=A0pm, 'use_real_email' wrote: > Hi, > i am using a Actel ProAsic3 Device (A3P015 QN68) , i have > completed the design and now layout is been done.Now i found out that > Clock and Reset is given to a normal I/O pin instead of global pins . > > My question is, can we use CLKBUF macro( or any other) on this > inputed clock via normal I/o to connect to FPGA global network. > > Can any help, or have to alter the layout =A0board and thats > costly?? > > Regards > Manish > > -- > manishsingh1981 > ------------------------------------------------------------------------ > manishsingh1981's Profile:http://www.fpgacentral.com/group/member.php?use= rid=3D73 > View this thread:http://www.fpgacentral.com/group/showthread.php?t=3D8961= 5 CLKINTArticle: 140007
Is it possible to put area routing contraints in a xilinx flow ? I want PAR to route a part of a my design in a specefic area ... Best regards, barme2iArticle: 140008
On Apr 23, 4:35=A0am, 'use_real_email' wrote: > Gabor > Thank you for the reply.I'm sorry I didn't describe it clearly. > --What about data from B to A? > No data should be transferred from B to A. > --If not can you use LVDS for the interconnect? > Yes,I use LVDS for the interconnect . > If Virtex2 is the source, you can use DDR flops to drive the > interface. > I will have a look at DDR flops. > --What makes you think the problem is crosstalk? Do you have adequate > --grounding on the cables? > I just think it should be crosstalk,because 8 links work at the high > speed at the same time.The cables are network cables,which are not > grounded. > --Are you using DCI or series resistors at the driver to reduce > overshoot? > No,I didn't use any DCI or resistros.Can ou get a single link to work > reliably? > I just did the test in only B board,which means B sends and B receives > it back. > For one link,it workes reliably. > But for more than one link,it doesn't work,the received data is > wrong.when I do post simulation in questasim,more than one links > receiver have unknown state.even if I reduce the speed to 100 MHZ,I > don't know why. > > -- > mingyuexin > ------------------------------------------------------------------------ > mingyuexin's Profile:http://www.fpgacentral.com/group/member.php?userid= =3D72 > View this thread:http://www.fpgacentral.com/group/showthread.php?t=3D8959= 6 So you have not actually successfully tested one link, over cable, from one board to a different board? I suspect the different boards are not properly grounded, since LVDS has a very low common mode range, meaning that if their grounds differ by much, the data is incomprehendable. You need to provide for a very ground connection between the boards. Since your signaling is differential, the ground connection need not be in the network cable, but it could be put there. Network cables work with ethernet and no common ground because the signals are transformer isolated and have almost infinite common mode range. You may also be having a problem with properly synchronizing the incoming data stream and clock. Loop-backs from the same board usually share a common clock (already synchronous), so it does not show up there. AndyArticle: 140009
On Apr 23, 4:12=A0pm, barm...@gmail.com wrote: > Is it possible to put area routing contraints in a xilinx flow ? > I want PAR to route a part of a my design in a specefic area ... > > Best regards, > barme2i wait til monday ise 11.1 has PLANAHEAD integrated fully.. AnttiArticle: 140010
On Apr 23, 8:23 am, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > On Apr 23, 2:56 pm, jleslie48 <j...@jonathanleslie.com> wrote: > > > > > On Apr 23, 3:31 am, "Antti.Luk...@googlemail.com" > > > <Antti.Luk...@googlemail.com> wrote: > > > On Apr 23, 3:22 am, jleslie48 <j...@jonathanleslie.com> wrote: > > > > > On Apr 21, 8:24 pm, Brian Davis <brimda...@aol.com> wrote: > > > > > > jleslie48 wrote: > > > > > > > So it appears that driving PIN15 is not an issue at all when the > > > > > > program loads from the SP flash, and I'm leaning to the conclusion > > > > > > that the CRC error is a function of the impact 10.1 having an issue, > > > > > > making higgley-piggley out of my program and locking up the FPGA. > > > > > > >Xilinx has no documentation of any of this, and their support, well > > > > > >let's just leave it as leaves a lot to be desired. > > > > > > The conflict between SPI-mode configuration and JTAG configuration > > > > > in various Spartan-3's is well known and documented in several places > > > > > by Xilinx (see below), as well as being a fairly regular topic here. > > > > > > The only workarounds I know of are to either erase the flash > > > > > (as Antti suggested), disconnect/disable the flash, or to set > > > > > the configuration mode on the chip to JTAG when programming > > > > > the FPGA directly. > > > > > > After a quick look at the Drigmorn1 board schematic, it does not > > > > > appear that the configuration mode can be changed, as the mode pins > > > > > are hardwired to VCC/ground; the erase-the-flash-before-JTAG-download > > > > > method is probably your best bet if you want to program the FPGA > > > > > directly without loading up the SPI flash. > > > > > > Brian > > > > > > Xilinx Documentation: > > > > > > XAPP951 v1.2 Configuring Xilinx FPGAs with SPI Serial Flashhttp://www.xilinx.com/support/documentation/application_notes/xapp951... > > > > > figure3, footnote 6 : > > > > > " > > > > > " 6. For dual configuration mode usage, it is recommended to have the > > > > > " option to hold the M2 signal High for JTAG configuration mode. > > > > > " > > > > > > Answer Records: > > > > > >http://www.xilinx.com/support/answers/9013.htmhttp://www.xilinx.com/s... > > > > > Brian, > > > > > Thank you very much. It wasn't untll the end that I connected the > > > > JTAG load problem with my previous SPI load, mostly because after I > > > > loaded the SPI, I successfully changed the code using the JTAG to FPGA > > > > without any issue. It was only when I added signals to pins did the > > > > error message pop up. > > > > > One would think Xilinx would have that listed in the possible causes > > > > of the 2217 error and that a search of Xilinx for "iMpact:2217 crc > > > > error bit not 0" (the actual error message that pops up) would be > > > > acknowledged. > > > > > For the amount of money I paid for this development suite and support > > > > I cannot believe the level and frequency of bugs in the software and > > > > lack of support I get from these folks.- Hide quoted text - > > > > > - Show quoted text - > > > > impact s**** > > > always has... > > > > there are things to KNOW > > > JTAG configuration mode does OVERRIDE other modes > > > but it not always works with impact > > > > this may depend 2 bitfiles bit difference you are trying to load > > > or the speed of the PC, or the type of cable you use.. > > > > so while it should be ALWAYS be possible to configure > > > over jtag without concern of the MODE pins settings > > > with impact this isnt true > > > > i once designed a workaround that used boundary scan > > > to place the SPI flash into deep powerdown mode > > > to allow the configuration to be done properly.. > > > > Antti > > > The thing that really burns my, err kiester, is that here the iMPACT > > tool not only generates an error, but a full blown pop up window: > > > "WARNING:iMPACT:2217 - Error shows in the status register, CRC Error > > bit is NOT 0. " > > > that I have to click an [OK] button to get around. > > > first off, its not a warning it totally KILLS the fpga. that's not a > > warning thats a FATAL ERROR. > > > secondly and more importantly, How in god's name can it be that if I > > search Xilinx for that exact error I don't get a connection to the > > links that Brian so nicely provided? Here the problem is a known > > issue for 2 years, yet its most glaring symptom, a big pop up window > > with an error code, can't be cross referenced against what caused the > > error. That is pathetic. > > > Meantime Webcase support is 3 days into looking at the issue, and all > > they can tell me is do I have the unit powered up... > > > This I pay $600 a year for. This forum should be getting the $600... > > > Thanks everyone. > > > - Jon- Hide quoted text - > > > - Show quoted text - > > Jon, > > I forgot... your problem is you are paying too little !!! > > there is "Xilinx Platinum support" option they promise > that clients will speed up time to market by 6 months > if they use Platinum support. > > 6 month TTM is more then 6 man-manths, I wonder > how much Xilinx takes for this service. But I can > see how those 6 months are posssible to save.. > (you need sick software, and sick documents and support - > this opens the window for the platinum guys todo miracle > in saving customer frustration) > > everybody can milder the above saying to their liking.. > > its not that bad always, even xilinx software is getting better > (in some ways at least) > > Antti My letter to Xilinx: Possibly the worst website support center/response to issues I have ever had to pay for. Thursday, April 23, 2009 9:28 AM From: "Jonathan Leslie" <jleslie48@yahoo.com> To: isscs_cases@xilinx.com Cc: eucases@xilinx.com, apaccase@xilinx.com The level of amateur responses and website development at the Xilinx website and support center is inexcusable. Between having to login in every 10 minutes, and a search engine that can't find anything, and webcase responses that make make a rag of a newspapers horoscope section seem intelligent. I cannot believe that you have the nerve to charge money for this. Ok, so I found my solution, this is an known issue. a known issue for some 2 years and yet to be fixed: Answer Records: http://www.xilinx.com/support/answers/9013.htm http://www.xilinx.com/support/answers/22142.htm http://www.xilinx.com/support/answers/22255.htm http://www.xilinx.com/support/answers/16829.htm the moral is you can't use the JTAG load if the SPI is loaded with a program. Just load up the SPI. The thing that really annoys me is that here the iMPACT tool not only generates an error, but a full blown pop up window: "WARNING:iMPACT:2217 - Error shows in the status register, CRC Error bit is NOT 0. " that I have to click an [OK] button to get around. first off, its not a warning, it totally KILLS the fpga. that's not a warning, that's a FATAL ERROR. secondly and more importantly, How in god's name can it be that if I search Xilinx for that exact error I don't get a connection to the known issue? Here the problem is a known issue for 2 years, yet its most glaring symptom, a big pop up window with an error code, can't be cross referenced against what caused the error. That is inexcusable. For that matter, not one response of your search engine for "warning 2217" comes up with any match against any of your hundreds of 1000's of documents. IT'S YOUR OWN ERROR MESSAGE. How is it possible I can't look up YOUR OWN ERROR MESSAGE ON YOUR OWN WEBSITE????? It is inexcusable. I have always said that Xilinx puts out so much documentation just to say its documented (aka, CYA) but really is just hiding behind complete incompetence in organization. Here is just another example. Meantime Webcase support is 3 days into looking at the issue, and all they can tell me is do I have the unit powered up... This I pay $600 a year for. I bother you guys 3 maybe 4 times a year, and I can't even get someone with half a brain to look at the problem, which if they properly organized their errors and known issues should of been a 10-minute to solution lookup.Article: 140011
On Apr 23, 7:56 am, jleslie48 <j...@jonathanleslie.com> wrote: > On Apr 23, 3:31 am, "Antti.Luk...@googlemail.com" > > > > <Antti.Luk...@googlemail.com> wrote: > > On Apr 23, 3:22 am, jleslie48 <j...@jonathanleslie.com> wrote: > > > > On Apr 21, 8:24 pm, Brian Davis <brimda...@aol.com> wrote: > > > > > jleslie48 wrote: > > > > > > So it appears that driving PIN15 is not an issue at all when the > > > > > program loads from the SP flash, and I'm leaning to the conclusion > > > > > that the CRC error is a function of the impact 10.1 having an issue, > > > > > making higgley-piggley out of my program and locking up the FPGA. > > > > > >Xilinx has no documentation of any of this, and their support, well > > > > >let's just leave it as leaves a lot to be desired. > > > > > The conflict between SPI-mode configuration and JTAG configuration > > > > in various Spartan-3's is well known and documented in several places > > > > by Xilinx (see below), as well as being a fairly regular topic here. > > > > > The only workarounds I know of are to either erase the flash > > > > (as Antti suggested), disconnect/disable the flash, or to set > > > > the configuration mode on the chip to JTAG when programming > > > > the FPGA directly. > > > > > After a quick look at the Drigmorn1 board schematic, it does not > > > > appear that the configuration mode can be changed, as the mode pins > > > > are hardwired to VCC/ground; the erase-the-flash-before-JTAG-download > > > > method is probably your best bet if you want to program the FPGA > > > > directly without loading up the SPI flash. > > > > > Brian > > > > > Xilinx Documentation: > > > > > XAPP951 v1.2 Configuring Xilinx FPGAs with SPI Serial Flashhttp://www.xilinx.com/support/documentation/application_notes/xapp951... > > > > figure3, footnote 6 : > > > > " > > > > " 6. For dual configuration mode usage, it is recommended to have the > > > > " option to hold the M2 signal High for JTAG configuration mode. > > > > " > > > > > Answer Records: > > > > >http://www.xilinx.com/support/answers/9013.htmhttp://www.xilinx.com/s... > > > > Brian, > > > > Thank you very much. It wasn't untll the end that I connected the > > > JTAG load problem with my previous SPI load, mostly because after I > > > loaded the SPI, I successfully changed the code using the JTAG to FPGA > > > without any issue. It was only when I added signals to pins did the > > > error message pop up. > > > > One would think Xilinx would have that listed in the possible causes > > > of the 2217 error and that a search of Xilinx for "iMpact:2217 crc > > > error bit not 0" (the actual error message that pops up) would be > > > acknowledged. > > > > For the amount of money I paid for this development suite and support > > > I cannot believe the level and frequency of bugs in the software and > > > lack of support I get from these folks.- Hide quoted text - > > > > - Show quoted text - > > > impact s**** > > always has... > > > there are things to KNOW > > JTAG configuration mode does OVERRIDE other modes > > but it not always works with impact > > > this may depend 2 bitfiles bit difference you are trying to load > > or the speed of the PC, or the type of cable you use.. > > > so while it should be ALWAYS be possible to configure > > over jtag without concern of the MODE pins settings > > with impact this isnt true > > > i once designed a workaround that used boundary scan > > to place the SPI flash into deep powerdown mode > > to allow the configuration to be done properly.. > > > Antti > > The thing that really burns my, err kiester, is that here the iMPACT > tool not only generates an error, but a full blown pop up window: > > "WARNING:iMPACT:2217 - Error shows in the status register, CRC Error > bit is NOT 0. " > > that I have to click an [OK] button to get around. > > first off, its not a warning it totally KILLS the fpga. that's not a > warning thats a FATAL ERROR. > > secondly and more importantly, How in god's name can it be that if I > search Xilinx for that exact error I don't get a connection to the > links that Brian so nicely provided? Here the problem is a known > issue for 2 years, yet its most glaring symptom, a big pop up window > with an error code, can't be cross referenced against what caused the > error. That is pathetic. > > Meantime Webcase support is 3 days into looking at the issue, and all > they can tell me is do I have the unit powered up... > > This I pay $600 a year for. This forum should be getting the $600... > > Thanks everyone. If you want a connection to be made between the problem and the links Brian provided, try making a report. First, be sure to search in other ways for these links in the Xilinx data base. If you find them, it may have just been a glitch in the search engine. If you don't find them, then making a report will likely result in a data base entry. That is how most of the data base is built, from reported problems and solutions that are found. RickArticle: 140012
Any other way ?Article: 140013
On Apr 23, 5:11=A0pm, barm...@gmail.com wrote: > Any other way ? there is this recobuilder thing try that anttiArticle: 140014
hi antti, thanks for quick responce...but isnt CLKINT is for putting signal from internal logic onto global network, my signal is coming from normal I/O pin.So should i use CLKINT or CLKBUF ?? rgds manish -- manishsingh1981 ------------------------------------------------------------------------ manishsingh1981's Profile: http://www.fpgacentral.com/group/member.php?userid=73 View this thread: http://www.fpgacentral.com/group/showthread.php?t=89615Article: 140015
On Apr 23, 6:17=A0pm, 'use_real_email' wrote: > hi antti, > thanks for quick responce...but isnt CLKINT is for putting > signal from internal logic onto global network, my signal is coming from > normal I/O pin.So should i use CLKINT or CLKBUF ?? > > rgds > manish > > -- > manishsingh1981 > ------------------------------------------------------------------------ > manishsingh1981's Profile:http://www.fpgacentral.com/group/member.php?use= rid=3D73 > View this thread:http://www.fpgacentral.com/group/showthread.php?t=3D8961= 5 CLKINTArticle: 140016
On Apr 22, 5:27=A0pm, jprovide...@yahoo.com wrote: > For faster simulations of my design, I developed a Verilog functional > model of > the Xilinx MIG DDR2 memory controller user application interface. > Since > it is intended to for testing "user" logic, it does not implement a > real controller > (the DDR2 pins don't wiggle). =A0Instead, the model uses an internal > sparse memory array > to store data instead of using an actual (slow) DDR2 memory model. > Rows of memory > are allocated as needed up to a maximum number of rows set by an > internal parameter. > > Peek & Poke are also implemented to allow preloading or verifying > memory by a testbed. > > I have not thoroughly tested the model yet, but it is passing my basic > tests. > > You can access the model at > =A0 =A0 =A0 =A0 =A0http://probo.com/mig_ddr2_bfm.php > > Hopefully, the code is well enough commented to get you going! > > Comments & feedback are welcome. > > John Providenza I wish I'd had this when I did my last Virtex-5 design :) Any plans to do the Spartan-3 interface version? It's entirely different from the Virtex DDR2 at the user interface side... Regards, GaborArticle: 140017
On Apr 23, 10:15=A0am, gabor <ga...@alacron.com> wrote: > On Apr 22, 5:27=A0pm, jprovide...@yahoo.com wrote: > > > > > For faster simulations of my design, I developed a Verilog functional > > model of > > the Xilinx MIG DDR2 memory controller user application interface. > > Since > > it is intended to for testing "user" logic, it does not implement a > > real controller > > (the DDR2 pins don't wiggle). =A0Instead, the model uses an internal > > sparse memory array > > to store data instead of using an actual (slow) DDR2 memory model. > > Rows of memory > > are allocated as needed up to a maximum number of rows set by an > > internal parameter. > > > Peek & Poke are also implemented to allow preloading or verifying > > memory by a testbed. > > > I have not thoroughly tested the model yet, but it is passing my basic > > tests. > > > You can access the model at > > =A0 =A0 =A0 =A0 =A0http://probo.com/mig_ddr2_bfm.php > > > Hopefully, the code is well enough commented to get you going! > > > Comments & feedback are welcome. > > > John Providenza > > I wish I'd had this when I did my last Virtex-5 design :) > > Any plans to do the Spartan-3 interface version? =A0It's entirely > different from the Virtex DDR2 at the user interface side... > > Regards, > Gabor I don't have any immediate plans to do a S3 version. I suspect that it shouldn't be that much work to use my V5 version as a springboard to create a S3 version. I should note that I haven't spent a bunch of time yet testing the DDR2 burst order logic. I'll try to do that today. John ProvidenzaArticle: 140018
When I started this project I only had one file in the prject I got used
to the convention of
a.v creating a_timesim.v
creating a_synthesis.v
creating a_timesim.sdf
Now that I have 3 modules designed and in separate files I would like to
continue the above convention.
When I ticked the Generate Multiple Hierarchical Netlist files button I got
a,v creates a_a_sim.v
b.v creates b_synthese.v
Is there any way of continuing the first naming convention. Do I need a
different synthesis option or to write a tcl script to do it? Thanks in
advance for any pointers. Andy
Article: 140019I'm looking for a development board with an on-board ARM9. I've seen the ARM-Cortex-M1 that is available on Altera. That might work. In that case, the ARM core is synthesized directly inside the FPGA... probably ok for me. But I have to assume that there are already boards out there with an FPGA plus an ARM9. Xilinx would be nice since I already have the tools and a rough familiarity. But any FPGA vendor is probably ok. Cheers.Article: 140020
On Thu, 23 Apr 2009 05:16:57 -0700 (PDT), "Antti.Lukats@googlemail.com" <Antti.Lukats@googlemail.com> wrote: > >HA HA HA > >I talked with my wife once about xilinx "Answer Record" system >saying, you know they have special AR database, there are 30K+ > >here she interrupted me: > >"Ah this is the place where you DO NOT GET ANSWERS!" > >I said, yes this is the place. > >If you dont know the AR number, you would not find it. Heh, that's a BIG improvement! Used to be, if you DID know the AR# you still didn't find it! You could search on an AR number and search would come up with nothing... The only way I could find the AR was to search for something else, click on any AR, then edit the AR# into the URL... So at least Xilinx have fixed something! I even opened a webcase that they should do the same for error, warning and info numbers; even if you only get a default page for that number until there is some content to add. Like "see <link to AR12345> for more information" or "No content yet. Open a webcase to start the content for this page" - BrianArticle: 140021
I realize that it is not completely achievable, but there is much commonality across o/s - message, timer, mutex/semaphore, thread, etc Does anyone know of an open source cross-platform operating system abstraction solution? I code generally in either C or C++ and am interested in unit testing on PC code which is destined for an embedded system. Are there any good solutions out there? How do others do it? Thanks in advance for any help.Article: 140022
Antti wrote: > Hi _o/ <snip> > japanese mr16 is a small 16 bit RISC with assembler > (aasm-with sources and mr16 support macros) > small soc with mr16+12 16 bit gpout, + timer unit > takes 291 xilinx slices > it might be the nices 16 bit core around... I would enjoy seeing this :-) > Antti yg -- http://ygdes.com / http://yasep.orgArticle: 140023
Hi while organizing my past life projects, i refound the NIOX code it is somewhat NIOS-II compatible, vendor neutral verilog xilinx tools say 740 slices if anybody interested to take a look or use-modify it please contact me, I am not sure if i re-release the sources again or not --------------------- 2] japanese mr16 is a small 16 bit RISC with assembler (aasm-with sources and mr16 support macros) small soc with mr16+12 16 bit gpout, + timer unit takes 291 xilinx slices it might be the nices 16 bit core around... AnttiArticle: 140024
On Apr 24, 10:27=A0am, whygee <why...@yg.yg> wrote: > Antti wrote: > > Hi > > _o/ > > <snip> > > > japanese mr16 is a small 16 bit RISC with assembler > > (aasm-with sources and mr16 support macros) > > small soc with mr16+12 16 bit gpout, + timer unit > > takes 291 xilinx slices > > it might be the nices 16 bit core around... > > I would enjoy seeing this :-) > > > Antti > > yg > > --http://ygdes.com/http://yasep.org google mr16 verilog take first hit
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