Messages from 140100

Article: 140100
Subject: Re: FPGA/DSP/Video Board
From: Petter Gustad <newsmailcomp6@gustad.com>
Date: Tue, 28 Apr 2009 22:45:20 +0200
Links: << >> << T >> << A >>

Andy Peters <google@latke.net> writes:


> I have a Solios eCL (digital Camera Link) in my development machine
> and we use both Solios and Helios cards. Medium CL supports up to 85
> MHz pixel clock with a variety of pixel formats. There's not enough
> bandwidth for 1080p/60 but it can do 30 no problem.

Thank you for your reply. I'm looking for something which can handle
1080p/60 or more. 

Petter

-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 140101
Subject: ISE11.1 environment variables mess
From: "MM" <mbmsv@yahoo.com>
Date: Tue, 28 Apr 2009 17:28:48 -0400
Links: << >> << T >> << A >>

Arghhh! Is Xilinx ever going to learn to make things relative?!!! If they 
defined %XILINX% why do they put whole bunch of absolute paths to the PATH?

C:\Xilinx\11.1\ChipScope\bin\nt;C:\Xilinx\11.1\common\bin\nt;C:\Xilinx\11.1\common\lib\nt;

Don't really expect an answer, just needed to let the steam out ....

/Mikhail

Article: 140102
Subject: Re: ISE 11.1 Webpack: How to install for Suse 64 Bits?
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Tue, 28 Apr 2009 23:26:32 +0100
Links: << >> << T >> << A >>

On Tue, 28 Apr 2009 10:14:44 +0000 (UTC), Uwe Bonnes
<bon@elektron.ikp.physik.tu-darmstadt.de> wrote:

>Software_matrix.pdf for Xilinx ISE 11.1 lists "SUSE Linux Enterprise 10*
>64-bit" supported for webpack.  Downloading the whole file
>Xilinx_11.1_WebPack_SFD.tar, untarring and running ./xsetup gives
>"Product is not supported on "Linux x86_64" platform" as with 10.1, and there
>is no bin/lin64 as required by xsetup.
>
>What counts?

Is Webpack supported for 64 bit in ISE11? 
It never was in ISE10.1 ... but would happily install and run in Suse 64 anyway
(with the Suse 32-bit compatibility libraries)

All I had to do was find the 32-bit/64 bit platform test in the setup script,
and comment out the "exit" line so it went on to install anyway. 
Perhaps the same still applies in 11.1?

- Brian

Article: 140103
Subject: Re: a basics question: using input pins, pullup, short to ground
From: Jeff Cunningham <jcc@sover.net>
Date: Tue, 28 Apr 2009 20:07:32 -0400
Links: << >> << T >> << A >>

jleslie48 wrote:
> Ok, my electrical non-background is showing.
> 
> So I've got some pins that I'm driving and all is well on a
> Spartan3e.
> looking at the pins on the scope, they sit at 0 volts for a '0' and
> looks like 3.3v on a '1'
> 
> 
> Now the only inputs I use are on pins 11 and 12, and the UCF looks
> like this:
> 
> NET "BUTTON_1" LOC = "F12" | PULLUP ;    #"FPGA_IO17"  pin 11
> NET "BUTTON_2" LOC = "F14" | PULLUP ;    #"FPGA_IO18"  pin 12
> NET "PIN13_LED" LOC = "F2";                     #"FPGA_IO19"   driven
> output.
> 
> Now the way the buttons work is on the scope they show 3.3 volts, and
> I have them hooked up to a normally open momentary switch that will
> attach this signal to ground when closed.  When I push the button (viz
> "pull to ground"????) the button, the VHDL program recognizes the
> signal as a switch from 0 to 1 (give or take a debounce) Now when I
> put a scope on my input pin, I see it is up at 3.3 volts, and when the
> button is pushed, it drops to 0.
> 
> It seems to me this is not a good setup for using one of my output
> pins attached to one of my inputs.  At some point both pins have 3.3
> volts on them, and those two wires are attached.
> 
> My question is if I want to take my driven output and run it around as
> an input signal, how do I do that?

Are you saying you want to connect an output pin to an input pin and 
leave the pushbutton connected so that either can drive the input?

Make the output pin so called "open collector" that only drives low and 
floats high.

outputpin <= '0' when mysignal = '0' else 'Z;

-Jeff

Article: 140104
Subject: Re: a basics question: using input pins, pullup, short to ground vs
From: jleslie48 <jon@jonathanleslie.com>
Date: Tue, 28 Apr 2009 17:22:31 -0700 (PDT)
Links: << >> << T >> << A >>

On Apr 28, 8:07 pm, Jeff Cunningham <j...@sover.net> wrote:
> jleslie48 wrote:
> > Ok, my electrical non-background is showing.
>
> > So I've got some pins that I'm driving and all is well on a
> > Spartan3e.
> > looking at the pins on the scope, they sit at 0 volts for a '0' and
> > looks like 3.3v on a '1'
>
> > Now the only inputs I use are on pins 11 and 12, and the UCF looks
> > like this:
>
> > NET "BUTTON_1" LOC = "F12" | PULLUP ;    #"FPGA_IO17"  pin 11
> > NET "BUTTON_2" LOC = "F14" | PULLUP ;    #"FPGA_IO18"  pin 12
> > NET "PIN13_LED" LOC = "F2";                     #"FPGA_IO19"   driven
> > output.
>
> > Now the way the buttons work is on the scope they show 3.3 volts, and
> > I have them hooked up to a normally open momentary switch that will
> > attach this signal to ground when closed.  When I push the button (viz
> > "pull to ground"????) the button, the VHDL program recognizes the
> > signal as a switch from 0 to 1 (give or take a debounce) Now when I
> > put a scope on my input pin, I see it is up at 3.3 volts, and when the
> > button is pushed, it drops to 0.
>
> > It seems to me this is not a good setup for using one of my output
> > pins attached to one of my inputs.  At some point both pins have 3.3
> > volts on them, and those two wires are attached.
>
> > My question is if I want to take my driven output and run it around as
> > an input signal, how do I do that?
>
> Are you saying you want to connect an output pin to an input pin and
> leave the pushbutton connected so that either can drive the input?
>
> Make the output pin so called "open collector" that only drives low and
> floats high.
>
> outputpin <= '0' when mysignal = '0' else 'Z;
>
> -Jeff

nothing so complicated.

So far for input I've taken an input pin that was labeled in the UCF
as

NET "BUTTON_1" LOC = "F12" | PULLUP ;    #"FPGA_IO17"  pin 11

attached a wire to itand tied it to ground with a normally open switch
in between to control whether or not the FPGA is seeing a 0 or a 1.

Now I have an external wire that I have to hook up to a pin that I
label as an "IN STD_LOGIC;"  and that external wire has nothing to do
with being tied to ground, its just a wire with either 3.3 volts or 0
volts, how do I get the FPGA to recognize that the volts are supposed
to come from the external wire and be interpreted as a 0 or a 1?

Article: 140105
Subject: Re: a basics question: using input pins, pullup, short to ground vs
From: jleslie48 <jon@jonathanleslie.com>
Date: Tue, 28 Apr 2009 17:30:35 -0700 (PDT)
Links: << >> << T >> << A >>

On Apr 28, 8:07 pm, Jeff Cunningham <j...@sover.net> wrote:
> jleslie48 wrote:
> > Ok, my electrical non-background is showing.
>
> > So I've got some pins that I'm driving and all is well on a
> > Spartan3e.
> > looking at the pins on the scope, they sit at 0 volts for a '0' and
> > looks like 3.3v on a '1'
>
> > Now the only inputs I use are on pins 11 and 12, and the UCF looks
> > like this:
>
> > NET "BUTTON_1" LOC = "F12" | PULLUP ;    #"FPGA_IO17"  pin 11
> > NET "BUTTON_2" LOC = "F14" | PULLUP ;    #"FPGA_IO18"  pin 12
> > NET "PIN13_LED" LOC = "F2";                     #"FPGA_IO19"   driven
> > output.
>
> > Now the way the buttons work is on the scope they show 3.3 volts, and
> > I have them hooked up to a normally open momentary switch that will
> > attach this signal to ground when closed.  When I push the button (viz
> > "pull to ground"????) the button, the VHDL program recognizes the
> > signal as a switch from 0 to 1 (give or take a debounce) Now when I
> > put a scope on my input pin, I see it is up at 3.3 volts, and when the
> > button is pushed, it drops to 0.
>
> > It seems to me this is not a good setup for using one of my output
> > pins attached to one of my inputs.  At some point both pins have 3.3
> > volts on them, and those two wires are attached.
>
> > My question is if I want to take my driven output and run it around as
> > an input signal, how do I do that?
>
> Are you saying you want to connect an output pin to an input pin and
> leave the pushbutton connected so that either can drive the input?
>
> Make the output pin so called "open collector" that only drives low and
> floats high.
>
> outputpin <= '0' when mysignal = '0' else 'Z;
>
> -Jeff

the part that confuses me, is the 3.3 volts that I see sitting on the
input pin when its not tied to ground.  how can I send "in" from the
external wire 3.3 volts when it already has 3.3 volts on it?

Article: 140106
Subject: Re: a basics question: using input pins, pullup, short to ground vs
From: jleslie48 <jon@jonathanleslie.com>
Date: Tue, 28 Apr 2009 17:38:05 -0700 (PDT)
Links: << >> << T >> << A >>

On Apr 28, 8:07 pm, Jeff Cunningham <j...@sover.net> wrote:
> jleslie48 wrote:
> > Ok, my electrical non-background is showing.
>
> > So I've got some pins that I'm driving and all is well on a
> > Spartan3e.
> > looking at the pins on the scope, they sit at 0 volts for a '0' and
> > looks like 3.3v on a '1'
>
> > Now the only inputs I use are on pins 11 and 12, and the UCF looks
> > like this:
>
> > NET "BUTTON_1" LOC = "F12" | PULLUP ;    #"FPGA_IO17"  pin 11
> > NET "BUTTON_2" LOC = "F14" | PULLUP ;    #"FPGA_IO18"  pin 12
> > NET "PIN13_LED" LOC = "F2";                     #"FPGA_IO19"   driven
> > output.
>
> > Now the way the buttons work is on the scope they show 3.3 volts, and
> > I have them hooked up to a normally open momentary switch that will
> > attach this signal to ground when closed.  When I push the button (viz
> > "pull to ground"????) the button, the VHDL program recognizes the
> > signal as a switch from 0 to 1 (give or take a debounce) Now when I
> > put a scope on my input pin, I see it is up at 3.3 volts, and when the
> > button is pushed, it drops to 0.
>
> > It seems to me this is not a good setup for using one of my output
> > pins attached to one of my inputs.  At some point both pins have 3.3
> > volts on them, and those two wires are attached.
>
> > My question is if I want to take my driven output and run it around as
> > an input signal, how do I do that?
>
> Are you saying you want to connect an output pin to an input pin and
> leave the pushbutton connected so that either can drive the input?
>
> Make the output pin so called "open collector" that only drives low and
> floats high.
>
> outputpin <= '0' when mysignal = '0' else 'Z;
>
> -Jeff

nothing that complicated.   I just don't understand how to take a 3.3
volt signal and send it in to the input pin.

so far, the only way I've gotten input on a pin to work is to have a
wire on the pin attached to a normally open switch.  When the switch
is open I see 3.3 volts on the wire, but when I close the switch, the
input pin is connected to ground and the oscilliscope show 0 volts on
the wire not, 3.3.  the open switch is a logical 0, and when its
grounded a logical 1 (or vice versa)

In the new situation, there is no ground, just the input pin and some
other wire that has a signal on it, at 3.3 volts.

Its an electrical question, I mean I somehow have to attach my input
pin to the external wire rather than to ground, but that means there
will be two 3.3 volt signals on that wire, that doesn't sound good.

Article: 140107
Subject: Re: a basics question: using input pins, pullup, short to ground vs
From: jleslie48 <jon@jonathanleslie.com>
Date: Tue, 28 Apr 2009 17:42:09 -0700 (PDT)
Links: << >> << T >> << A >>

On Apr 28, 8:38 pm, jleslie48 <j...@jonathanleslie.com> wrote:
> On Apr 28, 8:07 pm, Jeff Cunningham <j...@sover.net> wrote:
>
>
>
> > jleslie48 wrote:
> > > Ok, my electrical non-background is showing.
>
> > > So I've got some pins that I'm driving and all is well on a
> > > Spartan3e.
> > > looking at the pins on the scope, they sit at 0 volts for a '0' and
> > > looks like 3.3v on a '1'
>
> > > Now the only inputs I use are on pins 11 and 12, and the UCF looks
> > > like this:
>
> > > NET "BUTTON_1" LOC = "F12" | PULLUP ;    #"FPGA_IO17"  pin 11
> > > NET "BUTTON_2" LOC = "F14" | PULLUP ;    #"FPGA_IO18"  pin 12
> > > NET "PIN13_LED" LOC = "F2";                     #"FPGA_IO19"   driven
> > > output.
>
> > > Now the way the buttons work is on the scope they show 3.3 volts, and
> > > I have them hooked up to a normally open momentary switch that will
> > > attach this signal to ground when closed.  When I push the button (viz
> > > "pull to ground"????) the button, the VHDL program recognizes the
> > > signal as a switch from 0 to 1 (give or take a debounce) Now when I
> > > put a scope on my input pin, I see it is up at 3.3 volts, and when the
> > > button is pushed, it drops to 0.
>
> > > It seems to me this is not a good setup for using one of my output
> > > pins attached to one of my inputs.  At some point both pins have 3.3
> > > volts on them, and those two wires are attached.
>
> > > My question is if I want to take my driven output and run it around as
> > > an input signal, how do I do that?
>
> > Are you saying you want to connect an output pin to an input pin and
> > leave the pushbutton connected so that either can drive the input?
>
> > Make the output pin so called "open collector" that only drives low and
> > floats high.
>
> > outputpin <= '0' when mysignal = '0' else 'Z;
>
> > -Jeff
>
> nothing that complicated.   I just don't understand how to take a 3.3
> volt signal and send it in to the input pin.
>
> so far, the only way I've gotten input on a pin to work is to have a
> wire on the pin attached to a normally open switch.  When the switch
> is open I see 3.3 volts on the wire, but when I close the switch, the
> input pin is connected to ground and the oscilliscope show 0 volts on
> the wire not, 3.3.  the open switch is a logical 0, and when its
> grounded a logical 1 (or vice versa)
>
> In the new situation, there is no ground, just the input pin and some
> other wire that has a signal on it, at 3.3 volts.
>
> Its an electrical question, I mean I somehow have to attach my input
> pin to the external wire rather than to ground, but that means there
> will be two 3.3 volt signals on that wire, that doesn't sound good.

In the new situation, there is no ground AND NO SWITCH. just the input
pin and some
other wire that has a signal on it, at 3.3 volts.

- I keep forgetting to say that.  the switch is no longer there.  I
~should~ just be sending in the external signal to the input pin, but
my instinct tells me I'm gonna smoke something when I solder two wires
with 3.3 volts together...

Article: 140108
Subject: Re: a basics question: using input pins, pullup, short to ground vs
From: jleslie48 <jon@jonathanleslie.com>
Date: Tue, 28 Apr 2009 17:42:48 -0700 (PDT)
Links: << >> << T >> << A >>

On Apr 28, 8:38 pm, jleslie48 <j...@jonathanleslie.com> wrote:
> On Apr 28, 8:07 pm, Jeff Cunningham <j...@sover.net> wrote:
>
>
>
> > jleslie48 wrote:
> > > Ok, my electrical non-background is showing.
>
> > > So I've got some pins that I'm driving and all is well on a
> > > Spartan3e.
> > > looking at the pins on the scope, they sit at 0 volts for a '0' and
> > > looks like 3.3v on a '1'
>
> > > Now the only inputs I use are on pins 11 and 12, and the UCF looks
> > > like this:
>
> > > NET "BUTTON_1" LOC = "F12" | PULLUP ;    #"FPGA_IO17"  pin 11
> > > NET "BUTTON_2" LOC = "F14" | PULLUP ;    #"FPGA_IO18"  pin 12
> > > NET "PIN13_LED" LOC = "F2";                     #"FPGA_IO19"   driven
> > > output.
>
> > > Now the way the buttons work is on the scope they show 3.3 volts, and
> > > I have them hooked up to a normally open momentary switch that will
> > > attach this signal to ground when closed.  When I push the button (viz
> > > "pull to ground"????) the button, the VHDL program recognizes the
> > > signal as a switch from 0 to 1 (give or take a debounce) Now when I
> > > put a scope on my input pin, I see it is up at 3.3 volts, and when the
> > > button is pushed, it drops to 0.
>
> > > It seems to me this is not a good setup for using one of my output
> > > pins attached to one of my inputs.  At some point both pins have 3.3
> > > volts on them, and those two wires are attached.
>
> > > My question is if I want to take my driven output and run it around as
> > > an input signal, how do I do that?
>
> > Are you saying you want to connect an output pin to an input pin and
> > leave the pushbutton connected so that either can drive the input?
>
> > Make the output pin so called "open collector" that only drives low and
> > floats high.
>
> > outputpin <= '0' when mysignal = '0' else 'Z;
>
> > -Jeff
>
> nothing that complicated.   I just don't understand how to take a 3.3
> volt signal and send it in to the input pin.
>
> so far, the only way I've gotten input on a pin to work is to have a
> wire on the pin attached to a normally open switch.  When the switch
> is open I see 3.3 volts on the wire, but when I close the switch, the
> input pin is connected to ground and the oscilliscope show 0 volts on
> the wire not, 3.3.  the open switch is a logical 0, and when its
> grounded a logical 1 (or vice versa)
>
> In the new situation, there is no ground, just the input pin and some
> other wire that has a signal on it, at 3.3 volts.
>
> Its an electrical question, I mean I somehow have to attach my input
> pin to the external wire rather than to ground, but that means there
> will be two 3.3 volt signals on that wire, that doesn't sound good.


In the new situation, there is no ground AND NO SWITCH. just the input
pin and some
other wire that has a signal on it, at 3.3 volts.

- I keep forgetting to say that.  the switch is no longer there.  I
~should~ just be sending in the external signal to the input pin, but
my instinct tells me I'm gonna smoke something when I solder two wires
with 3.3 volts together...

Article: 140109
Subject: Re: a basics question: using input pins, pullup, short to ground vs
From: jleslie48 <jon@jonathanleslie.com>
Date: Tue, 28 Apr 2009 17:45:01 -0700 (PDT)
Links: << >> << T >> << A >>

On Apr 28, 8:07 pm, Jeff Cunningham <j...@sover.net> wrote:
> jleslie48 wrote:
> > Ok, my electrical non-background is showing.
>
> > So I've got some pins that I'm driving and all is well on a
> > Spartan3e.
> > looking at the pins on the scope, they sit at 0 volts for a '0' and
> > looks like 3.3v on a '1'
>
> > Now the only inputs I use are on pins 11 and 12, and the UCF looks
> > like this:
>
> > NET "BUTTON_1" LOC = "F12" | PULLUP ;    #"FPGA_IO17"  pin 11
> > NET "BUTTON_2" LOC = "F14" | PULLUP ;    #"FPGA_IO18"  pin 12
> > NET "PIN13_LED" LOC = "F2";                     #"FPGA_IO19"   driven
> > output.
>
> > Now the way the buttons work is on the scope they show 3.3 volts, and
> > I have them hooked up to a normally open momentary switch that will
> > attach this signal to ground when closed.  When I push the button (viz
> > "pull to ground"????) the button, the VHDL program recognizes the
> > signal as a switch from 0 to 1 (give or take a debounce) Now when I
> > put a scope on my input pin, I see it is up at 3.3 volts, and when the
> > button is pushed, it drops to 0.
>
> > It seems to me this is not a good setup for using one of my output
> > pins attached to one of my inputs.  At some point both pins have 3.3
> > volts on them, and those two wires are attached.
>
> > My question is if I want to take my driven output and run it around as
> > an input signal, how do I do that?
>
> Are you saying you want to connect an output pin to an input pin and
> leave the pushbutton connected so that either can drive the input?
>
> Make the output pin so called "open collector" that only drives low and
> floats high.
>
> outputpin <= '0' when mysignal = '0' else 'Z;
>
> -Jeff


In the new situation, there is no ground AND NO SWITCH. just the input
pin and some
other wire that has a signal on it, at 3.3 volts.

- I keep forgetting to say that.  the switch is no longer there.  I
~should~ just be sending in the external signal to the input pin, but
my instinct tells me I'm gonna smoke something when I solder two wires
with 3.3 volts together...

Article: 140110
Subject: Re: a basics question: using input pins, pullup, short to ground vs driven signal.
From: Muzaffer Kal <kal@dspia.com>
Date: Tue, 28 Apr 2009 17:46:44 -0700
Links: << >> << T >> << A >>

On Tue, 28 Apr 2009 17:30:35 -0700 (PDT), jleslie48
<jon@jonathanleslie.com> wrote:

>> > My question is if I want to take my driven output and run it around as
>> > an input signal, how do I do that?
>>
>> Are you saying you want to connect an output pin to an input pin and
>> leave the pushbutton connected so that either can drive the input?
>>
>> Make the output pin so called "open collector" that only drives low and
>> floats high.
>>
>> outputpin <= '0' when mysignal = '0' else 'Z;
>>
>> -Jeff
>
>the part that confuses me, is the 3.3 volts that I see sitting on the
>input pin when its not tied to ground.  how can I send "in" from the
>external wire 3.3 volts when it already has 3.3 volts on it?

If you consider that there is always a connection to the input pin, I
think it would clear up your issue. If you have a pull-up with 3.3V
and the input agrees with it, you are sending in a high signal. If
your external driver disagrees with the pull-up and drives a 0, you're
sending in a low signal. If you had a 3rd state where you didn't know
if a driver is connected then you might need another signal to detect
if there is a driver or only if the pull-up is connected but I don't
think that's your configuration (actually even in that case, with a
true tri-state IO you can detect if a driver is "driving" or not).
Does that help?
-- 
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

Article: 140111
Subject: Re: a basics question: using input pins, pullup, short to ground vs driven signal.
From: Muzaffer Kal <kal@dspia.com>
Date: Tue, 28 Apr 2009 17:56:33 -0700
Links: << >> << T >> << A >>

On Tue, 28 Apr 2009 17:38:05 -0700 (PDT), jleslie48
<jon@jonathanleslie.com> wrote:

>Its an electrical question, I mean I somehow have to attach my input
>pin to the external wire rather than to ground, but that means there
>will be two 3.3 volt signals on that wire, that doesn't sound good.

You directly attach the external wire to the input pin. The pull-up on
the input pin is a weak pull-up so when the external wire is at 3.3V,
it agrees with the pull-up and you see a high signal internally. When
the external signal is driving 0V, it overrides the pull-up and pulls
the input node to ground and you see a low internally. There is no
issue with the pull-up pulling to 3.3V and the external wire also
driving a 3.3V to the same node.
-- 
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

Article: 140112
Subject: Re: a basics question: using input pins, pullup, short to ground vs ?driven signal.
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Wed, 29 Apr 2009 00:56:37 +0000 (UTC)
Links: << >> << T >> << A >>

jleslie48 <jon@jonathanleslie.com> wrote:
(snip)

>> > NET "BUTTON_1" LOC = "F12" | PULLUP ;    #"FPGA_IO17"  pin 11
(snip)

> the part that confuses me, is the 3.3 volts that I see sitting on the
> input pin when its not tied to ground.  how can I send "in" from the
> external wire 3.3 volts when it already has 3.3 volts on it?

See the part that says PULLUP?  That turns on a resistor to 3.3V
on the output.  Then you can pull down to ground with the switch
or an output configured to sink current only.  

Another post indicates how to generate an "open drain" output,
or what was "open collector" in the TTL days.

-- glen

Article: 140113
Subject: Re: a basics question: using input pins, pullup, short to ground vs
From: jleslie48 <jon@jonathanleslie.com>
Date: Tue, 28 Apr 2009 17:59:19 -0700 (PDT)
Links: << >> << T >> << A >>

On Apr 28, 8:46 pm, Muzaffer Kal <k...@dspia.com> wrote:
> On Tue, 28 Apr 2009 17:30:35 -0700 (PDT), jleslie48
>
>
>
> <j...@jonathanleslie.com> wrote:
> >> > My question is if I want to take my driven output and run it around as
> >> > an input signal, how do I do that?
>
> >> Are you saying you want to connect an output pin to an input pin and
> >> leave the pushbutton connected so that either can drive the input?
>
> >> Make the output pin so called "open collector" that only drives low and
> >> floats high.
>
> >> outputpin <= '0' when mysignal = '0' else 'Z;
>
> >> -Jeff
>
> >the part that confuses me, is the 3.3 volts that I see sitting on the
> >input pin when its not tied to ground.  how can I send "in" from the
> >external wire 3.3 volts when it already has 3.3 volts on it?
>
> If you consider that there is always a connection to the input pin, I
> think it would clear up your issue. If you have a pull-up with 3.3V
> and the input agrees with it, you are sending in a high signal. If
> your external driver disagrees with the pull-up and drives a 0, you're
> sending in a low signal. If you had a 3rd state where you didn't know
> if a driver is connected then you might need another signal to detect
> if there is a driver or only if the pull-up is connected but I don't
> think that's your configuration (actually even in that case, with a
> true tri-state IO you can detect if a driver is "driving" or not).
> Does that help?
> --
> Muzaffer Kal
>
> DSPIA INC.
> ASIC/FPGA Design Services
>
> http://www.dspia.com

ahh! so if I connect these two wires, the input (at a steady 3.3
volts) and the other wire (that changes between 0 and 3.3 volts) that
is a normal thing to do. When both wires are at 3.3 volts I'll get one
signal on the input pin, and when one is at 3.3 (the input pin) and
what its connected to is at 0 volts (the external wire) the external
wire acts just like the closing the switch scenario aka, connecting
the pin to ground, and thus changes the state on the input pin from 0
to 1 (or 1 to 0, whatever.) It that how it works?

Article: 140114
Subject: Re: a basics question: using input pins, pullup, short to ground vs
From: jleslie48 <jon@jonathanleslie.com>
Date: Tue, 28 Apr 2009 18:07:59 -0700 (PDT)
Links: << >> << T >> << A >>

On Apr 28, 8:56 pm, Muzaffer Kal <k...@dspia.com> wrote:
> On Tue, 28 Apr 2009 17:38:05 -0700 (PDT), jleslie48
>
> <j...@jonathanleslie.com> wrote:
> >Its an electrical question, I mean I somehow have to attach my input
> >pin to the external wire rather than to ground, but that means there
> >will be two 3.3 volt signals on that wire, that doesn't sound good.
>
> You directly attach the external wire to the input pin. The pull-up on
> the input pin is a weak pull-up so when the external wire is at 3.3V,
> it agrees with the pull-up and you see a high signal internally. When
> the external signal is driving 0V, it overrides the pull-up and pulls
> the input node to ground and you see a low internally. There is no
> issue with the pull-up pulling to 3.3V and the external wire also
> driving a 3.3V to the same node.
> --
> Muzaffer Kal
>
> DSPIA INC.
> ASIC/FPGA Design Services
>
> http://www.dspia.com

ahh! so if I connect these two wires, the input (at a steady 3.3
volts) and the other wire (that changes between 0 and 3.3 volts) that
is a normal thing to do. When both wires are at 3.3 volts I'll get one
signal on the input pin, and when one is at 3.3 (the input pin) and
what its connected to is at 0 volts (the external wire) the external
wire acts just like the closing the switch scenario aka, connecting
the pin to ground, and thus changes the state on the input pin from 0
to 1 (or 1 to 0, whatever.) If that is correct I think I've got it.

So I'm perfectly fine having the two 3.3 volts values on both wires.
I just wanted to make sure.  My first two years with the company I
earned a reputation for smoking equipment (I toasted easily $70,000
worth of stuff,) and I'm determined this year to not fry anything.

Thanks

Jon

Article: 140115
Subject: Re: a basics question: using input pins, pullup, short to ground vs driven signal.
From: Muzaffer Kal <kal@dspia.com>
Date: Tue, 28 Apr 2009 18:19:22 -0700
Links: << >> << T >> << A >>

On Tue, 28 Apr 2009 18:07:59 -0700 (PDT), jleslie48
<jon@jonathanleslie.com> wrote:

>ahh! so if I connect these two wires, the input (at a steady 3.3
>volts) and the other wire (that changes between 0 and 3.3 volts) that
>is a normal thing to do. 

Yes but only because the input 3.3V is being generated by a weak
pull-up.

> When both wires are at 3.3 volts I'll get one
>signal on the input pin, and when one is at 3.3 (the input pin) and
>what its connected to is at 0 volts (the external wire) the external
>wire acts just like the closing the switch scenario aka, connecting
>the pin to ground, and thus changes the state on the input pin from 0
>to 1 (or 1 to 0, whatever.) If that is correct I think I've got it.

That's correct.

-- 
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

Article: 140116
Subject: Re: I have some doubts in verilog
From: Prashanth Kumar <prashaenator@gmail.com>
Date: Tue, 28 Apr 2009 23:03:04 -0700 (PDT)
Links: << >> << T >> << A >>

Thanks glen,


 I am doing 64 point FFT using verilog HDL.

The input to FFT may be integers are floating point values.

Tell me, how can we represent floating point values in binay. I mean,
whether I shoud follow IEEE 754 format or some thing else.

Also tell me, if there are any alternatives.

Thanks again

Article: 140117
Subject: Re: I have some doubts in verilog
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Wed, 29 Apr 2009 06:08:41 +0000 (UTC)
Links: << >> << T >> << A >>

Prashanth Kumar <prashaenator@gmail.com> wrote:

> I am doing 64 point FFT using verilog HDL.

> The input to FFT may be integers are floating point values.

> Tell me, how can we represent floating point values in binay. I mean,
> whether I shoud follow IEEE 754 format or some thing else.

There are many possibilities, but IEEE 754 isn't a bad choice.
You may not want to handle all the IEEE features, such as NaN,
Infinities, denormals, etc.  

> Also tell me, if there are any alternatives.

I presume you are posting in an FPGA group because you are
interested in an FPGA implementation.  You probably want some type
of parallel architecture.  I recommmend the systolic array 
for many types of FPGA problems.  I haven't implement FFT in
a systolic array, but I believe that it has been done.

-- glen

Article: 140118
Subject: Re: FPGA/DSP/Video Board
From: Petter Gustad <newsmailcomp6@gustad.com>
Date: Wed, 29 Apr 2009 09:48:51 +0200
Links: << >> << T >> << A >>

"cwoodring" <cwoodring@cox.net> writes:

> Try checking out Gidel Inc.  They make some StratixII  cards with 
> Cameralink, 2-4 GB memory etc. The one I'm using is based on PCIe. Their 
> development tools are pretty good but pricey.

Thanks, that looks promising.

Petter

-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 140119
Subject: Re: best soft core(s) that have C compiler support
From: Tommy Thorn <tommy.thorn@gmail.com>
Date: Wed, 29 Apr 2009 00:58:24 -0700 (PDT)
Links: << >> << T >> << A >>

On Apr 17, 7:45=A0am, "Antti.Luk...@googlemail.com"
<Antti.Luk...@googlemail.com> wrote:
> your verilog is ICARUS verilog, and ALTERA verilog
>
> but not fully portable verilog
> fixed 4 different issues that prevent your code to pass synthesis with
> XST but still some problems to solve :(

Antti was absolutely right, but I've fixed this now and I have it
support Xilinx now. My distribution has partial support (SSRAM support
missing) for the Virtex-4 based ML401. Others should be easy as well.

Regards,
Tommy

Article: 140120
Subject: Re: hard macro basic clock reset question
From: Dirk Koch <dirk.koch@cs.fau.de>
Date: Wed, 29 Apr 2009 12:08:10 +0200
Links: << >> << T >> << A >>

oktem@su.sabanciuniv.edu wrote:
> I'm making a hardmacro usinx Xilinx 9.1.03i Fpga Editor. My
> implementation will be on Spartan 3 200.
> 
> I am trying to connect resets of the Slices and make only one reset
> input for my macro in the top module of my hdl. Likely,
> I am trying to connect clocks of the Slices and make only one clock
> input for my macro in the top module of my hdl.
> 
In some documentation I found that this is not possible.
In our ReCoBus macros we export all clocks as a vector
and simply connect all pins with clk (in VHDL):
   macro_clk_connect_signal <= (others => clk);

regards
Dirk

> Is it not possible? I connected the resets of the Slices. I tried to
> auto route but it does not auto route. Should I just connect them
> ignore the errors and hope that the tool will take care when I combine
> the macro in the top module or am I doint something wrong.
> 
> If I dont connect all of them but make external macro pins for each of
> them seperately, I can not give the same name to the resets or
> clocks.
> I do not want to make 16 resets or clocks  (and connect each of them
> to real reset and clock using VHDL/Verilog on my  top module.)

Article: 140121
Subject: Re: ISE 11.1 Webpack: How to install for Suse 64 Bits?
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Wed, 29 Apr 2009 10:26:42 +0000 (UTC)
Links: << >> << T >> << A >>

Brian Drummond <brian_drummond@btconnect.com> wrote:
> On Tue, 28 Apr 2009 10:14:44 +0000 (UTC), Uwe Bonnes
> <bon@elektron.ikp.physik.tu-darmstadt.de> wrote:

> >Software_matrix.pdf for Xilinx ISE 11.1 lists "SUSE Linux Enterprise 10*
> >64-bit" supported for webpack.  Downloading the whole file
> >Xilinx_11.1_WebPack_SFD.tar, untarring and running ./xsetup gives
> >"Product is not supported on "Linux x86_64" platform" as with 10.1, and there
> >is no bin/lin64 as required by xsetup.
> >
> >What counts?

> Is Webpack supported for 64 bit in ISE11? 
> It never was in ISE10.1 ... but would happily install and run in Suse 64 anyway
> (with the Suse 32-bit compatibility libraries)

> All I had to do was find the 32-bit/64 bit platform test in the setup script,
> and comment out the "exit" line so it went on to install anyway. 
> Perhaps the same still applies in 11.1?

I have installed 10.1 on Suse-64-it before, and am able to do so with 11.1
However I was disturbed by the missleading  information on the webpage and
wanted to share my distract with others. 

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 140122
Subject: Re: a basics question: using input pins, pullup, short to ground vs driven signal.
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Wed, 29 Apr 2009 12:44:58 +0100
Links: << >> << T >> << A >>

On Tue, 28 Apr 2009 17:30:35 -0700 (PDT), jleslie48 <jon@jonathanleslie.com>
wrote:

>On Apr 28, 8:07 pm, Jeff Cunningham <j...@sover.net> wrote:
>> jleslie48 wrote:

>> Make the output pin so called "open collector" that only drives low and
>> floats high.
>>
>> outputpin <= '0' when mysignal = '0' else 'Z;
>>
>> -Jeff
>
>the part that confuses me, is the 3.3 volts that I see sitting on the
>input pin when its not tied to ground.  how can I send "in" from the
>external wire 3.3 volts when it already has 3.3 volts on it?

Since this is a pushbutton input, you can be sure that isn't a "hard" 3.3V, i.e.
a direct connection to the 3.3V supply. Otherwise the pushbutton would be a dead
short across the supply. (The pushbuttons normally used are simple "make" or
occasionally "break" contacts rather than changeover switches. Unlike the slide
switch in one of Antti's recent puzzles, which had a "neither" position between
its two intended states.)

First step. Confirm this by looking at the board schematic; expect to see a
pullup resistor to 5(er... 3.3)V and a simple switch to 0V. And note the
resistor value (say 1k, 4.7k or 10k) That 3.3V you see has to come from
somewhere. Usually a resistor, but check to be certain.
(Re-reads post: the "PULLUP" constraint enables a resistor built into the I/O
circuit attached to the pin. This is usually a weak - high value- resistor, but
on some Spartan-3s I recall someone finding it a lot lower than advertised;
possibly down to 3.5K)

Then you can connect an output to that input pin  (or even declare the pin to be
I/O, both input and output; it saves external wiring). 

This is where Jeff's advice comes in.

Connecting a 3.3V output to this 3.3V signal is no problem - they are at
(almost) the same potential so (virtually) no current will flow between them,
and the input pin will just see 3.3V.

The problem comes when the input pin and output pin are set to DIFFERENT levels;
setting up a conflict between them. There are two possible cases; you must
safely cover both cases, or understand how Jeff's advice safely covers both of
them.

If the output is set to 0 and the input is pulled to 3.3V by a 1K resistor, the
output must sink 3.3ma through the resistor to properly control the level on the
input pin. Setting its drive strength (in the UCF file) to 2ma is definitely not
recommended! (a 10k resistor would require 0.33ma, quite safe). In this case,
also pressing the button will do no harm.

If the output is set to 1, the input will read 1 ... until the button is
pressed. Now the output is shorted to ground - the input will read 0 - but the
output is driving a large current (its "drive strength" is a lower limit and
only applies into a recommended load, which a short circuit is not!) and can
potentially be destroyed.

Jeff's advice - allow the output to pull to 0, or turn off - covers both cases.
Instead of driving 1, the output turns off, and let the resistor do the work.
This is called a wire-AND configuration (often a wire-OR by people who remember
negative logic) because the input sees ((switch=1) and (output=1))

(Not recommended at MHz speeds; there are tricks to improve its speed)

- Brian

Article: 140123
Subject: Re: ERROR: NgdBuild:604 - logical block
From: lolita.tangier@gmail.com
Date: Wed, 29 Apr 2009 06:10:08 -0700 (PDT)
Links: << >> << T >> << A >>

I don=92t know, i have just begun in ISE .

When I remove everything between "--synopsys synthesis_off" and "--
synopsys synthesis_on" I was able to synthesize but only the entity
and I don=92t have an architecture for it.

I tried to implement just the ramx=92s  module and I has  the following
error:

 ERROR: Pack:198 - NCD was not produced. All logic was removed from
design.  This  is usually due to having no input or output PAD
connections in the design and  no nets or symbols marked as 'SAVE'.
You can either add PADs or 'SAVE'  attributes to the design, or run
'map -u' to disable logic trimming in the  mapper.

So, I has a another code for a real  ram  ( because the other is just
a simulation model), I was able to synthesize and I can implement it,
I changed it for use.
The new code is:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
--library mc8051;
--use mc8051.mc8051_p.all;
------------------------ ENTITY DECLARATION -------------------------
entity mc8051_ram is

  port (clk        : in  std_logic;  			-- clock signal
        reset      : in  std_logic;  			-- reset signal
        ram_data_i : in  std_logic_vector(7 downto 0);  -- data input
        ram_data_o : out std_logic_vector(7 downto 0);  -- data output
        ram_adr_i  : in  std_logic_vector(15 downto 0);  -- adresses
        ram_wr_i   : in  std_logic;  			-- read=3D0, write=3D1
        Bypass_TM   : in  std_logic);  			-- inactive=3D0;active=3D1

end mc8051_ram;

architecture sim of mc8051_ram is

  type   ram_type is array (65535 downto 0) of std_logic_vector(7
downto 0);

   signal gpram:        ram_type;             -- general purpose RAM

begin

---------------------------------------------------------------------------=
---
-- ram_read
---------------------------------------------------------------------------=
---

  p_read : process (clk, reset)
  begin
    if reset=3D'1' then
      ram_data_o <=3D "00000000";
    else
      if Rising_Edge(clk) then
        ram_data_o <=3D gpram(conv_integer(unsigned(ram_adr_i)));
      end if;
    end if;
  end process p_read;

---------------------------------------------------------------------------=
---
-- ram_write
---------------------------------------------------------------------------=
---

  p_write : process (clk, reset)
  begin
    if reset=3D'1' then
      gpram <=3D (others =3D> (others =3D>'0'));    -- reset every bit
    else
      if Rising_Edge(clk) then
        if  (ram_wr_i=3D'1') then
          gpram(conv_integer(unsigned(ram_adr_i))) <=3D ram_data_i;
        end if;
      end if;
    end if;
  end process p_write;

end sim;

when I was able to synthesize I have the following error:

ERROR:Pack:18 - The design is too large for the given device and
package.

Therefore, I taught to use the bram_block but i dont' know how.

Regards.
lolita

Article: 140124
Subject: Re: ERROR: NgdBuild:604 - logical block
From: lolita.tangier@gmail.com
Date: Wed, 29 Apr 2009 06:12:13 -0700 (PDT)
Links: << >> << T >> << A >>

I don=92t know, i have just begun in ISE .

When I remove everything between "--synopsys synthesis_off" and "--
synopsys synthesis_on" I was able to synthesize but only the entity
and I don=92t have an architecture for it.

I tried to implement just the ramx=92s  module and I has  the following
error:

 ERROR: Pack:198 - NCD was not produced. All logic was removed from
design.  This  is usually due to having no input or output PAD
connections in the design and  no nets or symbols marked as 'SAVE'.
You can either add PADs or 'SAVE'  attributes to the design, or run
'map -u' to disable logic trimming in the  mapper.

So, I has a another code for a real  ram  ( because the other is just
a simulation model), I was able to synthesize and I can implement it,
I changed it for use.
The new code is:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
--library mc8051;
--use mc8051.mc8051_p.all;
------------------------ ENTITY DECLARATION -------------------------
entity mc8051_ram is

  port (clk        : in  std_logic;  			-- clock signal
        reset      : in  std_logic;  			-- reset signal
        ram_data_i : in  std_logic_vector(7 downto 0);  -- data input
        ram_data_o : out std_logic_vector(7 downto 0);  -- data output
        ram_adr_i  : in  std_logic_vector(15 downto 0);  -- adresses
        ram_wr_i   : in  std_logic;  			-- read=3D0, write=3D1
        Bypass_TM   : in  std_logic);  			-- inactive=3D0;active=3D1

end mc8051_ram;

architecture sim of mc8051_ram is

  type   ram_type is array (65535 downto 0) of std_logic_vector(7
downto 0);

   signal gpram:        ram_type;             -- general purpose RAM

begin

---------------------------------------------------------------------------=
---
-- ram_read
---------------------------------------------------------------------------=
---

  p_read : process (clk, reset)
  begin
    if reset=3D'1' then
      ram_data_o <=3D "00000000";
    else
      if Rising_Edge(clk) then
        ram_data_o <=3D gpram(conv_integer(unsigned(ram_adr_i)));
      end if;
    end if;
  end process p_read;

---------------------------------------------------------------------------=
---
-- ram_write
---------------------------------------------------------------------------=
---

  p_write : process (clk, reset)
  begin
    if reset=3D'1' then
      gpram <=3D (others =3D> (others =3D>'0'));    -- reset every bit
    else
      if Rising_Edge(clk) then
        if  (ram_wr_i=3D'1') then
          gpram(conv_integer(unsigned(ram_adr_i))) <=3D ram_data_i;
        end if;
      end if;
    end if;
  end process p_write;

end sim;

when I was able to synthesize I have the following error:

ERROR:Pack:18 - The design is too large for the given device and
package.

Therefore, I taught to use the bram_block but i don't how.

Regards.
lolita

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