Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
The top level module in Xilinx ISE 11.1 projects apparently cannot contain more than one VHDL architecture. If that module is already the top level in the project, both (all) architectures are marked as top-level in the Design pane Heirarchy view. Both architectures are apparently synthesized. (Device utilization approximately doubled.) Neither top level architecture is available to select as the Top Level Module, as they are already top-level from the tool's point of view. Setting some other module as top level temporarily allows reselection of the intended top-level in the tool. However, doing so causes _pn.exe to spin continually and Project Navigator to become unresponsive. The Project Navigator status bar flashes "Generating Summary Page", while _pn.exe spins at 100% of its core. Killing the ise.exe process (minutes later) leaves the _pn.exe process orphaned, still spinning at 100%. _pn.exe has to be killed manually. (Win XP, 32-bit.) Setting the top-level module and architecture using TCL has the identical effect. (project set top RTL fooModule). _pn.exe spins, while PN flashes "Generating Summary Page" in its status bar. ISIM post-route simulation apparently also has problems with multiple architectures. One architecture is consistently selected over the other, perhaps by first in alphabetic order. Direct instantiation with entity work.<module>(<arch>) does not find the module in work. Behavioral simulation worked fine with this notation. I didn't pursue this further. Selecting the desired top level architecture for implementation, in the Design pane heirarchy, does not influence the behavior. Both architectures are synthesized. Most curious of all, commenting out the extraneous architecture in the VHD module has NO EFFECT on synthesis and implementation UNTIL the project files are removed with the Project menu|Cleanup project files... Example indications: Device utilization still shows the bloated size; the synthesis report lists FSM encodings for modules referenced only from the "deleted" architecture; the map report lists utilization from modules no longer referenced; etc. Last, the .XISE project file became no longer usable, whether from the thrashing it received or from some other garbage. Opening the project in ISE caused it to crash with a messagebox. I had to recover the project file from version control. The errors are easy enough to reproduce. Add a second architecture to the top level VHDL module in the project.Article: 140776
[Addendum]: ISE continues to crash with an exception messagebox during startup with that .xise project, even after recovering an old version of the <project>.xise file from version control. Deleting and recreating an empty project directory solved the problem. "MikeWhy" <boat042-nospam@yahoo.com> wrote in message news:AoFSl.27311$c45.3926@nlpi065.nbdc.sbc.com... > The top level module in Xilinx ISE 11.1 projects apparently cannot contain > more than one VHDL architecture. If that module is already the top level > in the project, both (all) architectures are marked as top-level in the > Design pane Heirarchy view. Both architectures are apparently synthesized. > (Device utilization approximately doubled.) > > Neither top level architecture is available to select as the Top Level > Module, as they are already top-level from the tool's point of view. > Setting some other module as top level temporarily allows reselection of > the intended top-level in the tool. However, doing so causes _pn.exe to > spin continually and Project Navigator to become unresponsive. The Project > Navigator status bar flashes "Generating Summary Page", while _pn.exe > spins at 100% of its core. Killing the ise.exe process (minutes later) > leaves the _pn.exe process orphaned, still spinning at 100%. _pn.exe has > to be killed manually. (Win XP, 32-bit.) > > Setting the top-level module and architecture using TCL has the identical > effect. (project set top RTL fooModule). _pn.exe spins, while PN flashes > "Generating Summary Page" in its status bar. > > ISIM post-route simulation apparently also has problems with multiple > architectures. One architecture is consistently selected over the other, > perhaps by first in alphabetic order. Direct instantiation with entity > work.<module>(<arch>) does not find the module in work. Behavioral > simulation worked fine with this notation. I didn't pursue this further. > > Selecting the desired top level architecture for implementation, in the > Design pane heirarchy, does not influence the behavior. Both architectures > are synthesized. > > Most curious of all, commenting out the extraneous architecture in the VHD > module has NO EFFECT on synthesis and implementation UNTIL the project > files are removed with the Project menu|Cleanup project files... Example > indications: Device utilization still shows the bloated size; the > synthesis report lists FSM encodings for modules referenced only from the > "deleted" architecture; the map report lists utilization from modules no > longer referenced; etc. > > Last, the .XISE project file became no longer usable, whether from the > thrashing it received or from some other garbage. Opening the project in > ISE caused it to crash with a messagebox. I had to recover the project > file from version control. > > The errors are easy enough to reproduce. Add a second architecture to the > top level VHDL module in the project. >Article: 140777
On May 25, 2:28=A0pm, Andy <jonesa...@comcast.net> wrote: > Weng, > > You've told the synthesizer that state2_ns (the combinatorial signal, > not the register) has to remember its previous value under certain > circumstances, so it generates a latch to remember the value. > > Your choices to avoid the latch include a) avoiding combinatorial > processes, b) including a default assignment (perhaps from the output > of the associated register) in combinatorial processes, or c) making > sure every possible execution path through the process results in all > driven signals being assigned a value (and not just to themselves). > > I always choose (a). If you just have to use a combinatorial process, > then (b) is much easier to read/write/verify/review than is(c). > > Andy Hi Andy, "You've told the synthesizer that state2_ns (the combinatorial signal, not the register) has to remember its previous value under certain circumstances, so it generates a latch to remember the value." You are right and I understand it. I am interested in your method a. Could you give me an example on how to use your method a. in the above situation. Thank you. WengArticle: 140778
On May 25, 10:29=A0pm, Andy <jonesa...@comcast.net> wrote: > On May 25, 4:56=A0am, sbatt...@yahoo.co.jp wrote: > > > > > On May 25, 6:43=A0pm, "Andrew Holme" <a...@nospam.co.uk> wrote: > > > > <sbatt...@yahoo.co.jp> wrote in message > > > >news:2508079e-f147-4e15-b6bd-ac96f220afbd@s1g2000prd.googlegroups.com.= .. > > > > > Hi guys, > > > > At the moment I'm waiting to find out whether I will be using Xilin= x > > > > or Actel for my project, and so I'm putting it together for both ju= st > > > > in case. > > > > > In the Actel IP cores, there is an array adder which allows a good > > > > number of inputs, and there's some optional pipelining. I figure it= 's > > > > sufficient to just drop this in and wire up as many inputs as I nee= d. > > > > > Xilinx IP cores seem to have only 2-input adders, and I guess these > > > > are probably inferred by XST with the + operator anyway, so I don't > > > > want to bother with the IP core gen unless there's some reason why = I > > > > should. > > > > Supposing I want: > > > > > Result <=3D A + B + C + D + E; > > > > Note, I used only five inputs in my example for brevity, I will hav= e > > > > more like 25 in my actual system. > > > > > (looking in the XST manual, I can either pad the inputs with leadin= g > > > > zeros or convert to integer and back to std_logic_vector to get car= ry > > > > bits to fill my wider result) > > > > > At the end of the day, when I synthesize this, would there be any > > > > difference between coding it in stages (adding pairs of two togethe= r, > > > > then adding their sums together, and so on until all are added up) = and > > > > just putting A+B+C+D+E in one statement? > > > > All I can think of is that (depending how well conversions to/from > > > > integer are optimized in XST) I might save a few bits of space in t= he > > > > first stages. > > > > Using the bit padding method, I suppose that all of the adders in t= he > > > > first stages would wind up unnecessarily being the same width as th= e > > > > result. > > > > > Anyway, I'm just curious how this will end up working... any insigh= t > > > > appreciated! > > > > > Steve > > > > How fast do you need to clock it? =A0How many bits wide is your resul= t? > > > Assuming 25 8-bit inputs, the maximum result is 25*255 =3D 6375, meanin= g > > 13-bit output. > > Serial data comes in at 57.6 kilobits/second =3D 7200 bytes/second, and > > the sum of my array is checked once per byte so there will be a little > > over 1ms between clock pulses (I can't imagine that being anywhere > > near playing with timing issues). For the project I won't need > > anything any faster than that. > > > I'm just wondering how XST would handle such an addition statement > > with multiple operands (my synthesis report doesn't say anything about > > adders). Is it smart enough to automatically do some kind of tree > > algorithm, or would it do a "dumb" array of one adder feeding into the > > next for each extra operand? > > > Thanks for the quick response! > > > Steve- Hide quoted text - > > > - Show quoted text - > > Do you really need to recompute the entire array sum every time, or > can you compute a running sum (accumulator) as the data comes in? You > can also subtract the last discarded term from your running sum if you > are looking for a continuous N-term running sum (as is used in a > boxcar filter, etc.) > > As long as integers will handle your data size, you are much better > off using them than padding vectors. Simulations will run much faster, > and there is no hardware associated with conversion from/to SLV/signed/ > unsigned to/from integer. > > Andy Well, I have thought about the accumulator approach, but this is a 5x5 array being fed data through some delay lines, so I would then need one accumulator for each 5-byte row. Then I would still have to sum up the output of the five accumulators, leaving me one stage deeper than a tree of adders taking all 25 inputs. Peter, I'm not converting 25 lines to 6 bits, but rather taking a sum of 25 8-bit values resulting in a 13-bit value. Thanks again for the replies so far!Article: 140779
On May 26, 3:58=A0am, Weng Tianxiang <wtx...@gmail.com> wrote: > On May 25, 9:16=A0am, Peter Alfke <al...@sbcglobal.net> wrote: > > > > > On May 25, 2:11=A0am, sbatt...@yahoo.co.jp wrote: > > > > Hi guys, > > > At the moment I'm waiting to find out whether I will be using Xilinx > > > or Actel for my project, and so I'm putting it together for both just > > > in case. > > > > In the Actel IP cores, there is an array adder which allows a good > > > number of inputs, and there's some optional pipelining. I figure it's > > > sufficient to just drop this in and wire up as many inputs as I need. > > > > Xilinx IP cores seem to have only 2-input adders, and I guess these > > > are probably inferred by XST with the + operator anyway, so I don't > > > want to bother with the IP core gen unless there's some reason why I > > > should. > > > Supposing I want: > > > > Result <=3D A + B + C + D + E; > > > Note, I used only five inputs in my example for brevity, I will have > > > more like 25 in my actual system. > > > > (looking in the XST manual, I can either pad the inputs with leading > > > zeros or convert to integer and back to std_logic_vector to get carry > > > bits to fill my wider result) > > > > At the end of the day, when I synthesize this, would there be any > > > difference between coding it in stages (adding pairs of two together, > > > then adding their sums together, and so on until all are added up) an= d > > > just putting A+B+C+D+E in one statement? > > > All I can think of is that (depending how well conversions to/from > > > integer are optimized in XST) I might save a few bits of space in the > > > first stages. > > > Using the bit padding method, I suppose that all of the adders in the > > > first stages would wind up unnecessarily being the same width as the > > > result. > > > > Anyway, I'm just curious how this will end up working... any insight > > > appreciated! > > > > Steve > > > If I understand you right, you have 25 parallel inputs, each sending > > you bit-serial data. > > You need to convert the 25 inputs into one 6-bit binary word, and then > > accumulate these words with increasing (or decreasing) binary weight. > > > Conversion of 25 lines to 6 bits can be done in many ways, including > > sequential scanning or shifting, which requires a faster clock of > > > 1.5 MHz. > > But here is an unconventional and simpler way: > > Use 13 inputs as address to one port of a BlockRAM with 4 parallel > > outputs =A0(8K x 4) > > Use the remaining 12 inputs as address to the other port of the same > > BlockRAM. > > Store the conversion of (# of active inputs to a binary value) in the > > BlockRAM. > > > Add the two 4 bit binary words together to form a 5-bit word that > > always represents the number of active inputs. > > Then feed this 5-bit value into a 13-bit accumulator, where you shift > > the content after each clock tick. > > > This costs you one BlockRAM plus three or four CLBs in Xilinx > > nomenclature, a tiny portion of the smallest Spartan or Virtex device, > > and it could be run a few thousand times faster than you need. > > If you have more than 26 inputs, just add another BlockRAM for a total > > of up to 52 inputs, and extend the adder and accumulator by one bit. > > (Yes, I know in Spartan you are limited to 12 address inputs, (4K x > > 4), but you can add the remaining bit outside...) > > > Peter Alfke, from home.- Hide quoted text - > > > - Show quoted text - > > Hi Steve, > 1. Set up a 16*8 FIFO; > 2. Each of 25 data sources is first registered in its 8-bit register > with valid bit when data bits are full from its serial data source; > 3. When valid =3D '1', push the data into FIFO and clear the valid bit; > 4. Set up a 13-bit register with initialized 0 data when a new > calculation starts; > 5. When FIFO is not empty, add 13-bit register with high 5-bit being > '0' and low 8-bit from FIFO output. > > There is no need for 25 data sources. > > Weng Hi Weng, I'm sorry I didn't explain in full what I am doing. There is only one serial source feeding a string of delay lines, and at the end of the delay lines is a 5x5 array of 8-bit registers whose sum I need to calculate. Each time the serial source gets a byte in, everything in the delay lines and 5x5 array gets shifted, and I have a new sum to calculate (this happens once every ms or so, though, so I'm not really worried about carry propagation). So in this case, I don't think a FIFO would help any? As far as I can see, as noted in my reply to Andy's post, my options are (a slightly modified version of) his suggested accumulator solution, or feeding my 25 inputs into a tree of adders. There could be some other clever solution though? I was originally just wondering if XST would generate such a tree with 25 operands in a sum statement, or if I would have to build the tree myself in a few statements. The Actel array adder IP apparently uses the DADDA algorithm to handle multiple inputs, but I haven't seen anything in the XST docs about multiple-operand addition.Article: 140780
On May 25, 7:00=A0pm, sbatt...@yahoo.co.jp wrote: > On May 25, 10:29=A0pm, Andy <jonesa...@comcast.net> wrote: > > > > > On May 25, 4:56=A0am, sbatt...@yahoo.co.jp wrote: > > > > On May 25, 6:43=A0pm, "Andrew Holme" <a...@nospam.co.uk> wrote: > > > > > <sbatt...@yahoo.co.jp> wrote in message > > > > >news:2508079e-f147-4e15-b6bd-ac96f220afbd@s1g2000prd.googlegroups.co= m... > > > > > > Hi guys, > > > > > At the moment I'm waiting to find out whether I will be using Xil= inx > > > > > or Actel for my project, and so I'm putting it together for both = just > > > > > in case. > > > > > > In the Actel IP cores, there is an array adder which allows a goo= d > > > > > number of inputs, and there's some optional pipelining. I figure = it's > > > > > sufficient to just drop this in and wire up as many inputs as I n= eed. > > > > > > Xilinx IP cores seem to have only 2-input adders, and I guess the= se > > > > > are probably inferred by XST with the + operator anyway, so I don= 't > > > > > want to bother with the IP core gen unless there's some reason wh= y I > > > > > should. > > > > > Supposing I want: > > > > > > Result <=3D A + B + C + D + E; > > > > > Note, I used only five inputs in my example for brevity, I will h= ave > > > > > more like 25 in my actual system. > > > > > > (looking in the XST manual, I can either pad the inputs with lead= ing > > > > > zeros or convert to integer and back to std_logic_vector to get c= arry > > > > > bits to fill my wider result) > > > > > > At the end of the day, when I synthesize this, would there be any > > > > > difference between coding it in stages (adding pairs of two toget= her, > > > > > then adding their sums together, and so on until all are added up= ) and > > > > > just putting A+B+C+D+E in one statement? > > > > > All I can think of is that (depending how well conversions to/fro= m > > > > > integer are optimized in XST) I might save a few bits of space in= the > > > > > first stages. > > > > > Using the bit padding method, I suppose that all of the adders in= the > > > > > first stages would wind up unnecessarily being the same width as = the > > > > > result. > > > > > > Anyway, I'm just curious how this will end up working... any insi= ght > > > > > appreciated! > > > > > > Steve > > > > > How fast do you need to clock it? =A0How many bits wide is your res= ult? > > > > Assuming 25 8-bit inputs, the maximum result is 25*255 =3D 6375, mean= ing > > > 13-bit output. > > > Serial data comes in at 57.6 kilobits/second =3D 7200 bytes/second, a= nd > > > the sum of my array is checked once per byte so there will be a littl= e > > > over 1ms between clock pulses (I can't imagine that being anywhere > > > near playing with timing issues). For the project I won't need > > > anything any faster than that. > > > > I'm just wondering how XST would handle such an addition statement > > > with multiple operands (my synthesis report doesn't say anything abou= t > > > adders). Is it smart enough to automatically do some kind of tree > > > algorithm, or would it do a "dumb" array of one adder feeding into th= e > > > next for each extra operand? > > > > Thanks for the quick response! > > > > Steve- Hide quoted text - > > > > - Show quoted text - > > > Do you really need to recompute the entire array sum every time, or > > can you compute a running sum (accumulator) as the data comes in? You > > can also subtract the last discarded term from your running sum if you > > are looking for a continuous N-term running sum (as is used in a > > boxcar filter, etc.) > > > As long as integers will handle your data size, you are much better > > off using them than padding vectors. Simulations will run much faster, > > and there is no hardware associated with conversion from/to SLV/signed/ > > unsigned to/from integer. > > > Andy > > Well, I have thought about the accumulator approach, but this is a 5x5 > array being fed data through some delay lines, so I would then need > one accumulator for each 5-byte row. > Then I would still have to sum up the output of the five accumulators, > leaving me one stage deeper than a tree of adders taking all 25 > inputs. > > Peter, I'm not converting 25 lines to 6 bits, but rather taking a sum > of 25 8-bit values resulting in a 13-bit value. > > Thanks again for the replies so far! Well, where do you store the 200 bits (5 x5 x 8) and how do you move them into the FPGA? Remember, the internal logic is thousands of times faster than you need... PeterArticle: 140781
On May 26, 11:48=A0am, Peter Alfke <al...@sbcglobal.net> wrote: > On May 25, 7:00=A0pm, sbatt...@yahoo.co.jp wrote: > > > > > On May 25, 10:29=A0pm, Andy <jonesa...@comcast.net> wrote: > > > > On May 25, 4:56=A0am, sbatt...@yahoo.co.jp wrote: > > > > > On May 25, 6:43=A0pm, "Andrew Holme" <a...@nospam.co.uk> wrote: > > > > > > <sbatt...@yahoo.co.jp> wrote in message > > > > > >news:2508079e-f147-4e15-b6bd-ac96f220afbd@s1g2000prd.googlegroups.= com... > > > > > > > Hi guys, > > > > > > At the moment I'm waiting to find out whether I will be using X= ilinx > > > > > > or Actel for my project, and so I'm putting it together for bot= h just > > > > > > in case. > > > > > > > In the Actel IP cores, there is an array adder which allows a g= ood > > > > > > number of inputs, and there's some optional pipelining. I figur= e it's > > > > > > sufficient to just drop this in and wire up as many inputs as I= need. > > > > > > > Xilinx IP cores seem to have only 2-input adders, and I guess t= hese > > > > > > are probably inferred by XST with the + operator anyway, so I d= on't > > > > > > want to bother with the IP core gen unless there's some reason = why I > > > > > > should. > > > > > > Supposing I want: > > > > > > > Result <=3D A + B + C + D + E; > > > > > > Note, I used only five inputs in my example for brevity, I will= have > > > > > > more like 25 in my actual system. > > > > > > > (looking in the XST manual, I can either pad the inputs with le= ading > > > > > > zeros or convert to integer and back to std_logic_vector to get= carry > > > > > > bits to fill my wider result) > > > > > > > At the end of the day, when I synthesize this, would there be a= ny > > > > > > difference between coding it in stages (adding pairs of two tog= ether, > > > > > > then adding their sums together, and so on until all are added = up) and > > > > > > just putting A+B+C+D+E in one statement? > > > > > > All I can think of is that (depending how well conversions to/f= rom > > > > > > integer are optimized in XST) I might save a few bits of space = in the > > > > > > first stages. > > > > > > Using the bit padding method, I suppose that all of the adders = in the > > > > > > first stages would wind up unnecessarily being the same width a= s the > > > > > > result. > > > > > > > Anyway, I'm just curious how this will end up working... any in= sight > > > > > > appreciated! > > > > > > > Steve > > > > > > How fast do you need to clock it? =A0How many bits wide is your r= esult? > > > > > Assuming 25 8-bit inputs, the maximum result is 25*255 =3D 6375, me= aning > > > > 13-bit output. > > > > Serial data comes in at 57.6 kilobits/second =3D 7200 bytes/second,= and > > > > the sum of my array is checked once per byte so there will be a lit= tle > > > > over 1ms between clock pulses (I can't imagine that being anywhere > > > > near playing with timing issues). For the project I won't need > > > > anything any faster than that. > > > > > I'm just wondering how XST would handle such an addition statement > > > > with multiple operands (my synthesis report doesn't say anything ab= out > > > > adders). Is it smart enough to automatically do some kind of tree > > > > algorithm, or would it do a "dumb" array of one adder feeding into = the > > > > next for each extra operand? > > > > > Thanks for the quick response! > > > > > Steve- Hide quoted text - > > > > > - Show quoted text - > > > > Do you really need to recompute the entire array sum every time, or > > > can you compute a running sum (accumulator) as the data comes in? You > > > can also subtract the last discarded term from your running sum if yo= u > > > are looking for a continuous N-term running sum (as is used in a > > > boxcar filter, etc.) > > > > As long as integers will handle your data size, you are much better > > > off using them than padding vectors. Simulations will run much faster= , > > > and there is no hardware associated with conversion from/to SLV/signe= d/ > > > unsigned to/from integer. > > > > Andy > > > Well, I have thought about the accumulator approach, but this is a 5x5 > > array being fed data through some delay lines, so I would then need > > one accumulator for each 5-byte row. > > Then I would still have to sum up the output of the five accumulators, > > leaving me one stage deeper than a tree of adders taking all 25 > > inputs. > > > Peter, I'm not converting 25 lines to 6 bits, but rather taking a sum > > of 25 8-bit values resulting in a 13-bit value. > > > Thanks again for the replies so far! > > Well, where do you store the 200 bits (5 x5 x 8) and how do you move > them into the FPGA? > Remember, the internal logic is thousands of times faster than you > need... > Peter I declared five arrays (0 to 4) of std_logic_vector(7 downto 0) in signals which get assigned in a clocked process, so if I understand correctly, each of these bits gets a DFF. I'm not worried about resources, as I am only using about 20% of the slices available to a 400k gate Spartan-3 and I don't have that many things more to add. I may be able to get away with the 200k gate chip even. And when I added this set of adders to the design, it didn't seem to take significantly more resources. I understand that the logic is much faster than I need, so I guess it doesn't really matter how I code it for the project, but I might like to go through later (just for myself) and see how well I could optimize it and how fast it could run ultimately if the incoming data rate was not limited. I didn't really post here because I feel like I would have any issues with my design, I was more just curious on how XST would handle: Result <=3D A + B + C + D + E + F + .... + X + Y; Cheers! SteveArticle: 140782
On May 25, 1:08=A0pm, Pablo <pbantu...@gmail.com> wrote: > > I use the MPMC to map memory ports to DDR2 external memory. This > > mechanism has been successfully tested with up to 7 microblazes. > > > /Per > > Firstly, thanks a lot. > > Secondly, I would be grateful if you could tell me if you used XUP > Board and the version of Xilinx Platform Studio. Do you know anything > else of this type of design? > > again, my best regards I've built multi-processors with both mb and ppc using the Xilinx ML401, ML403, ML505, ML506 demo boards. This works fine under multiple development environments (virtual pcs with ISE/EDK v9.2 and v10.1). IMHO the Xilinx docs/tutorials for multi-processors are so thin that they are not particularly useful. We have a fairly detailed appnote showing how to design/build/test MPSoC using our high-level tools for registered users at www.codetronix.com. Go to Downloads>AppNotes>MPSoC. This shows how to start from a single- processor BSP-wizard-generated xps system, replicate necessary hw structures, and download elf files -- it may provide some clues for you. /Per /PerArticle: 140783
As with every new SW release by Xilinx, the challenge to get the USB cables to work begins. It wouldn't be a new release if things would actually work, but we already got to expect that .... With 10.1xxx libusb seemed to fix the problem and everything worked file. With 11.1 Xilinx managed to break libusb support. Jungo, who makes the windrv, and periodically emails me advertising their "software development skills" is apparently clueless about driver development as well. Did anybody running linux (Fedora 7) 0n x86_64 had any luck with the cable drivers ? Can you tell I am frustrated ? :<| rudiArticle: 140784
On 26 mayo, 05:57, lj...@codetronix.com wrote: > On May 25, 1:08 pm, Pablo <pbantu...@gmail.com> wrote: > > > > I use the MPMC to map memory ports to DDR2 external memory. This > > > mechanism has been successfully tested with up to 7 microblazes. > > > > /Per > > > Firstly, thanks a lot. > > > Secondly, I would be grateful if you could tell me if you used XUP > > Board and the version of Xilinx Platform Studio. Do you know anything > > else of this type of design? > > > again, my best regards > > I've built multi-processors with both mb and ppc using the Xilinx > ML401, ML403, ML505, ML506 demo boards. This works fine under multiple > development environments (virtual pcs with ISE/EDK v9.2 and v10.1). > > IMHO the Xilinx docs/tutorials for multi-processors are so thin that > they are not particularly useful. We have a fairly detailed appnote > showing how to design/build/test MPSoC using our high-level tools for > registered users atwww.codetronix.com. Go to > Downloads>AppNotes>MPSoC. This shows how to start from a single- > processor BSP-wizard-generated xps system, replicate necessary hw > structures, and download elf files -- it may provide some clues for > you. > > /Per > > /Per thanks again. I am going to try it just now. my best regardsArticle: 140785
luudee <rudolf.usselmann@gmail.com> wrote: > As with every new SW release by Xilinx, the challenge to get the > USB cables to work begins. It wouldn't be a new release if things > would actually work, but we already got to expect that .... > With 10.1xxx libusb seemed to fix the problem and everything > worked file. With 11.1 Xilinx managed to break libusb support. > Jungo, who makes the windrv, and periodically emails me advertising > their "software development skills" is apparently clueless about > driver development as well. > Did anybody running linux (Fedora 7) 0n x86_64 had any luck with > the cable drivers ? > Can you tell I am frustrated ? :<| If you have a DLC5/Byteblaster or FTDI FT2232 based cable, please have a look at my xc3sprog service release, and the pending patch 2796767. I will try to upload a recent svn dump to sourceforge probably next week ( june 2-6, 2009) Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 140786
On 2009-05-21, Mike Treseler <mtreseler@gmail.com> wrote:
> I agree, but not everyone is a language wonk.
> This is straightforward in vhdl, and has been
> covered repeatedly in the vhdl newsgroup.
> If you have done it in verilog,
> let's see the code.
It is straight forward in Verilog as well. This is taken from an Ethernet
CRC32 module I wrote a long time ago:
// Ethernet's CRC32
always @(posedge clk125_i) begin
if(crc_enable) begin
crc_tmp = crc;
// Implement it as a for loop of the bit serial version
// and hope that the synthesizer optimize it well (at least ISE does)
for(i = 0; i < 8; i = i + 1) begin
fb = crc_tmp[31];
crc_tmp[31] = crc_tmp[30];
crc_tmp[30] = crc_tmp[29];
crc_tmp[29] = crc_tmp[28];
// ... and so on...
crc_tmp[2] = next_txd_o[i] ^ fb ^ crc_tmp[1]; // x^2
crc_tmp[1] = next_txd_o[i] ^ fb ^ crc_tmp[0]; // x^1
crc_tmp[0] = next_txd_o[i] ^ fb; // 1
end // for (i = 0; i < 8; i = i + 1)
crc <= crc_tmp;
end else if(crc_clear) begin
crc <= 32'hffffffff;
end
end
/Andreas
Article: 140787On 2009-05-26, ljung@codetronix.com <ljung@codetronix.com> wrote: > I've built multi-processors with both mb and ppc using the Xilinx > ML401, ML403, ML505, ML506 demo boards. This works fine under multiple > development environments (virtual pcs with ISE/EDK v9.2 and v10.1). I've seen quite a few papers about multiprocessor microblaze systems or multiprocessor nios systems. I'm somewhat curious though, is anyone using this kind of solution in a commercial setting? I can understand it for educational purposes, but for commercial purposes, wouldn't it be better to just buy an embedded multicore processor of some sort? /AndreasArticle: 140788
On Mon, 25 May 2009 16:44:28 -0700 (PDT), Weng Tianxiang <wtxwtx@gmail.com> wrote: >On May 25, 2:28 pm, Andy <jonesa...@comcast.net> wrote: >> Weng, >> >> You've told the synthesizer that state2_ns (the combinatorial signal, >> not the register) has to remember its previous value under certain >> circumstances, so it generates a latch to remember the value. >> >> Your choices to avoid the latch include a) avoiding combinatorial >> processes, >Hi Andy, >You are right and I understand it. I am interested in your method a. >Could you give me an example on how to use your method a. in the above >situation. Search for "Single Process State Machine" - it has been described many times on this group and it is the usual way to avoid combinatorial processes in your example - to avoid precisely the problem that you took a week to find. - BrianArticle: 140789
On Mon, 25 May 2009 17:58:40 -0500, "MikeWhy" <boat042-nospam@yahoo.com> wrote: >The top level module in Xilinx ISE 11.1 projects apparently cannot contain >more than one VHDL architecture. If that module is already the top level in >the project, both (all) architectures are marked as top-level in the Design >pane Heirarchy view. Both architectures are apparently synthesized. (Device >utilization approximately doubled.) Is this something you have used in previous versions of ISE, i.e. a regression, or something you hadn't tried previously? Are both architectures in the same file? If they are in different files, do the symptoms differ? Previous ISE versions have had problems recognising design units and selecting the correct design unit, both (a) because they couldn't handle configurations correctly (or even see them at all, unless there was an ent/arch in the same file!) and (b) because they didn't implement the VHDL library/use clauses. The latter was to be fixed in 11.1, according to previous reports from Xilinx. I haven't seen across this specific example in 10.1. Then I haven't specifically looked for it, but I have compiled two architectures in separate files for the same entity, and had trouble making it select a specific arch either through configurations or embedded configuration statements. I was looking forward to a shiny new version that cleared up the whole mess... - BrianArticle: 140790
> Thanks Mike, but I just don't see the rescan-project option.
>
> Here is what I do:
> =A0open a .vhd file
> =A0vhdl menu, select speedbar to open up the speedbar window
>
> When I right-click, hold down, speedbar: I don't see the rescan-
> project option. I see a list of options starting with Update, Auto-
> update, .... Customise, Close, Quit.
>
> I don't quite understand your hint "center-click the project file".
> vhdl menu export project creates a .prj file. But this file doesn't
> show up in the speed bar? Is this the .prj file you are suggesting I
> center-click in the speedbar?
>
> Cheers
> Andrew
On my vhdl-mode speedbar (vhdl-mode 3.33.21/Emacs 21.3.1/win XP
environment)
it pops up as a menu entry #16 from top, it also says (R) as a hint on
which key to press.
I also have a make target "mf" to do this:
[I put all emacs project setup stuff in emacs.prj]
# Makefile syntax (note tabs, not spaces!!)
mf :
$(if $(wildcard emacs.prj), \
${RM} -rf .emacs-vhdl-cache-*; \
emacs -batch -l vhdl-mode -project <your_project_name> -f vhdl-
generate-makefile, \
$(error You must have an emacs.prj file))
# end Makefile
Regards -- Pontus
Article: 140791On May 26, 5:09=A0pm, Uwe Bonnes <b...@elektron.ikp.physik.tu- darmstadt.de> wrote: > > If you have a DLC5/Byteblaster or FTDI FT2232 based cable, please have a = look > at =A0my xc3sprog =A0service release, and the pending patch 2796767. Actually it's a DLC9G, I have some older onces as well, but I think they are all DLC9__ Will they work as well ? > I will try to upload a recent svn dump to sourceforge probably next week = ( > june 2-6, 2009) > > Bye > -- > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-dar= mstadt.de Thanks, I will take a look ! rudiArticle: 140792
luudee <rudolf.usselmann@gmail.com> wrote: > On May 26, 5:09 pm, Uwe Bonnes <b...@elektron.ikp.physik.tu- > darmstadt.de> wrote: > > > > If you have a DLC5/Byteblaster or FTDI FT2232 based cable, > > please have a look > > at my xc3sprog service release, and the pending patch 2796767. > Actually it's a DLC9G, I have some older onces as well, but I think > they > are all DLC9__ > Will they work as well ? The XILINX FX2-USB cable will not work out of the box. I don't know if the protocoll is reversed engineered enough to write a usefull cable backend. Otherwise an alternative firmware could be used, but without some knowledge around the FX2 and the DLC9/10 chances are to brick the device. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 140793
Here ya go...
State2 : process(CLK)
begin
if rising_edge(CLK) then
if SINI = '1' then
State2 <= Idle_S;
else
case State2 is
when Idle_S =>
if A1 = '1' then
State2 <= X_S;
end if;
when X_S =>
if A2 = '1' then
State2 <= Idle_S;
end if;
end case;
end if; -- sini
end if; -- clk
end process;
Unless you know that SINI is initially asserted (to initialize the
state machine), you will need a reset for the state machine too.
Andy
Article: 140794On 26 Mai, 05:10, sbatt...@yahoo.co.jp wrote: > I didn't really post here because I feel like I would have any issues > with my design, I was more just curious on how XST would handle: > Result <= A + B + C + D + E + F + .... + X + Y; At first it surely will create a linear chain of adders in the order that the equation has to be parsed based on VHDL semantics. (I am not sure whether that is left to right or right to left) There might be some extra logic to optimize the structure either at the RTL level or later on the bitlevel. It actually is rather simple to do that after placement. See my paper: http://eis.eit.uni-kl.de/eis/research/publications/papers/iccd04.pdf I do not know whether ISE does implement any of this so it is probably better to force the order the equation is parsed using brackets and create a minimum depth tree: Result <= (A + B) + (C+D); Beware: The performance of this might actually be worse. The reason for this is, that when you go through N adders of M Bits your critical path does not have length N*M but only N+M because all the carries run in the same direction. Therefore a regularly laid out array of adders might be faster than a tree if the the regularity significantly reduces the routing delay between the adders. Do not be concerned about the additional input bits that receive 0 inputs when extending your adders. Logic optimizers are very good at propagating constants. Unnecessary LUTs will be removed. But I agree with the other posters: You do not need 25 adders, 15 adders and some shift registers are enough for your application. You only need to keep track of 5 sums and update them with every new data word using two adders. Have fun, Kolja SulimmaArticle: 140795
"Brian Drummond" <brian_drummond@btconnect.com> wrote in message news:0kin15hcan2n2u26pjakfbojt84q5balh8@4ax.com... > On Mon, 25 May 2009 17:58:40 -0500, "MikeWhy" <boat042-nospam@yahoo.com> > wrote: > >>The top level module in Xilinx ISE 11.1 projects apparently cannot contain >>more than one VHDL architecture. If that module is already the top level >>in >>the project, both (all) architectures are marked as top-level in the >>Design >>pane Heirarchy view. Both architectures are apparently synthesized. >>(Device >>utilization approximately doubled.) > > Is this something you have used in previous versions of ISE, i.e. a > regression, > or something you hadn't tried previously? I haven't tried previous to 11.1. > Are both architectures in the same file? > If they are in different files, do the symptoms differ? The architectures are in the same file. I did not try separating the arch into different files. > Previous ISE versions have had problems recognising design units and > selecting > the correct design unit, both (a) because they couldn't handle > configurations > correctly (or even see them at all, unless there was an ent/arch in the > same > file!) and (b) because they didn't implement the VHDL library/use clauses. > The latter was to be fixed in 11.1, according to previous reports from > Xilinx. > > I haven't seen across this specific example in 10.1. > Then I haven't specifically looked for it, but I have compiled two > architectures > in separate files for the same entity, and had trouble making it select a > specific arch either through configurations or embedded configuration > statements. > > I was looking forward to a shiny new version that cleared up the whole > mess... I could almost forgive it as a GUI tool issue, but the double implementation even with the "extra" architecture commented out in the source makes the situation extremely scary. Once the build is polluted this way, the intermediate files need to be removed to recover. It also raises questions about what else is tagging along, hidden, in the intermediate files after the code is modified.Article: 140796
Uwe, maybe you already know it... else you can be interessed in this project (GPL): http://www.urjtag.org/ They does support a lot of cable and EXPERIMENTALLY (they declare to NOT to use it) they can do something with xilinx platform cable too (both embedded and external)! (below you can find the list of cable supported) Rudi, with 10.x I successfully used http://www.rmdir.de/~michael/xilinx/ I didn't try with 11.x (still not downloaded...) maybe should you wait the new libusb-driver version ;-) List of urjtag supported cables: ARCOM Arcom JTAG Cable ByteBlaster Altera ByteBlaster/ByteBlaster II/ByteBlasterMV Parallel Port Download Cable UsbBlaster Altera USB-Blaster Cable FT2232 Generic FTDI FT2232 Cable JTAGkey Amontec JTAGkey (FT2232) Cable ARM-USB-OCD Olimex ARM-USB-OCD[-TINY] (FT2232) Cable gnICE Analog Devices Blackfin gnICE (FT2232) Cable (EXPERIMENTAL) OOCDLink-s OOCDLink-s (FT2232) Cable (EXPERIMENTAL) Signalyzer Xverve DT-USB-ST Signalyzer Tool (FT2232) Cable (EXPERIMENTAL) Turtelizer2 Turtelizer 2 Rev. B (FT2232) Cable (EXPERIMENTAL) USB-to-JTAG-IF USB to JTAG Interface (FT2232) Cable (EXPERIMENTAL) Flyswatter TinCanTools Flyswatter (FT2232) Cable usbScarab2 KrisTech usbScarabeus2 (FT2232) Cable DLC5 Xilinx DLC5 JTAG Parallel Cable III EA253 ETC EA253 JTAG Cable EI012 ETC EI012 JTAG Cable IGLOO Excelpoint IGLOO JTAG Cable KeithKoep Keith & Koep JTAG cable Lattice Lattice Parallel Port JTAG Cable MPCBDM Mpcbdm JTAG cable TRITON Ka-Ro TRITON Starterkit II (PXA255/250) JTAG Cable WIGGLER Macraigor Wiggler JTAG Cable WIGGLER2 Modified (with CPU Reset) WIGGLER JTAG Cable xpc_int Xilinx Platform Cable USB internal chain xpc_ext Xilinx Platform Cable USB external chain jlink Segger/IAR J-Link, Atmel SAM-ICE and others.Article: 140797
Sandro <sdroamt@netscape.net> wrote: > Uwe, > maybe you already know it... else you can be interessed > in this project (GPL): > http://www.urjtag.org/ > They does support a lot of cable and > EXPERIMENTALLY (they declare to NOT to use it) they can > do something with xilinx platform cable too (both embedded and > external)! (below you can find the > list of cable supported) > Rudi, > with 10.x I successfully used > http://www.rmdir.de/~michael/xilinx/ > I didn't try with 11.x (still not downloaded...) > maybe should you wait the new libusb-driver version ;-) xc3sprog takes JEDEC/Bitfile directly, so no need to generate SVF, and a chance to generated better error feedback. xc3sprog only needs command line parameters, so it integrated nice into makefiles. Speed may be another issue. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 140798
"Symon" <symon_brewer@hotmail.com> wrote in message news:gvf2nc$r78$1@news.eternal-september.org... > MM wrote: >>> 3. Why DSP and Memory are rectangular in shape ? >> >> Do you mean why they are not round? >> >> > No, why are they rectangular? Do you know? Poincare‘s conjecture says that no matter what it looks like, it’s a sphere.Article: 140799
On May 22, 8:23 pm, jleslie48 <j...@jonathanleslie.com> wrote: > On May 22, 5:55 pm, Muzaffer Kal <k...@dspia.com> wrote: > > > > > On Fri, 22 May 2009 14:20:59 -0700 (PDT), jleslie48 > > > <j...@jonathanleslie.com> wrote: > > >On May 22, 5:26 pm, doug <x...@xx.com> wrote: > > > >> Only FFs have reset. > > > >that doesn't mean anything to me. maybe I inlcuded too much code in > > >the snippet, the only part of the code > > >that is causing the issue I believe is this: > > > >----------------------------------------------------------------------------------- > > > type reg_file_type is array (2**W-1 downto 0) of > > > std_logic_vector(B-1 downto 0); > > > signal array_reg: reg_file_type; > > >----------------------------------------------------------------------------------- > > > >the error message in question has no issue with the reset. its > > >complaining about <array_reg> > > > The "warning" is just telling you that it couldn't map your "array" to > > memory. Doug has said the reason that couldn't be done probably was > > that you have some code which says: > > > if (reset) > > array <= 0 > > > or something similar. As "only ffs have reset" this "array" can't be > > mapped to memory. If you have code like this, remove it, add an > > initial statement to clear array instead and try again. > > -- > > Muzaffer Kal > > > DSPIA INC. > > ASIC/FPGA Design Services > > >http://www.dspia.com > > Thank you, that makes sense. I'll have to check. C:\jon\fpga_uartjl_01\Pchu_cc02\ms_d04\source>grep -in -B3 -A3 array_reg fifo.vhd 23-architecture arch of fifo is 24- type reg_file_type is array (2**W-1 downto 0) of 25- std_logic_vector(B-1 downto 0); 26: signal array_reg: reg_file_type; 27- signal w_ptr_reg, w_ptr_next, w_ptr_succ: 28- std_logic_vector(W-1 downto 0); 29- signal r_ptr_reg, r_ptr_next, r_ptr_succ: -- 39- process(clk,reset) 40- begin 41- if (reset='1') then 42: array_reg <= (others=>(others=>'0')); 43- elsif (clk'event and clk='1') then 44- if wr_en='1' then 45: array_reg(to_integer(unsigned(w_ptr_reg))) 46- <= w_data; 47- end if; 48- end if; 49- end process; 50- -- read port 51: r_data <= array_reg(to_integer(unsigned(r_ptr_reg))); 52- -- write enabled only when FIFO is not full 53- wr_en <= wr and (not full_reg); 54- Ok, so here's all the code pertaining to array_reg, specifically lines 42, 45, and 51. From what I can understand, it seems that the professionals here are concerned about line 42; the one resulting from the reset signal. What would be the correct way to implement this concept? In C I would of just done a memset(array_reg, 0, sizeof(array_reg)) but we ain't in C world any more...
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z