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how to implement bidirectional tristate buffer having two I/O ports and two control signals. I have tried but its not working properly.Article: 141276
Hi. I'm trying to communicate a Spartan 3e starter kit revision D whit a PC via ethernet using Microblaze and EDK 10.1, but i don't know how to use the ethernet IP EMAClite. If anyone have an example or documentation about it, would be very helpful. Thank you. Javier.Article: 141277
Weng Tianxiang schrieb: > On Jun 15, 4:36 am, rickman <gnu...@gmail.com> wrote: >> On Jun 14, 1:21 pm, Weng Tianxiang <wtx...@gmail.com> wrote: >> >> >> >> >> >>> Hi, >>> I recently read Altera Stratix II, III and IV device handbook and >>> found its 3-bit addition circuit is really a genius invention. But I >>> was surprised to find that Altera patent application "Logic Cell >>> Supporting Addition of Three Binary Words" filed on Nov. 21, 2003 has >>> not been approved to be a patent so far today, even though many Altera >>> later patent applications based on the invention have been approved >>> for U.S. patents. >>> Is anyone knowledgable about the patent application willing to >>> transfer the patent application context to me and disclose why it >>> hasn't been approved as a U.S. patent. >>> My guess is it may never be approved by U.S. Patent Office to be a >>> patent, the reason is not its novelty violation, but its context >>> didn't disclose enough information about the 3-bit addition circuit, a >>> requirement for any patent application to be approved to be a U.S. >>> patent. At least those skilled in the art cannot get the idea what is >>> done within its circuit having an encircled '+' with 3 inputs and 2 >>> outputs. >>> Altera another sister patent application "Arithmetic Structure is for >>> Programmable Logic Device" filed on Oct. 23, 2003 has the same fate. >>> Thank you. >>> Weng >> I don't know why Altera wouldn't disclose info on the structure being >> used in a device. It is relatively inexpensive to reverse engineer a >> chip, so if it is not disclosed in a patent, it is not protected and >> is vulnerable to being copied. >> >> What exactly *does* the patent claim? Maybe the design inside the >> circled + is not really novel and only the design around the circle is >> novel enough to be patented? >> >> In general, I think a three in put adder is *very useful*. I've never >> seen such a circuit, I guess the carry chain has multiple bits, eh? >> >> Rick- Hide quoted text - >> >> - Show quoted text - > > > Hi Rick, > Here is a link to Stratix IV Device Handbook Volumn 1 and page 43 > shows the invention circuit: > http://www.altera.com/literature/hb/stratix-iv/stx4_5v1.pdf > > Why is it very useful? In the Stratix IV Device Handbook Volumn 1, it > describes two applications: multiplication and correlation function. > > Any other applications? With multiplier hardware structure specially > introduced in FPGA, is multiplication circuit still used for > multiplication? The structure is useful for: - multipliers with a deep pipeline - constant coefficient multipliers - multipliers with small input values (i.e. few bits/operand) -MarkusArticle: 141278
On Jun 15, 9:06=A0am, Test01 <cpan...@yahoo.com> wrote: > I am using Virtex4 FPGA. =A0I have 32 bit data packets running at 200MHz > and would like to convet that into 64 bit data packets running at > 100MHz. =A0This is not at the FPGA I/O but needs to be done inside the > FPGA fabric. =A0I have done this conversion myself in verilog but I just > wanted to see how you all do this. > > Here is how I have done it > > (1) I used PMCD to divide the 200MHz clock by 2 (100MHz). =A0I am > assuming that the 200MHz and 100MHz clocks are completely phase > aligned. > (2) Latch the 32 bit packets on both positive and negative edges of > the clocks. =A0This give me 64 bits of data but it is not phase aligned > to one another. > (3) Latch the 64 bits of data on posedge of 100MHz clock > (4) If the first valid data after reset started out on the posedge of > the 100MHz clock then latch the data again at posedge of 100MHz clock > and use it. At this point the data is posedge aligned to 100MHz clock > (5) If the first valid data after reset stated out on the negedge of > the 100MHz clock then on posedge of 100MHz clock, latch the upper 32 > bits from step2 and lower 32 bits from step3. =A0This will give the > posedge aligned 64 bits of data. > > There are other sideband signal that go with this also. =A0I am trying > to use the same scheme but I am not sure if this can run into timing > isues in Virtex4 FPGA. =A0There is not much decoding needed to do thus > it helps from that standpoint. =A0But main concern I have is that I am > latching the data on neg edge of 100MHz clock and then latching the > same data on posedge of 100MHz clock. =A0I am not sure if there is any > timing concerns if I do not have much combinatorial logic in the path. > > Your opinions will be very helpful to me. > > Thanks. > > cp Why not just register the data in the 200 MHz clock domain with a second register following so that you always have the most recent 32 bits of data and the previous 32 bits of data. You monitor this data to see when you have a data start in the second register and capture both 32 bit registers in a 64 bit register. A simple 1 bit counter tells you when to capture subsequent 64 bit samples. I'm not really clear about how to detect your start condition. It sounds like you are just using the reset signal in which case it is very, very simple. In fact, is there a reason you even need a 100 MHz signal before Your solution is about the same thing, but by working in the 100 MHz clock domain with both clock edges, you are not really running at 100 MHz, but at 200 MHz for purposes of timing. The only difference I see is that the 64 bit wide multiplexer is not needed with my method and it is simpler to define the timing constraints... I think... timing constraints are seldom simple and the tool vendors have never provided a way to verify them! I've even had vendor representatives tell me that they don't need to be verified, I just need to write them correctly! :^) So much for the wisdom of vendors... RickArticle: 141279
On Jun 15, 10:13 am, Weng Tianxiang <wtx...@gmail.com> wrote: > On Jun 15, 4:36 am, rickman <gnu...@gmail.com> wrote: > > > > > On Jun 14, 1:21 pm, Weng Tianxiang <wtx...@gmail.com> wrote: > > > > Hi, > > > I recently read Altera Stratix II, III and IV device handbook and > > > found its 3-bit addition circuit is really a genius invention. But I > > > was surprised to find that Altera patent application "Logic Cell > > > Supporting Addition of Three Binary Words" filed on Nov. 21, 2003 has > > > not been approved to be a patent so far today, even though many Altera > > > later patent applications based on the invention have been approved > > > for U.S. patents. > > > > Is anyone knowledgable about the patent application willing to > > > transfer the patent application context to me and disclose why it > > > hasn't been approved as a U.S. patent. > > > > My guess is it may never be approved by U.S. Patent Office to be a > > > patent, the reason is not its novelty violation, but its context > > > didn't disclose enough information about the 3-bit addition circuit, a > > > requirement for any patent application to be approved to be a U.S. > > > patent. At least those skilled in the art cannot get the idea what is > > > done within its circuit having an encircled '+' with 3 inputs and 2 > > > outputs. > > > > Altera another sister patent application "Arithmetic Structure is for > > > Programmable Logic Device" filed on Oct. 23, 2003 has the same fate. > > > > Thank you. > > > > Weng > > > I don't know why Altera wouldn't disclose info on the structure being > > used in a device. It is relatively inexpensive to reverse engineer a > > chip, so if it is not disclosed in a patent, it is not protected and > > is vulnerable to being copied. > > > What exactly *does* the patent claim? Maybe the design inside the > > circled + is not really novel and only the design around the circle is > > novel enough to be patented? > > > In general, I think a three in put adder is *very useful*. I've never > > seen such a circuit, I guess the carry chain has multiple bits, eh? > > > Rick- Hide quoted text - > > > - Show quoted text - > > Hi Rick, > Here is a link to Stratix IV Device Handbook Volumn 1 and page 43 > shows the invention circuit:http://www.altera.com/literature/hb/stratix-iv/stx4_5v1.pdf > > Why is it very useful? In the Stratix IV Device Handbook Volumn 1, it > describes two applications: multiplication and correlation function. > > Any other applications? With multiplier hardware structure specially > introduced in FPGA, is multiplication circuit still used for > multiplication? Although they show the interconnections being used, they don't show the logic implemented in the LUTs. The carry from one bit to the next is done with two signals each of which has the same weight. As far as I can tell, this is just a pair of cascaded adders, the first done in the LUTs and the second done in dedicated hardware. The only novelty is that instead of adding two inputs with one adder chain (the LUTs) and then adding the result to the third input with the dedicated hardware chain, they add all three input bits using the LUTs and feed both carry bits into the dedicated hardware chain which means the carry chain always uses the fast, dedicated hardware. Does that sound like a patent worthy invention to you? I don't really know what is and what is not worthy of a patent. But other patents "based" on this patent will not be affected by the validity of this patent. Even if this patent is upheld, ***I*** could patent some additional feature that uses this design as a starting point. I just can't build it without permission from the patent holder of the original design. Still, this means he/she couldn't use my idea without my permission either. RickArticle: 141280
On Jun 15, 8:39=A0am, rickman <gnu...@gmail.com> wrote: > On Jun 15, 10:13 am, Weng Tianxiang <wtx...@gmail.com> wrote: > > > > > > > On Jun 15, 4:36 am, rickman <gnu...@gmail.com> wrote: > > > > On Jun 14, 1:21 pm, Weng Tianxiang <wtx...@gmail.com> wrote: > > > > > Hi, > > > > I recently read Altera Stratix II, III and IV device handbook and > > > > found its 3-bit addition circuit is really a genius invention. But = I > > > > was surprised to find that Altera patent application "Logic Cell > > > > Supporting Addition of Three Binary Words" filed on Nov. 21, 2003 h= as > > > > not been approved to be a patent so far today, even though many Alt= era > > > > later patent applications based on the invention have been approved > > > > for U.S. patents. > > > > > Is anyone knowledgable about the patent application willing to > > > > transfer the patent application context to me and disclose why it > > > > hasn't been approved as a U.S. patent. > > > > > My guess is it may never be approved by U.S. Patent Office to be a > > > > patent, the reason is not its novelty violation, but its context > > > > didn't disclose enough information about the 3-bit addition circuit= , a > > > > requirement for any patent application to be approved to be a U.S. > > > > patent. At least those skilled in the art cannot get the idea what = is > > > > done within its circuit having an encircled '+' with 3 inputs and 2 > > > > outputs. > > > > > Altera another sister patent application "Arithmetic Structure is f= or > > > > Programmable Logic Device" filed on Oct. 23, 2003 has the same fate= . > > > > > Thank you. > > > > > Weng > > > > I don't know why Altera wouldn't disclose info on the structure being > > > used in a device. =A0It is relatively inexpensive to reverse engineer= a > > > chip, so if it is not disclosed in a patent, it is not protected and > > > is vulnerable to being copied. > > > > What exactly *does* the patent claim? =A0Maybe the design inside the > > > circled + is not really novel and only the design around the circle i= s > > > novel enough to be patented? > > > > In general, I think a three in put adder is *very useful*. =A0I've ne= ver > > > seen such a circuit, I guess the carry chain has multiple bits, eh? > > > > Rick- Hide quoted text - > > > > - Show quoted text - > > > Hi Rick, > > Here is a link to Stratix IV Device Handbook Volumn 1 and page 43 > > shows the invention circuit:http://www.altera.com/literature/hb/stratix= -iv/stx4_5v1.pdf > > > Why is it very useful? In the Stratix IV Device Handbook Volumn 1, it > > describes two applications: multiplication and correlation function. > > > Any other applications? With multiplier hardware structure specially > > introduced in FPGA, is multiplication circuit still used for > > multiplication? > > Although they show the interconnections being used, they don't show > the logic implemented in the LUTs. =A0The carry from one bit to the next > is done with two signals each of which has the same weight. =A0As far as > I can tell, this is just a pair of cascaded adders, the first done in > the LUTs and the second done in dedicated hardware. =A0The only novelty > is that instead of adding two inputs with one adder chain (the LUTs) > and then adding the result to the third input with the dedicated > hardware chain, they add all three input bits using the LUTs and feed > both carry bits into the dedicated hardware chain which means the > carry chain always uses the fast, dedicated hardware. > > Does that sound like a patent worthy invention to you? =A0I don't really > know what is and what is not worthy of a patent. =A0But other patents > "based" on this patent will not be affected by the validity of this > patent. =A0Even if this patent is upheld, ***I*** could patent some > additional feature that uses this design as a starting point. =A0I just > can't build it without permission from the patent holder of the > original design. =A0Still, this means he/she couldn't use my idea > without my permission either. > > Rick- Hide quoted text - > > - Show quoted text - Hi Rick, There are two novel points there: 1. It transfers 3 adders into 2 adders which was described very clear: nobody before had invented that point. 2. Circuit is marked by circled '+' with 3 inputs and 2 outputs whose internal structure wasn't shown. 3. I am sure there may be more than 20 claims in the application as Altera patent claim trandition goes. WengArticle: 141281
You can try to go to USPTO database and lookup the history of this patent application. It's not under the patent search, but under "http://www.uspto.gov" -> "Patents" -> "view in PAIR" -> "public PAIR". This database contains a complete history of the patent, including the correspondence with patent examiners, etc. Also, can you post the patent application number. - outputlogic http://outputlogic.comArticle: 141282
"namit" <namitrarotra@gmail.com> wrote in message news:RcGdnY52m9ePwKvXnZ2dnUVZ_jSdnZ2d@giganews.com... > how to implement bidirectional tristate buffer having two I/O ports and > two > control signals. I have tried but its not working properly. > > LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY work; ENTITY Doodle IS PORT ( DIR : IN STD_LOGIC; TRISTATE : IN STD_LOGIC; BIDIR1 : INOUT STD_LOGIC; BIDIR2 : INOUT STD_LOGIC ); END Doodle; ARCHITECTURE bdf_type OF Doodle IS SIGNAL SYNTHESIZED_WIRE_0 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_1 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_2 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_5 : STD_LOGIC; BEGIN PROCESS(BIDIR1,SYNTHESIZED_WIRE_0) BEGIN if (SYNTHESIZED_WIRE_0 = '1') THEN BIDIR2 <= BIDIR1; ELSE BIDIR2 <= 'Z'; END IF; END PROCESS; PROCESS(BIDIR2,SYNTHESIZED_WIRE_1) BEGIN if (SYNTHESIZED_WIRE_1 = '1') THEN BIDIR1 <= BIDIR2; ELSE BIDIR1 <= 'Z'; END IF; END PROCESS; SYNTHESIZED_WIRE_2 <= NOT(DIR); SYNTHESIZED_WIRE_1 <= SYNTHESIZED_WIRE_2 AND SYNTHESIZED_WIRE_5; SYNTHESIZED_WIRE_0 <= SYNTHESIZED_WIRE_5 AND DIR; SYNTHESIZED_WIRE_5 <= NOT(TRISTATE); END bdf_type; PhilArticle: 141283
On Jun 15, 9:23=A0am, OutputLogic <evgen...@gmail.com> wrote: > You can try to go to USPTO database and lookup the history of this > patent application. > It's not under the patent search, but under "http://www.uspto.gov" -> > "Patents" -> "view in PAIR" -> "public PAIR". > This database contains a complete history of the patent, including the > correspondence with patent examiners, etc. > Also, can you post the patent application number. > > - outputlogic > > http://outputlogic.com Hi, Its application number is 10/718,968 filed on November 21, 2003. WengArticle: 141284
On Jun 15, 10:14=A0am, rickman <gnu...@gmail.com> wrote: > On Jun 15, 9:06=A0am, Test01 <cpan...@yahoo.com> wrote: > > > > > > > I am using Virtex4 FPGA. =A0I have 32 bit data packets running at 200MH= z > > and would like to convet that into 64 bit data packets running at > > 100MHz. =A0This is not at the FPGA I/O but needs to be done inside the > > FPGA fabric. =A0I have done this conversion myself in verilog but I jus= t > > wanted to see how you all do this. > > > Here is how I have done it > > > (1) I used PMCD to divide the 200MHz clock by 2 (100MHz). =A0I am > > assuming that the 200MHz and 100MHz clocks are completely phase > > aligned. > > (2) Latch the 32 bit packets on both positive and negative edges of > > the clocks. =A0This give me 64 bits of data but it is not phase aligned > > to one another. > > (3) Latch the 64 bits of data on posedge of 100MHz clock > > (4) If the first valid data after reset started out on the posedge of > > the 100MHz clock then latch the data again at posedge of 100MHz clock > > and use it. At this point the data is posedge aligned to 100MHz clock > > (5) If the first valid data after reset stated out on the negedge of > > the 100MHz clock then on posedge of 100MHz clock, latch the upper 32 > > bits from step2 and lower 32 bits from step3. =A0This will give the > > posedge aligned 64 bits of data. > > > There are other sideband signal that go with this also. =A0I am trying > > to use the same scheme but I am not sure if this can run into timing > > isues in Virtex4 FPGA. =A0There is not much decoding needed to do thus > > it helps from that standpoint. =A0But main concern I have is that I am > > latching the data on neg edge of 100MHz clock and then latching the > > same data on posedge of 100MHz clock. =A0I am not sure if there is any > > timing concerns if I do not have much combinatorial logic in the path. > > > Your opinions will be very helpful to me. > > > Thanks. > > > cp > > Why not just register the data in the 200 MHz clock domain with a > second register following so that you always have the most recent 32 > bits of data and the previous 32 bits of data. =A0You monitor this data > to see when you have a data start in the second register and capture > both 32 bit registers in a 64 bit register. =A0A simple 1 bit counter > tells you when to capture subsequent 64 bit samples. =A0I'm not really > clear about how to detect your start condition. =A0It sounds like you > are just using the reset signal in which case it is very, very > simple. =A0In fact, is there a reason you even need a 100 MHz signal > before > > Your solution is about the same thing, but by working in the 100 MHz > clock domain with both clock edges, you are not really running at 100 > MHz, but at 200 MHz for purposes of timing. =A0The only difference I see > is that the 64 bit wide multiplexer is not needed with my method and > it is simpler to define the timing constraints... I think... timing > constraints are seldom simple and the tool vendors have never provided > a way to verify them! =A0I've even had vendor representatives tell me > that they don't need to be verified, I just need to write them > correctly! =A0:^) > > So much for the wisdom of vendors... > > Rick- Hide quoted text - > > - Show quoted text - Hi Rick, I have 32 bit packets running at 200MHz in Single Data Rate Mode (posedge only), I convert that into 64 bit packet 100MHz Single Data Rate (Posedge only) Clock. The purpose behind doing so - We are trying to leverage some of the verilog modules that are written for 64 bit data path. Also my general feeling with the Virtex4 FPGA is that it has lots of flip-flops but it can not run too fast. Thus if I could widen the data path to 64 bits and run half the speed (100MHz) then that may be better to be able to meet the FPGA timing then to run 32 bits of data at 200MHz. So in a way I am not using both edges of 100MHz clock. CPArticle: 141285
On Jun 15, 9:23=A0am, OutputLogic <evgen...@gmail.com> wrote: > You can try to go to USPTO database and lookup the history of this > patent application. > It's not under the patent search, but under "http://www.uspto.gov" -> > "Patents" -> "view in PAIR" -> "public PAIR". > This database contains a complete history of the patent, including the > correspondence with patent examiners, etc. > Also, can you post the patent application number. > > - outputlogic > > http://outputlogic.com Hi OutputLogic, Thank you for your information. I had searched the website before I posed this message and got the error information: "Sorry, the entered Application Number "10/718968" is not available. The number may have been incorrectly typed, or assigned to an application that is not yet available for public inspection." I don't know why I got the error message. 10/718968 is available from reference literature in the invention: "Programmable Logic Device Having Complex Logic Blocks with Improved Logic Cell Functionality", patent number 7,394,287, by Alera from following website: http://www.google.com/patents/about?id=3D5yyrAAAAEBAJ&dq=3Dpatent:7394287&a= s_drrb_ap=3Dq&as_minm_ap=3D0&as_miny_ap=3D&as_maxm_ap=3D0&as_maxy_ap=3D&as_= drrb_is=3Dq&as_minm_is=3D0&as_miny_is=3D&as_maxm_is=3D0&as_maxy_is=3D WengArticle: 141286
On Jun 15, 8:39=A0am, rickman <gnu...@gmail.com> wrote: > On Jun 15, 10:13 am, Weng Tianxiang <wtx...@gmail.com> wrote: > > > > > > > On Jun 15, 4:36 am, rickman <gnu...@gmail.com> wrote: > > > > On Jun 14, 1:21 pm, Weng Tianxiang <wtx...@gmail.com> wrote: > > > > > Hi, > > > > I recently read Altera Stratix II, III and IV device handbook and > > > > found its 3-bit addition circuit is really a genius invention. But = I > > > > was surprised to find that Altera patent application "Logic Cell > > > > Supporting Addition of Three Binary Words" filed on Nov. 21, 2003 h= as > > > > not been approved to be a patent so far today, even though many Alt= era > > > > later patent applications based on the invention have been approved > > > > for U.S. patents. > > > > > Is anyone knowledgable about the patent application willing to > > > > transfer the patent application context to me and disclose why it > > > > hasn't been approved as a U.S. patent. > > > > > My guess is it may never be approved by U.S. Patent Office to be a > > > > patent, the reason is not its novelty violation, but its context > > > > didn't disclose enough information about the 3-bit addition circuit= , a > > > > requirement for any patent application to be approved to be a U.S. > > > > patent. At least those skilled in the art cannot get the idea what = is > > > > done within its circuit having an encircled '+' with 3 inputs and 2 > > > > outputs. > > > > > Altera another sister patent application "Arithmetic Structure is f= or > > > > Programmable Logic Device" filed on Oct. 23, 2003 has the same fate= . > > > > > Thank you. > > > > > Weng > > > > I don't know why Altera wouldn't disclose info on the structure being > > > used in a device. =A0It is relatively inexpensive to reverse engineer= a > > > chip, so if it is not disclosed in a patent, it is not protected and > > > is vulnerable to being copied. > > > > What exactly *does* the patent claim? =A0Maybe the design inside the > > > circled + is not really novel and only the design around the circle i= s > > > novel enough to be patented? > > > > In general, I think a three in put adder is *very useful*. =A0I've ne= ver > > > seen such a circuit, I guess the carry chain has multiple bits, eh? > > > > Rick- Hide quoted text - > > > > - Show quoted text - > > > Hi Rick, > > Here is a link to Stratix IV Device Handbook Volumn 1 and page 43 > > shows the invention circuit:http://www.altera.com/literature/hb/stratix= -iv/stx4_5v1.pdf > > > Why is it very useful? In the Stratix IV Device Handbook Volumn 1, it > > describes two applications: multiplication and correlation function. > > > Any other applications? With multiplier hardware structure specially > > introduced in FPGA, is multiplication circuit still used for > > multiplication? > > Although they show the interconnections being used, they don't show > the logic implemented in the LUTs. =A0The carry from one bit to the next > is done with two signals each of which has the same weight. =A0As far as > I can tell, this is just a pair of cascaded adders, the first done in > the LUTs and the second done in dedicated hardware. =A0The only novelty > is that instead of adding two inputs with one adder chain (the LUTs) > and then adding the result to the third input with the dedicated > hardware chain, they add all three input bits using the LUTs and feed > both carry bits into the dedicated hardware chain which means the > carry chain always uses the fast, dedicated hardware. > > Does that sound like a patent worthy invention to you? =A0I don't really > know what is and what is not worthy of a patent. =A0But other patents > "based" on this patent will not be affected by the validity of this > patent. =A0Even if this patent is upheld, ***I*** could patent some > additional feature that uses this design as a starting point. =A0I just > can't build it without permission from the patent holder of the > original design. =A0Still, this means he/she couldn't use my idea > without my permission either. > > Rick- Hide quoted text - > > - Show quoted text - Hi Rick, "The only novelty is that instead of adding two inputs with one adder chain (the LUTs) and then adding the result to the third input with the dedicated hardware chain, they add all three input bits using the LUTs and feed both carry bits into the dedicated hardware chain which means the carry chain always uses the fast, dedicated hardware. " The method I found was invented as early as 1963 by C.S. Wallace in paper "A suggestion for a Fast Multiplier" http://www.caip.rutgers.edu/~bushnell/dsmdesign/wallacepaper.pdf The circuit circled in '+' with 3 inputs and 2 outputs is novelty in my opinion, but they didn't disclose it. WengArticle: 141287
On Mon, 15 Jun 2009 16:44:19 -0700 (PDT), Weng Tianxiang <wtxwtx@gmail.com> wrote: >The circuit circled in '+' with 3 inputs and 2 outputs is novelty in >my opinion, but they didn't disclose it. > It would be interesting to see if it's anything other than a 3:2 compressor. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 141288
janigav wrote: > Hi. I'm trying to communicate a Spartan 3e starter kit revision D > whit a PC via ethernet using Microblaze and EDK 10.1, but i don't > know how to use the ethernet IP EMAClite. If anyone have an example > or documentation about it, would be very helpful. I suggest you first open the System Assembly View, right-click on the MAC core and open the PDF DataSheet and the API documentation and go through these. Then you can start browsing your EDK installation folder and should be able to find example applications for the core somewhere. You may also want to check out lwip if you need TCP/IP. HTH, RGArticle: 141289
On Jun 15, 5:06=A0pm, Muzaffer Kal <k...@dspia.com> wrote: > On Mon, 15 Jun 2009 16:44:19 -0700 (PDT), Weng Tianxiang > > <wtx...@gmail.com> wrote: > >The circuit circled in '+' with 3 inputs and 2 outputs is novelty in > >my opinion, but they didn't disclose it. > > It would be interesting to see if it's anything other than a 3:2 > compressor. > -- > Muzaffer Kal > > DSPIA INC. > ASIC/FPGA Design Services > > http://www.dspia.com Here is another good reference published in 1994 by Stanford Ph. D student Gary W. Bewick as his dissatation paper. ftp://reports.stanford.edu/pub/cstr/reports/csl/tr/94/617/CSL-TR-94-617.pdf= , page 34 where a 3:2 compressor was shown graphically. WengArticle: 141290
On Jun 15, 1:36 pm, Test01 <cpan...@yahoo.com> wrote: > On Jun 15, 10:14 am, rickman <gnu...@gmail.com> wrote: > > > > > On Jun 15, 9:06 am, Test01 <cpan...@yahoo.com> wrote: > > > > I am using Virtex4 FPGA. I have 32 bit data packets running at 200MHz > > > and would like to convet that into 64 bit data packets running at > > > 100MHz. This is not at the FPGA I/O but needs to be done inside the > > > FPGA fabric. I have done this conversion myself in verilog but I just > > > wanted to see how you all do this. > > > > Here is how I have done it > > > > (1) I used PMCD to divide the 200MHz clock by 2 (100MHz). I am > > > assuming that the 200MHz and 100MHz clocks are completely phase > > > aligned. > > > (2) Latch the 32 bit packets on both positive and negative edges of > > > the clocks. This give me 64 bits of data but it is not phase aligned > > > to one another. > > > (3) Latch the 64 bits of data on posedge of 100MHz clock > > > (4) If the first valid data after reset started out on the posedge of > > > the 100MHz clock then latch the data again at posedge of 100MHz clock > > > and use it. At this point the data is posedge aligned to 100MHz clock > > > (5) If the first valid data after reset stated out on the negedge of > > > the 100MHz clock then on posedge of 100MHz clock, latch the upper 32 > > > bits from step2 and lower 32 bits from step3. This will give the > > > posedge aligned 64 bits of data. > > > > There are other sideband signal that go with this also. I am trying > > > to use the same scheme but I am not sure if this can run into timing > > > isues in Virtex4 FPGA. There is not much decoding needed to do thus > > > it helps from that standpoint. But main concern I have is that I am > > > latching the data on neg edge of 100MHz clock and then latching the > > > same data on posedge of 100MHz clock. I am not sure if there is any > > > timing concerns if I do not have much combinatorial logic in the path. > > > > Your opinions will be very helpful to me. > > > > Thanks. > > > > cp > > > Why not just register the data in the 200 MHz clock domain with a > > second register following so that you always have the most recent 32 > > bits of data and the previous 32 bits of data. You monitor this data > > to see when you have a data start in the second register and capture > > both 32 bit registers in a 64 bit register. A simple 1 bit counter > > tells you when to capture subsequent 64 bit samples. I'm not really > > clear about how to detect your start condition. It sounds like you > > are just using the reset signal in which case it is very, very > > simple. In fact, is there a reason you even need a 100 MHz signal > > before > > > Your solution is about the same thing, but by working in the 100 MHz > > clock domain with both clock edges, you are not really running at 100 > > MHz, but at 200 MHz for purposes of timing. The only difference I see > > is that the 64 bit wide multiplexer is not needed with my method and > > it is simpler to define the timing constraints... I think... timing > > constraints are seldom simple and the tool vendors have never provided > > a way to verify them! I've even had vendor representatives tell me > > that they don't need to be verified, I just need to write them > > correctly! :^) > > > So much for the wisdom of vendors... > > > Rick- Hide quoted text - > > > - Show quoted text - > > Hi Rick, > > I have 32 bit packets running at 200MHz in Single Data Rate Mode > (posedge only), I convert that into 64 bit packet 100MHz Single Data > Rate (Posedge only) Clock. The purpose behind doing so - We are > trying to leverage some of the verilog modules that are written for 64 > bit data path. Also my general feeling with the Virtex4 FPGA is that > it has lots of flip-flops but it can not run too fast. Thus if I > could widen the data path to 64 bits and run half the speed (100MHz) > then that may be better to be able to meet the FPGA timing then to run > 32 bits of data at 200MHz. > > So in a way I am not using both edges of 100MHz clock. I am not suggesting that you not use the 100 MHz clock, I am saying that for the conversion, you might do better to use the 200 MHz clock until it is "safely" in the 100 MHz clock domain instead of trying to use both phases of the 100 MHz clock. 200 MHz ___---___---___---___---___---___---___---___---___ 100 MHz ___------______------______------______------______ 32 bit data =1=x==2==x==3==x==4==x==5==x==6==x==7==x==8==x==9== Reg A 32 bit ===x==1==x==2==x==3==x==4==x==5==x==6==x==7==x==8== Reg B 32 bit ===x=====x==1==x==2==x==3==x==4==x==5==x==6==x==7== Reg C 64 bit ===x=====x=====x====1/2====x====3/4====x====5/6==== The details of the phasing are not clear from your description. I think you are saying that the 32 bit data may not be in phase with the 64 bit clock (100 MHz). If that is the case, you can either change the phase of the 100 MHz clock (which may not be practical) or use a clock enable for the 100 MHz data with the 200 MHz clock (again may not work with your preexisting code) or you can make Reg B a 64 bit register on the 200 MHz clock receiving both the input 32 bit data and the delayed 32 bit data. The 64 bit B register is enabled on the correct phase of the data then the 100 MHz 64 bit register can clock the data on the correct edge of that clock. 200 MHz ___---___---___---___---___---___---___---___---___ 100 MHz ___------______------______------______------______ 32 bit data =1=x==2==x==3==x==4==x==5==x==6==x==7==x==8==x==9== Reg A 32 bit ===x==1==x==2==x==3==x==4==x==5==x==6==x==7==x==8== Reg B enable _____------______------______------______------____ Reg B 64 bit =========x====1/2====x====3/4====x====5/6====x==7/8 Reg C 64 bit ===x===========x====1/2====x====3/4====x====5/6==== I'm not sure how accurately you can get the edges of the two clock aligned. Is the chip guaranteed to align the phases enough that you can load 200 MHz data into 100 MHz registers when both rising edges are active? The timing diagram above shows them a half clock out so it would work easily, but if the input data slips a 200 MHz clock, then both 64 bit registers are changing at the same time with different clocks. RickArticle: 141291
On Jun 15, 12:22=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote: > On Jun 15, 8:39=A0am, rickman <gnu...@gmail.com> wrote: > > > > > On Jun 15, 10:13 am, Weng Tianxiang <wtx...@gmail.com> wrote: > > > > On Jun 15, 4:36 am, rickman <gnu...@gmail.com> wrote: > > > > > On Jun 14, 1:21 pm, Weng Tianxiang <wtx...@gmail.com> wrote: > > > > > > Hi, > > > > > I recently read Altera Stratix II, III and IV device handbook and > > > > > found its 3-bit addition circuit is really a genius invention. Bu= t I > > > > > was surprised to find that Altera patent application "Logic Cell > > > > > Supporting Addition of Three Binary Words" filed on Nov. 21, 2003= has > > > > > not been approved to be a patent so far today, even though many A= ltera > > > > > later patent applications based on the invention have been approv= ed > > > > > for U.S. patents. > > > > > > Is anyone knowledgable about the patent application willing to > > > > > transfer the patent application context to me and disclose why it > > > > > hasn't been approved as a U.S. patent. > > > > > > My guess is it may never be approved by U.S. Patent Office to be = a > > > > > patent, the reason is not its novelty violation, but its context > > > > > didn't disclose enough information about the 3-bit addition circu= it, a > > > > > requirement for any patent application to be approved to be a U.S= . > > > > > patent. At least those skilled in the art cannot get the idea wha= t is > > > > > done within its circuit having an encircled '+' with 3 inputs and= 2 > > > > > outputs. > > > > > > Altera another sister patent application "Arithmetic Structure is= for > > > > > Programmable Logic Device" filed on Oct. 23, 2003 has the same fa= te. > > > > > > Thank you. > > > > > > Weng > > > > > I don't know why Altera wouldn't disclose info on the structure bei= ng > > > > used in a device. =A0It is relatively inexpensive to reverse engine= er a > > > > chip, so if it is not disclosed in a patent, it is not protected an= d > > > > is vulnerable to being copied. > > > > > What exactly *does* the patent claim? =A0Maybe the design inside th= e > > > > circled + is not really novel and only the design around the circle= is > > > > novel enough to be patented? > > > > > In general, I think a three in put adder is *very useful*. =A0I've = never > > > > seen such a circuit, I guess the carry chain has multiple bits, eh? > > > > > Rick- Hide quoted text - > > > > > - Show quoted text - > > > > Hi Rick, > > > Here is a link to Stratix IV Device Handbook Volumn 1 and page 43 > > > shows the invention circuit:http://www.altera.com/literature/hb/strat= ix-iv/stx4_5v1.pdf > > > > Why is it very useful? In the Stratix IV Device Handbook Volumn 1, it > > > describes two applications: multiplication and correlation function. > > > > Any other applications? With multiplier hardware structure specially > > > introduced in FPGA, is multiplication circuit still used for > > > multiplication? > > > Although they show the interconnections being used, they don't show > > the logic implemented in the LUTs. =A0The carry from one bit to the nex= t > > is done with two signals each of which has the same weight. =A0As far a= s > > I can tell, this is just a pair of cascaded adders, the first done in > > the LUTs and the second done in dedicated hardware. =A0The only novelty > > is that instead of adding two inputs with one adder chain (the LUTs) > > and then adding the result to the third input with the dedicated > > hardware chain, they add all three input bits using the LUTs and feed > > both carry bits into the dedicated hardware chain which means the > > carry chain always uses the fast, dedicated hardware. > > > Does that sound like a patent worthy invention to you? =A0I don't reall= y > > know what is and what is not worthy of a patent. =A0But other patents > > "based" on this patent will not be affected by the validity of this > > patent. =A0Even if this patent is upheld, ***I*** could patent some > > additional feature that uses this design as a starting point. =A0I just > > can't build it without permission from the patent holder of the > > original design. =A0Still, this means he/she couldn't use my idea > > without my permission either. > > > Rick- Hide quoted text - > > > - Show quoted text - > > Hi Rick, > There are two novel points there: > 1. It transfers 3 adders into 2 adders which was described very clear: > nobody before had invented that point. No, it is not 3 adders using 2 adders, it is always just 2 adders. The only difference is that there is only one cascaded chain. There are two carries between each bit of the adder, sort of like a "Propagate/Generate" style of carry, only one results in a chained delay calculation. But I don't see any real advantage to that. I think the real advantage of this circuit is that it takes advantage of the large, 6 input LUT by breaking it into dual 4 input LUTs... but wait, that is still wasting half the 6 input LUTs. So it is really just an optimization of their particular architecture. The only possible novelty here is that they are doing this in an FPGA. > 2. Circuit is marked by circled '+' with 3 inputs and 2 outputs whose > internal structure wasn't shown. Yep, that is because that part is not very patentable, in my opinion. You don't put anything in a patent that is not patentable. Anything you don't explain in a patent is not part of it. > 3. I am sure there may be more than 20 claims in the application as > Altera patent claim trandition goes. Sure, any patent attorney worth his salt is going to put as many claims in as possible. If I understand correctly any claim can stand alone even if the others are struck down. RickArticle: 141292
On Jun 15, 8:06=A0pm, Muzaffer Kal <k...@dspia.com> wrote: > On Mon, 15 Jun 2009 16:44:19 -0700 (PDT), Weng Tianxiang > > <wtx...@gmail.com> wrote: > >The circuit circled in '+' with 3 inputs and 2 outputs is novelty in > >my opinion, but they didn't disclose it. > > It would be interesting to see if it's anything other than a 3:2 > compressor. Someone is missing something. What is the three input, two output circuit? Each bit of the adder has five inputs and three outputs. The three addend inputs can add up to 3 and with the two carry inputs the total can be up to five requiring two carrie outputs of weight 2 and the sum output of weight 1. Of course, I am looking at the data sheet and I guess you are looking at the patent. RickArticle: 141293
On Jun 15, 1:39=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote: > On Jun 15, 9:23=A0am, OutputLogic <evgen...@gmail.com> wrote: > > > You can try to go to USPTO database and lookup the history of this > > patent application. > > It's not under the patent search, but under "http://www.uspto.gov" -> > > "Patents" -> "view in PAIR" -> "public PAIR". > > This database contains a complete history of the patent, including the > > correspondence with patent examiners, etc. > > Also, can you post the patent application number. > > > - outputlogic > > >http://outputlogic.com > > Hi OutputLogic, > Thank you for your information. > > I had searched the website before I posed this message and got the > error information: > "Sorry, the entered Application Number "10/718968" is not available. > The number may have been incorrectly typed, or assigned to an > application > that is not yet available for public inspection." > > I don't know why I got the error message. > > 10/718968 is available from reference literature in the invention: > "Programmable Logic Device Having Complex Logic Blocks with Improved > Logic Cell Functionality", patent number 7,394,287, by Alera from > following website:http://www.google.com/patents/about?id=3D5yyrAAAAEBAJ&d= q=3Dpatent:7394287... > > Weng 7,394,287 is the patent number. It works for me at the USPTO. What is the number you are searching for? RickArticle: 141294
Hi All,
I am having problems with a vendors XBD file. Specifically I
get the following error message:
ERROR:MDT - issued from TCL procedure "check_partno" line 21
DDR2_SDRAM (mpmc) -
The parameter C_MEM_PARTNO=EBE52UD6AJUA-6E-E is not found in the
memory
database.
ERROR:MDT - platgen failed with errors!
I understand that Xilinx tools do not know the "EBE52UD6AJUA-6E-E"
memory module. How do I fix this problem ? The module seems to
be described in the XBD file. What is the "memory database" the
message above refers to ?
Thanks,
rudi
Article: 141295Hi all, Would someone explain what is non-aligned- memory accesses please ? Thank you. Barme2iArticle: 141296
hassen Karray <barme2i@gmail.com> wrote: > Hi all, > > Would someone explain what is non-aligned- memory accesses please ? > > Thank you. Best person to ask is your teacher. He or she probably doesn't really want you to ask on a usenet group for you answer. NobbyArticle: 141297
On Jun 16, 3:55=A0am, hassen Karray <barm...@gmail.com> wrote: > Hi all, > > Would someone explain what is non-aligned- memory accesses please ? > > Thank you. > > Barme2i A non-aligned memory access is usually when a processor requests a multiple byte data word from an address that is not a multiple of the number of bytes (i.e. a long word access starting at an odd byte address). In the worst case, the data word requested may be less than the width of the data bus, but due to mis-alignment, it may span two transactions on that bus, which slows down the access. AndyArticle: 141298
On Jun 15, 9:25=A0pm, rickman <gnu...@gmail.com> wrote: > On Jun 15, 12:22=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote: > > > > > > > On Jun 15, 8:39=A0am, rickman <gnu...@gmail.com> wrote: > > > > On Jun 15, 10:13 am, Weng Tianxiang <wtx...@gmail.com> wrote: > > > > > On Jun 15, 4:36 am, rickman <gnu...@gmail.com> wrote: > > > > > > On Jun 14, 1:21 pm, Weng Tianxiang <wtx...@gmail.com> wrote: > > > > > > > Hi, > > > > > > I recently read Altera Stratix II, III and IV device handbook a= nd > > > > > > found its 3-bit addition circuit is really a genius invention. = But I > > > > > > was surprised to find that Altera patent application "Logic Cel= l > > > > > > Supporting Addition of Three Binary Words" filed on Nov. 21, 20= 03 has > > > > > > not been approved to be a patent so far today, even though many= Altera > > > > > > later patent applications based on the invention have been appr= oved > > > > > > for U.S. patents. > > > > > > > Is anyone knowledgable about the patent application willing to > > > > > > transfer the patent application context to me and disclose why = it > > > > > > hasn't been approved as a U.S. patent. > > > > > > > My guess is it may never be approved by U.S. Patent Office to b= e a > > > > > > patent, the reason is not its novelty violation, but its contex= t > > > > > > didn't disclose enough information about the 3-bit addition cir= cuit, a > > > > > > requirement for any patent application to be approved to be a U= .S. > > > > > > patent. At least those skilled in the art cannot get the idea w= hat is > > > > > > done within its circuit having an encircled '+' with 3 inputs a= nd 2 > > > > > > outputs. > > > > > > > Altera another sister patent application "Arithmetic Structure = is for > > > > > > Programmable Logic Device" filed on Oct. 23, 2003 has the same = fate. > > > > > > > Thank you. > > > > > > > Weng > > > > > > I don't know why Altera wouldn't disclose info on the structure b= eing > > > > > used in a device. =A0It is relatively inexpensive to reverse engi= neer a > > > > > chip, so if it is not disclosed in a patent, it is not protected = and > > > > > is vulnerable to being copied. > > > > > > What exactly *does* the patent claim? =A0Maybe the design inside = the > > > > > circled + is not really novel and only the design around the circ= le is > > > > > novel enough to be patented? > > > > > > In general, I think a three in put adder is *very useful*. =A0I'v= e never > > > > > seen such a circuit, I guess the carry chain has multiple bits, e= h? > > > > > > Rick- Hide quoted text - > > > > > > - Show quoted text - > > > > > Hi Rick, > > > > Here is a link to Stratix IV Device Handbook Volumn 1 and page 43 > > > > shows the invention circuit:http://www.altera.com/literature/hb/str= atix-iv/stx4_5v1.pdf > > > > > Why is it very useful? In the Stratix IV Device Handbook Volumn 1, = it > > > > describes two applications: multiplication and correlation function= . > > > > > Any other applications? With multiplier hardware structure speciall= y > > > > introduced in FPGA, is multiplication circuit still used for > > > > multiplication? > > > > Although they show the interconnections being used, they don't show > > > the logic implemented in the LUTs. =A0The carry from one bit to the n= ext > > > is done with two signals each of which has the same weight. =A0As far= as > > > I can tell, this is just a pair of cascaded adders, the first done in > > > the LUTs and the second done in dedicated hardware. =A0The only novel= ty > > > is that instead of adding two inputs with one adder chain (the LUTs) > > > and then adding the result to the third input with the dedicated > > > hardware chain, they add all three input bits using the LUTs and feed > > > both carry bits into the dedicated hardware chain which means the > > > carry chain always uses the fast, dedicated hardware. > > > > Does that sound like a patent worthy invention to you? =A0I don't rea= lly > > > know what is and what is not worthy of a patent. =A0But other patents > > > "based" on this patent will not be affected by the validity of this > > > patent. =A0Even if this patent is upheld, ***I*** could patent some > > > additional feature that uses this design as a starting point. =A0I ju= st > > > can't build it without permission from the patent holder of the > > > original design. =A0Still, this means he/she couldn't use my idea > > > without my permission either. > > > > Rick- Hide quoted text - > > > > - Show quoted text - > > > Hi Rick, > > There are two novel points there: > > 1. It transfers 3 adders into 2 adders which was described very clear: > > nobody before had invented that point. > > No, it is not 3 adders using 2 adders, it is always just 2 adders. > The only difference is that there is only one cascaded chain. =A0There > are two carries between each bit of the adder, sort of like a > "Propagate/Generate" style of carry, only one results in a chained > delay calculation. =A0But I don't see any real advantage to that. =A0I > think the real advantage of this circuit is that it takes advantage of > the large, 6 input LUT by breaking it into dual 4 input LUTs... but > wait, that is still wasting half the 6 input LUTs. =A0So it is really > just an optimization of their particular architecture. > > The only possible novelty here is that they are doing this in an > FPGA. > > > 2. Circuit is marked by circled '+' with 3 inputs and 2 outputs whose > > internal structure wasn't shown. > > Yep, that is because that part is not very patentable, in my opinion. > You don't put anything in a patent that is not patentable. =A0Anything > you don't explain in a patent is not part of it. > > > 3. I am sure there may be more than 20 claims in the application as > > Altera patent claim trandition goes. > > Sure, any patent attorney worth his salt is going to put as many > claims in as possible. =A0If I understand correctly any claim can stand > alone even if the others are struck down. > > Rick- Hide quoted text - > > - Show quoted text - Hi Rick, "No, it is not 3 adders using 2 adders, it is always just 2 adders. The only difference is that there is only one cascaded chain. There are two carries between each bit of the adder, sort of like a "Propagate/Generate" style of carry, only one results in a chained delay calculation. But I don't see any real advantage to that. I think the real advantage of this circuit is that it takes advantage of the large, 6 input LUT by breaking it into dual 4 input LUTs... but wait, that is still wasting half the 6 input LUTs. So it is really just an optimization of their particular architecture. The only possible novelty here is that they are doing this in an FPGA. " Thank you for your comments. You are right. I realized it after I posed the message and re-read other papers about 3:2 compressor and I didn't correct it myself.Article: 141299
On Jun 15, 9:41=A0pm, rickman <gnu...@gmail.com> wrote: > On Jun 15, 1:39=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote: > > > > > > > On Jun 15, 9:23=A0am, OutputLogic <evgen...@gmail.com> wrote: > > > > You can try to go to USPTO database and lookup the history of this > > > patent application. > > > It's not under the patent search, but under "http://www.uspto.gov" -> > > > "Patents" -> "view in PAIR" -> "public PAIR". > > > This database contains a complete history of the patent, including th= e > > > correspondence with patent examiners, etc. > > > Also, can you post the patent application number. > > > > - outputlogic > > > >http://outputlogic.com > > > Hi OutputLogic, > > Thank you for your information. > > > I had searched the website before I posed this message and got the > > error information: > > "Sorry, the entered Application Number "10/718968" is not available. > > The number may have been incorrectly typed, or assigned to an > > application > > that is not yet available for public inspection." > > > I don't know why I got the error message. > > > 10/718968 is available from reference literature in the invention: > > "Programmable Logic Device Having Complex Logic Blocks with Improved > > Logic Cell Functionality", patent number 7,394,287, by Alera from > > following website:http://www.google.com/patents/about?id=3D5yyrAAAAEBAJ= &dq=3Dpatent:7394287... > > > Weng > > 7,394,287 is the patent number. =A0It works for me at the USPTO. =A0What > is the number you are searching for? > > Rick- Hide quoted text - > > - Show quoted text - Hi Rick, I have tried to find the text and its drawings of patent application "Logic Cell Supporting Addition of Three Binary Words" filed on Nov. 21, 2003, US application number 10/718968, but it must pay to get its context from USPTO, even though it was in public domain about 6 years ago. Can you help get the context and drawings from USPTO for me? Weng
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