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Hi NG. Have anyone worked with the Cortex M1 Softcore processor and some kind of graphical user interface? Does the processor have enough processing power to control such a GUI (for example on a touch display) and still have enough power to address other computations? Kind RegardsArticle: 141301
Hi, Do you know how aggressive the patent fighting between Xilinx and Alters is going? I give you some tastes here. But I have to make a statement first: I don't have any internal personal relationships from neither companies and all information about the patent fighting is derived from the following patent I recently read: Patent number: 7,394, 287, "Programmable Logic Device Having Complex Logic Blocks with Improved Logic Cell Functionality" filed on May 21, 2007, by Altera. Here is the patent website: http://www.google.com/patents/about?id=5yyrAAAAEBAJ&dq=patent:7394287&as_drrb_ap=q&as_minm_ap=0&as_miny_ap=&as_maxm_ap=0&as_maxy_ap=&as_drrb_is=q&as_minm_is=0&as_miny_is=&as_maxm_is=0&as_maxy_is= The patent contexts are all about Xilinx circuitry, but it was filed by Altera so that O5 and O6 must be in their current status: O5 and O6 must share 5 inputs, eliminating the chance O6 can be figured with the 6th input, an easy point to make for Xilinx. All inventions in the patent are trivial in its ideas, but important for Xilinx architecture to further improve its efficiency. What does it mean? It means Altera has occupied a strategic high point to prevent Xilinx from further improving its Virtex V cell structure without avoiding its patent violations. The working price paid by Altera is minimum and its benifits to Altera in market competition are huge and tremendous. In another words, it is not exaggeratory to say that Altera hit a Superlotto in the market competition. I think both companies, #1 and #2, would establish, or have already established, a division to specially research main opponent's technology and file aggressive patents to avoid its improvements in the future. It is right and normal for fighters in battlefield to use minimum of force to get superiority in the market. That is why I would like to say the patent fighting between Xilinx and Altera is so aggressive that anyone having read the patent 7394287 would smell the powder of the fighting hanging in the air without any internal messages leaked from both companied. WengArticle: 141302
On Jun 12, 6:38=A0pm, -jg <Jim.Granvi...@gmail.com> wrote: > On Jun 13, 6:55=A0am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > > > > > Why does this post come on the day that broadcast analog NTSC > > is gone forever (in the US)? > > Perhaps: > a) The USA is only a small market > b) New Standards Conversion to NTSC is likely to be a major market > c) NTSC/PAL are going to exist in security/automotive cameras > =A0 =A0for a very long time. > > -jg One more point. More US TV viewers get their video from a cable than over the air. So the broadcast NTSC market is almost as big as it ever was, only now it's no longer wireless. Cheers, GaborArticle: 141303
On Jun 16, 9:34=A0am, Weng Tianxiang <wtx...@gmail.com> wrote: > On Jun 15, 9:41=A0pm, rickman <gnu...@gmail.com> wrote: > > > > > On Jun 15, 1:39=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote: > > > > On Jun 15, 9:23=A0am, OutputLogic <evgen...@gmail.com> wrote: > > > > > You can try to go to USPTO database and lookup the history of this > > > > patent application. > > > > It's not under the patent search, but under "http://www.uspto.gov" = -> > > > > "Patents" -> "view in PAIR" -> "public PAIR". > > > > This database contains a complete history of the patent, including = the > > > > correspondence with patent examiners, etc. > > > > Also, can you post the patent application number. > > > > > - outputlogic > > > > >http://outputlogic.com > > > > Hi OutputLogic, > > > Thank you for your information. > > > > I had searched the website before I posed this message and got the > > > error information: > > > "Sorry, the entered Application Number "10/718968" is not available. > > > The number may have been incorrectly typed, or assigned to an > > > application > > > that is not yet available for public inspection." > > > > I don't know why I got the error message. > > > > 10/718968 is available from reference literature in the invention: > > > "Programmable Logic Device Having Complex Logic Blocks with Improved > > > Logic Cell Functionality", patent number 7,394,287, by Alera from > > > following website:http://www.google.com/patents/about?id=3D5yyrAAAAEB= AJ&dq=3Dpatent:7394287... > > > > Weng > > > 7,394,287 is the patent number. =A0It works for me at the USPTO. =A0Wha= t > > is the number you are searching for? > > > Rick- Hide quoted text - > > > - Show quoted text - > > Hi Rick, > I have tried to find the text and its drawings of patent application > "Logic Cell > Supporting Addition of Three Binary Words" filed on Nov. 21, 2003, US > application number 10/718968, but it must pay to get its context from > USPTO, even though it was in public domain about 6 years ago. > > Can you help get the context and drawings from USPTO for me? > > Weng Where did you get the above info? That does not appear to be a valid document number. It needs to have 11 digits where the first four appear to be the year. I searched on "Three Binary Words" in the title and came up with nothing. I did search on this for patents and found this one which I think is interesting... maybe this is why the adder is just a plus sign with a circle... 4,783,757. Note that the owner is Intel, not Altera. Rick RickArticle: 141304
Dear friends, I am implementing a digital QPSK demodulator (Data rate is: 42.4515 MBps) with VHDL for realizing on FPGA. For this, I have developed the sub modules such as: (1- ) 16 bit Edge sensitive Phase-Frequency Detector (PFD) with up/down counter (2- ) 32 bit Numerically Controlled Oscillator (NCO) with 9 bit outputs for Sin/Cos generation at a scaling factor of 255 and reference clock is 125MHz . (3- ) FIR filters (In phase and Quad phase) with pass band frequency at 23MHz, stop band frequency at 30MHz and sampling frequency at 250 MHz. Sampling factor is 512. Input is 16 bit, Coefficient is 13 bit and output is 29 bits. (4- ) Loop filter for second order PLL with the tracking range of +- 400 KHz, critical damping at (0.707), Scaling factor for present input is 1 and for previous input is -0.09. Input is 29 bit, output is 32 bit. (5-) A simple adder of FIR_I and FIR_Q contents (6-) Integration of all these blocks with an additional clock gen block. I have simulated all the blocks individually before integration and I got the expected outputs. But, after integration, the results are not coming properly. My output signal’s frequency is not exactly tracking with the input frequency. It is coming as 2-3 times lower than the expected frequency. Once even if it acquired the lock, it is not holding. What might be the problem in integration? I got several doubts as follows: (1) What is the correct clock I have to give for an Up/down counter i.e., is it the data rate or is the same reference clock given for NCO or any other clock? Theoretically, how to analyze which clock has to be given for counting? Similarly for FIRs and loop filter? (2) Coefficients calculation for FIRs; is it w.r.t. 125MHz or any other high frequency or low frequency clock? (3) Loop filter design considerations: How to calculate the gain of PFD and NCO and the constraints of loop filter? (4) How to determine a lock? Is it just a compare or any other logic has to be used? (5) Is the inputs to PFD is the simple MSB bits of modulator o/p and the NCO o/p? Or whether I have to use all their 9 bits for comparison? (6) Whether any Bit sizes of up/down counter, coefficients, loop filter o/p, NCO frequency input and phase offset, etc..is affecting the final o/p? (7) Whether any default value has to be set initially under the NCO design? If so, which value? (8) How to check the spectral response of NCO (simulation results from Modelsim as a raw file to Mat lab)? Kindly guide me to solve the integration problem what I am facing………. Thanking you, Demod Proj team.Article: 141305
I am working on building a PC/104+ board with support for a 32 bit master target PCI interface. I want to be able to support the 32-bit 33MHz PCI bus at both 3.3V and 5.0V. I want to use the Altera PCI master/target IP core to support the PCI interface and connect it to my SOPC builder system through the Avalon memory mapped interface. I have read through Altera App Note 330, which talks about connecting 3.3V PCI devices to a 5.0V PCI Bus. ( http://www.altera.com/literature/an/an330.pdf ) I was wondering, if I use bus switches as suggested in AN330, do I need to run the banks on my Cyclone III configured for PCI style IO at 3.0V, with VCCIO at 3.0V, or should I configure these banks for 3.3V LVTTL style IO with VCCIO at 3.3V? Apparently the Cyclone III is a bit finicky with 3.3V IO and you have to be careful about overshoot. Normally if you want to connect the Cyclone III to a 3.3V PCI bus, you have to configure the connected IO pins to run at 3.0V PCI and run associated VCCIO rails at 3.0V. ( http://www.altera.com/support/kdb/solutions/rd01142008_525.html ) To switch between 3.3V PCI and 5.0V PCI, I think I can put a switch on the board to select either 5.0V or 3.3V to be connected as the reference input rail for my bus switches. Do you think this is a sound strategy? Another question for anyone who has experience with the Altera PCI IP core is this: Can the PCI 32-bit Master/Target IP core act as the host for other devices that I might wish to slave to it, for instance if I want to stack several PC/104+ boards on the board that I am building, can the Cyclone III act as master and control all the other boards on my PCI bus? I think I need to include a bunch of pullup resistors on many of my PCI control signal pins if I want to do this. Any comments here? Has anyone tried using the Opencores.org PCI master/target core? Have you had any success with it? thanks for the help...Article: 141306
On Jun 16, 8:51=A0am, rickman <gnu...@gmail.com> wrote: > On Jun 16, 9:34=A0am, Weng Tianxiang <wtx...@gmail.com> wrote: > > > > > > > On Jun 15, 9:41=A0pm, rickman <gnu...@gmail.com> wrote: > > > > On Jun 15, 1:39=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote: > > > > > On Jun 15, 9:23=A0am, OutputLogic <evgen...@gmail.com> wrote: > > > > > > You can try to go to USPTO database and lookup the history of thi= s > > > > > patent application. > > > > > It's not under the patent search, but under "http://www.uspto.gov= " -> > > > > > "Patents" -> "view in PAIR" -> "public PAIR". > > > > > This database contains a complete history of the patent, includin= g the > > > > > correspondence with patent examiners, etc. > > > > > Also, can you post the patent application number. > > > > > > - outputlogic > > > > > >http://outputlogic.com > > > > > Hi OutputLogic, > > > > Thank you for your information. > > > > > I had searched the website before I posed this message and got the > > > > error information: > > > > "Sorry, the entered Application Number "10/718968" is not available= . > > > > The number may have been incorrectly typed, or assigned to an > > > > application > > > > that is not yet available for public inspection." > > > > > I don't know why I got the error message. > > > > > 10/718968 is available from reference literature in the invention: > > > > "Programmable Logic Device Having Complex Logic Blocks with Improve= d > > > > Logic Cell Functionality", patent number 7,394,287, by Alera from > > > > following website:http://www.google.com/patents/about?id=3D5yyrAAAA= EBAJ&dq=3Dpatent:7394287... > > > > > Weng > > > > 7,394,287 is the patent number. =A0It works for me at the USPTO. =A0W= hat > > > is the number you are searching for? > > > > Rick- Hide quoted text - > > > > - Show quoted text - > > > Hi Rick, > > I have tried to find the text and its drawings of patent application > > "Logic Cell > > Supporting Addition of Three Binary Words" filed on Nov. 21, 2003, US > > application number 10/718968, but it must pay to get its context from > > USPTO, even though it was in public domain about 6 years ago. > > > Can you help get the context and drawings from USPTO for me? > > > Weng > > Where did you get the above info? =A0That does not appear to be a valid > document number. =A0It needs to have 11 digits where the first four > appear to be the year. > I searched on "Three Binary Words" in the title and came up with > nothing. > > I did search on this for patents and found this one which I think is > interesting... maybe this is why the adder is just a plus sign with a > circle... 4,783,757. =A0Note that the owner is Intel, not Altera. > > Rick > > Rick- Hide quoted text - > > - Show quoted text - Hi Rick, I got the number from the patent "Programmable Logic Device Having Complex Logic Blocks with Improved Logic Cell Functionality" in its page 1 under "Other publications". http://www.google.com/patents/about?id=3D5yyrAAAAEBAJ&dq=3Dpatent:7394287&a= s_drrb_ap=3Dq&as_minm_ap=3D0&as_miny_ap=3D&as_maxm_ap=3D0&as_maxy_ap=3D&as_= drrb_is=3Dq&as_minm_is=3D0&as_miny_is=3D&as_maxm_is=3D0&as_maxy_is=3D Here is an email I sent to USPTO for confirmation and its response: Hi, I want to research patent application"Logic Cell Supporting Addition of Three Binary Words." U.S. Application Number 10/718,968, filed November 21, 2003. It should have been published long ago and in public domain. Please tell how to find the patent application. Thank you. Weng Hello The status of the application is 93 /NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS. Thank you have a great day. Agent 31 I don't know what it means. WengArticle: 141307
On 16 =D0=B8=D1=8E=D0=BD, 20:26, "demod" <projde...@yahoo.com> wrote: > Dear friends, > > I am implementing a digital QPSK demodulator (Data rate is: 42.4515 MBps) > with VHDL for realizing on FPGA. =C2=A0For this, I have developed the sub > modules such as: > > (1- ) 16 bit Edge sensitive Phase-Frequency Detector (PFD) with up/down > counter > (2- ) 32 bit Numerically Controlled Oscillator (NCO) with 9 bit outputs > for Sin/Cos generation at a scaling factor of 255 and reference clock is > 125MHz . > (3- ) FIR filters (In phase and Quad phase) with pass band frequency at > 23MHz, stop band frequency at 30MHz and sampling frequency at 250 MHz. > Sampling factor is 512. > Input is 16 bit, Coefficient is 13 bit and output is 29 bits. > (4- ) Loop filter for second order PLL with the tracking range of +- 400 > KHz, critical damping at (0.707), Scaling factor for present input is 1 a= nd > for previous input is -0.09. Input is 29 bit, output is 32 bit. > (5-) A simple adder of FIR_I and FIR_Q contents > (6-) Integration of all these blocks with an additional clock gen block. > > I have simulated all the blocks individually before integration and I got > the expected outputs. But, after integration, the results are not coming > properly. My output signal=E2=80=99s frequency is not exactly tracking wi= th the > input frequency. It is coming as 2-3 times lower than the expected > frequency. Once even if it acquired the lock, it is not holding. What mig= ht > be the problem in integration? > > I got several doubts as follows: > (1) What is the correct clock I have to give for an Up/down counter i.e., > is it the data rate or is the same reference clock given for NCO or any > other clock? Theoretically, how to analyze which clock has to be given fo= r > counting? Similarly for FIRs and loop filter? > (2) Coefficients calculation for FIRs; is it w.r.t. 125MHz or any other > high frequency or low frequency clock? > (3) Loop filter design considerations: How to calculate the gain of PFD > and NCO and the constraints of loop filter? > (4) How to determine a lock? Is it just a compare or any other logic has > to be used? > (5) Is the inputs to PFD is the simple MSB bits of modulator o/p and the > NCO o/p? Or whether I have to use all their 9 bits for comparison? > (6) Whether any Bit sizes of up/down counter, coefficients, loop filter > o/p, NCO frequency input and phase offset, etc..is affecting the final > o/p? > (7) Whether any default value has to be set initially under the NCO > design? If so, which value? > (8) =C2=A0How to check the spectral response of NCO (simulation results f= rom > Modelsim as a raw file to Mat lab)? > Kindly guide me to solve the integration problem what I am > facing=E2=80=A6=E2=80=A6=E2=80=A6. > > Thanking you, > Demod Proj team. You need try to see on all sensivity list in all process in your code. Then try to undestend where you use falling and rising edge of clock and can you use it in your chip. Then you need find and think about assinhronius resets that you use. And then you need cut all project on parts and implement it step by step. For find clocks and other you need use test pins and program like ChipScope (like I undestend you use Xilinx) Best Regards, IvanArticle: 141308
Not Altera, at least not yet, but you can see the bus switch technique on a range of our boards - Hollybush1, Hollybush2, Raggedstone1 and so on. Generally running the I/O at 3.3V is good enough for 3V3 and 5V signalling.. Bias the bus switches are the right point and you don't need to switch anything. On Opencores we have a number of customers apparently doing ok with it. John Adair Enterpoint Ltd. On 16 June, 18:38, wallge <wal...@gmail.com> wrote: > I am working on building a PC/104+ board with support for a 32 bit > master target PCI interface. I want to be able to support the 32-bit > 33MHz PCI bus at both 3.3V and 5.0V. I want to use the Altera PCI > master/target IP core to support the PCI interface and connect it to > my SOPC builder system through the Avalon memory mapped interface. > > I have read through Altera App Note 330, which talks about connecting > 3.3V PCI devices to a 5.0V PCI Bus. > (http://www.altera.com/literature/an/an330.pdf) > > I was wondering, if I use bus switches as suggested in AN330, do I > need to run the banks on my Cyclone III configured for PCI style IO at > 3.0V, with VCCIO at 3.0V, or should I configure these banks for 3.3V > LVTTL style IO with VCCIO at 3.3V? > > Apparently the Cyclone III is a bit finicky with 3.3V IO and you have > to be careful about overshoot. Normally if you want to connect the > Cyclone III to a 3.3V PCI bus, you have to configure the connected IO > pins to run at 3.0V PCI and run associated VCCIO rails at 3.0V. > (http://www.altera.com/support/kdb/solutions/rd01142008_525.html) > > To switch between 3.3V PCI and 5.0V PCI, I think I can put a switch on > the board to select either 5.0V or 3.3V to be connected as the > reference input rail for my bus switches. Do you think this is a sound > strategy? > > Another question for anyone who has experience with the Altera PCI IP > core is this: Can the PCI 32-bit Master/Target IP core act as the host > for other devices that I might wish to slave to it, for instance if I > want to stack several PC/104+ boards on the board that I am building, > can the Cyclone III act as master and control all the other boards on > my PCI bus? I think I need to include a bunch of pullup resistors on > many of my PCI control signal pins if I want to do this. Any comments > here? > > Has anyone tried using the Opencores.org PCI master/target core? Have > you had any success with it? > > thanks for the help...Article: 141309
Weng Tianxiang wrote: > On Jun 16, 8:51 am, rickman <gnu...@gmail.com> wrote: >> On Jun 16, 9:34 am, Weng Tianxiang <wtx...@gmail.com> wrote: >> >> >> >> >> >>> On Jun 15, 9:41 pm, rickman <gnu...@gmail.com> wrote: >>>> On Jun 15, 1:39 pm, Weng Tianxiang <wtx...@gmail.com> wrote: >>>>> On Jun 15, 9:23 am, OutputLogic <evgen...@gmail.com> wrote: >>>>>> You can try to go to USPTO database and lookup the history of this >>>>>> patent application. >>>>>> It's not under the patent search, but under "http://www.uspto.gov" -> >>>>>> "Patents" -> "view in PAIR" -> "public PAIR". >>>>>> This database contains a complete history of the patent, including the >>>>>> correspondence with patent examiners, etc. >>>>>> Also, can you post the patent application number. >>>>>> - outputlogic >>>>>> http://outputlogic.com >>>>> Hi OutputLogic, >>>>> Thank you for your information. >>>>> I had searched the website before I posed this message and got the >>>>> error information: >>>>> "Sorry, the entered Application Number "10/718968" is not available. >>>>> The number may have been incorrectly typed, or assigned to an >>>>> application >>>>> that is not yet available for public inspection." >>>>> I don't know why I got the error message. >>>>> 10/718968 is available from reference literature in the invention: >>>>> "Programmable Logic Device Having Complex Logic Blocks with Improved >>>>> Logic Cell Functionality", patent number 7,394,287, by Alera from >>>>> following website:http://www.google.com/patents/about?id=5yyrAAAAEBAJ&dq=patent:7394287... >>>>> Weng >>>> 7,394,287 is the patent number. It works for me at the USPTO. What >>>> is the number you are searching for? >>>> Rick- Hide quoted text - >>>> - Show quoted text - >>> Hi Rick, >>> I have tried to find the text and its drawings of patent application >>> "Logic Cell >>> Supporting Addition of Three Binary Words" filed on Nov. 21, 2003, US >>> application number 10/718968, but it must pay to get its context from >>> USPTO, even though it was in public domain about 6 years ago. >>> Can you help get the context and drawings from USPTO for me? >>> Weng >> Where did you get the above info? That does not appear to be a valid >> document number. It needs to have 11 digits where the first four >> appear to be the year. >> I searched on "Three Binary Words" in the title and came up with >> nothing. >> >> I did search on this for patents and found this one which I think is >> interesting... maybe this is why the adder is just a plus sign with a >> circle... 4,783,757. Note that the owner is Intel, not Altera. >> >> Rick >> >> Rick- Hide quoted text - >> >> - Show quoted text - > > Hi Rick, > I got the number from the patent "Programmable Logic Device Having > Complex Logic Blocks with Improved Logic Cell Functionality" > in its page 1 under "Other publications". > http://www.google.com/patents/about?id=5yyrAAAAEBAJ&dq=patent:7394287&as_drrb_ap=q&as_minm_ap=0&as_miny_ap=&as_maxm_ap=0&as_maxy_ap=&as_drrb_is=q&as_minm_is=0&as_miny_is=&as_maxm_is=0&as_maxy_is= > > Here is an email I sent to USPTO for confirmation and its response: > Hi, > I want to research patent application"Logic Cell Supporting Addition > of Three Binary Words." U.S. Application Number 10/718,968, filed > November 21, 2003. > > It should have been published long ago and in public domain. > > Please tell how to find the patent application. > > Thank you. > > Weng > > Hello > > The status of the application is > 93 /NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF > PUBLICATIONS. > Thank you have a great day. Agent 31 > > I don't know what it means. > > Weng I'm confused: the Google page you linked to has a "Download PDF" button which gets you the full 19 page patient. There's also a link for "View patient at USPTO" which takes you directly to the page for patient number 7,394,287 at the USPTO site. So what is it that you're looking for? ChrisArticle: 141310
Chris Abele wrote: > Weng Tianxiang wrote: >> On Jun 16, 8:51 am, rickman <gnu...@gmail.com> wrote: >>> On Jun 16, 9:34 am, Weng Tianxiang <wtx...@gmail.com> wrote: >>> >>> >>> >>> >>> >>>> On Jun 15, 9:41 pm, rickman <gnu...@gmail.com> wrote: >>>>> On Jun 15, 1:39 pm, Weng Tianxiang <wtx...@gmail.com> wrote: >>>>>> On Jun 15, 9:23 am, OutputLogic <evgen...@gmail.com> wrote: >>>>>>> You can try to go to USPTO database and lookup the history of this >>>>>>> patent application. >>>>>>> It's not under the patent search, but under >>>>>>> "http://www.uspto.gov" -> >>>>>>> "Patents" -> "view in PAIR" -> "public PAIR". >>>>>>> This database contains a complete history of the patent, >>>>>>> including the >>>>>>> correspondence with patent examiners, etc. >>>>>>> Also, can you post the patent application number. >>>>>>> - outputlogic >>>>>>> http://outputlogic.com >>>>>> Hi OutputLogic, >>>>>> Thank you for your information. >>>>>> I had searched the website before I posed this message and got the >>>>>> error information: >>>>>> "Sorry, the entered Application Number "10/718968" is not available. >>>>>> The number may have been incorrectly typed, or assigned to an >>>>>> application >>>>>> that is not yet available for public inspection." >>>>>> I don't know why I got the error message. >>>>>> 10/718968 is available from reference literature in the invention: >>>>>> "Programmable Logic Device Having Complex Logic Blocks with Improved >>>>>> Logic Cell Functionality", patent number 7,394,287, by Alera from >>>>>> following >>>>>> website:http://www.google.com/patents/about?id=5yyrAAAAEBAJ&dq=patent:7394287... >>>>>> >>>>>> Weng >>>>> 7,394,287 is the patent number. It works for me at the USPTO. What >>>>> is the number you are searching for? >>>>> Rick- Hide quoted text - >>>>> - Show quoted text - >>>> Hi Rick, >>>> I have tried to find the text and its drawings of patent application >>>> "Logic Cell >>>> Supporting Addition of Three Binary Words" filed on Nov. 21, 2003, US >>>> application number 10/718968, but it must pay to get its context from >>>> USPTO, even though it was in public domain about 6 years ago. >>>> Can you help get the context and drawings from USPTO for me? >>>> Weng >>> Where did you get the above info? That does not appear to be a valid >>> document number. It needs to have 11 digits where the first four >>> appear to be the year. >>> I searched on "Three Binary Words" in the title and came up with >>> nothing. >>> >>> I did search on this for patents and found this one which I think is >>> interesting... maybe this is why the adder is just a plus sign with a >>> circle... 4,783,757. Note that the owner is Intel, not Altera. >>> >>> Rick >>> >>> Rick- Hide quoted text - >>> >>> - Show quoted text - >> >> Hi Rick, >> I got the number from the patent "Programmable Logic Device Having >> Complex Logic Blocks with Improved Logic Cell Functionality" >> in its page 1 under "Other publications". >> http://www.google.com/patents/about?id=5yyrAAAAEBAJ&dq=patent:7394287&as_drrb_ap=q&as_minm_ap=0&as_miny_ap=&as_maxm_ap=0&as_maxy_ap=&as_drrb_is=q&as_minm_is=0&as_miny_is=&as_maxm_is=0&as_maxy_is= >> >> >> Here is an email I sent to USPTO for confirmation and its response: >> Hi, >> I want to research patent application"Logic Cell Supporting Addition >> of Three Binary Words." U.S. Application Number 10/718,968, filed >> November 21, 2003. >> >> It should have been published long ago and in public domain. >> >> Please tell how to find the patent application. >> >> Thank you. >> >> Weng >> >> Hello >> >> The status of the application is >> 93 /NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF >> PUBLICATIONS. >> Thank you have a great day. Agent 31 >> >> I don't know what it means. >> >> Weng > > I'm confused: the Google page you linked to has a "Download PDF" button > which gets you the full 19 page patient. There's also a link for "View > patient at USPTO" which takes you directly to the page for patient > number 7,394,287 at the USPTO site. So what is it that you're looking for? > > Chris Ignore that post - I see now. The patient application that you're looking for is referenced in the one you pointed to. (Note to self - engage brain before pushing send.)Article: 141311
On Jun 16, 7:02=A0pm, Chris Abele <ccab...@yahoo.com> wrote: > Weng Tianxiang wrote: > > On Jun 16, 8:51 am, rickman <gnu...@gmail.com> wrote: > >> On Jun 16, 9:34 am, Weng Tianxiang <wtx...@gmail.com> wrote: > > >>> On Jun 15, 9:41 pm, rickman <gnu...@gmail.com> wrote: > >>>> On Jun 15, 1:39 pm, Weng Tianxiang <wtx...@gmail.com> wrote: > >>>>> On Jun 15, 9:23 am, OutputLogic <evgen...@gmail.com> wrote: > >>>>>> You can try to go to USPTO database and lookup the history of this > >>>>>> patent application. > >>>>>> It's not under the patent search, but under "http://www.uspto.gov"= -> > >>>>>> "Patents" -> "view in PAIR" -> "public PAIR". > >>>>>> This database contains a complete history of the patent, including= the > >>>>>> correspondence with patent examiners, etc. > >>>>>> Also, can you post the patent application number. > >>>>>> - outputlogic > >>>>>>http://outputlogic.com > >>>>> Hi OutputLogic, > >>>>> Thank you for your information. > >>>>> I had searched the website before I posed this message and got the > >>>>> error information: > >>>>> "Sorry, the entered Application Number "10/718968" is not available= . > >>>>> The number may have been incorrectly typed, or assigned to an > >>>>> application > >>>>> that is not yet available for public inspection." > >>>>> I don't know why I got the error message. > >>>>> 10/718968 is available from reference literature in the invention: > >>>>> "Programmable Logic Device Having Complex Logic Blocks with Improve= d > >>>>> Logic Cell Functionality", patent number 7,394,287, by Alera from > >>>>> following website:http://www.google.com/patents/about?id=3D5yyrAAAA= EBAJ&dq=3Dpatent:7394287... > >>>>> Weng > >>>> 7,394,287 is the patent number. =A0It works for me at the USPTO. =A0= What > >>>> is the number you are searching for? > >>>> Rick- Hide quoted text - > >>>> - Show quoted text - > >>> Hi Rick, > >>> I have tried to find the text and its drawings of patent application > >>> "Logic Cell > >>> Supporting Addition of Three Binary Words" filed on Nov. 21, 2003, US > >>> application number 10/718968, but it must pay to get its context from > >>> USPTO, even though it was in public domain about 6 years ago. > >>> Can you help get the context and drawings from USPTO for me? > >>> Weng > >> Where did you get the above info? =A0That does not appear to be a vali= d > >> document number. =A0It needs to have 11 digits where the first four > >> appear to be the year. > >> I searched on "Three Binary Words" in the title and came up with > >> nothing. > > >> I did search on this for patents and found this one which I think is > >> interesting... maybe this is why the adder is just a plus sign with a > >> circle... 4,783,757. =A0Note that the owner is Intel, not Altera. > > >> Rick > > >> Rick- Hide quoted text - > > >> - Show quoted text - > > > Hi Rick, > > I got the number from the patent "Programmable Logic Device Having > > Complex Logic Blocks with Improved Logic Cell Functionality" > > in its page 1 under "Other publications". > >http://www.google.com/patents/about?id=3D5yyrAAAAEBAJ&dq=3Dpatent:739428= 7... > > > Here is an email I sent to USPTO for confirmation and its response: > > Hi, > > I want to research patent application"Logic Cell Supporting Addition > > of Three Binary Words." U.S. Application Number 10/718,968, filed > > November 21, 2003. > > > It should have been published long ago and in public domain. > > > Please tell how to find the patent application. > > > Thank you. > > > Weng > > > Hello > > > The status of the application is > > 93 /NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF > > PUBLICATIONS. > > Thank you have a great day. Agent 31 > > > I don't know what it means. > > > Weng > > I'm confused: the Google page you linked to has a "Download PDF" button > which gets you the full 19 page patient. =A0There's also a link for "View > patient at USPTO" which takes you directly to the page for patient > number 7,394,287 at the USPTO site. =A0So what is it that you're looking = for? > > Chris- Hide quoted text - > > - Show quoted text - Hi Chris, You have to download full patent papers to get the idea that the patent application "Logic Cell Supproting Addition of Three Binary Words" has not been approved for last 6.5 years. In the link I listed there is no the reference about the patent application. When you download the patent 7,394,287, in its page 1 there is an item named "OTHER PUBLICATION". The first paper listed under the item is the patent application "Logic Cell Supproting Addition of Three Binary Words" which applied on November 21, 2003 from where I've learned that the "Logic Cell Supproting Addition of Three Binary Words" has not been approved for last 6.5 years after I searched for the patent application name through USPTO patent website. WengArticle: 141312
With the CycloneIIIs you have to be careful that any 3.3V interfaces don't overshoot but using the bus switch (I've used IDT quickswitches) should reduce the overshoot risk. As John says 3.3V output should be OK with 5V PCI because the 5V signalling Vih is 2.0V NialArticle: 141313
Don't they all have cross licensing agreements in place? JonArticle: 141314
On Jun 17, 4:03=A0am, Jon <j...@beniston.com> wrote: > Don't they all have cross licensing agreements in place? > > Jon Hi Jon, I don't think so. FPGA industry is different from CPU industry where Intel and AMD have known patent exchange agreements. Xilinx and Altera fought 7 years in the 1990s' for the FPGA first patent rights owned by Xilinx, (as you may know Xilinx is the birthplace of FPGA industry), but finally Altera won, it means Altera didn't give any compensation money to Xilinx which I heard from a Xilinx field engineer. WengArticle: 141315
Please note that on or around July 15, 2009, AT&T will no longer be offering access to the Usenet Netnews service. If you wish to continue reading Usenet newsgroups, access is available through third-party vendors. http://support.att.net/usenet Distribution: AT&T SouthEast Newsgroups ServersArticle: 141316
On Jun 17, 9:16=A0am, Weng Tianxiang <wtx...@gmail.com> wrote: > On Jun 17, 4:03=A0am, Jon <j...@beniston.com> wrote: > > > Don't they all have cross licensing agreements in place? > > > Jon > > Hi Jon, > I don't think so. FPGA industry is different from CPU industry where > Intel and AMD have known patent exchange agreements. > > Xilinx and Altera fought 7 years in the 1990s' for the FPGA first > patent rights owned by Xilinx, (as you may know Xilinx is the > birthplace of FPGA industry), but finally Altera won, it means Altera > didn't give any compensation money to Xilinx which I heard from a > Xilinx field engineer. > > Weng I'd be very surprised if they had no cross-licensing at all. Competing vendors often "trade" patent licenses. Xilinx may have something Altera wants, and Altera may have something Xilinx wants, so they trade licenses. AndyArticle: 141317
On Jun 17, 7:31=A0am, Andy <jonesa...@comcast.net> wrote: > On Jun 17, 9:16=A0am, Weng Tianxiang <wtx...@gmail.com> wrote: > > > > > > > On Jun 17, 4:03=A0am, Jon <j...@beniston.com> wrote: > > > > Don't they all have cross licensing agreements in place? > > > > Jon > > > Hi Jon, > > I don't think so. FPGA industry is different from CPU industry where > > Intel and AMD have known patent exchange agreements. > > > Xilinx and Altera fought 7 years in the 1990s' for the FPGA first > > patent rights owned by Xilinx, (as you may know Xilinx is the > > birthplace of FPGA industry), but finally Altera won, it means Altera > > didn't give any compensation money to Xilinx which I heard from a > > Xilinx field engineer. > > > Weng > > I'd be very surprised if they had no cross-licensing at all. Competing > vendors often "trade" patent licenses. Xilinx may have something > Altera wants, and Altera may have something Xilinx wants, so they > trade licenses. > > Andy- Hide quoted text - > > - Show quoted text - Hi Andy, No. Can you point out any technique in current most advanced or most obsolete FPGA products commonly shared by Xilinx and Altera? except lookup table. WengArticle: 141318
PCI is an open termination bus which is capable of huge overshoots. The PCI spec requires 3.3V parts to have clamp diodes. Many of the manufacturers fail to comply with this requirement. I don't know about Altera. Take a look at the following Xilinx appnote about PCI compliancy. You might find it useful... http://www.xilinx.com/support/documentation/application_notes/xapp311.pdf /Mikhail "wallge" <wallge@gmail.com> wrote in message news:9817eec3-e820-4ce7-ab9d-a01fcefa4cf4@h2g2000yqg.googlegroups.com... >I am working on building a PC/104+ board with support for a 32 bit > master target PCI interface. I want to be able to support the 32-bit > 33MHz PCI bus at both 3.3V and 5.0V. I want to use the Altera PCI > master/target IP core to support the PCI interface and connect it to > my SOPC builder system through the Avalon memory mapped interface. > > I have read through Altera App Note 330, which talks about connecting > 3.3V PCI devices to a 5.0V PCI Bus. > ( http://www.altera.com/literature/an/an330.pdf ) > > I was wondering, if I use bus switches as suggested in AN330, do I > need to run the banks on my Cyclone III configured for PCI style IO at > 3.0V, with VCCIO at 3.0V, or should I configure these banks for 3.3V > LVTTL style IO with VCCIO at 3.3V? > > Apparently the Cyclone III is a bit finicky with 3.3V IO and you have > to be careful about overshoot. Normally if you want to connect the > Cyclone III to a 3.3V PCI bus, you have to configure the connected IO > pins to run at 3.0V PCI and run associated VCCIO rails at 3.0V. > ( http://www.altera.com/support/kdb/solutions/rd01142008_525.html ) > > To switch between 3.3V PCI and 5.0V PCI, I think I can put a switch on > the board to select either 5.0V or 3.3V to be connected as the > reference input rail for my bus switches. Do you think this is a sound > strategy? > > Another question for anyone who has experience with the Altera PCI IP > core is this: Can the PCI 32-bit Master/Target IP core act as the host > for other devices that I might wish to slave to it, for instance if I > want to stack several PC/104+ boards on the board that I am building, > can the Cyclone III act as master and control all the other boards on > my PCI bus? I think I need to include a bunch of pullup resistors on > many of my PCI control signal pins if I want to do this. Any comments > here? > > Has anyone tried using the Opencores.org PCI master/target core? Have > you had any success with it? > > thanks for the help...Article: 141319
On Jun 17, 10:16=A0am, "MM" <mb...@yahoo.com> wrote: > PCI is an open termination bus which is capable of huge overshoots. The P= CI > spec requires 3.3V parts to have clamp diodes. Many of the manufacturers > fail to comply with this requirement. I don't know about Altera. Take a l= ook > at the following Xilinx appnote about PCI compliancy. You might find it > useful...http://www.xilinx.com/support/documentation/application_notes/xa= pp311... > > /Mikhail > > "wallge" <wal...@gmail.com> wrote in message > > news:9817eec3-e820-4ce7-ab9d-a01fcefa4cf4@h2g2000yqg.googlegroups.com... > > >I am working on building a PC/104+ board with support for a 32 bit > > master target PCI interface. I want to be able to support the 32-bit > > 33MHz PCI bus at both 3.3V and 5.0V. I want to use the Altera PCI > > master/target IP core to support the PCI interface and connect it to > > my SOPC builder system through the Avalon memory mapped interface. > > > I have read through Altera App Note 330, which talks about connecting > > 3.3V PCI devices to a 5.0V PCI Bus. > > (http://www.altera.com/literature/an/an330.pdf) > > > I was wondering, if I use bus switches as suggested in AN330, do I > > need to run the banks on my Cyclone III configured for PCI style IO at > > 3.0V, with VCCIO at 3.0V, or should I configure these banks for 3.3V > > LVTTL style IO with VCCIO at 3.3V? > > > Apparently the Cyclone III is a bit finicky with 3.3V IO and you have > > to be careful about overshoot. Normally if you want to connect the > > Cyclone III to a 3.3V PCI bus, you have to configure the connected IO > > pins to run at 3.0V PCI and run associated VCCIO rails at 3.0V. > > (http://www.altera.com/support/kdb/solutions/rd01142008_525.html) > > > To switch between 3.3V PCI and 5.0V PCI, I think I can put a switch on > > the board to select either 5.0V or 3.3V to be connected as the > > reference input rail for my bus switches. Do you think this is a sound > > strategy? > > > Another question for anyone who has experience with the Altera PCI IP > > core is this: Can the PCI 32-bit Master/Target IP core act as the host > > for other devices that I might wish to slave to it, for instance if I > > want to stack several PC/104+ boards on the board that I am building, > > can the Cyclone III act as master and control all the other boards on > > my PCI bus? I think I need to include a bunch of pullup resistors on > > many of my PCI control signal pins if I want to do this. Any comments > > here? > > > Has anyone tried using the Opencores.org PCI master/target core? Have > > you had any success with it? > > > thanks for the help... In theory, Cyclone III's have PCI clamp diodes on general purpose I/O pins (specifically NOT on dedicated clock inputs or repurposed programming pins). However, I'm not sure I would trust them on a live bus, so I'd still put the clamping diodes in. The diodes do add a bit to the board size, but are probably worth it for the protection they offer. If you are putting in bus switches, you might go ahead and specify a local side of 2.5V - Altera has pretty much stated that they don't recommend using 3.3V I/O for the Cyclone III.Article: 141320
On Jun 17, 1:30=A0pm, radarman <jsham...@gmail.com> wrote: > On Jun 17, 10:16=A0am, "MM" <mb...@yahoo.com> wrote: > > > > > PCI is an open termination bus which is capable of huge overshoots. The= PCI > > spec requires 3.3V parts to have clamp diodes. Many of the manufacturer= s > > fail to comply with this requirement. I don't know about Altera. Take a= look > > at the following Xilinx appnote about PCI compliancy. You might find it > > useful...http://www.xilinx.com/support/documentation/application_notes/= xapp311... > > > /Mikhail > > > "wallge" <wal...@gmail.com> wrote in message > > >news:9817eec3-e820-4ce7-ab9d-a01fcefa4cf4@h2g2000yqg.googlegroups.com... > > > >I am working on building a PC/104+ board with support for a 32 bit > > > master target PCI interface. I want to be able to support the 32-bit > > > 33MHz PCI bus at both 3.3V and 5.0V. I want to use the Altera PCI > > > master/target IP core to support the PCI interface and connect it to > > > my SOPC builder system through the Avalon memory mapped interface. > > > > I have read through Altera App Note 330, which talks about connecting > > > 3.3V PCI devices to a 5.0V PCI Bus. > > > (http://www.altera.com/literature/an/an330.pdf) > > > > I was wondering, if I use bus switches as suggested in AN330, do I > > > need to run the banks on my Cyclone III configured for PCI style IO a= t > > > 3.0V, with VCCIO at 3.0V, or should I configure these banks for 3.3V > > > LVTTL style IO with VCCIO at 3.3V? > > > > Apparently the Cyclone III is a bit finicky with 3.3V IO and you have > > > to be careful about overshoot. Normally if you want to connect the > > > Cyclone III to a 3.3V PCI bus, you have to configure the connected IO > > > pins to run at 3.0V PCI and run associated VCCIO rails at 3.0V. > > > (http://www.altera.com/support/kdb/solutions/rd01142008_525.html) > > > > To switch between 3.3V PCI and 5.0V PCI, I think I can put a switch o= n > > > the board to select either 5.0V or 3.3V to be connected as the > > > reference input rail for my bus switches. Do you think this is a soun= d > > > strategy? > > > > Another question for anyone who has experience with the Altera PCI IP > > > core is this: Can the PCI 32-bit Master/Target IP core act as the hos= t > > > for other devices that I might wish to slave to it, for instance if I > > > want to stack several PC/104+ boards on the board that I am building, > > > can the Cyclone III act as master and control all the other boards on > > > my PCI bus? I think I need to include a bunch of pullup resistors on > > > many of my PCI control signal pins if I want to do this. Any comments > > > here? > > > > Has anyone tried using the Opencores.org PCI master/target core? Have > > > you had any success with it? > > > > thanks for the help... > > In theory, Cyclone III's have PCI clamp diodes on general purpose I/O > pins (specifically NOT on dedicated clock inputs or repurposed > programming pins). However, I'm not sure I would trust them on a live > bus, so I'd still put the clamping diodes in. The diodes do add a bit > to the board size, but are probably worth it for the protection they > offer. If you are putting in bus switches, you might go ahead and > specify a local side of 2.5V - Altera has pretty much stated that they > don't recommend using 3.3V I/O for the Cyclone III. Altera Support told me that if I was going to use the bus switches I would still need to configure the connected cyclone III banks for 3.0V PCI which means using the onboard clamp diodes. I would also have to set the associated VCCIOs at 3.0V. One thing I was wondering about with the bus switches: I want to be able to interface with standard 3.3V PCI as well as 5.0V PCI. I believe I cannot do both at the same time, so it is either one or the other. Can I just put a switch on my board that will connect either 3.3V ref or 5V ref to the bus switches to determine which mode I am in? I don't want to be in 5V mode all the time, because if I want to master a 3.3V peripheral PCI device, 5V PCI signaling might burn up the peripheral. Anyone have any thoughts here?Article: 141321
On Tue, 16 Jun 2009 07:10:05 -0700 (PDT), Weng Tianxiang <wtxwtx@gmail.com> wrote: |Hi, |Do you know how aggressive the patent fighting between Xilinx and |Alters is going? | |I give you some tastes here. But I have to make a statement first: I |don't have any internal personal relationships from neither companies |and all information about the patent fighting is derived from the |following patent I recently read: |Patent number: 7,394, 287, "Programmable Logic Device Having Complex |Logic Blocks with Improved Logic Cell Functionality" filed on May 21, |2007, by Altera. | |Here is the patent website: |http://www.google.com/patents/about?id=5yyrAAAAEBAJ&dq=patent:7394287&as_drrb_ap=q&as_minm_ap=0&as_miny_ap=&as_maxm_ap=0&as_maxy_ap=&as_drrb_is=q&as_minm_is=0&as_miny_is=&as_maxm_is=0&as_maxy_is= | |The patent contexts are all about Xilinx circuitry, but it was filed |by Altera so that O5 and O6 must be in their current status: O5 and O6 |must share 5 inputs, eliminating the chance O6 can be figured with the |6th input, an easy point to make for Xilinx. All inventions in the |patent are trivial in its ideas, but important for Xilinx architecture |to further improve its efficiency. | |What does it mean? | |It means Altera has occupied a strategic high point to prevent Xilinx |from further improving its Virtex V cell structure without avoiding |its patent violations. The working price paid by Altera is minimum and |its benifits to Altera in market competition are huge and tremendous. |In another words, it is not exaggeratory to say that Altera hit a |Superlotto in the market competition. | |I think both companies, #1 and #2, would establish, or have already |established, a division to specially research main opponent's |technology and file aggressive patents to avoid its improvements in |the future. | |It is right and normal for fighters in battlefield to use minimum of |force to get superiority in the market. | |That is why I would like to say the patent fighting between Xilinx and |Altera is so aggressive that anyone having read the patent 7394287 |would smell the powder of the fighting hanging in the air without any |internal messages leaked from both companied. | |Weng | | |============ It is not uncommon to imrove or try to circumvent another companies patents. In doing an improvement or include an area not covered by another's patent you do have to reference that patent to explain why your invention is different and improves on an existing patent. patents are a lifeline for companies. They are desired as much as gold. jamesArticle: 141322
Weng Tianxiang wrote: > On Jun 17, 4:03 am, Jon <j...@beniston.com> wrote: >> Don't they all have cross licensing agreements in place? >> >> Jon > > Hi Jon, > I don't think so. FPGA industry is different from CPU industry where > Intel and AMD have known patent exchange agreements. > > Xilinx and Altera fought 7 years in the 1990s' for the FPGA first > patent rights owned by Xilinx, (as you may know Xilinx is the > birthplace of FPGA industry), but finally Altera won, it means Altera > didn't give any compensation money to Xilinx which I heard from a > Xilinx field engineer. > > Weng Altera paid Xilinx $20M to settle the patent litigation back in July 2001. The agreement include a patent cross license. http://www.altera.com/corporate/news_room/releases/releases_archive/2001/corporate_partners/pr-corp0718_release.html Ed McGettigan -- Xilinx Inc.Article: 141323
On Jun 17, 3:53=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > Weng Tianxiang wrote: > > On Jun 17, 4:03 am, Jon <j...@beniston.com> wrote: > >> Don't they all have cross licensing agreements in place? > > >> Jon > > > Hi Jon, > > I don't think so. FPGA industry is different from CPU industry where > > Intel and AMD have known patent exchange agreements. > > > Xilinx and Altera fought 7 years in the 1990s' for the FPGA first > > patent rights owned by Xilinx, (as you may know Xilinx is the > > birthplace of FPGA industry), but finally Altera won, it means Altera > > didn't give any compensation money to Xilinx which I heard from a > > Xilinx field engineer. > > > Weng > > Altera paid Xilinx $20M to settle the patent litigation back in July > 2001. =A0The agreement include a patent cross license. > > http://www.altera.com/corporate/news_room/releases/releases_archive/2... > > Ed McGettigan > -- > Xilinx Inc.- Hide quoted text - > > - Show quoted text - Hi Ed, Thank you for your correct and proper information about the case and you information prevents any rumors from spreading further. I really heared about the case from a Xilinx field engineer and he seemed to be unknown of $20 million after my project was switched from Altera's chips to Xilinx's and he told the story to boast the Xilinx technology reputation. WengArticle: 141324
"Dr. Thomas Ansorg" <dl7jsk@online.de> wrote in message news:h1gtdt$oig$1@online.de... > Hello all! > I need a preselection counter that divides the 50 MHz clock of my > Spartan-3E-board down to 20 MHz. Since I have no clue about verilog, only > vhdl, would someone please post me the source code? > > Tom > Assuming you have a 50:50 50MHz clock on the input and you do not need a 50:50 ratio clock on output then:- LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY work; ENTITY Test006 IS PORT ( CK_50MHz : IN STD_LOGIC; CK_20MHz : OUT STD_LOGIC ); END Test006; ARCHITECTURE bdf_type OF Test006 IS COMPONENT lpm_counter1 PORT(clock : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) ); END COMPONENT; SIGNAL Q : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL SYNTHESIZED_WIRE_3 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_2 : STD_LOGIC; SIGNAL SYNTHESIZED_WIRE_4 : STD_LOGIC; BEGIN b2v_inst : lpm_counter1 PORT MAP(clock => SYNTHESIZED_WIRE_3, q => Q); PROCESS(SYNTHESIZED_WIRE_3) BEGIN IF (RISING_EDGE(SYNTHESIZED_WIRE_3)) THEN SYNTHESIZED_WIRE_4 <= SYNTHESIZED_WIRE_2; END IF; END PROCESS; SYNTHESIZED_WIRE_3 <= CK_50MHz XOR SYNTHESIZED_WIRE_4; SYNTHESIZED_WIRE_2 <= NOT(SYNTHESIZED_WIRE_4); CK_20MHz <= Q(2); END bdf_type; will work - its a bit $hite but the only solution if you do not have a PLL available. Phil
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