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Hi Glen, The EDK is Xilinx's Embedded Development Kit. The way components, such as the ADC and flash memory, are implemented as reconfigurable Intellectual Property (IP) cores. These are essentially reconfigurable blocks of VHDL code that you set in the GUI. So, I believe I'll need to modify this VHDL code after it's generated, since the EDK gui will not let me set a single pin from the flash data bus to a specific location. Rather, the IP core only lets you map a 16-bit bus. Thanks. Matt >mstanisz <matt.staniszewski@gmail.com> wrote: > >> Thanks for the quick response. I've read through the User's Guide and saw >> that part. I have a GPIO set up for all the CENs and CSs that I need to >> control as specified in the documentation. However, I wasn't sure how to >> multiplex the two devices to the N10 net in the EDK, since the flash IP >> core specifies a 16-bit bus and I only need to share 1 bit of that with the >> MISO signal. I feel I need to modify the system VHDL file that the EDK >> generates, but I wasn't sure where I should do that. Any help would be >> great. Thanks! > >I am not sure what EDK is. > >I think the usual way is to use only one at a time, and make >sure that the other one is disabled. > >There is a similar double use on the LCD display. > >-- glen >Article: 140201
Busses become single pins in the .ucf. Comment out the Data<0> and SPI_MISO nets in the ucf so they become internal ports, and add a new NET to represent their combined function. You'll need a module to connect and select between them. I suspect this is much easier said than done, especially if the functions are in different clock domains or if the enables are less than dead simple. Also, the added logic might push a marginal design beyond timing allowances. All the same, modifying supplied HDL always seems a bad idea. "mstanisz" <matt.staniszewski@gmail.com> wrote in message news:1t6dnfigwrwkXmDUnZ2dnUVZ_qmdnZ2d@giganews.com... > Hi Glen, > > The EDK is Xilinx's Embedded Development Kit. The way components, such as > the ADC and flash memory, are implemented as reconfigurable Intellectual > Property (IP) cores. These are essentially reconfigurable blocks of VHDL > code that you set in the GUI. > > So, I believe I'll need to modify this VHDL code after it's generated, > since the EDK gui will not let me set a single pin from the flash data bus > to a specific location. Rather, the IP core only lets you map a 16-bit > bus. > > Thanks. > > Matt > > >>mstanisz <matt.staniszewski@gmail.com> wrote: >> >>> Thanks for the quick response. I've read through the User's Guide and > saw >>> that part. I have a GPIO set up for all the CENs and CSs that I need > to >>> control as specified in the documentation. However, I wasn't sure how > to >>> multiplex the two devices to the N10 net in the EDK, since the flash > IP >>> core specifies a 16-bit bus and I only need to share 1 bit of that with > the >>> MISO signal. I feel I need to modify the system VHDL file that the > EDK >>> generates, but I wasn't sure where I should do that. Any help would > be >>> great. Thanks! >> >>I am not sure what EDK is. >> >>I think the usual way is to use only one at a time, and make >>sure that the other one is disabled. >> >>There is a similar double use on the LCD display. >> >>-- glen >>Article: 140202
Hi, I'm working a design that has isolation between two sub-systems on one PCB (the grounds are separate). One side is a "high-speed" digital side with FPGAs and DDR doing DSP and the other side is an analog side that has high-resolution 24-bit ADCs and DACs. I'm planning on using DC-balanced capacitive coupling to move data back and forth between the two sides. My concern is at happens when I AC-couple my signals across cross the split-grounds? Am I creating more noise due to the return/image current not having a continuous return plane? I have worked out both single-ended AC-coupling and schemes using LVDS/CML. The capacitively coupled signals are <= 75 MHz, with 5 ns rise/fall times. The isolation is due partially to safety and to keep as much noise away from analog side as I can. I haven't found much literature on isolation and crossing split-grounds. Your opinions are welcome.Article: 140203
On May 4, 2:06=A0pm, ee_ether <xjjzdv...@sneakemail.com> wrote: > Hi, > > I'm working a design that has isolation between two sub-systems on one > PCB (the grounds are separate). =A0One side is a "high-speed" digital > side with FPGAs and DDR doing DSP and the other side is an analog side > that has high-resolution 24-bit ADCs and DACs. > > I'm planning on using DC-balanced capacitive coupling to move data > back and forth between the two sides. =A0My concern is at happens when I > AC-couple my signals across cross the split-grounds? =A0Am I creating > more noise due to the return/image current not having a continuous > return plane? =A0I have worked out both single-ended AC-coupling and > schemes using LVDS/CML. > > The capacitively coupled signals are <=3D 75 MHz, with 5 ns rise/fall > times. > > The isolation is due partially to safety and to keep as much noise > away from analog side as I can. =A0I haven't found much literature on > isolation and crossing split-grounds. > > Your opinions are welcome. Sounds like you are rolling your own? Might be smarter/easier to look at Analog Devices Digital Isolators ? -jgArticle: 140204
Isolation for safety purposes should probably be done in front of the ADC. In most other cases splitting ground creates more problems than it solves. If you can show that you need roughly more than 60 dB of isolation between your circuits then you might need to resort to splitting grounds, but you need to know what you are doing very well. AC coupled or not return currents will still want to travel through the plane, so you can only split it under the chip. The best resource for discussions on this topic is the Signal Integrity mailing list. The SI-List archive can be found at http://www.freelists.org/archive/si-list/. /Mikhail "ee_ether" <xjjzdv402@sneakemail.com> wrote in message news:707a89a7-c3cf-4953-b776-b5d36265f5b4@r13g2000vbr.googlegroups.com... > Hi, > > I'm working a design that has isolation between two sub-systems on one > PCB (the grounds are separate). One side is a "high-speed" digital > side with FPGAs and DDR doing DSP and the other side is an analog side > that has high-resolution 24-bit ADCs and DACs. > > I'm planning on using DC-balanced capacitive coupling to move data > back and forth between the two sides. My concern is at happens when I > AC-couple my signals across cross the split-grounds? Am I creating > more noise due to the return/image current not having a continuous > return plane? I have worked out both single-ended AC-coupling and > schemes using LVDS/CML. > > The capacitively coupled signals are <= 75 MHz, with 5 ns rise/fall > times. > > The isolation is due partially to safety and to keep as much noise > away from analog side as I can. I haven't found much literature on > isolation and crossing split-grounds. > > Your opinions are welcome.Article: 140205
ee_ether wrote: > Hi, > > I'm working a design that has isolation between two sub-systems on one > PCB (the grounds are separate). One side is a "high-speed" digital > side with FPGAs and DDR doing DSP and the other side is an analog side > that has high-resolution 24-bit ADCs and DACs. > > I'm planning on using DC-balanced capacitive coupling to move data > back and forth between the two sides. My concern is at happens when I > AC-couple my signals across cross the split-grounds? Am I creating > more noise due to the return/image current not having a continuous > return plane? I have worked out both single-ended AC-coupling and > schemes using LVDS/CML. > > The capacitively coupled signals are <= 75 MHz, with 5 ns rise/fall > times. > > The isolation is due partially to safety and to keep as much noise > away from analog side as I can. I haven't found much literature on > isolation and crossing split-grounds. > > Your opinions are welcome. Are you sure that split ground planes would really help? Think about the layout of your board, and the way current on the ground plane would flow. DC ground currents aim to follow a direct path on the ground plane, and high frequency currents aim to minimize the current loop area (i.e., minimal impedance in both cases). If the ground currents created by the digital logic are flowing around the digital parts, there is no reason they should wander off under the analogue parts to cause noise there. (That's my understanding of the theory - I've not worked on any high frequency, high sensitivity analogue boards in practice.)Article: 140206
In comp.arch.fpga MM <mbmsv@yahoo.com> wrote: > Isolation for safety purposes should probably be done in front of the ADC. > In most other cases splitting ground creates more problems than it solves. > If you can show that you need roughly more than 60 dB of isolation between The OP mentioned a 24 bit ADC, which suggests much more than 60dB is needed. > your circuits then you might need to resort to splitting grounds, but you > need to know what you are doing very well. AC coupled or not return currents > will still want to travel through the plane, so you can only split it under > the chip. If it is differential shouldn't it be mostly balanced? (snip) -- glenArticle: 140207
-jg wrote: > On May 4, 2:06 pm, ee_ether <xjjzdv...@sneakemail.com> wrote: >> Hi, >> >> I'm working a design that has isolation between two sub-systems on one >> PCB (the grounds are separate). One side is a "high-speed" digital >> side with FPGAs and DDR doing DSP and the other side is an analog side >> that has high-resolution 24-bit ADCs and DACs. >> >> I'm planning on using DC-balanced capacitive coupling to move data >> back and forth between the two sides. My concern is at happens when I >> AC-couple my signals across cross the split-grounds? Am I creating >> more noise due to the return/image current not having a continuous >> return plane? I have worked out both single-ended AC-coupling and >> schemes using LVDS/CML. >> >> The capacitively coupled signals are <= 75 MHz, with 5 ns rise/fall >> times. >> >> The isolation is due partially to safety and to keep as much noise >> away from analog side as I can. I haven't found much literature on >> isolation and crossing split-grounds. >> >> Your opinions are welcome. > > Sounds like you are rolling your own? > > Might be smarter/easier to look at Analog Devices Digital Isolators ? > > -jg > > I agree with jg - the AD parts are worth looking into. They're not that expensive, and they've been tested to international standards for high voltage isolation. That will help with agency certification, assuming that your product requires it. ChrisArticle: 140208
Sean Durkin schrieb: > LittleAlex wrote: >> How do you tell them that this is a bad idea? By designing in Altera >> or LatticeSemi parts. > > Well, at least Lattice's licensing system is the same as it is now with > Xilinx: node-locked licenses per machine or floating licenses for a > considerably higher price, so that won't really solve anything. Found some info now: http://www.xilinx.com/support/documentation/customer_notices/xcn09015.pdf There still are EDU-versions at a reduced price, they're just not listed under "related products" yet. cu, Sean -- Replace "MONTH" with the three-letter abbreviation of the current month (simple, eh?).Article: 140209
Does anyone have the latest version of PCCOMP written by Francesco Poderico? Google helped me to find the version alpha 1.7.x at http://www.asm.ro/fpga/, but I found some references to version 1.8.4 in this newsgroups. Any assistence will be appreciated. Selensky.Article: 140210
Sean Durkin wrote: > Any news on the educational versions of ISE? Avnet and NuHorizons don't > list them at all, and the XUP-Website hasn't been updated yet (it still > talks about "ISE Foundation"...). Found some info now: http://www.xilinx.com/support/documentation/customer_notices/xcn09015.pdf There still are EDU-versions at a reduced price, they're just not listed under "related products" yet. cu, Sean -- Replace "MONTH" with the three-letter abbreviation of the current month (simple, eh?).Article: 140211
Well it finally worked for me. i had many problems especially with the PAR tool of Xilinx ... Thanks for all those who helped me with my questions .. (thanks Dirl , thanks Antti ..) Recobus builder is also working fine ( i didn't try the Bus system though ..) If any one of you guys need DPR on spartan 3, let me know ... Hassen Karray.Article: 140212
Hello, I have problem with IP CoreGen Asynch FIFO. I need to be able to latch data in BRAM asynchronic manner. Is it possible at all ? I assert wr_en to 1 and wr_clock is my combinatory logic that generating 1 in some events. And it does not work. In constraint editor global clock showing two clocks one is real clock and second is signal that is asserting to wr_clock in fifo but i don't know how to define constraint for it. when I assign real clock to wr_clock it work. I need to be able to operate under clock frequency because I need to report asynch events that havent nothing in common with clock... please help, and i relly sorry about my english and FPGA newbie...Article: 140213
On May 3, 7:06=A0pm, ee_ether <xjjzdv...@sneakemail.com> wrote: > Hi, > > I'm working a design that has isolation between two sub-systems on one > PCB (the grounds are separate). =A0One side is a "high-speed" digital > side with FPGAs and DDR doing DSP and the other side is an analog side > that has high-resolution 24-bit ADCs and DACs. > > I'm planning on using DC-balanced capacitive coupling to move data > back and forth between the two sides. =A0My concern is at happens when I > AC-couple my signals across cross the split-grounds? =A0Am I creating > more noise due to the return/image current not having a continuous > return plane? =A0I have worked out both single-ended AC-coupling and > schemes using LVDS/CML. > > The capacitively coupled signals are <=3D 75 MHz, with 5 ns rise/fall > times. > > The isolation is due partially to safety and to keep as much noise > away from analog side as I can. =A0I haven't found much literature on > isolation and crossing split-grounds. > > Your opinions are welcome. My experiences have shown: You can probably run data lines single-ended, with series resistors to slow the edges and limit the current. You are right about the long return current path causing radiated noise, but the random nature of the data lines will make it rather spread-spectrum, so it should be tolerable. Clocks, on the other hand, should only cross a split-plane as differential signals. You still get radiated emissions, but much less. The diff pair over split plane can be modeled as a diff pair over continuous plane plus a small loop antenna with dimensions equal to the split width and the pair spacing. So make the split small and the lvds traces close together. Henry Ott covered this in one of his books; sorry I don't remember which one. BarryArticle: 140214
"glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message news:gtm4pd$fa6$1@naig.caltech.edu... > > The OP mentioned a 24 bit ADC, which suggests much more than > 60dB is needed. > Glen, I noticed this fact, but taken out of the context of application it doesn't necessarily mean anything. > If it is differential shouldn't it be mostly balanced? Balanced doesn't mean that return current for one side actually uses another side. /MikhailArticle: 140215
On May 4, 8:28=A0am, "de4" <d...@poczta.onet.pl> wrote: > Hello, > > I have problem with IP CoreGen Asynch FIFO. I need to be able to latch > data in =A0BRAM asynchronic manner. Is it possible at all ? I assert wr_e= n to > 1 and wr_clock is my combinatory logic that generating 1 in some events. > And it does not work. In constraint editor global clock showing two clock= s > one is real clock and second is signal that is asserting to wr_clock in > fifo but i don't know how to define constraint for it. when I assign real > clock to wr_clock it work. I need to be able to operate under clock > frequency because I need to report asynch events that havent nothing in > common with clock... The BRAMs are synchronous. You do NOT want to gate the clock. Learn how to use clock enables. -aArticle: 140216
On May 4, 8:28=A0am, "de4" <d...@poczta.onet.pl> wrote: > Hello, > > I have problem with IP CoreGen Asynch FIFO. I need to be able to latch > data in =A0BRAM asynchronic manner. Is it possible at all ? I assert wr_e= n to > 1 and wr_clock is my combinatory logic that generating 1 in some events. > And it does not work. In constraint editor global clock showing two clock= s > one is real clock and second is signal that is asserting to wr_clock in > fifo but i don't know how to define constraint for it. when I assign real > clock to wr_clock it work. I need to be able to operate under clock > frequency because I need to report asynch events that havent nothing in > common with clock... > > please help, and i relly sorry about my english and FPGA newbie... Use free-running clocks for writing and reading. They can have different (unrelated) frequencies. Then use WE and RE to perform the write or read function. Anything else gets very messy... Peter AlfkeArticle: 140217
On May 4, 11:28 am, "de4" <d...@poczta.onet.pl> wrote: > Hello, > > I have problem with IP CoreGen Asynch FIFO. I need to be able to latch > data in BRAM asynchronic manner. Is it possible at all ? I assert wr_en to > 1 and wr_clock is my combinatory logic that generating 1 in some events. > And it does not work. In constraint editor global clock showing two clocks > one is real clock and second is signal that is asserting to wr_clock in > fifo but i don't know how to define constraint for it. when I assign real > clock to wr_clock it work. I need to be able to operate under clock > frequency because I need to report asynch events that havent nothing in > common with clock... > > please help, and i relly sorry about my english and FPGA newbie... You need to learn how to synchronize events that use different clocks. In your case, it sounds like you have an external event that is not related to any clock and you are generating a strobe from your combinatorial logic. If that is the case, you need to synchronize the combinatorial clock to your system clock along with the data you want to write to the BRAM. Then it is a simple matter to enable the write to the BRAM. For this to work the system clock controlling the BRAM must run as least as fast as the asynchronous event and preferably twice as fast to relieve timing issues. Be sure to consider metastability in your circuit. If you don't know what that is, you need to do a search for it. There is a lot to learn there although in practice the "solution" is very simple. RickArticle: 140218
In comp.arch.fpga MM <mbmsv@yahoo.com> wrote: (snip) > I noticed this fact, but taken out of the context of > application it doesn't necessarily mean anything. (after I wrote) >> If it is differential shouldn't it be mostly balanced? > Balanced doesn't mean that return current for one side actually > uses another side. I qualified with "mostly". One would have to look at the individual case. Properly terminated, it is hard to see whereelse the current would go, but signals aren't always properly terminated. -- glenArticle: 140219
"glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message news:gtncrq$1a8$2@naig.caltech.edu... > > (after I wrote) >>> If it is differential shouldn't it be mostly balanced? > >> Balanced doesn't mean that return current for one side actually >> uses another side. > > I qualified with "mostly". One would have to look at the > individual case. Properly terminated, it is hard to see whereelse > the current would go, but signals aren't always properly terminated. Please check out this article by Eric Bogatin: http://www.thefreelibrary.com/So+far,+so+close:+understanding+return+current+in+a+differential...-a0103123486 It should be available on his web site (http://www.bethesignal.net/) as well in a better format but I couldn't find it quickly... /MikhailArticle: 140220
On Apr 27, 2:39=A0pm, "xdsd98123" <xdsd98...@163.com> wrote: > Hi, > > Many thanks for your time. > > I'm looking for a board to pre-process the video signal from camera. > > The followings are the features of the camera I will use: > -- The camera is of RGB type and has three separate CCD sensors. > -- The interface of 3CCD camera is not limited, can be Camera link, GigE, > 1394 or analog RGB (three channels), it depends on which kind of > development board I can use. > -- The frame rate of this camera is about 30f/s, and resolution about > 1024*768, 8/10bit. > > The followings are the features of the board I am looking for: > -- Proper interface to receive data from 3CCD camera. > -- FPGA or combination of FPGA and DSP. Combination of boards, e.g., a DS= P > kit and a plug-in FPGA board can also work. > -- Big memory and high performance. > -- Proper interface to transmit the processing result to PC: Ethernet or > USB or=85 But not PCI or PCI express. > > I didn=92t find a board with Camera link interface. And I am a litter > confused by the interface and format of camera. > -- What is the difference between composite and VGA? > --Does RGB output mean 3 analog channels corresponding to R/G/B, and each > channel has the same format with black-white camera video output and has > sync information included in each channel? > --What kind of chip do I need to transform RGB output to raw data that > FPGA can process? > > In my application, about 30 images will be received per second and I want > to use 30 images to produce an averaged image. After 30 images add togeth= er > and form one image, the board transmits it to computer online. Any > suggestions? > > I really appreciate your help. > > Danny Hi Danny, Have you looked at the SMT339 from Sundance Multiprocessor Technology? http://www.sundance.com/web/files/productpage.asp?STRFilter=3DSMT339 The SMT339 can be adapted to any interface by the mean of Sundance SLB FPGA mezzanine cards: Camera link, DVI, RS-422, GigE, PAL/NTSC... It also has a Xilinx FPGA (with embedded PowerPC core and dedicated fast ZBT SRAM for image manipulation) and a TI DSP running at 700MHz (with a large amont of SDRAM for image buffering). If you use the SMT339 module combined with the SMT111 (http:// www.sundance.com/web/files/productpage.asp?STRFilter=3DSMT111), you will have a proper USB link. It is also possible to have a gigabit ethernet interface if you prefer. - SebastienArticle: 140221
In comp.arch.fpga MM <mbmsv@yahoo.com> wrote: > "glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message > news:gtncrq$1a8$2@naig.caltech.edu... >> I qualified with "mostly". One would have to look at the >> individual case. Properly terminated, it is hard to see whereelse >> the current would go, but signals aren't always properly terminated. > Please check out this article by Eric Bogatin: > http://www.thefreelibrary.com/So+far,+so+close:+understanding+return+current+in+a+differential...-a0103123486 I will look at it, though it is the OP who really needs to know. Also, for a similar question not so long ago I was calculating the capacitance of a ground plane. (Even with no other plate nearby the capacitance is still there. Much higher with other planes nearby.) > It should be available on his web site (http://www.bethesignal.net/) as well > in a better format but I couldn't find it quickly... thanks, -- glenArticle: 140222
On Apr 24, 1:37=A0pm, muthu...@gmail.com wrote: > Hello, > > I am planning to evaluate a SD/SDHC Host Controller. Do Xilinx has any > suitable evaluation boards? From the Websearch, I couldn't find any > Xilinx board with SD/SDHC card interface. > > Best regards, > Muthu Hi, There is a MicroSD controller available on the Sundance SMT945 FPGA mezzanine card (http://www.sundance.com/web/files/productpage.asp? STRFilter=3DSMT945) and also on the SMT111 (http://www.sundance.com/web/ files/productpage.asp?STRFilter=3DSMT111). - SebastienArticle: 140223
Thank you for your answers - it gave me a lot to think of. World of FPGA , digital circuits and computer architecture is still very far from me unfortunatly. I thinking now how for example InChipScope debbugging in circuit working in order to save some asynchronious event in FPGA that can occur independly from clock because it is very similar to my task that I'm trying to reach....I only know that it stores changes of states in BRAM but how it store asynch states if writing to Block RAM must be synchronious... Once again thanks to all...Article: 140224
"de4" <de4@poczta.onet.pl> wrote in message news:K8ednSNliKhh02LUnZ2dnUVZ_sCdnZ2d@giganews.com... > I thinking now how for example InChipScope debbugging in > circuit working in order to save some asynchronious event in FPGA that can > occur independly from clock because it is very similar to my task that I'm > trying to reach....I only know that it stores changes of states in BRAM > but > how it store asynch states if writing to Block RAM must be synchronious... > ChipScope doesn't do anything at all to help you with capturing async events "properly". It simply samples whatever it sees at the clock rate it is set to. So, when you are looking at the captured waveform you need to be aware that it is only an approximation and there are might be things there that you don't see, e.g. glitches shorter than a sample clock period may be completely left out. The transition times on the waveform are not exactly the same as they were in the original async signal, but sort of snapped to a "sampling grid".. /Mikhail
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