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Messages from 135575

Article: 135575
Subject: Re: How to synthesize a delay of around 10 ns in FPGA?
From: Peter Alfke <peter@xilinx.com>
Date: Wed, 8 Oct 2008 14:31:53 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 8, 12:46=A0pm, Thomas Heller <thel...@python.net> wrote:
> Peter Alfke schrieb:
>
> [Ah, back again?]
>
>
>
> > On Oct 8, 7:35 am, Pratap <pratap.i...@gmail.com> wrote:
> >> Hi,
> >> I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro. So
> >> I put around 200 inverters in series and get the desired delay. So I
> >> did port map the BASIC cell "INV" according to the XST settings.
> >> But when i place and route I guess the optimizer removes all the
> >> intermediate buffers and I get very less delay when I do a post route
> >> simulation.
> >> How can I get rid of this problem?
> >> Thanks in advance.
> >> -Pratap
>
> > Use the IDELAY in Xilinx Virtex-4 or later. It gives you max 5 ns
> > delay, but that delay is stable over temperature, voltage, and
> > processing, because it is referenced to a 200 MHz clock (I call that
> > servo-stabilized).
> > Peter Alfke, Xilinx
>
> Which jitter does this give?
>
> Thanks,
> Thomas

Very little, since this is really a string of concatenated 75-ps delay
elements, held constant by a 200 MHz oscillator that controls the
delay stable through Vcc adjustments.
You can even modulate this delay by 10% up and down.
Teaching is addictive...
Peter A.

Article: 135576
Subject: Re: How to synthesize a delay of around 10 ns in FPGA?
From: Selensky <selensky@gmail.com>
Date: Wed, 8 Oct 2008 16:01:08 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 8 out, 18:31, Peter Alfke <pe...@xilinx.com> wrote:
> On Oct 8, 12:46=A0pm, Thomas Heller <thel...@python.net> wrote:
>
>
>
> > Peter Alfke schrieb:
>
> > [Ah, back again?]
>
> > > On Oct 8, 7:35 am, Pratap <pratap.i...@gmail.com> wrote:
> > >> Hi,
> > >> I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro. =
So
> > >> I put around 200 inverters in series and get the desired delay. So I
> > >> did port map the BASIC cell "INV" according to the XST settings.
> > >> But when i place and route I guess the optimizer removes all the
> > >> intermediate buffers and I get very less delay when I do a post rout=
e
> > >> simulation.
> > >> How can I get rid of this problem?
> > >> Thanks in advance.
> > >> -Pratap
>
> > > Use the IDELAY in Xilinx Virtex-4 or later. It gives you max 5 ns
> > > delay, but that delay is stable over temperature, voltage, and
> > > processing, because it is referenced to a 200 MHz clock (I call that
> > > servo-stabilized).
> > > Peter Alfke, Xilinx
>
> > Which jitter does this give?
>
> > Thanks,
> > Thomas
>
> Very little, since this is really a string of concatenated 75-ps delay
> elements, held constant by a 200 MHz oscillator that controls the
> delay stable through Vcc adjustments.
> You can even modulate this delay by 10% up and down.
> Teaching is addictive...
> Peter A.

Hi Peter,

You said that Virtex-4 IDELAY element is stable over temperature,
voltage and processing. Is it stable over continuous years of
operation too?
In our project we are currently using IDELAY to adjust optimal
sampling points in LVDS buses between two Virtex-4 devices (-11 grade)
@ 700 Mbps.
We want to know if PCB's issues like capacitance and humidity
variations would be more critical than FPGA deviations along
continuous years of operation.

Thanks,
Selensky

Article: 135577
Subject: Xilinx VHDL inferred RAMs
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Wed, 8 Oct 2008 16:26:17 -0700
Links: << >>  << T >>  << A >>
Hello,

I had an inferred dual port ram in my design
where I stuffed three 10bit std_logic_vectors
into a single std_logic_vector padded to 36bit.

This synthesized OK in ISE9.2 but was difficult
to read the individual 10bit vectors in ModelSim
when I expanded the ram.

So I declared a record of three 10bit std_logic_
vectors and connected those signals to the inputs
and outputs of the dual port ram. This looks great
in ModelSim. But the synthesis went bad and seemed
to place the RAM in the fabric and not in the BRAM.

So my question is can you have data inputs and data
outputs of non std_logic_vectors and still be able
to infer a dual port ram?

Brad Smallridge
Ai Vision
 



Article: 135578
Subject: Re: I need a good reference for VHDL
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Wed, 8 Oct 2008 16:31:38 -0700
Links: << >>  << T >>  << A >>
> Please recommend either a book or web reference or learning VHDL that 
> would be good for someone that is experienced in FPGA
> architecture and Verilog.

Aha! The exact book you want is HDL Programming Fundamentals VHDL and 
Verilog by Nazeih M. Botros. Well written. Interesting examples. Side by 
side comparison of Verilog and VHDL.

Brad Smallridge
Ai Vision



Article: 135579
Subject: Update Altera MAXII UFM post production
From: Owen Duffy <none@no.where>
Date: Thu, 09 Oct 2008 00:15:52 GMT
Links: << >>  << T >>  << A >>

Does anyone have hints on how to use the USB Blaster JTAG programmer to 
update the MAX II UFM (only) from a hex file.

It looks like I need to create a .pof file for the UFM contents alone, but 
I cannot find a utility to convert .hex to .pof.

Hints appreciated.

Thanks
Owen


Article: 135580
Subject: ChipScope on Ubuntu 7.10 - blank screen
From: james.e.steward@gmail.com
Date: Wed, 8 Oct 2008 17:53:23 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi all,

There was a brief mention of something like this on one thread I
followed, but I couldn't see a resolution.

I've got ISE and ChipScope 9.2i installed.  I followed the
installation rules carefully.  ISE runs fine, and I can add a
chipscope core to a project and generate a programming (bin) file.

When I start chipscope, either from ISE or from the command line with
analyser.sh, I get a new blank window appear, and that's it.

Things are installed in my home dir, so I ran analyser.sh with sh -x,
to see what happens....

~/Xilinx/ChipScope_Pro_9_2i/bin/lin$ sh -x ./analyzer.sh
+ args=
+ which ./analyzer.sh
+ which=./analyzer.sh
+ dirname ./analyzer.sh
+ mydir=.
+ cs_root=./../..
+ uname
+ [ Linux = Linux ]
+ [ . = . ]
+ OS=lin
+ export XILINX=./../../xilinx
+ export PATH=./../../bin/lin:./../../xilinx/bin/lin:/opt/symphonyeda/
Simili31/tcl/bin:/opt/ActiveTcl-8.4/bin:/usr/local/sbin:/usr/local/
bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/opt/codesourcery/
arm-2007q1/bin:/home/james/Xilinx92i/bin/lin/
+ export LD_LIBRARY_PATH=./../../bin/lin:./../../xilinx/bin/lin::/home/
james/Xilinx92i/bin/lin
+ export TCL_LIBRARY=./../../xilinx/bin/lib/tcl8.4
+ JAVA=./../../bin/lin/jre1.5.0/bin/java
+ CLASSPATH=./../../bin/lin/jdom.jar:./../../bin/lin/jbcl.jar:./../../
bin/lin/ip.jar:./../../bin/lin/coreutil.jar:./../../bin/lin/
sim.jar:./../../bin/lin/xcc.jar:./../../bin/lin/chipscope.jar:./../../
bin/lin/ipce.jar:./../../bin/lin/iText.jar
+ ./../../bin/lin/jre1.5.0/bin/java -Xdebug -Xmx512m -Xss16m -
classpath ./../../bin/lin/jdom.jar:./../../bin/lin/jbcl.jar:./../../
bin/lin/ip.jar:./../../bin/lin/coreutil.jar:./../../bin/lin/
sim.jar:./../../bin/lin/xcc.jar:./../../bin/lin/chipscope.jar:./../../
bin/lin/ipce.jar:./../../bin/lin/iText.jar
com.xilinx.chipscope.analyzer.gui.CSGui


That's it.  When I try to close the window, I get prompted to save my
new project.

Anyone seen this before?

James.

Article: 135581
Subject: Re: Do two clock system blocks with one clock running half of other's
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: Wed, 8 Oct 2008 18:38:04 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 8, 10:04=A0am, Andy <jonesa...@comcast.net> wrote:
> Just speculating, but I'd bet large processors use derived clocks,
> with known phase relationships, to avoid the typical asynchronous
> clock boundary crossing logic wherever possible. Running large cache
> structures at twice the clock frequency needed is too power hungry.
> They might have been able to get away with it in the past, when caches
> were smaller and power consumption was less important, but not any
> longer.
>
> Andy

Hi Andy,
Glad to hear you again. We are always on opposite sides of any coin.

Peter misses the point and your response hits the point:
"I'd bet large processors use derived clocks,
with known phase relationships, to avoid the typical asynchronous
clock boundary crossing logic wherever possible. "

I disagree with you. How can they manage the huge range of
temperatures that causes clock circiut shifting.

Peter, what is your opinion? From Xilinx FPGA designer's point of
view, there are large uncertain range for derived clocks. I remember
it may be 300 ps at least for a range of temperature.

Thank you.

Weng

Article: 135582
Subject: Re: Does XST support global signals?
From: Brian Davis <brimdavis@aol.com>
Date: Wed, 8 Oct 2008 18:53:18 -0700 (PDT)
Links: << >>  << T >>  << A >>
EM wrote:
> Thanks for the quick reply, Brian.  Sorry for not responding sooner.
> I guess my Usenet reader was slow to update, because it didn't look
> like anyone replied within 24 hours, so I stopped checking.

 I don't read the newsgroup using a newsreader, but just check
the google news archives from time to time; my replies sometimes
are a bit delayed.

> I experimented with their search engine, to see if I could find
> the article you linked to, but no luck.  I even used the same
> terms they put in their description:

 That one was old enough that it's in the archived answers.
 - Go to the Xilinx webpage
 - click the "advanced search" link (below the search button)
 - enter your search terms
 - check what to search ( answer records, archive, etc. )

 Note that although the search terms are filled in again
on the results page, that is just the plain-old-search,
not the advanced one; you have to back up to the advanced
search page again to properly modify your search terms.

>
> It's good to know someone else has managed to use global signals with
> XST.  Now we know it's worth the effort to making it work.
>
 I'll try to extract a working example from some old code
in the next week or few if I have the time.( My from-scratch
hack at it just now got me a bunch of XST "undriven signal"
errors if I try reading the signal for synthesis outside
the level of hierarchy it's assigned in. )

I think these links originally got me pointed in this direction:
  http://groups.google.com/group/comp.arch.fpga/msg/d52079ad3378b452
  http://www.eda.org/comp.lang.vhdl/FAQ1.html#monitor

Brian

Article: 135583
Subject: Re: Newbie question
From: Masca <salinasv@gmail.com>
Date: Wed, 8 Oct 2008 20:51:49 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 7 oct, 16:16, andrea.cor...@gmail.com wrote:
> On Oct 7, 1:58=A0pm, Mike Treseler <mtrese...@gmail.com> wrote:
>
> > andrea.cor...@gmail.com wrote:
> > > However, I am not clear yet how do I get the results of a fpga
> > > computation back to my PC. Is there any cable I am missing (maybe
> > > serial)? How do I read and use this stream?
>
> > Pg 28:
> > On the board, LEDs 0, 1, 2, and 3 are lit,
> > indicating that the counter is running.
>
> > An fpga output is a high or low voltage on a device pin.
> > The counter pins are connected to LEDs for this demo.
>
> > Maybe your board has demos for other interfaces like rs232 or usb?
>
> > =A0 =A0 =A0 =A0 -- Mike Treseler
>
> Thanks Mike,
>
> When I run the tutorial the four leds are lit indeed: so far so good.
>
> A demo is exactly what I am looking for: a demonstration of how to
> make a simple program that takes two variables in input (say a and b)
> from the pc, calculates their sum c=3Da+b on the FPGA, and finally
> passes the variable c to the pc for further computations.
> The Spartan board I have does have a rs232 interface. Does anybody
> know of such a demo for my board? Many thanks again.
>
> Andrea

You are looking for UART module, take a look at xilinx appnotes.

You must know the board is not a coprocessor, it's a stand-alone chip.
I guess your best bet to get started with FPGA on this board is to get
working the displays.

Article: 135584
Subject: Re: How to synthesize a delay of around 10 ns in FPGA?
From: Peter Alfke <alfke@sbcglobal.net>
Date: Wed, 8 Oct 2008 20:57:02 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 8, 4:01=A0pm, Selensky <selen...@gmail.com> wrote:
> On 8 out, 18:31, Peter Alfke <pe...@xilinx.com> wrote:
>
>
>
> > On Oct 8, 12:46=A0pm, Thomas Heller <thel...@python.net> wrote:
>
> > > Peter Alfke schrieb:
>
> > > [Ah, back again?]
>
> > > > On Oct 8, 7:35 am, Pratap <pratap.i...@gmail.com> wrote:
> > > >> Hi,
> > > >> I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro=
. So
> > > >> I put around 200 inverters in series and get the desired delay. So=
 I
> > > >> did port map the BASIC cell "INV" according to the XST settings.
> > > >> But when i place and route I guess the optimizer removes all the
> > > >> intermediate buffers and I get very less delay when I do a post ro=
ute
> > > >> simulation.
> > > >> How can I get rid of this problem?
> > > >> Thanks in advance.
> > > >> -Pratap
>
> > > > Use the IDELAY in Xilinx Virtex-4 or later. It gives you max 5 ns
> > > > delay, but that delay is stable over temperature, voltage, and
> > > > processing, because it is referenced to a 200 MHz clock (I call tha=
t
> > > > servo-stabilized).
> > > > Peter Alfke, Xilinx
>
> > > Which jitter does this give?
>
> > > Thanks,
> > > Thomas
>
> > Very little, since this is really a string of concatenated 75-ps delay
> > elements, held constant by a 200 MHz oscillator that controls the
> > delay stable through Vcc adjustments.
> > You can even modulate this delay by 10% up and down.
> > Teaching is addictive...
> > Peter A.
>
> Hi Peter,
>
> You said that Virtex-4 IDELAY element is stable over temperature,
> voltage and processing. Is it stable over continuous years of
> operation too?
> In our project we are currently using IDELAY to adjust optimal
> sampling points in LVDS buses between two Virtex-4 devices (-11 grade)
> @ 700 Mbps.
> We want to know if PCB's issues like capacitance and humidity
> variations would be more critical than FPGA deviations along
> continuous years of operation.
>
> Thanks,
> Selensky

No variations.
It is a Phase-Locked-Loop, controlled by a user oscillator of approx
200 MHz, which makes sure that the total delay over 64 taps is exactly
one period of 200 MHz.
It assumes that delays of neighboring IDELAY blocks track, but that is
a sure thing in ICs. Capacitance and humidity have no impact on a
digital control circuit.
The world is full of frequency synthesizers that rely on far more
complex PLL circuits, apparently without problems.
Peter Alfke, from home.

Article: 135585
Subject: Re: Actel constraints?
From: Thomas Stanka <usenet_nospam_valid@stanka-web.de>
Date: Wed, 8 Oct 2008 22:48:35 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 7 Okt., 18:58, "Nial Stewart"
<nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote:
> Does anyone have any pointers to a good document describing how to apply
> constraints to Actel FPGAs?
>
> I'm trying to transfer a design from a Cyclone II to an Actel A3P600
> (Pro-Asic 3) but am having problems applying and passing IO timing
> constraints relative to the internal clock.

In designer the tool SmartTimer is used for timing constraints.
It should be no problem to constraint the delay between input and
clock.
Could you explain a bit more detailed what you tried and what you
liked to get?

bye Thomas

Article: 135586
Subject: Re: Another problem....
From: Thomas Stanka <usenet_nospam_valid@stanka-web.de>
Date: Wed, 8 Oct 2008 22:50:04 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 8 Okt., 11:02, "Nial Stewart"
<nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote:
> One other problem I've had is that the tools don't seem to be able to
> handle buried tri-state control of busses.

For internal tri-state or external?
I had no problem to control external tri-state busses with the Actel
tools. Never tried AP3, but there should be no difference.

bye Thomas


Article: 135587
Subject: Re: Packet sniffer help
From: Fred <fred__bloggs@lycos.com>
Date: Thu, 9 Oct 2008 01:22:37 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 8 Oct, 13:28, Fred <fred__blo...@lycos.com> wrote:
> I'm currently using Wireshark which in general is great software.
> However there appears to be a problem in quoting received packet
> checksums as good despite being seemingly good.
>
> Is there an alternative network sniffer which would give a clear
> indication of packets with incorrect checksums, preferably not using
> the WinPcap driver so to get a clear comparison.
>
> Has anyone else come across this problem with Wireshark with large
> packets?

The problem was mine with respect to "addding the carries" to the
checksum where I was occasionally one out!

Article: 135588
Subject: Re: Xilinx VHDL inferred RAMs
From: Rob <BertyBooster@googlemail.com>
Date: Thu, 9 Oct 2008 01:37:34 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 8, 11:26=A0pm, "Brad Smallridge" <bradsmallri...@dslextreme.com>
wrote:
> Hello,
>
> I had an inferred dual port ram in my design
> where I stuffed three 10bit std_logic_vectors
> into a single std_logic_vector padded to 36bit.
>
> This synthesized OK in ISE9.2 but was difficult
> to read the individual 10bit vectors in ModelSim
> when I expanded the ram.
>
> So I declared a record of three 10bit std_logic_
> vectors and connected those signals to the inputs
> and outputs of the dual port ram. This looks great
> in ModelSim. But the synthesis went bad and seemed
> to place the RAM in the fabric and not in the BRAM.
>
> So my question is can you have data inputs and data
> outputs of non std_logic_vectors and still be able
> to infer a dual port ram?
>
> Brad Smallridge
> Ai Vision

My suggestion would be to keep the record but just before you connect
the data to the memory assign each element of the record to its own
std_logic_vector and concatenate them together as before.

Rob

Article: 135589
Subject: Re: Actel constraints?
From: "Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk>
Date: Thu, 9 Oct 2008 09:52:05 +0100
Links: << >>  << T >>  << A >>
> In designer the tool SmartTimer is used for timing constraints.
> It should be no problem to constraint the delay between input and
> clock.
> Could you explain a bit more detailed what you tried and what you
> liked to get?


I'm just trying to constrain a TSU and TCO of 4ns against the clock.

If I can get the input, output and tri-state control registers into
the IOB then I presume these should be met OK, although the timing
report is including long clock delays across the device so I'm not
sure I'm specifying things against the right clock/point.


Thanks,

Nial.




Article: 135590
Subject: Re: Do two clock system blocks with one clock running half of other's need asynchronous input/output buffers?
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Thu, 09 Oct 2008 11:42:25 +0100
Links: << >>  << T >>  << A >>
On Wed, 8 Oct 2008 18:38:04 -0700 (PDT), Weng Tianxiang
<wtxwtx@gmail.com> wrote:

>On Oct 8, 10:04 am, Andy <jonesa...@comcast.net> wrote:

>Peter misses the point and your response hits the point:
>"I'd bet large processors use derived clocks,
>with known phase relationships, to avoid the typical asynchronous
>clock boundary crossing logic wherever possible. "
>
>I disagree with you. How can they manage the huge range of
>temperatures that causes clock circiut shifting.

There is probably a lot less logic involved in continuously
auto-calibrating a clock DLL to eliminate temperature/voltage drift,
than there is in boundary crossing logic for a 256-bit or wider internal
bus.

- Brian

Article: 135591
Subject: Re: Reading files from CF (microblaze 7 and plb)
From: lomtikster@gmail.com
Date: Thu, 9 Oct 2008 03:45:21 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 6, 5:40 am, jason.hy...@gmail.com wrote:
> On Oct 6, 4:21 pm, lomtiks...@gmail.com wrote:
>
>
>
> > Hi everyone,
>
> > I would like to read a file from a CF card on xupv2p board using PLB
> > and Microblaze 7.10d. There are a few questions that I am trying to
> > answer.
>
> > There is an xps_sysace interface controller v1.00a which seats between
> > the PLB and the system ace CF peripheral and has sysace v1_11_a driver
> > with functions like XSysAce_SectorRead and XSysAce_SectorWrite.
> > However, I have not found any file system management soft like
> > sysace_fopen and sysace_fread provided with XilFatfs FATFile System
> > access library (xilfatfs_v1_00_a) that, from its doc, requires OPB
> > SYSACE Interface Controller - Logicore module. How else would you read
> > files from the a CF via PLB?
> > Would it require modifying xilfatfs to support PLB?
>
> > Probably I could reuse the xilfatfs_v1_00_a if I use the older MB 6
> > with OPB bus and opb_sysace or OPB2PLB bridge and xps_sysace.
>
> I am using MB 7.10a + plb + xps_sysace 1.00a with xilfatfs 1.00.a. I
> also use
> sysace_fopen, sysace_fread, sysace_fwrite for my sysace operations. So
> I don't
> think you need to redesign your system again.XSysAce_SectorRead and
> XSysAce_SectorWrite are the raw operations as I remember.

Thanks Goran, Jason. It was great to hear the confirmation that
xilfatfs worked for you with with the xps_sysace 1.00a. I came back to
the original setup with PLB and xps_sysace and fixed all the
compilation errors that I had. I also added the ddr ram plb controller
and able to debug the code now.

I have another issue now that am trying to figure out. For some
reason, when reading the first file, the program is hitting a
_vector_sw_exception which I get after exiting
int update_bufcache(int sector, unsigned char *sector_buf, int dirty)
function. This function is called multiple times before the exception
is made.

update_bufcache() is called by read_sector(), which in turn is read
from read_from_file()

Why could this exception happen?
I've checked my address ranges and they don't seem to overlap.
I formatted my CF card as suggested by the xupv2p's user guide for
128mb with mkdosfs and placed a few images there, and the exception
happens on the first.
As example, I am using the slideshow code available from xilinx/
digilent: http://www.digilentinc.com/Products/Detail.cfm?Prod=XUPV2P
I disabled //XCache_EnableDCache(0xF000000F) and //
XCache_EnableICache(0xF000000F) lines. Could it relate to the problem?
My DDR ram has these disabled in Assembly System View too.



Article: 135592
Subject: Re: Connecting MPD I/O ports in xps_sysace
From: lomtikster@gmail.com
Date: Thu, 9 Oct 2008 03:54:01 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 6, 4:03=A0am, Brian Drummond <brian_drumm...@btconnect.com>
wrote:
> On Mon, 6 Oct 2008 00:15:37 -0700 (PDT), lomtiks...@gmail.com wrote:
> >Hi all,
>
> >When instantiating the xps_sysace core, the XPS SYSACE (System ACE)
> >Interface Controller (v1.00a) document mentions that SysACE_MPD port
> >is formed in the IOB from SysACE_MPD_I, SysACE_MPD_0, and
> >SysACE_MPD_T. Does it mean that I connect only SysACE_MPD to FPGA's
> >pin and should leave SysACE_MPD_I, SysACE_MPD_0, and SysACE_MPD_T
> >unconnected? That's what I've seen in the few posts here.
>
> >The XPS System ACE Interface Controller I/O Signals table only
> >mentions _0, _I and _T ports however.
>
> You may find that XPS builds a "system_stub" example file which
> illustrates how the _0, _I and _T ports can be combined in instantiated
> IOB ports to connect to the pin.
>
> - Brian

Thanks Brian,

So, I left the MPD_0, MPD_I, and MPD_T port unconnected so far. I have
not understood how these can coexist within the same block with MPD
yet. Are you referring to system_stub file that is located in the \
\microblaze_0\code\ directory? I've seen a reference to it somewhere
else, but did not find it in my dir structure. "Help" does not have
the system_stub topic, yet refers to debug options. I'll need to look
further...



Article: 135593
Subject: how to share infered ROM memories in synplify?
From: richard.draelos@gmail.com
Date: Thu, 9 Oct 2008 04:45:10 -0700 (PDT)
Links: << >>  << T >>  << A >>

Is there anyway to make synplify to share memories used for ROMS?


More specific, assume I have this big lookup table in VHDL:

  function dummy( a : unsigned(7 downto 0)) return unsigned(7 downto
0);
  ...

Which I then use in multiple locations

  output1 <= dummy( input1);
  output2 <= dummy( input2);
  output3 <= dummy( input3);
  output4 <= dummy( input4);

Now, when no dedicated ROM cells are left synplify may try to map
these to one memory each. I think this a a huge waste of space since
the memories are all dual port. A more intelligent synthesis would put
two instances in each memory. To make synplify understand this, I did
the following changes to my code:


 constant dummy1 : array (0 to 255) of unsigned(7 downto 0) := ...
 constant dummy2 : array (0 to 255) of unsigned(7 downto 0) := ...

Which I can use like this

  output1 <= dummy1( to_integer(input1) );
  output2 <= dummy1( to_integer(input2) );
  output3 <= dummy2( to_integer(input3) );
  output4 <= dummy2( to_integer(input4) );

But the tool still refuses to share the memories. The only way around
this was to generate the memories blocks with correct initialisation
outside the tool and then import them (so the architecture does
supports dual port ROMs). However, I generally let the tool do the
thinking and don't like this inflexible approach.


Has anyone else seen this behaviour?
Any suggestion how to fix this would be most appreciated!

Article: 135594
Subject: Re: Packet sniffer help
From: Rich Webb <bbew.ar@mapson.nozirev.ten>
Date: Thu, 09 Oct 2008 08:17:59 -0400
Links: << >>  << T >>  << A >>
On Thu, 9 Oct 2008 01:22:37 -0700 (PDT), Fred <fred__bloggs@lycos.com>
wrote:

>On 8 Oct, 13:28, Fred <fred__blo...@lycos.com> wrote:
>> I'm currently using Wireshark which in general is great software.
>> However there appears to be a problem in quoting received packet
>> checksums as good despite being seemingly good.
>>
>> Is there an alternative network sniffer which would give a clear
>> indication of packets with incorrect checksums, preferably not using
>> the WinPcap driver so to get a clear comparison.
>>
>> Has anyone else come across this problem with Wireshark with large
>> packets?
>
>The problem was mine with respect to "addding the carries" to the
>checksum where I was occasionally one out!

Those ^#$&#! checksums are indeed annoying. I'm working through an
occasional project to code a TCP/IP stack, mostly to get a better
understanding of what's really going on down there, and I feel yer pain!

-- 
Rich Webb     Norfolk, VA

Article: 135595
Subject: Re: how to share infered ROM memories in synplify?
From: Gabor <gabor@alacron.com>
Date: Thu, 9 Oct 2008 05:52:41 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 9, 7:45=A0am, richard.drae...@gmail.com wrote:
> Is there anyway to make synplify to share memories used for ROMS?
>
> More specific, assume I have this big lookup table in VHDL:
>
> =A0 function dummy( a : unsigned(7 downto 0)) return unsigned(7 downto
> 0);
> =A0 ...
>
> Which I then use in multiple locations
>
> =A0 output1 <=3D dummy( input1);
> =A0 output2 <=3D dummy( input2);
> =A0 output3 <=3D dummy( input3);
> =A0 output4 <=3D dummy( input4);
>
> Now, when no dedicated ROM cells are left synplify may try to map
> these to one memory each. I think this a a huge waste of space since
> the memories are all dual port. A more intelligent synthesis would put
> two instances in each memory. To make synplify understand this, I did
> the following changes to my code:
>
> =A0constant dummy1 : array (0 to 255) of unsigned(7 downto 0) :=3D ...
> =A0constant dummy2 : array (0 to 255) of unsigned(7 downto 0) :=3D ...
>
> Which I can use like this
>
> =A0 output1 <=3D dummy1( to_integer(input1) );
> =A0 output2 <=3D dummy1( to_integer(input2) );
> =A0 output3 <=3D dummy2( to_integer(input3) );
> =A0 output4 <=3D dummy2( to_integer(input4) );
>
> But the tool still refuses to share the memories. The only way around
> this was to generate the memories blocks with correct initialisation
> outside the tool and then import them (so the architecture does
> supports dual port ROMs). However, I generally let the tool do the
> thinking and don't like this inflexible approach.
>
> Has anyone else seen this behaviour?
> Any suggestion how to fix this would be most appreciated!

Whose FPGA are you targetting?  They should have a template
for inference of dual-port memory.  You could explicitly make
your ROM dual-ported, although this means you must also
choose the association of ROM pairs in your source code
rather than leaving it up to synthesis.

Also looking at the template may show some reason the
synthesis refuses to share memories.

Regards,
Gabor

Article: 135596
Subject: Re: Xilinx VHDL inferred RAMs
From: Gabor <gabor@alacron.com>
Date: Thu, 9 Oct 2008 05:56:13 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 9, 4:37=A0am, Rob <BertyBoos...@googlemail.com> wrote:
> On Oct 8, 11:26=A0pm, "Brad Smallridge" <bradsmallri...@dslextreme.com>
> wrote:
>
>
>
> > Hello,
>
> > I had an inferred dual port ram in my design
> > where I stuffed three 10bit std_logic_vectors
> > into a single std_logic_vector padded to 36bit.
>
> > This synthesized OK in ISE9.2 but was difficult
> > to read the individual 10bit vectors in ModelSim
> > when I expanded the ram.
>
> > So I declared a record of three 10bit std_logic_
> > vectors and connected those signals to the inputs
> > and outputs of the dual port ram. This looks great
> > in ModelSim. But the synthesis went bad and seemed
> > to place the RAM in the fabric and not in the BRAM.
>
> > So my question is can you have data inputs and data
> > outputs of non std_logic_vectors and still be able
> > to infer a dual port ram?
>
> > Brad Smallridge
> > Ai Vision
>
> My suggestion would be to keep the record but just before you connect
> the data to the memory assign each element of the record to its own
> std_logic_vector and concatenate them together as before.
>
> Rob

Or you could include the record only for simulation, not for
synthesis...

Article: 135597
Subject: Re: Reading files from CF (microblaze 7 and plb)
From: morphiend <morphiend@gmail.com>
Date: Thu, 9 Oct 2008 06:30:24 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 9, 6:45=A0am, lomtiks...@gmail.com wrote:
> On Oct 6, 5:40 am, jason.hy...@gmail.com wrote:
>
>
>
> > On Oct 6, 4:21 pm, lomtiks...@gmail.com wrote:
>
> > > Hi everyone,
>
> > > I would like to read a file from a CF card on xupv2p board using PLB
> > > and Microblaze 7.10d. There are a few questions that I am trying to
> > > answer.
>
> > > There is an xps_sysace interface controller v1.00a which seats betwee=
n
> > > the PLB and the system ace CF peripheral and has sysace v1_11_a drive=
r
> > > with functions like XSysAce_SectorRead and XSysAce_SectorWrite.
> > > However, I have not found any file system management soft like
> > > sysace_fopen and sysace_fread provided with XilFatfs FATFile System
> > > access library (xilfatfs_v1_00_a) that, from its doc, requires OPB
> > > SYSACE Interface Controller - Logicore module. How else would you rea=
d
> > > files from the a CF via PLB?
> > > Would it require modifying xilfatfs to support PLB?
>
> > > Probably I could reuse the xilfatfs_v1_00_a if I use the older MB 6
> > > with OPB bus and opb_sysace or OPB2PLB bridge and xps_sysace.
>
> > I am using MB 7.10a + plb + xps_sysace 1.00a with xilfatfs 1.00.a. I
> > also use
> > sysace_fopen, sysace_fread, sysace_fwrite for my sysace operations. So
> > I don't
> > think you need to redesign your system again.XSysAce_SectorRead and
> > XSysAce_SectorWrite are the raw operations as I remember.
>
> Thanks Goran, Jason. It was great to hear the confirmation that
> xilfatfs worked for you with with the xps_sysace 1.00a. I came back to
> the original setup with PLB and xps_sysace and fixed all the
> compilation errors that I had. I also added the ddr ram plb controller
> and able to debug the code now.
>
> I have another issue now that am trying to figure out. For some
> reason, when reading the first file, the program is hitting a
> _vector_sw_exception which I get after exiting
> int update_bufcache(int sector, unsigned char *sector_buf, int dirty)
> function. This function is called multiple times before the exception
> is made.
>
> update_bufcache() is called by read_sector(), which in turn is read
> from read_from_file()
>
> Why could this exception happen?
> I've checked my address ranges and they don't seem to overlap.
> I formatted my CF card as suggested by the xupv2p's user guide for
> 128mb with mkdosfs and placed a few images there, and the exception
> happens on the first.
> As example, I am using the slideshow code available from xilinx/
> digilent:http://www.digilentinc.com/Products/Detail.cfm?Prod=3DXUPV2P
> I disabled //XCache_EnableDCache(0xF000000F) and //
> XCache_EnableICache(0xF000000F) lines. Could it relate to the problem?
> My DDR ram has these disabled in Assembly System View too.

SW exception could be occuring because you compiled your software for
the wrong microblaze. In other words, you used instructions that were
not selected when the system was built.

Article: 135598
Subject: Re: Xilinx VHDL inferred RAMs
From: KJ <kkjennings@sbcglobal.net>
Date: Thu, 9 Oct 2008 06:35:29 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 9, 4:37=A0am, Rob <BertyBoos...@googlemail.com> wrote:
> On Oct 8, 11:26=A0pm, "Brad Smallridge" <bradsmallri...@dslextreme.com>

> > So my question is can you have data inputs and data
> > outputs of non std_logic_vectors and still be able
> > to infer a dual port ram?

>
> My suggestion would be to keep the record but just before you connect
> the data to the memory assign each element of the record to its own
> std_logic_vector and concatenate them together as before.
>

I generally create a pair of functions right along with the record
definition called to_std_logic_vector and from_std_logic_vector that
convert between the record type and std_logic_vectors.  That way
interfacing to something that requires use of std_logic_vectors is a
simple function call away...still, ISE should've been able to infer
the dual port memory in the first place.

KJ

Article: 135599
Subject: Re: Newbie question
From: andrea.cortis@gmail.com
Date: Thu, 9 Oct 2008 06:39:09 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 8, 8:51=A0pm, Masca <salin...@gmail.com> wrote:
> On 7 oct, 16:16, andrea.cor...@gmail.com wrote:
>
>
>
> > On Oct 7, 1:58=A0pm, Mike Treseler <mtrese...@gmail.com> wrote:
>
> > > andrea.cor...@gmail.com wrote:
> > > > However, I am not clear yet how do I get the results of a fpga
> > > > computation back to my PC. Is there any cable I am missing (maybe
> > > > serial)? How do I read and use this stream?
>
> > > Pg 28:
> > > On the board, LEDs 0, 1, 2, and 3 are lit,
> > > indicating that the counter is running.
>
> > > An fpga output is a high or low voltage on a device pin.
> > > The counter pins are connected to LEDs for this demo.
>
> > > Maybe your board has demos for other interfaces like rs232 or usb?
>
> > > =A0 =A0 =A0 =A0 -- Mike Treseler
>
> > Thanks Mike,
>
> > When I run the tutorial the four leds are lit indeed: so far so good.
>
> > A demo is exactly what I am looking for: a demonstration of how to
> > make a simple program that takes two variables in input (say a and b)
> > from the pc, calculates their sum c=3Da+b on the FPGA, and finally
> > passes the variable c to the pc for further computations.
> > The Spartan board I have does have a rs232 interface. Does anybody
> > know of such a demo for my board? Many thanks again.
>
> > Andrea
>
> You are looking for UART module, take a look at xilinx appnotes.
>
> You must know the board is not a coprocessor, it's a stand-alone chip.
> I guess your best bet to get started with FPGA on this board is to get
> working the displays.

Thank you, I will check this out!

-A



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