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On Oct 6, 4:48=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrote: > Nicolas Matringe <nicolas.matri...@fre.fre> writes: > > Hello all > > I have a design that occupies 65% of FFS, 85% of LUTs but 110% of slice= s. > > I can't seem to find the right options to force logic packing > > I am using ISE Webpack 10.1 SP3 > > I seem to recall having to add "-timing" to MAP's command line to get > it to do the right thing at some point in the past (even though that > seems unrelated to the problem)... =A0I don't know how to do that the > pointy-clicky way :) > > Cheers, > Martin > > -- > martin.j.thomp...@trw.com > TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://w= ww.conekt.net/electronics.html I believe the setting that usually helps in this case is "disable register ordering". I found that until I did this there was no "unrelated" packing done. Still 85% of any resource may be tough to fit. Regards, GaborArticle: 135526
girl_aj wrote: > Hello!please help me with this VHDL code. related example: http://mysite.verizon.net/miketreseler/barrel.vhd -- Mike TreselerArticle: 135527
Alex wrote: > Thank you, Frank and Peter! > > It helps and I really try to read documentation. > > Is CPLD (mine is CoolRunner-II XC2C64A) also volatile? > > ... > > p.s I also think that maybe Xilinx could produce pair of each kind of > FPGAs with only difference between these that one is SRAM based and > another is OTP (one-time programmable) so that design could be tested > on the former and when it's good enough it can be just downloaded once > on the latter.. > > Vladimir If you have a processor design and you program the processor with flash memory, do you expect to be able to move the processor to another board and have the "programmed" processor work there? Think of the FPGA configuration memory - or the programming cable - as the programming flash. If you develop the programming for the processor, you can move the flash to a second board or program that flash on a second board. Same goes for the FPGA: you can move a programmed configuration flash device from one board to another or you can add a very simple programming interface to the FPGA+flash combination on the second board. I would recommend the latter. The configuration memory chips are not volatile memory. If you look at the documentation for your kit, you'll find you can program the flash memory (are there 2 different memories on your board you can configure from?) and your board will work every time you power up. The interface to hook the programmer to those flash memories is very straightforward. You will need to buy a separate FPGA for a new design - the one from the kit is pretty much only useful on the kit board because it's soldered down. The cost and labor associated with trying to move a chip of that caliber is significantly greater than buying a new FPGA (assuming you don't have the super-high-end FPGA in a kit). In-system programming of configuration memory is so clean and straight-forward that there's no gains from an OTP part. If you need the one thing that would deliver - security - consider the Spartan-3AN which has an embedded configuration flash chip or the Virtex-5 security features that have a cypher key on the FPGA to allow crypto programming files. Chances are you don't need the security, only an external configuration memory. Look at the data sheet and XIlinx site for "configuration memory" and you may get more good info. - John_HArticle: 135528
Eric, First, this isn't the place to post pictures. You should post a link here only (read Usenet FAQ's). The Xilinx impact GUI is not very intuitive. The picture you (almost) posted shows a window for generating a file to load into the flash memory. If you want to program the FPGA directly you can just use the .bit file created in the "generate program file" step. To generate the PROM file from the window you see, either right click in the white area of the right window and select "generate file" (or something like that). Or use the Operations menu from the toolbar to do the same thing. Then look for your .mcs file to load into the flash. Regards, GaborArticle: 135529
On Oct 5, 8:09=A0am, FP <FPGA.unkn...@gmail.com> wrote: > I dont have a license for Xilinx cores like PCIe, RocketIO, DDR2 > controller and Chipscope. Can I use these cores in my project if my > friends can email me the cores generated on their PC with their > license? The tools used are Endpoint Block Plus 1.9, Virtex-5 Aurora, > MIG2.3. > > Please help. Thank you for your co-operation. I didn't think you needed a license for these on Virtex 5 as they are all built-in functions (make sure you've selected the correct core, usually containing the word "wrapper"). Or did you mean you don't have the ISE Foundation license to use CoreGen in the first place?Article: 135530
> What am I doing wrong? Find out what's in your JTAG chain. Understand which device you are actually trying to program. Figure what kind of file it needs. Read the iMPACT's user guide. /MikhailArticle: 135531
I have the same problem for recalculating the CRCs for our Virtex 4 bitstream. Has anyone got a program that can calculate those CRCs?Article: 135532
hi all respected one i am newbi to the field of edk tools as i am very much familier with ise tools of xilinx i want some of the links where i can have tutorial videos of EDK tools of xilinx in particularly about SPARTAN 3E fpga startar kit. i will be highly thankful to all help and support given by all of you.Article: 135533
On Oct 6, 2:32 pm, KJ <kkjenni...@sbcglobal.net> wrote: > Did you write the source code in the ASIC world or, as you stated > earlier, place the gates? Ah, you thought I came from layout? No, I placed the gates in schematic capture. A common way to do designs in the 90's before RTL came around. -- SvennArticle: 135534
Gabor a écrit : >> TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://www.conekt.net/electronics.html > > I believe the setting that usually helps in this case is "disable > register ordering". > I found that until I did this there was no "unrelated" packing done. > Still 85% of > any resource may be tough to fit. I finazlly completely rewrote the buffer controller for the 64 deserializers and now it fits. Thanbk you all for your ideas and tips NicolasArticle: 135535
Alex wrote: > p.s I also think that maybe Xilinx could produce pair of each kind of > FPGAs with only difference between these that one is SRAM based and > another is OTP (one-time programmable) so that design could be tested > on the former and when it's good enough it can be just downloaded once > on the latter.. Configuration serial flash memory is not that expensive compared to the price of big FPGAs. Because you are starting with FPGAs, some ideas: Sometimes it is better to use a smaller FPGA for the parts for which you need it and a standard microcontroller for the rest, including things like USB, ethernet, UART etc., which is available for about $10 (e.g. the nice STM32 series with a fast Cortex M3 core). Implementing this in a FPGA needs much logic elements and probably expensive IPs. The microcontroller provides this in tested hardware and for less money than you would need for a larger FPGA with this functions. And if you are using a microcontroller, maybe with some large integrated flash memory, you can program the FPGA from the microcontroller, with parts of the flash content of the microcontroller. Or maybe you need some external NAND flash anyway, which then can be used from the microcontroller to program the FPGA at startup. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 135536
"Gabor" <gabor@alacron.com> wrote in message news:6be815a6-5850-4221-a4c8-9a6bc3d74f14@e17g2000hsg.googlegroups.com... > I didn't think you needed a license for [PCIe, etc] on Virtex 5 > as they are all built-in functions I certainly needed a license for PCIe, but it was free, automated, and fast. PeteArticle: 135537
On 2008-10-05, bjzhangwn@gmail.com <bjzhangwn@gmail.com> wrote: > Now I use the V5-lx30t as PCIE interface,and the pcb done.When I use > the borad to download a demo for testing,and the board does't work,the > PC can't find new hardware insert, Are you getting your FPGA programmed before booting the system so the BIOS can see the device? -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 135538
On Mon, 6 Oct 2008 02:10:27 -0700 (PDT), Svenn Are Bjerkem <svenn.bjerkem@googlemail.com> wrote: >On Oct 2, 1:38 pm, KJ <kkjenni...@sbcglobal.net> wrote: >> No, but it is also unneeded and not helpful to use the negative edge >> You should be using the rising edge for the clock >> enable, using the negative edge simply cuts down by 1/2 the max clock >> rate that you can run the design at. > >Shouldn't the enable mask be available well before and after the >rising edge of the system clock? I see no other possibility than to >use the negative edge to achieve this. What happens when there is skew >on the enable input related to the clock input on a ff due to wire >lengths? It doesn't have to be available longer than the "hold time" after the clock edge; and a typical hold time specification is 0 ns. More importantly; this is understood by the timing analysis tools, which take into account the hold time, plus every individual register's clock skews and all the internal circuit delays. (It helps that the clock tree is separate from normal routing; low skew, and fast) So, within an FPGA, a simple clock period constraint will suffice to guarantee that your enable signal will meet timings; the tools will either report that timings are met (in which case, worry no more) or a list of failures (in which case, fix the problem). Stick to a single clock and you can trust the tools to account for those skews and delays. They just work. On inputs to the FPGA or outputs to another device, OR (crucially for the above debate between clock enables vs separate clocks) signals passing from one clock domain to another, analysis gets more complicated and it is harder to generate correct constraints. - BrianArticle: 135539
On Mon, 6 Oct 2008 05:32:54 -0700 (PDT), KJ <kkjennings@sbcglobal.net> wrote: >On Oct 6, 5:10 am, Svenn Are Bjerkem <svenn.bjer...@googlemail.com> >> I see no other possibility than to >> use the negative edge to achieve this. > >Then you are apparently new to digital logic design. This is not >anything FPGA specific. He may just be from a different era of digital logic design. I remember having to worry about such things when mixing different technologies, when the main tool was a wire-wrap gun (and we had to walk in the snow to work, uphill both ways) - BrianArticle: 135540
On Mon, 06 Oct 2008 07:20:38 -0500, "girl_aj" <bzerk512_ace@yahoo.com>
wrote:
>thank you sooo much for ur advice! it did solve my problem with the
>architecture of barrel_shifter!:)..thanks!...i did the same with
>architecture of ShiftLeft but i had this problem:
>Line 49. parse error, unexpected PORT, expecting OPENPAR or TICK or
>LSQBRACK
>Line 49. Label BaS_0 is ignored..i had the same problem with Lines 58 and
>67. Please spare me your time, thank you! (",)
ah...
you can't put components inside processes.
I'm guessing you come from a software background.
Most software is written as a single process (like a single C program
which can call functions etc) ... this is about to change with multicore
processors, and software folks are going to have a big shock learning
how to program processes in parallel ...
you are just hitting that learning curve a bit earlier. But it can be
easy...
VHDL operates on two levels; a parallel processing level, and a serial
processing level (like a C or Java program); but you have to keep them
separate.
So, with the barrel shifter, you wrote a little program, (which any
software coder would recognise) and called it a process.
But to do anything with it, you need to interconnect it to other
processes - these interconnections are called signals.
Do this by adding the component instances to the architecture
(not the process!) and using signals to communicate between the process
and the components...
I've started below.
There are probably other problems, but you'll come to them in due time.
One hint: look for information on VHDL signal assignment rules in
processes.
The rules are one way to get simple and give reliable communication
between processes; without them, parallel processing gets difficult and
dangerous. (There are other ways of communicating between processes, in
other languages, but this is the right one for this job)
> component barrel_shifter
> port ( w : in integer;
> x : in std_logic_vector(7 downto 0);
> y : out std_logic_vector(7 downto 0));
> end component;
>
> signal C,D: std_logic_vector(7 downto 0);
-- you'll need more signals
signal B0_in, B0_out: std_logic_vector(7 downto 0);
signal B1_in, B1_out: std_logic_vector(7 downto 0);
signal w0,w1 : integer;
>
> begin
--Remember I said you could put one OR MORE processes inside the
--architecture?
--You can put them here (outside the process)
BaS_0: barrel_shifter PORT MAP(w0,B0_in,B0_out);
-- it's much better style to use named association; easier to read
BaS_1: barrel_shifter PORT MAP( w => w1,
x => B1_in,
y => B1_out);
> process(A)
> variable z : integer := 0;
> begin
> if A(0) = '1' then
> LINE 49 HERE ... gone!
-- Here you need to assign data to the signals into the component, and
-- do something with the signal coming out.
> else
> for i in 0 to 7 loop
> C(i)<= B(i);
> end loop;
> end if;
-- and so on
> end process;
>end dataflow;
Article: 135541Hi, I am looking for an FPGA board for high speed image processing applications with large memory on board (16 GB). High speed interfaces like PCIX/PCI-Express or fiber optic are preferred on board. The FPGA should be from Xilinx. If anyone knows any such board, kindly update me. best wishes SMFArticle: 135542
Many thanks, it's very helpful indeed! :)Article: 135543
My chipscope version is 9.1, then I find it does not work. The problem as follows: I'm sure I have set the trigger condition not to be met. But every time I run it, I will get the waveform. Anyone ever had a similar problem?Article: 135544
On Oct 7, 1:11=A0am, maverick <sheikh.m.far...@gmail.com> wrote: > Hi, > I am looking for an FPGA board for high speed image processing > applications with large memory on board (16 GB). High speed interfaces > like PCIX/PCI-Express or =A0fiber optic are preferred on board. The FPGA > should be from Xilinx. If anyone knows any such board, kindly update > me. > > best wishes > SMF The only thing I can think of off the top of my head would be the ML410 or ML510 boards. The ML410 only has comes with (supports?) 256MB of DDR2 (via DIMM) and 64MB of DDR (via discrete chips). The ML510 has (2) DDR2 DIMM slots and they come populated with 512MB DIMMs, for a grand total of 1GB. Both boards have RocketI/O, GTX, and PCIe support. With regards to your memory needs, they both have CompactFlash that could be used as storage. I've successfully used 1GB cards (Sandisk ULTRA's) w/ the SystemACE. I know this still isn't 16GB of memory, though, and CF is slower than the DDR/2 memory interfaces. HTH, - MikeArticle: 135545
On Oct 7, 6:34=A0pm, morphiend <morphi...@gmail.com> wrote: > On Oct 7, 1:11=A0am, maverick <sheikh.m.far...@gmail.com> wrote: > > > Hi, > > I am looking for an FPGA board for high speed image processing > > applications with large memory on board (16 GB). High speed interfaces > > like PCIX/PCI-Express or =A0fiber optic are preferred on board. The FPG= A > > should be from Xilinx. If anyone knows any such board, kindly update > > me. > > > best wishes > > SMF > > The only thing I can think of off the top of my head would be the > ML410 or ML510 boards. > > The ML410 only has comes with (supports?) 256MB of DDR2 (via DIMM) and > 64MB of DDR (via discrete chips). > > The ML510 has (2) DDR2 DIMM slots and they come populated with 512MB > DIMMs, for a grand total of 1GB. > > Both boards have RocketI/O, GTX, and PCIe support. > > With regards to your memory needs, they both have CompactFlash that > could be used as storage. I've successfully used 1GB cards (Sandisk > ULTRA's) w/ the SystemACE. I know this still isn't 16GB of memory, > though, and CF is slower than the DDR/2 memory interfaces. > > HTH, > - Mike Thanks Mike for the reply, I have found a board from alpha-data with 16 GB of DDR DIMM memory, the board is ADX-PCI and the link is www.alpha-data.comArticle: 135546
On Oct 7, 7:34=A0am, "chenzcdyb" <zhc.c...@163.com> wrote: > My chipscope version is 9.1, then I find it does not work. > The problem as follows: > I'm sure I have set the trigger condition not to be met. > But every time I run it, I will get the waveform. > > Anyone ever had a similar problem? My understanding of the trigger in Chipscope is that it is level sensitive. So if you trigger on signal A high, you don't need an edge on signal A to trigger. Are you sure you're not generating the trigger pattern? Are you trigger signals also in the capture list so you can view their state? Regards, GaborArticle: 135547
Does anyone have any pointers to a good document describing how to apply constraints to Actel FPGAs? I'm trying to transfer a design from a Cyclone II to an Actel A3P600 (Pro-Asic 3) but am having problems applying and passing IO timing constraints relative to the internal clock. Thanks for any pointers, NialArticle: 135548
Hi, I am *real* fpga newbie After much searching on the web, I have decided to address this newsgroup with a very basic question: I would appreciate any help or pointers to any relevant faqs, information, etc. I have acquired a Spartan-3 Starter Board from Digilent connected to my PC through a JTAG 3 download cable from the parallel port. I was able to run the very first tutorial in: http://toolbox.xilinx.com/docsan/xilinx9/books/docs/qst/qst.pdf However, I am not clear yet how do I get the results of a fpga computation back to my PC. Is there any cable I am missing (maybe serial)? How do I read and use this stream? I really apologize for asking this very basic question, but I do not know who to ask. Many thanks in advance! AndreaArticle: 135549
Thanks for the quick reply, Brian. Sorry for not responding sooner. I guess my Usenet reader was slow to update, because it didn't look like anyone replied within 24 hours, so I stopped checking. > =A0http://www.xilinx.com/support/answers/13895.htm I really appreciate the link. I experimented with their search engine, to see if I could find the article you linked to, but no luck. I even used the same terms they put in their description: "signal declaration package vhdl" and it still couldn't find the article! I guess software hasn't completely replaced a knowledgeable, experienced human being ;) > =A0Are you doing anything funky with the global signal, like trying > to write to it from two places? Nothing that funky. We basically want a quick way to lay down probes, to hook up to ChipScope. Our Xilinx FAE didn't seem to understand why we wanted to use global signals. He recommended using the Chipscope Inserter thing instead :p > =A0I'd also suggest tinkering with XST/PAR options to see whether > that affects the NGDBUILD error; e.g., turn off global optimization > and turn on the keep_hierarchy flags in XST and PAR option settings. Great pointers. I'll have to give them a try later. Right now there's a ton of other things on my plate. Thanks again for the speedy and easy to understand response, Brian. It's good to know someone else has managed to use global signals with XST. Now we know it's worth the effort to making it work.
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Compare FPGA features and resources
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