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On Sun, 05 Oct 2008 22:18:00 +0200, Nicolas Matringe wrote: >I have a design that occupies 65% of FFS, 85% of LUTs but 110% of slices. Just speculating, but... do you have a long shift register, or a RAM block, that's being implemented in FFs instead of in BlockRAM or SRL16s? That 110% might be: 45% of the slices doing combinational logic, no FF 40% of slices with logic and FF 25% of slices with only the FF used (LUT used as feedthru) Clearly that last 25% is either memory or delay elements, and it might be possible to implement it in BlockRAM or SRL16 to save resources. Apologies if you've already covered that possibility. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 135501
On Oct 4, 10:25=A0am, "kadhiem_ayob" <kadhiem_a...@yahoo.co.uk> wrote: > >Hi, > >I have no such experiences and ask for the question answers: > > >is it possible that two clock system blocks with one clock running > >half of other's of same clock source don't need asynchronous input/ > >output buffers in best circuit and logic design? > > >Especially, for example Intel and AMD CPU chip's, their cache I runs > >half frequency of CPU clock and gets almost 1/2 data rate as documents > >show. > > >What is their designs standout? I know Xilinx chip has divided clock > >outputs in addition to the main clock output and never have such an > >experiences to use the technique. > > >I need a guidance and direction instructions on the subject. A book or > >a paper reference is preferred. > > >Thank you. > > >Weng > > Hi Weng, > > I am not sure about your design platform but from FPGA perspective: > If the two clocks are locked(frequency and phase), then you can consider > them synchronised assuming we trust the generating source. In this case > there is no need to make extra efforts to cross domains. The issue you > should be aware of is that they might not always be in phase as assumed a= nd > in this case any phase-sensitive logic may occasionally fail. For example= a > pulse generated in the fast domain failing to be seen by the edge of slow > clock, this commonly leads to power-up problems. If the clocks are not in > phase "by design, for some reason" then your compiler should tell you if > there is any setup or hold violations. If there is violation I will > consider them asynchronous. > > For asynchronous clocks inside FPGAs, I normally use dual clock fifos for > main crossing areas. Alternatively, you can make your crossing plans base= d > on double register synchronisation and correct data transfer > > If your clocks are external(between chips) - as I understand from your > description - then this is a different matter. Board delay differences ar= e > inevitable. All I can say is that they are asynchronous. So you better > cross domains with care or lock them together(e.g. inside an FPGA but thi= s > requires costly loop design). > > Remember a phase lock loop uses phase difference to lock two frequencies > but this doesn't usually mean they are locked with respect to absolute > phase unless extra design effort is added. > > Kadhiem =A0- Hide quoted text - > > - Show quoted text - Hi Kadhiem, thank you for your response. I am learning Intel 82496/82491 cache II controller chip and cache II SRAM chip running at 66 MHz. the book was published in 1994. I want to learn how they design 3 chips with same cycles from same clock source in the board, including Pentium processor. In the book, it doesn't mention asynchronous input/output FIFO are used. Now cache II chip controller and cache II SRAM are included in new multiprocessor. I am wondering the question: how they design the multiprocessor chip: From Intel documents, 4 processors run at 2GHz or so and all their cache I controller and cache I SRAM run at half rate (1 data rate per cycle for core and 1 data rate per 2 cycles for cache I.) If I were the designer, there might be two choices: 1. cache I controller and cache I SRAM run on clock which is main clock source divided by 2 with input/output asynchronous FIFO in the interface; 2. cache I controller and cache I SRAM run on clock which is main clock source NOT divided by 2 withOUT input/output asynchronous FIFO in the interface and with enable signal to run them at half rate. Option 1 is reliable, but has a performance penalty. It seems one cannot get the data rate with input/output asynchronous FIFO in the interface, based on my experiences. Option 2 is reliable too, but it has more energy usage, because its clock runs at double rate than option 1. But it guarantees one data per 2 cycles for cache I. It seems to me that they must use option 2 instead of option 1. I would like experts' opinion. Even though it may be a lip work. WengArticle: 135502
Hello!please help me with this VHDL code. When I checked it syntax is said
(Line 16. parse error, unexpected FOR). Don't know what's wrong here.please
do help.Thank you!
library ieee;
use ieee.std_logic_1164.all;
entity barrel_shifter is
port ( w : in std_logic;
x : in std_logic_vector(7 downto 0);
y : out std_logic_vector(7 downto 0));
end barrel_shifter;
architecture behavioral of barrel_shifter is
begin
for i in 0 to w loop
y(i) <= '0';
end loop;
z <= 0;
for i in (w+1) to 7 loop
y(i) <= x(z);
z<= z+1;
end loop;
end behavioral;
-------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ShiftLeft is
port (A, B: in std_logic_vector(7 downto 0);
E: out std_logic_vector (7 downto 0));
end ShiftLeft;
architecture dataflow of ShiftLeft is
component barrel_shifter
port ( w : in std_logic;
x : in std_logic_vector(7 downto 0);
y : out std_logic_vector(7 downto 0));
end component;
signal B,C,D: std_logic_vector(7 downto 0);
begin
if A(0) = '1' then
z=0;
BaS_i: barrel_shifter PORT MAP(z,B(7 downto 0),C(7 downto 0));
if A(1) = '1' then
z=1;
BaS_i: barrel_shifter PORT MAP(z,C(7 downto 0),D(7 downto 0));
if A(2) = '1' then
z=2;
BaS_i: barrel_shifter PORT MAP(z,D(7 downto 0),E(7 downto 0));
end if;
end if;
end if;
end dataflow;
Article: 135503On Oct 4, 9:09=A0am, Weng Tianxiang <wtx...@gmail.com> wrote: > Hi, > I have no such experiences and ask for the question answers: > > is it possible that two clock system blocks with one clock running > half of other's of same clock source don't need asynchronous input/ > output buffers in best circuit and logic design? > > Especially, for example Intel and AMD CPU chip's, their cache I runs > half frequency of CPU clock and gets almost 1/2 data rate as documents > show. > > What is their designs standout? I know Xilinx chip has divided clock > outputs in addition to the main clock output and never have such an > experiences to use the technique. > > I need a guidance and direction instructions on the subject. A book or > a paper reference is preferred. > > Thank you. > > Weng Weng, let me explain the basics: You want to drive a system with two clocks, one of them has half the frequency of the other. The important question is now: what is the phase relationship between the frequencies? Or, in simpler terms, assuming you use rising edge triggering of the flipflops and registers: What is the timing delay between rising edges of both clocks. If you are sure that there is no delay (which I would never really believe) then there is no problem. If, however there is a short systematic delay, where the rising edge of f2 is always a few ns later than the rising edge of f1, then any data transfer from f1-based to f2-based might be unreliable, because the f2 clock might pick up either the old data or the new data that had just been changed by f1. That's would be a race condition, or a hold-time violation. In the opposite direction, there is no problem, provided you still have enough set-up time available, after you lost some due to the phase difference. This all assumes that the phase relationship is known and stable. If it isn't, then you should treat the phase relationship as unknown and use asynchronous FIFOs or some handshaking. If your system is slow, you can deliberately offset the rising edges by half a period of the faster clock, which would give you well- defined timing relationship and clock margin (but you gave up half the potential speed) Peter Alfke, still there, lurking on weekends...Article: 135504
here is my new code...found a number of errors with the first...still I had
the same error with this one: "Line 12. parse error, unexpected
FOR"..please help me!:)
library ieee;
use ieee.std_logic_1164.all;
entity barrel_shifter is
port ( w : in integer;
x : in std_logic_vector(7 downto 0);
y : out std_logic_vector(7 downto 0));
end barrel_shifter;
architecture behavioral of barrel_shifter is
begin
for i in 0 to (w-1) loop
y(i) <= '0';
end loop;
variable z : integer :=0 ;
for i in (w+1) to 7 loop
y(i) <= x(z);
z:= z+1;
end loop;
end behavioral;
-------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ShiftLeft is
port (A, B: in std_logic_vector(7 downto 0);
E: out std_logic_vector (7 downto 0));
end ShiftLeft;
architecture dataflow of ShiftLeft is
component barrel_shifter
port ( w : in integer;
x : in std_logic_vector(7 downto 0);
y : out std_logic_vector(7 downto 0));
end component;
signal C,D: std_logic_vector(7 downto 0);
begin
if A(0) = '1' then
variable z : integer :=1 ;
BaS_i: barrel_shifter PORT MAP(z,B(7 downto 0),C(7 downto 0));
else
for i in 0 to 7 loop
C(i) := B(i);
exit when B(i) = NUL;
end loop;
end if;
if A(1) = '1' then
z:=1;
BaS_i: barrel_shifter PORT MAP(z,C(7 downto 0),D(7 downto 0));
else
for i in 0 to 7 loop
D(i) := C(i);
exit when C(i) = NUL;
end loop;
end if;
if A(2) = '1' then
z:=2;
BaS_i: barrel_shifter PORT MAP(z,D(7 downto 0),E(7 downto 0));
else
for i in 0 to 7 loop
E(i) := D(i);
exit when D(i) = NUL;
end loop;
end if;
end dataflow;
Article: 135505On Oct 5, 12:57=A0pm, Alex <vict...@gmail.com> wrote: > Hello All, > > I am a beginner in FPGA design and interested whether it's possible to > use FPGA after it's being programmed (I have Spartan3E 1600E > Microblaze Development Kit which is equipped with XC3S1600E) somewhere > else - not only on the kit board but with other PCBs as well. For > example, after my design is downloaded on FPGA I may wish to take this > FPGA out of socket and insert it somewhere else, to other PCB, would > it work then? (assuming that all soldering is well done) > > I guess that as it's SRAM-based FPGA it can be used only on the board > where it's programmed - is this correct? If so, then my FPGA is > suitable only for use with the kit and I can implement only one design > at a moment of time, isn't it? > > Thank you. > > Vladimir Vladimir, the FPGA must be re-loaded with its configuration data, every time you re-apply the power-supply voltages. That's what we mean when we call it "volatile" There is no way to move a configured (i.e. programmed) FPGA from one board to an other. If you design your own board, you also must provide a way to configure the FPGA on that board. Maybe you just copy the configuration circuitry from the evaluation board. Peter AlfkeArticle: 135506
Hi Weng,
When I was struggling with metastability, Philip Freidin was good
enough to point out where I was going wrong. I think his explanation
was very clear and helpful - it's at http://tinyurl.com/473w92 if you
want to have a look...
Cheers,
Simon (just giving back, and feeling good about it :)
Article: 135507Hi everyone, I would like to read a file from a CF card on xupv2p board using PLB and Microblaze 7.10d. There are a few questions that I am trying to answer. There is an xps_sysace interface controller v1.00a which seats between the PLB and the system ace CF peripheral and has sysace v1_11_a driver with functions like XSysAce_SectorRead and XSysAce_SectorWrite. However, I have not found any file system management soft like sysace_fopen and sysace_fread provided with XilFatfs FATFile System access library (xilfatfs_v1_00_a) that, from its doc, requires OPB SYSACE Interface Controller - Logicore module. How else would you read files from the a CF via PLB? Would it require modifying xilfatfs to support PLB? Probably I could reuse the xilfatfs_v1_00_a if I use the older MB 6 with OPB bus and opb_sysace or OPB2PLB bridge and xps_sysace.Article: 135508
Thank you, Frank and Peter! It helps and I really try to read documentation. Is CPLD (mine is CoolRunner-II XC2C64A) also volatile? ... p.s I also think that maybe Xilinx could produce pair of each kind of FPGAs with only difference between these that one is SRAM based and another is OTP (one-time programmable) so that design could be tested on the former and when it's good enough it can be just downloaded once on the latter.. VladimirArticle: 135509
Hi all, When instantiating the xps_sysace core, the XPS SYSACE (System ACE) Interface Controller (v1.00a) document mentions that SysACE_MPD port is formed in the IOB from SysACE_MPD_I, SysACE_MPD_0, and SysACE_MPD_T. Does it mean that I connect only SysACE_MPD to FPGA's pin and should leave SysACE_MPD_I, SysACE_MPD_0, and SysACE_MPD_T unconnected? That's what I've seen in the few posts here. The XPS System ACE Interface Controller I/O Signals table only mentions _0, _I and _T ports however. ThanksArticle: 135510
Hi, First, MicroBlaze v7 still handles OPB interface, the default is just PLB. The parameter C_USE_INTERFACE determines what interface MicroBlaze should use. I don't know the details of the XilFatfs library but I doubt that it only works with the opb based version. Have you tried using it for the xps based version? Göran <lomtikster@gmail.com> wrote in message news:e5ef2d98-e7e4-466e-87b5-274a90255a3b@k36g2000pri.googlegroups.com... > Hi everyone, > > I would like to read a file from a CF card on xupv2p board using PLB > and Microblaze 7.10d. There are a few questions that I am trying to > answer. > > There is an xps_sysace interface controller v1.00a which seats between > the PLB and the system ace CF peripheral and has sysace v1_11_a driver > with functions like XSysAce_SectorRead and XSysAce_SectorWrite. > However, I have not found any file system management soft like > sysace_fopen and sysace_fread provided with XilFatfs FATFile System > access library (xilfatfs_v1_00_a) that, from its doc, requires OPB > SYSACE Interface Controller - Logicore module. How else would you read > files from the a CF via PLB? > Would it require modifying xilfatfs to support PLB? > > Probably I could reuse the xilfatfs_v1_00_a if I use the older MB 6 > with OPB bus and opb_sysace or OPB2PLB bridge and xps_sysace. >Article: 135511
Bah, The parameter is called C_INTERCONNECT and nothing else. Göran "Göran Bilski" <goran.bilski@xilinx.com> wrote in message news:gcch95$ill1@cnn.xsj.xilinx.com... > Hi, > > First, MicroBlaze v7 still handles OPB interface, the default is just PLB. > The parameter C_USE_INTERFACE determines what interface MicroBlaze should > use. > > I don't know the details of the XilFatfs library but I doubt that it only > works with the opb based version. > Have you tried using it for the xps based version? > > Göran > > <lomtikster@gmail.com> wrote in message > news:e5ef2d98-e7e4-466e-87b5-274a90255a3b@k36g2000pri.googlegroups.com... >> Hi everyone, >> >> I would like to read a file from a CF card on xupv2p board using PLB >> and Microblaze 7.10d. There are a few questions that I am trying to >> answer. >> >> There is an xps_sysace interface controller v1.00a which seats between >> the PLB and the system ace CF peripheral and has sysace v1_11_a driver >> with functions like XSysAce_SectorRead and XSysAce_SectorWrite. >> However, I have not found any file system management soft like >> sysace_fopen and sysace_fread provided with XilFatfs FATFile System >> access library (xilfatfs_v1_00_a) that, from its doc, requires OPB >> SYSACE Interface Controller - Logicore module. How else would you read >> files from the a CF via PLB? >> Would it require modifying xilfatfs to support PLB? >> >> Probably I could reuse the xilfatfs_v1_00_a if I use the older MB 6 >> with OPB bus and opb_sysace or OPB2PLB bridge and xps_sysace. >> > >Article: 135512
Jonathan Bromley a écrit :
> On Sun, 05 Oct 2008 22:18:00 +0200, Nicolas Matringe wrote:
>
>> I have a design that occupies 65% of FFS, 85% of LUTs but 110% of slices.
>
> Just speculating, but... do you have a long shift register, or
> a RAM block, that's being implemented in FFs instead of in
> BlockRAM or SRL16s?
I don't think so. I have many small shift registers (65 8-bits
deserializers actually), and some buffers implementeds as BlockRAM. I
even changed my code to force the use of BlockRAM instead of LUTs for
small buffers (I have spare BlockRAM)
Note that 64 deserializers share a single buffer, with some arbitration
logic.
> Apologies if you've already covered that possibility.
It had been a long time since I'd used a Xilinx part so I'm a bit rusty
there.
Here is the map report file from my last iteration :
Design Summary
--------------
Number of errors: 1
Number of warnings: 0
Logic Utilization:
Number of Slice Flip Flops: 3,087 out of 4,896 63%
Number of 4 input LUTs: 4,073 out of 4,896 83%
Logic Distribution:
Number of occupied Slices: 2,571 out of 2,448 105%
(OVERMAPPED)
Number of Slices containing only related logic: 2,571 out of
2,571 100%
Number of Slices containing unrelated logic: 0 out of
2,571 0%
*See NOTES below for an explanation of the effects of unrelated
logic.
Total Number of 4 input LUTs: 4,174 out of 4,896 85%
Number used as logic: 4,073
Number used as a route-thru: 101
Number of bonded IOBs: 156 out of 158 98%
IOB Flip Flops: 151
Number of RAMB16s: 5 out of 12 41%
Number of BUFGMUXs: 1 out of 24 4%
Article: 135513Moti <motic.mail@gmail.com> writes: > Hi all, > First of all I would like to mention that I'm not familiar with video > processing at all. OK > I need to have FPGA based board that will in order to perform a > demo. That sounds a bit "cart before horse". What do you want to demo? What makes you think and FPGA is the best way to implement whatever that demo is? > For that reason I would like to buy a (ready-to-use) board that will > get a video signal (preferably by camera but it can also come from PC > or other video sources) as an input to the FPGA than I would like to > do some basic real-time processing on the video stream (Color,2D etc.) > and send the resulting video stream to an external LCD monitor. Since you have your heart set on it, I'll answer your questions below: > > I will be happy to learn the following: > > 1) I saw that there are several types of interfaces (S-video/VGA/DVI > etc.) and also several digital video protocols. What are the most easy > to use digital interfaces that I should use (both for video in/out) ? > DVI is easy for the output side, assuming you have a DVI encoder device connected to the FPGA. > 2) What type of camera should I use ? > What do you want to do with it? A board level camera with an easy interface (parallel data with sync signals and a pixel clock) is easiest. > 3) is there a proto board that you can recommend on that comply with > the answers to questions 1/2 ? > Any of these look OK: http://www.xilinx.com/products/devkits/DO-S3ADSP-VIDEO-SK-UNI-G.htm - even comes with a camera http://www.altera.com/products/devkits/altera/kit-dsp-professional.html http://www.altera.com/products/devkits/altera/kit-video-cyclone2.html I'm sure there are others as well. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 135514
Nicolas Matringe <nicolas.matringe@fre.fre> writes: > Hello all > I have a design that occupies 65% of FFS, 85% of LUTs but 110% of slices. > I can't seem to find the right options to force logic packing > I am using ISE Webpack 10.1 SP3 I seem to recall having to add "-timing" to MAP's command line to get it to do the right thing at some point in the past (even though that seems unrelated to the problem)... I don't know how to do that the pointy-clicky way :) Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 135515
On Oct 2, 1:38 pm, KJ <kkjenni...@sbcglobal.net> wrote: > On Oct 1, 4:33 pm, Svenn Are Bjerkem <svenn.bjer...@googlemail.com> > wrote: > > Pulse shortener is made with one flip-flop clocked by sys_clk taking > > qn to and with sys_clk. Both the counter and the pulse shortener is > > clocked by the negative edge of sys_clk to have the clock enable > > signal high when rising_edge on sys_clk happens. (Does using negative > > edge (inverted sys_clk) need another clock buffer?) > > No, but it is also unneeded and not helpful to use the negative edge > of the clock. You should be using the rising edge for the clock > enable, using the negative edge simply cuts down by 1/2 the max clock > rate that you can run the design at. Shouldn't the enable mask be available well before and after the rising edge of the system clock? I see no other possibility than to use the negative edge to achieve this. What happens when there is skew on the enable input related to the clock input on a ff due to wire lengths? > I have no idea why you are using any DCMs for SPI. At the start you > said that you had implemented the counter and clock enable both > running off of the system clock. In any case, it is simple to add > whatever additional clock enables you may need. What I meant was that the chip only has 2 DCM modules and 8 global clock buffers. The synthesiser used all global clock buffers and wanted more before I had integrated all my SPI modules. I then only had the DCMs to spend, but they are assigned for other purposes in the final design. > > I think I have understood the benefits of using clock enable, both > > through not having enough ressources and through different postings in > > webforums, so I sat down and coded and coded but didn't really like > > what I saw as a result. > > What did you see? Why did you not like it? When I looked at the code that I wrote to generate the two enables, one for the spi clock toggling and one for the state machine, the number of code lines were almost exceeding the number of lines in my spi code. I am maybe too minimalistic since I come from ASIC full custom design where I place my gates by hand. The synthesized logic also looked larger than nescessary, but I think the mapper reduce things for me "magically" when I generate the FPGA binary file. (I still use ISE in noob mode) > > > I have searched on the net for some hours without finding any document > > that really shows a best-practices solution on how to generate and use > > clock enables for peripheral serial devices. > > You didn't look too hard then. Symon reply also shows how to generate > and use the clock enables. Symons code was a reply to my statement .... > > > I really wonder why. It > > is not rocket science, is it? > > Not rocket science, just simple sequential boolean logic. I am in the transition from ASIC to FPGA. Re-learning threshold, you know .... -- SvennArticle: 135516
Ali <ali.arabi@gmail.com> wrote in news:e3ebcf87-0420-443e-9f57- 8318c1fd0f0b@y29g2000hsf.googlegroups.com: > I have a specific query regarding the usage of SelectIO/RocketIO > SERDES features available in Vertex 4. I want to implement OTU2 with > Virtex 4 and I wonder if this possible that use RocketIO .What I have > understood that these features are mainly applicable for high speed > serial communication protocols like PCI express, SATA etc. They also > have some special hardware features like 8B/10B encoding/decoding > logic built into the device for specific high speed serial > communication applications. > In my application, I need to add FEC data to STM64 and generate G.709 > OTU2 data format. None of the built-in features will help you with STM64 or OTU2. You'll have to roll your own framers, etc. using the FPGA fabric. This is not a difficult task, since the functions are reasonably well specified. I would feel uncomfortable even thinking about trying to meet the various jitter requirements at 10Gb/s using an on-board SERDES. You might be better off using an external SERDES made by AMCC, PMC-Sierra, etc. These will typically have a 16 bit LVDS interface to your FPGA. You still need to do your own framers, FEC, etc. Regards, AllanArticle: 135517
>here is my new code...found a number of errors with the first...still I had > the same error with this one: "Line 12. parse error, unexpected >FOR"..please help me!:) > In VHDL, it is necessary to use 'process' structures... http://www.google.co.uk/search?hl=en&q=%22vhdl+tutorial%22Article: 135518
>Thank you, Frank and Peter! > >It helps and I really try to read documentation. > >Is CPLD (mine is CoolRunner-II XC2C64A) also volatile? > >... > >p.s I also think that maybe Xilinx could produce pair of each kind of >FPGAs with only difference between these that one is SRAM based and >another is OTP (one-time programmable) so that design could be tested >on the former and when it's good enough it can be just downloaded once >on the latter.. > >Vladimir > OTP FPGAs are availaible from Actel and QuickLogic, possibly others. But they are not pin-for-pin compatible with Xilinx and Altera parts.Article: 135519
On Sun, 05 Oct 2008 18:42:57 -0500, "girl_aj" <bzerk512_ace@yahoo.com> wrote: >Hello!please help me with this VHDL code. When I checked it syntax is said >(Line 16. parse error, unexpected FOR). Don't know what's wrong here.please >do help.Thank you! For loops belong in processes. You can put one or more processes inside an architecture. I would put all the logic in the barrel_shifter architecture inside a single process. That way the initial loop setting y(*) to 0 and the second loop aren't both trying to drive y with different values, which would just create another problem. You should easily find more information about processes. Hope this helps you get started. - Brian >architecture behavioral of barrel_shifter is > begin > for i in 0 to w loop > y(i) <= '0'; > end loop; > > z <= 0; > for i in (w+1) to 7 loop > y(i) <= x(z); > z<= z+1; > end loop; >end behavioral;Article: 135520
On Mon, 6 Oct 2008 00:15:37 -0700 (PDT), lomtikster@gmail.com wrote: >Hi all, > >When instantiating the xps_sysace core, the XPS SYSACE (System ACE) >Interface Controller (v1.00a) document mentions that SysACE_MPD port >is formed in the IOB from SysACE_MPD_I, SysACE_MPD_0, and >SysACE_MPD_T. Does it mean that I connect only SysACE_MPD to FPGA's >pin and should leave SysACE_MPD_I, SysACE_MPD_0, and SysACE_MPD_T >unconnected? That's what I've seen in the few posts here. > >The XPS System ACE Interface Controller I/O Signals table only >mentions _0, _I and _T ports however. > You may find that XPS builds a "system_stub" example file which illustrates how the _0, _I and _T ports can be combined in instantiated IOB ports to connect to the pin. - BrianArticle: 135521
thank you sooo much for ur advice! it did solve my problem with the
architecture of barrel_shifter!:)..thanks!...i did the same with
architecture of ShiftLeft but i had this problem:
Line 49. parse error, unexpected PORT, expecting OPENPAR or TICK or
LSQBRACK
Line 49. Label BaS_0 is ignored..i had the same problem with Lines 58 and
67. Please spare me your time, thank you! (",)
here is my code:
library ieee;
use ieee.std_logic_1164.all;
entity barrel_shifter is
port ( w : in integer;
x : in std_logic_vector(7 downto 0);
y : out std_logic_vector(7 downto 0));
end barrel_shifter;
architecture behavioral of barrel_shifter is
begin
process(w, x)
variable z : integer :=0 ;
begin
for i in 0 to (w-1) loop
y(i) <= '0';
end loop;
for i in (w+1) to 7 loop
y(i) <= x(z);
z:= z+1;
end loop;
end process;
end behavioral;
-------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ShiftLeft is
port (A, B: in std_logic_vector(7 downto 0);
E: out std_logic_vector (7 downto 0));
end ShiftLeft;
architecture dataflow of ShiftLeft is
component barrel_shifter
port ( w : in integer;
x : in std_logic_vector(7 downto 0);
y : out std_logic_vector(7 downto 0));
end component;
signal C,D: std_logic_vector(7 downto 0);
begin
process(A)
variable z : integer := 0;
begin
if A(0) = '1' then
LINE 49 HERE BaS_0: barrel_shifter PORT MAP(z,B(7 downto 0),C(7 downto
0));
else
for i in 0 to 7 loop
C(i)<= B(i);
end loop;
end if;
if A(1) = '1' then
z:= 1;
LINE 58 HERE BaS_1: barrel_shifter PORT MAP(z,C(7 downto 0),D(7 downto
0));
else
for i in 0 to 7 loop
D(i)<= C(i);
end loop;
end if;
if A(2) = '1' then
z:= 2;
LINE 67 HERE BaS_2: barrel_shifter PORT MAP(z,D(7 downto 0),E(7 downto
0));
else
for i in 0 to 7 loop
E(i)<= D(i);
end loop;
end if;
end process;
end dataflow;
Article: 135522On Oct 6, 5:10=A0am, Svenn Are Bjerkem <svenn.bjer...@googlemail.com> wrote: > On Oct 2, 1:38 pm, KJ <kkjenni...@sbcglobal.net> wrote: > > On Oct 1, 4:33 pm, Svenn Are Bjerkem <svenn.bjer...@googlemail.com> > > wrote: > > > Pulse shortener is made with one flip-flop clocked by sys_clk taking > > > qn to and with sys_clk. Both the counter and the pulse shortener is > > > clocked by the negative edge of sys_clk to have the clock enable > > > signal high when rising_edge on sys_clk happens. (Does using negative > > > edge (inverted sys_clk) need another clock buffer?) > > > No, but it is also unneeded and not helpful to use the negative edge > > of the clock. =A0You should be using the rising edge for the clock > > enable, using the negative edge simply cuts down by 1/2 the max clock > > rate that you can run the design at. > > Shouldn't the enable mask be available well before and after the > rising edge of the system clock? Yes it should be available before the rising edge of the clock...just like every other input, the clock enable is not in any way special. > I see no other possibility than to > use the negative edge to achieve this. Then you are apparently new to digital logic design. This is not anything FPGA specific. > What happens when there is skew > on the enable input related to the clock input on a ff due to wire > lengths? The global clock nets in an FPGA are designed to have skew small enough that they can guarantee that no flip flop anywhere will arrive at a destination later than the earliest that any input could possibly switch. Yes there is skew, but no it will not cause a design issue. The reason is because the flip flops (and synchronous memories for that matter) are not at unknown locations in the die, they don't move around, they are fixed in place, which means that the entire clock net can be designed and built into the chip and can have the properties needed (i.e. effectively no skew to concern about). Not only that, but the performance of the net can be guaranteed even if you clock every single flip flop in that device off of the same clock signal. > > > I have no idea why you are using any DCMs for SPI. =A0At the start you > > said that you had implemented the counter and clock enable both > > running off of the system clock. =A0In any case, it is simple to add > > whatever additional clock enables you may need. > > What I meant was that the chip only has 2 DCM modules and 8 global > clock buffers. The synthesiser used all global clock buffers and > wanted more before I had integrated all my SPI modules. I then only > had the DCMs to spend, but they are assigned for other purposes in the > final design. > Well if you have a design that runs off of a single clock then maybe you should ask why it takes 2 DCMs and 8 global clock buffers? My guess is that you really don't have just one clock but are generating your own variants of clocks. How many clocks are really in your design? > > > I think I have understood the benefits of using clock enable, both > > > through not having enough ressources and through different postings i= n > > > webforums, so I sat down and coded and coded but didn't really like > > > what I saw as a result. > > > What did you see? =A0Why did you not like it? > > When I looked at the code that I wrote to generate the two enables, > one for the spi clock toggling and one for the state machine, the > number of code lines were almost exceeding the number of lines in my > spi code. Generating the clock enable signal consists of writing the code for a counter and decoding a particular count...both of these tasks are only a couple lines of code as I demonstrated in the previous post. > I am maybe too minimalistic since I come from ASIC full > custom design where I place my gates by hand. When doing logic design you don't place gates, you write a logic description of the functionality. Even when doing ASICs there is still such a logic description in hand long before anybody would place gates so I don't get what you're driving at here other than maybe to say that you're doing something completely different than what you're used to (i.e. logic design versus ASIC layout). > The synthesized logic > also looked larger than nescessary, but I think the mapper reduce > things for me "magically" when I generate the FPGA binary file. (I > still use ISE in noob mode) > When things don't look right, it always come back to the source code that it is written. It's not the synthesizer that is doing a poor job of implementing a good logic description, it is always (or darn near always) not a good logic description (i.e. the source code). In any case, it's difficult to imagine what is not to like about how a counter and decoder get written and implemented. > > > I really wonder why. It > > > is not rocket science, is it? > > > Not rocket science, just simple sequential boolean logic. > > I am in the transition from ASIC to FPGA. Re-learning threshold, you > know .... > Did you write the source code in the ASIC world or, as you stated earlier, place the gates? Kevin JenningsArticle: 135523
On Oct 6, 4:21=A0pm, lomtiks...@gmail.com wrote: > Hi everyone, > > I would like to read a file from a CF card on xupv2p board using PLB > and Microblaze 7.10d. There are a few questions that I am trying to > answer. > > There is an xps_sysace interface controller v1.00a which seats between > the PLB and the system ace CF peripheral and has sysace v1_11_a driver > with functions like XSysAce_SectorRead and XSysAce_SectorWrite. > However, I have not found any file system management soft like > sysace_fopen and sysace_fread provided with XilFatfs FATFile System > access library (xilfatfs_v1_00_a) that, from its doc, requires OPB > SYSACE Interface Controller - Logicore module. How else would you read > files from the a CF via PLB? > Would it require modifying xilfatfs to support PLB? > > Probably I could reuse the xilfatfs_v1_00_a if I use the older MB 6 > with OPB bus and opb_sysace or OPB2PLB bridge and xps_sysace. I am using MB 7.10a + plb + xps_sysace 1.00a with xilfatfs 1.00.a. I also use sysace_fopen, sysace_fread, sysace_fwrite for my sysace operations. So I don't think you need to redesign your system again.XSysAce_SectorRead and XSysAce_SectorWrite are the raw operations as I remember.Article: 135524
On Oct 6, 3:02=A0am, Alex <vict...@gmail.com> wrote: > Thank you, Frank and Peter! > > It helps and I really try to read documentation. > > Is CPLD (mine is CoolRunner-II XC2C64A) also volatile? > > ... > > p.s I also think that maybe Xilinx could produce pair of each kind of > FPGAs with only difference between these that one is SRAM based and > another is OTP (one-time programmable) so that design could be tested > on the former and when it's good enough it can be just downloaded once > on the latter.. > > Vladimir Xilinx actually does this for the Spartan 3A line, at least for some of the device / package varieties. Spartan 3A is volatile requiring external configuration parts. Spartan 3AN has the configuration storage built in. CPLD's are generally not volatile. CoolRunner II will hold its configuration after programming. Regards, Gabor
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