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On Feb 13, 11:48 am, jleslie48 <j...@jonathanleslie.com> wrote:
> Synthesize seems to be ok, but I get this on simulate behavior:
>
> Running Fuse ...
> fuse -intstyle ise -incremental -o jb02_tb_isim_beh.exe -prj
> jb02_tb_beh.prj -top jb02_tb
> Running : C:\Xilinx\10.1\ISE\bin\nt\unwrapped\fuse.exe -ise C:/jon/
> fpga_uarted_01/2009_01_28_jl_mod/11jlmod/uart_jb_02_goto/
> uart_jb_02_goto.ise -intstyle ise -incremental -o jb02_tb_isim_beh.exe
> -prj jb02_tb_beh.prj -top jb02_tb
> Determining compilation order of HDL files
> Analyzing VHDL file source/jb02_version_goto/New_UART_With_FIFOs/
> kcuart_tx.vhd
> Restoring VHDL parse-tree ieee.std_logic_1164 from c:/xilinx/10.1/ise/
> vhdl/hdp/nt/ieee/std_logic_1164.vdb
> Restoring VHDL parse-tree std.standard from c:/xilinx/10.1/ise/vhdl/
> hdp/nt/std/standard.vdb
> Restoring VHDL parse-tree ieee.std_logic_arith from c:/xilinx/10.1/ise/
> vhdl/hdp/nt/ieee/std_logic_arith.vdb
> Restoring VHDL parse-tree ieee.std_logic_unsigned from c:/xilinx/10.1/
> ise/vhdl/hdp/nt/ieee/std_logic_unsigned.vdb
> Restoring VHDL parse-tree unisim.vcomponents from c:/xilinx/10.1/ise/
> vhdl/hdp/nt/unisim/unisim.vdbl
> Analyzing VHDL file source/jb02_version_goto/New_UART_With_FIFOs/
> kcuart_rx.vhd
> Analyzing VHDL file source/jb02_version_goto/New_UART_With_FIFOs/
> bbfifo_16x8.vhd
> Analyzing VHDL file source/jb02_version_goto/New_UART_With_FIFOs/
> uart_tx.vhd
> Analyzing VHDL file source/jb02_version_goto/New_UART_With_FIFOs/
> uart_rx.vhd
> Analyzing VHDL file source/jb02_version_goto/data_gen.vhd
> Restoring VHDL parse-tree ieee.numeric_std from c:/xilinx/10.1/ise/
> vhdl/hdp/nt/ieee/numeric_std.vdb
> Analyzing VHDL file source/jb02_version_goto/JB_Loki_Top.vhd
> Analyzing VHDL file source/jb02_version_goto/jb02_tb.vhd
> Saving VHDL parse-tree work.kcuart_tx into c:/jon/
> fpga_uarted_01/2009_01_28_jl_mod/11jlmod/uart_jb_02_goto/isim/work/
> kcuart_tx.vdb
> Saving VHDL parse-tree work.kcuart_rx into c:/jon/
> fpga_uarted_01/2009_01_28_jl_mod/11jlmod/uart_jb_02_goto/isim/work/
> kcuart_rx.vdb
> Saving VHDL parse-tree work.bbfifo_16x8 into c:/jon/
> fpga_uarted_01/2009_01_28_jl_mod/11jlmod/uart_jb_02_goto/isim/work/
> bbfifo_16x8.vdb
> Saving VHDL parse-tree work.uart_tx into c:/jon/
> fpga_uarted_01/2009_01_28_jl_mod/11jlmod/uart_jb_02_goto/isim/work/
> uart_tx.vdb
> Saving VHDL parse-tree work.uart_rx into c:/jon/
> fpga_uarted_01/2009_01_28_jl_mod/11jlmod/uart_jb_02_goto/isim/work/
> uart_rx.vdb
> Saving VHDL parse-tree work.data_gen_pkg into c:/jon/
> fpga_uarted_01/2009_01_28_jl_mod/11jlmod/uart_jb_02_goto/isim/work/
> data_gen_pkg.vdb
> Saving VHDL parse-tree work.data_gen into c:/jon/
> fpga_uarted_01/2009_01_28_jl_mod/11jlmod/uart_jb_02_goto/isim/work/
> data_gen.vdb
> Saving VHDL parse-tree work.lprj_top into c:/jon/
> fpga_uarted_01/2009_01_28_jl_mod/11jlmod/uart_jb_02_goto/isim/work/
> lprj_top.vdb
> Saving VHDL parse-tree work.jb02_tb into c:/jon/
> fpga_uarted_01/2009_01_28_jl_mod/11jlmod/uart_jb_02_goto/isim/work/
> jb02_tb.vdb
> Starting static elaboration
> Restoring VHDL parse-tree unisim.lut4 from c:/xilinx/10.1/ise/vhdl/hdp/
> nt/unisim/unisim.vdbl
> Restoring VHDL parse-tree std.textio from c:/xilinx/10.1/ise/vhdl/hdp/
> nt/std/textio.vdb
> Restoring VHDL parse-tree ieee.vital_timing from c:/xilinx/10.1/ise/
> vhdl/hdp/nt/ieee/vital_timing.vdb
> Restoring VHDL parse-tree ieee.vital_primitives from c:/xilinx/10.1/
> ise/vhdl/hdp/nt/ieee/vital_primitives.vdb
> Restoring VHDL parse-tree unisim.vpkg from c:/xilinx/10.1/ise/vhdl/hdp/
> nt/unisim/unisim.vdbl
> Restoring VHDL parse-tree unisim.muxf5 from c:/xilinx/10.1/ise/vhdl/
> hdp/nt/unisim/unisim.vdbl
> Restoring VHDL parse-tree unisim.muxf6 from c:/xilinx/10.1/ise/vhdl/
> hdp/nt/unisim/unisim.vdbl
> Restoring VHDL parse-tree unisim.fdrs from c:/xilinx/10.1/ise/vhdl/hdp/
> nt/unisim/unisim.vdbl
> Restoring VHDL parse-tree unisim.fdre from c:/xilinx/10.1/ise/vhdl/hdp/
> nt/unisim/unisim.vdbl
> Restoring VHDL parse-tree unisim.lut2 from c:/xilinx/10.1/ise/vhdl/hdp/
> nt/unisim/unisim.vdbl
> Restoring VHDL parse-tree unisim.mult_and from c:/xilinx/10.1/ise/vhdl/
> hdp/nt/unisim/unisim.vdbl
> Restoring VHDL parse-tree unisim.muxcy from c:/xilinx/10.1/ise/vhdl/
> hdp/nt/unisim/unisim.vdbl
> Restoring VHDL parse-tree unisim.xorcy from c:/xilinx/10.1/ise/vhdl/
> hdp/nt/unisim/unisim.vdbl
> Restoring VHDL parse-tree unisim.lut3 from c:/xilinx/10.1/ise/vhdl/hdp/
> nt/unisim/unisim.vdbl
> Restoring VHDL parse-tree unisim.fde from c:/xilinx/10.1/ise/vhdl/hdp/
> nt/unisim/unisim.vdbl
> Restoring VHDL parse-tree unisim.srl16e from c:/xilinx/10.1/ise/vhdl/
> hdp/nt/unisim/unisim.vdbl
> Restoring VHDL parse-tree unisim.fd from c:/xilinx/10.1/ise/vhdl/hdp/
> nt/unisim/unisim.vdbl
> Restoring VHDL parse-tree unisim.fdr from c:/xilinx/10.1/ise/vhdl/hdp/
> nt/unisim/unisim.vdbl
> Completed static elaboration
> Fuse Memory Usage: 63060 Kb
> Fuse CPU Usage: 1327 ms
> Using precompiled package standard from library std
> Using precompiled package std_logic_1164 from library ieee
> Using precompiled package std_logic_arith from library ieee
> Using precompiled package std_logic_unsigned from library ieee
> Using precompiled package numeric_std from library ieee
> Using precompiled package textio from library std
> Using precompiled package vital_timing from library ieee
> Using precompiled package vital_primitives from library ieee
> Compiling package data_gen_pkg
> Compiling package vcomponents
> Compiling package vpkg
> Compiling architecture lut4_v of entity lut4 [\LUT4("1110010011111111")
> \]
> Compiling architecture lut4_v of entity lut4 [\LUT4("0000000110010000")
> \]
> Compiling architecture lut4_v of entity lut4 [\LUT4("0001010101000000")
> \]
> Compiling architecture lut4_v of entity lut4 [\LUT4("0000000110000000")
> \]
> Compiling architecture lut4_v of entity lut4 [\LUT4("0110011000000110")
> \]
> Compiling architecture lut4_v of entity lut4 [\LUT4("0000000000000001")
> \]
> Compiling architecture lut4_v of entity lut4 [\LUT4("1000000000000000")
> \]
> Compiling architecture lut4_v of entity lut4 [\LUT4("1011111110100000")
> \]
> Compiling architecture lut4_v of entity lut4 [\LUT4("0000000001000000")
> \]
> Compiling architecture muxf5_v of entity muxf5 [muxf5_default]
> Compiling architecture muxf6_v of entity muxf6 [muxf6_default]
> Compiling architecture fdrs_v of entity fdrs [\FDRS('0')\]
> Compiling architecture fdre_v of entity fdre [\FDRE('0')\]
> Compiling architecture lut2_v of entity lut2 [\LUT2("1000")\]
> Compiling architecture mult_and_v of entity mult_and
> [mult_and_default]
> Compiling architecture muxcy_v of entity muxcy [muxcy_default]
> Compiling architecture xorcy_v of entity xorcy [xorcy_default]
> Compiling architecture lut3_v of entity lut3 [\LUT3("00010000")\]
> Compiling architecture lut3_v of entity lut3 [\LUT3("10010100")\]
> Compiling architecture lut3_v of entity lut3 [\LUT3("11000100")\]
> Compiling architecture lut3_v of entity lut3 [\LUT3("01010100")\]
> Compiling architecture fde_v of entity fde [\FDE('0')\]
> Compiling architecture srl16e_v of entity srl16e [\SRL16E
> ("0000000000000000")\]
> Compiling architecture fd_v of entity fd [\FD('0')\]
> Compiling architecture low_level_definition of entity kcuart_tx
> [kcuart_tx_default]
> Compiling architecture fdr_v of entity fdr [\FDR('0')\]
> Compiling architecture low_level_definition of entity bbfifo_16x8
> [bbfifo_16x8_default]
> Compiling architecture macro_level_definition of entity uart_tx
> [uart_tx_default]
> Compiling architecture low_level_definition of entity kcuart_rx
> [kcuart_rx_default]
> Compiling architecture macro_level_definition of entity uart_rx
> [uart_rx_default]
> Compiling architecture rtl of entity data_gen [\data_gen(9,
> (84,200,77,32,32,32,...]
> Compiling architecture behavorial of entity lprj_top
> [lprj_top_default]
> Compiling architecture behavior of entity jb02_tb
> ERROR:Simulator - Failed to link the design. Check to see if any
> previous simulation executables are still running.
>
> I added this code:
> ------------------------------------------------------------------------
> -- A LABEL is a marker, a noop, but used for the GOTOL
> constant op_LABEL : t_ubyte := 176; --NON standard ascii char.
>
> subtype t_lbl_r is integer range 0 to 15; -- 16 labels are
> availabe for now.
>
> subtype t_lbl is t_ubyte_array(t_lbl_r);
>
> function find_label(pgm: t_ubyte_array) return t_lbl is
> constant p: t_ubyte_array (0 to pgm'length-1) := pgm;
> variable it: t_lbl;
> begin
> it := (others => 0);
> for i in 0 to (p'length-2) loop
> if (p(i)= op_label) then
> it(p(i)) := i;
> end if;
> end loop;
> return it;
> end;
>
> constant the_label: t_lbl := find_label(the_program);
>
> ------------------------------------------------------------------------------------
>
> to working and simulating code that had t_ubyte_array
> already working:
> ------------------------------------
> subtype t_ubyte is integer range 0 to 255;
> --
> -- and an array of those things.
> type t_ubyte_array is array(natural range <>) of t_ubyte;
>
> -- Function to convert the generic value into ROM-contents format
> function contents(pgm: t_ubyte_array) return t_rom is
> constant p: t_ubyte_array (0 to pgm'length-1) := pgm;
> variable it: t_rom;
> begin
> it := (others => 0);
> for i in p'range loop
> it(i) := p(i);
> end loop;
> return it;
> end;
> -----------------------------------
>
> Any ideas?
Ok, I think I got it.
Prior, I tried to simulate something with a syntax error,
I checked with the Windows Task Manager, and the *isim_beh.exe,
(in my example, jb02_tbg_isim_beh.exe) was still in the processes
section. I right-clicked on it, ended the process tree, and was then
able to restart simulation without error.
Article: 138301Hi, I suffer from a problem. when I implement the reference design from xilinx xapp485, there comes an error after implement the design, but I don't know why,can anybody tell me...? thanks in advance,I really appreciate your help. # November 1st 2006 # Timespec should be set to period plus an amount for jitter # For example : pixel clock of 90 MHz => high speed clock of 315 MHz (3175 pS). # From spreadsheet : jitter is 464 pS # 1/(3175 - (0.5*464)) => 340 MHz net rxclk35 tnm = rxclk35 ; net rxclk35not tnm = rxclk35not ; net rxclk tnm = rxclk1 ; timespec tsrx00 = period rxclk35 340 Mhz ; timespec tsrx01 = period rxclk1 tsrx00/3.5 ; timespec tsrx02 = from rxclk35 to rxclk1 = tsrx00/2 ; # receive clock input 1, bank 0 net "rxclkina1_p" loc = "B8" ; # net "rxclkina1_n" loc = "B9" ; # # channel A lvds inputs - Bank 3 net "dataina_p(3)" loc = "C8" ; # net "dataina_n(3)" loc = "D8" ; # net "dataina_p(2)" loc = "E8" ; # net "dataina_n(2)" loc = "F8" ; # net "dataina_p(1)" loc = "C7" ; # net "dataina_n(1)" loc = "D7" ; # net "dataina_p(0)" loc = "F7" ; # net "dataina_n(0)" loc = "E7" ; # inst "rx0" rloc_origin = "X18y86" ; inst "apa0" rloc_origin = "X42Y90" ; # Delete or comment this line if auto phase alignment is not being used timespec tsapa00 = from ffs(apa0/chfoundc) to ffs(apa0/sm) = tsrx00/2 ; # Delete or comment this line if autArticle: 138302
Just to bring those up to date, with a lot of Help from the folks
here (JB, RC thank you! the project is taking some shape now.
Jonathan Bromley's I/O model is really a good point for the infamous
"hello world" program that I have been trying to find. The Output
model has been expanded to this now:
JSEB_DATA_GENERATOR: entity work.data_gen
generic map
( PC_bits => 9
, the_program =>
-- Long startup delay
op_DELAY & 200
& --2 bytes long
-- Welcome message
op_MESSAGE & tua(LF& " Lprj version jb02-04-labels
added"&LF) & EOM &
op_LABEL & 01 &
op_MESSAGE & tua("Enter continuation character:"&LF) &
EOM &
-- Wait for a "+" from the keyboard...
op_WAIT_FOR_CHAR & tua("+") &
-- and then print another message
op_LABEL & 02 &
op_MESSAGE & tua("abcdefghijklmnopqrstuvwxyz"&LF) & EOM
&
-- Wait for a "-" from the keyboard
op_WAIT_FOR_CHAR & tua("-") &
op_MESSAGE &tua("just pressed a '-' sign!!!!"&LF) &EOM
&
-- and then go back to the beginning! - no delay this
time.
op_GOTOL & 02 & -- ok here is the new gotol, it will
jump to the label rather
-- than the array index, so the length
of the strings no longer
-- needs to be calculated (thank
god...)
--
-- this is a dead line now, cant get
here and GOTOL is much more.
-- useful.
op_GOTO & 29 & -- 27 is first op:2+ 2nd op:29 old
value was:2
-- should be 29, lets try a mistake at
26
op_HALT
)
port map
( clock => SYSTEM_CLOCK
, reset => initialize_data_gen -- NOT USED in the real
hardware? - fixed, hooked to initialize_data_gen
, timer => UART_EN_16_x_BAUD
, tx_data => TX_DATA_IN
, tx_valid => tx_valid
, tx_ready => tx_ready
, rx_data => RX_DATA_OUT
, rx_valid => RX_BUFFER_DATA_PRESENT
, rx_ready => rx_ready
, reset_out => UART_RESET_BUFFER
, halted => halted
, error_cond => error_cond_main
);
all is working, now, and I'm quite happy with this layout. I imagine
after every op_MESSAGE I will be placing a
op_WAIT_FOR_LABEL in the future. My UART mesages will all reside in
this packet, with the Top process changing a LABEL_TO_BE SENT byte and
zeroing it out on completion. In this way My entire array of canned
output messages can be called up on demand. Next up is the
LABEL_WAIT model, and then onto dynamic messaging (aka, type 5 values
into the RS232, and send the message, "the values are, x1, x2, x3, x4,
x5 and the sum is yyy").
Thanks to all on this website for their help on this journey!
Sincerely,
Jon
Article: 138303Hi, I have the need to capture a 8-bit parallel data with its associated clock (Min 1 MHz / max 8 MHz). The clock of the FPGA is 64 MHz. How to take the 8-bit parallel with clock into domain of the fpga ? I had thought of a fifo but I do not want to use a fifo with dual clock.Then you need a circuit input How to capture external data and then write in the fifo to 64 MHz ? Do you have any example in VHDL ? Thanks. Kappa.Article: 138304
On Sat, 14 Feb 2009 10:12:54 +0100, "Kappa" wrote:
>I have the need to capture a 8-bit parallel data with its associated clock
>(Min 1 MHz / max 8 MHz). The clock of the FPGA is 64 MHz.
>
>How to take the 8-bit parallel with clock into domain of the fpga ?
>
>I had thought of a fifo but I do not want to use a fifo with dual clock.
Why not? You can get a reliable dual-clock FIFO from
your FPGA tool easily.
>How to capture external data and then write in the fifo to 64 MHz ?
>
>Do you have any example in VHDL ?
Yes :-)
In your case, the maximum input rate is only 1/8 of the FPGA clock.
So it would be easy to oversample the clock. However, you need
to be careful because the input clock might have an asymmetric
mark/space ratio. Consequently, it's better to toggle a flag
signal on every input clock, and oversample that toggling flag.
Here's how it might work:
-- INPUT CLOCK DOMAIN: Use it to capture
-- the data, and toggle a flag signal
process (data_clock, async_reset)
begin
if async_reset = '1' then
flag <= '0';
data_register <= (others => '0');
elsif rising_edge(data_clock) then
data_register <= data_input;
flag <= not flag;
end if;
end process;
-- FPGA CLOCK DOMAIN: Detect the flag change,
-- and use it to create a data-enable signal.
-- The flag must be resynchronised and delayed
-- by a chain of at least 2 flip-flops; 3 is better.
process (FPGA_clock, async_reset)
begin
if async_reset = '1' then
new_data <= '0';
resync_flag_0 <= '0';
resync_flag_1 <= '0';
resync_flag_2 <= '0';
elsif rising_edge(FPGA_clock) then
resync_flag_0 <= flag;
resync_flag_1 <= resync_flag_0;
resync_flag_2 <= resync_flag_1;
new_data <= resync_flag_2 xor resync_flag_1;
end if;
end process;
Your main FPGA logic should now take the contents
of "data_register" on every clock cycle when "new_data"
is asserted....
-- USEFUL DATA PROCESSING:
process(FPGA_clock)
begin
if rising_edge(FPGA_clock) then
if new_data = '1' then
-- DO SOMETHING WITH THE DATA IN data_register
-- (for example, write it to a FIFO)
end if;
end if;
end process;
PLEASE NOTE that this method will work ONLY if the input
data clock is much slower than the FPGA clock.
Exercises for student, to make the assignment look better:
1) Don't forget all the necessary VHDL declarations.
2) Determine the maximum input frequency for which this
design will reliably capture the input data.
3) Suggest design modifications that would increase
the maximum frequency you calculated in (2).
Determine the ultimate maximum input frequency
that could reliably be captured using this technique.
4) Give a rigorous proof that this design will not
create a spurious data item immediately after reset.
5) Determine the mean time to metastability failure of
this design, in an FPGA of your choice, with
FPGA_clock=64MHz and data_clock=8MHz.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 138305Hi Jonathan Thanks for your replay. > You can get a reliable dual-clock FIFO from your FPGA tool easily. Input (8-bit with clock) can be connected / disconnected at hot. There are problems with this system? >>How to capture external data and then write in the fifo to 64 MHz ? >> >>Do you have any example in VHDL ? > > Yes :-) Thanks > In your case, the maximum input rate is only 1/8 of the FPGA clock. > So it would be easy to oversample the clock. However, you need > to be careful because the input clock might have an asymmetric > mark/space ratio. Consequently, it's better to toggle a flag > signal on every input clock, and oversample that toggling flag. OK. > Here's how it might work: > > -- INPUT CLOCK DOMAIN: Use it to capture > -- the data, and toggle a flag signal > process (data_clock, async_reset) > begin > if async_reset = '1' then > flag <= '0'; > data_register <= (others => '0'); > elsif rising_edge(data_clock) then > data_register <= data_input; > flag <= not flag; > end if; > end process; > > -- FPGA CLOCK DOMAIN: Detect the flag change, > -- and use it to create a data-enable signal. > -- The flag must be resynchronised and delayed > -- by a chain of at least 2 flip-flops; 3 is better. > process (FPGA_clock, async_reset) > begin > if async_reset = '1' then > new_data <= '0'; > resync_flag_0 <= '0'; > resync_flag_1 <= '0'; > resync_flag_2 <= '0'; > elsif rising_edge(FPGA_clock) then > resync_flag_0 <= flag; > resync_flag_1 <= resync_flag_0; > resync_flag_2 <= resync_flag_1; > new_data <= resync_flag_2 xor resync_flag_1; > end if; > end process; > > Your main FPGA logic should now take the contents > of "data_register" on every clock cycle when "new_data" > is asserted.... > > -- USEFUL DATA PROCESSING: > process(FPGA_clock) > begin > if rising_edge(FPGA_clock) then > if new_data = '1' then > -- DO SOMETHING WITH THE DATA IN data_register > -- (for example, write it to a FIFO) > end if; > end if; > end process; > > PLEASE NOTE that this method will work ONLY if the input > data clock is much slower than the FPGA clock. Yes, the clock reaches a maximum 8 MHz. > Exercises for student, to make the assignment look better: > 1) Don't forget all the necessary VHDL declarations. > 2) Determine the maximum input frequency for which this > design will reliably capture the input data. > 3) Suggest design modifications that would increase > the maximum frequency you calculated in (2). > Determine the ultimate maximum input frequency > that could reliably be captured using this technique. > 4) Give a rigorous proof that this design will not > create a spurious data item immediately after reset. > 5) Determine the mean time to metastability failure of > this design, in an FPGA of your choice, with > FPGA_clock=64MHz and data_clock=8MHz. Thanks. Kappa.Article: 138306
On Sat, 14 Feb 2009 11:55:56 +0100, "Kappa" wrote: >Input (8-bit with clock) can be connected / disconnected at hot. There are >problems with this system? There are ALWAYS problems with hot-plugging. You must find some way to avoid spurious clocks on connect/disconnect. This is a tricky analog problem. Do you have some pins on the connector that are guaranteed to mate after, and unmate before, all other pins? If so, you can use them to establish a "connection valid" signal. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 138307
Hi Jonathan,
> There are ALWAYS problems with hot-plugging. You must find some
> way to avoid spurious clocks on connect/disconnect. This is
> a tricky analog problem. Do you have some pins on the
> connector that are guaranteed to mate after, and unmate
> before, all other pins? If so, you can use them to establish
> a "connection valid" signal.
The input is SAT Tuner. Clock output is invalid if transponder is not found.
In other case the input is parallel port for parallel transport stream.
I have made some change on code. This code could be ok to connect input of
fifo ?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity synchronizer is
port (
ce : in std_logic;
clk : in std_logic;
rst : in std_logic;
dclk : in std_logic;
din : in std_logic_vector (7 downto 0);
we : out std_logic;
dout : out std_logic_vector (7 downto 0)
);
end synchronizer;
architecture Behavioral of synchronizer is
-- Internal Signal
signal flag : std_logic;
signal new_data : std_logic;
signal we_int : std_logic;
signal resync : std_logic_vector(2 downto 0);
signal din_int : std_logic_vector(7 downto 0);
signal dout_int : std_logic_vector(7 downto 0);
begin
-- INPUT CLOCK DOMAIN: Use it to capture
-- the data, and toggle a flag signal
process (dclk, rst)
begin
if rst = '1' then
flag <= '0';
din_int <= (others => '0');
elsif rising_edge(dclk) then
flag <= not flag;
din_int <= din;
end if;
end process;
-- FPGA CLOCK DOMAIN: Detect the flag change,
-- and use it to create a data-enable signal.
-- The flag must be resynchronised and delayed
-- by a chain of at least 2 flip-flops; 3 is better.
process (ce, clk, rst)
begin
if ce = '1' then
if rst = '1' then
new_data <= '0';
resync <= "000";
elsif rising_edge(clk) then
resync(0) <= flag;
resync(1) <= resync(0);
resync(2) <= resync(1);
new_data <= resync(2) xor resync(1);
end if;
end if;
end process;
--Your main FPGA logic should now take the contents
--of "data_register" on every clock cycle when "new_data"
--is asserted....
-- USEFUL DATA PROCESSING:
process(ce, clk, rst)
begin
if ce = '1' then
if rst = '1' then
we_int <= '0';
dout_int <= (others => '0');
elsif rising_edge(clk) then
if new_data = '1' then
we_int <= '1';
dout_int <= din_int;
else
we_int <= '0';
dout_int <= dout_int;
end if;
end if;
end if;
end process;
-- Output Data
dout <= dout_int;
we <= we_int;
end Behavioral;
Thanks for your patience.
Kappa.
Article: 138308On Thu, 12 Feb 2009 12:39:46 -0800 (PST), giuseppe.marullo@iname.com wrote: >Yes, >this project is very interesting, I could end up using it, the only >"problem" is that I don't have the board and should port it to mine, >oh I am not a big fan of Java but if the client is good enough, at >that price... > >I could add the protection stuff, could you please share your design? >I think is the usual serie resistor with a double fat zeners to clip >to a tolerable level the input. Parts used? > >Giuseppe I just bought one of these boards , fits directly on the S3 Board. And is only $20 http://oakmicros.com/shop/product_info.php?products_id=50 CarstenArticle: 138309
Howdy All,
wondering if anybody run in to this problem and might know
how to solve it.
I am registering a interrupt handler. Setting up the interrupt
controller, enabling interrupts. I start my HW wich eventually
generates an interrupt.
Now is the weired thing: Instead of executing my interrupt handler,
it seems like microblaze starts execution from the beginning
(address zero).
btw, this is standalone system ...
XInterruptHandler my_handler(void *CallbackRef)
{
stl(INT_IAR, 0x07);
printf("\n\r\nRecieved Interrupt 1 ...\n\n\r");
return;
}
main() {
microblaze_register_handler( (XInterruptHandler)my_handler, (void *)
0);
stl(INT_IER, 0x00000007);
stl(INT_MER, 0x00000003);
microblaze_enable_interrupts();
...
}
Any ideas or suggestions ?
Thanks,
rudi
Article: 138310Great info, thanks. They have a User guide for the Logic Analyzer: http://oakmicros.com/content/downloads/View-document/Logic-Analyzer-User-Guide.html Carsten, do you mind sharing any .sla and or .slp ? I would like to travel around the gui with something on the screen. In the meantime I tried to create the bitfile for my board (a Xylo-LM with a Spartan3E-500) but got a bunch of errors. I have found the Digilent Spartan3 board, but it is the 400K version, so I need to fix the problem with the WebISE, I need the correct bitfile anyway. I hope that this board can be used as well. Giuseppe giuseppe.marullo@nospaminame.comArticle: 138311
On Feb 15, 8:23=A0pm, luudee <rudolf.usselm...@gmail.com> wrote:
> Howdy All,
>
> wondering if anybody run in to this problem and might know
> how to solve it.
>
> I am registering a interrupt handler. Setting up the interrupt
> controller, enabling interrupts. I start my HW wich eventually
> generates an interrupt.
>
> Now is the weired thing: Instead of executing my interrupt handler,
> it seems like microblaze starts execution from the beginning
> (address zero).
>
> btw, this is standalone system ...
>
> XInterruptHandler my_handler(void *CallbackRef)
> {
> stl(INT_IAR, 0x07);
> printf("\n\r\nRecieved Interrupt 1 ...\n\n\r");
> return;
>
> }
>
> main() {
> microblaze_register_handler( (XInterruptHandler)my_handler, (void *)
> 0);
> stl(INT_IER, 0x00000007);
> stl(INT_MER, 0x00000003);
> microblaze_enable_interrupts();
>
> ...
>
> }
>
> Any ideas or suggestions ?
>
> Thanks,
> rudi
yes
one
suggesion
ALWAYS before using stl(xxxx) in your code,
take KNOWN GOOD WORKING example code first.
\EDK\sw\XilinxProccessorIPlib\drivers\intc_v1_11_a\examples
\xintc_example.c
would be the file to test out first.
if that works, then proceed from that code step by step to the code
you want
if that doesnt work, then fix your system until it works or open a
webcase
Antti
Article: 138312On Feb 16, 2:13=A0am, Antti <Antti.Luk...@googlemail.com> wrote: > > yes > one > suggesion > > ALWAYS before using stl(xxxx) in your code, > take KNOWN GOOD WORKING example code first. > > \EDK\sw\XilinxProccessorIPlib\drivers\intc_v1_11_a\examples > \xintc_example.c > > would be the file to test out first. > if that works, then proceed from that code step by step to the code > you want > > if that doesnt work, then fix your system until it works or open a > webcase > > Antti Yeah, I should have probably mentioned that I wasted several hours trying to get the XINTC API to work. Basically I had *exactly* the same results with it. I thought I was doing something wrong, and decided to go to the lower level. That's when I found out that no matter what I do, it *does* get my interrupt, BUT does not execute my handler, but apparently is taking the reset vector ... I have traced this problem now for two days, and I am certain that I set everything up the way EDK and User docs suggest. I can poll the ISR register (and disable microblaze interrupt) and see the interrupts happen ... Thanks, rudiArticle: 138313
Hi All, A new beta version of the TimingAnalyzer is available. Since it taking much longer than expected to finish the program, a few changes have occurred. 1) There is only one version now that includes all the features that are functional to this point. You can download and use without any restrictions. 2) A new license simply says that the TimingAnalyzer will always be completely free to use with no limitations for personal and academic use. There will be a one time charge for commercial use when the final release occurs. Expected cost will be very low compared to the competition. www.timing-diagrams.com As always, feedback and suggestions are welcome. This way, you can shape the look and feel of the TimingAnalyzer. Regards, DanArticle: 138314
On Sat, 14 Feb 2009 13:33:10 +0100, "Kappa" wrote:
>The input is SAT Tuner. Clock output is invalid if transponder is not found.
>In other case the input is parallel port for parallel transport stream.
I don't understand this. I thought you said it was to be
hot-swappable. What do you mean by "Clock output is invalid"?
How do you know if the "transponder is not found"?
>I have made some change on code.
> process (ce, clk, rst)
> begin
> if ce = '1' then
Do you REALLY intend that reset should be
disabled if "ce" is false? The code you
presented doesn't match the standard
synchronous template. It is conventional
to use
process(clock, reset)
begin
if reset = '1' then
...... reset actions ......
elsif rising_edge(clock) then
if ce = '1' then
..... clocked actions enabled by ce ......
end if;
end if;
end process;
> resync(0) <= flag;
> resync(1) <= resync(0);
> resync(2) <= resync(1);
Good idea, but this is even better:
resync <= resync(1 downto 0) & flag;
I didn't use arrays in my example code because I did
not know how familiar you are with VHDL. The array
solution is much better.
> -- USEFUL DATA PROCESSING:
> process(ce, clk, rst)
> begin
> if ce = '1' then
Same question about this use of "ce".
> if new_data = '1' then
> we_int <= '1';
> dout_int <= din_int;
> else
> we_int <= '0';
> dout_int <= dout_int;
> end if;
Looks good to me. Maybe it's even easier -
could you use "new_data" directly as a
write-enable for the FIFO?
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 138315On Fri, 13 Feb 2009 12:24:36 -0800 (PST), jleslie48 wrote: >expanded to this now: > op_GOTOL & 02 & -- ok here is the new gotol, it will > -- jump to the label rather > -- than the array index, so the length > -- of the strings no longer > -- needs to be calculated Well done for making this work - I reckon it's a good "rite of passage" and you should be able to make progress with reasonable confidence now. However, I question the motivation. Wouldn't it have been way, way easier to write a little "compiler" to do all the necessary string length and address calculations in advance, generating a piece of VHDL code (or a Xilinx memory-format file) to graft into your project, so that you could stick with the nice simple "goto address" hardware? Scanning the program to find its labels must be a non-trivial overhead. >all is working, now, and I'm quite happy with this layout. I imagine >after every op_MESSAGE I will be placing a >op_WAIT_FOR_LABEL in the future. My UART mesages will all reside in >this packet, with the Top process changing a LABEL_TO_BE SENT byte and >zeroing it out on completion. In this way My entire array of canned >output messages can be called up on demand. Consider a redirection table, where the addresses of the various strings are stored in a simple lookup table indexed by label number. > then onto dynamic messaging (aka, type 5 values >into the RS232, and send the message, "the values are, >x1, x2, x3, x4, >x5 and the sum is yyy"). I still don't understand the ideological barrier to using a soft-core CPU in the FPGA. However cunning your programmable functionality, you'll soon enough encounter a problem where it's not cunning enough, but real SOFTWARE would easily do what you need. The CPU doesn't need to be big or clever - but it *does* need to be a real computing engine, which is unlikely to be true of your string-indexing machine.... Picoblaze is FREE, by almost any reasonable measure. Having such a soft-core on your FPGA doesn't call your manhood into question, nor does it inhibit your ability to do very fast stuff (far too fast for a CPU) elsewhere on the FPGA. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 138316
Hello, I created an ipcore plb_usb_link (with edk's wizard) interfacing the plb and added it to the edk reference design.While running generate bitstream, synthesis stage runs through, but implementation stage aborts with ERROR:NgdBuild:604. --------------------------- ERROR:NgdBuild:604 - logical block 'plb_usb_link_0/plb_usb_link_0/ USER_LOGIC_I' with type 'user_logic' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'user_logic' is not supported in target 'spartan3e'. --------------------------- My userdefined ipcore is directory structure : -plb_usb_link_v1_20a |-data |-devl |-hdl ||verilog\usb_libk.v,USER_LOGIC.v ||vhdl\plb_usb_link.vhd |-netlist\plb_usb_link.ngc can experts help me in knowing what is the real problem and how do I have to solve it ? I'm working under edk10.1.03(nt) ,Apps Version Build:EDK_K_SP3.6+0 and ise version 10.1 with service packs. The reference design is not the problem, because it's already working in other designs. Thanks in advance, Regards, AliArticle: 138317
On Feb 15, 11:48=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On Fri, 13 Feb 2009 12:24:36 -0800 (PST), jleslie48 wrote:
> >expanded to this now:
> > =A0 op_GOTOL & 02 & -- ok here is the new gotol, it will
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- jump to the label rather
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- than the array index, so the len=
gth
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- of the strings no longer
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- needs to be calculated
>
> Well done for making this work - I reckon it's a good
> "rite of passage" and you should be able to make progress
> with reasonable confidence now.
>
> However, I question the motivation. =A0Wouldn't it have
> been way, way easier to write a little "compiler" to do
> all the necessary string length and address calculations
> in advance, generating a piece of VHDL code (or a Xilinx
> memory-format file) to graft into your project, so that
> you could stick with the nice simple "goto address"
> hardware? =A0Scanning the program to find its labels
> must be a non-trivial overhead.
>
> >all is working, now, and I'm quite happy with this layout. =A0I imagine
> >after every op_MESSAGE I will be placing a
> >op_WAIT_FOR_LABEL in the future. =A0My UART mesages will all reside in
> >this packet, with the Top process changing a LABEL_TO_BE SENT byte and
> >zeroing it out on completion. =A0In this way My entire array of canned
> >output messages can be called up on demand.
>
> Consider a redirection table, where the addresses of
> the various strings are stored in a simple lookup table
> indexed by label number.
>
> > then onto dynamic messaging (aka, type 5 values
> >into the RS232, and send the message, "the values are,
> >x1, x2, x3, x4, >x5 and the sum is yyy").
>
> I still don't understand the ideological barrier to using
> a soft-core CPU in the FPGA. =A0However cunning your
> programmable functionality, you'll soon enough encounter
> a problem where it's not cunning enough, but real SOFTWARE
> would easily do what you need. =A0The CPU doesn't need to be
> big or clever - but it *does* need to be a real computing
> engine, which is unlikely to be true of your string-indexing
> machine.... =A0
> Picoblaze is FREE, by almost any reasonable measure. =A0Having
> such a soft-core on your FPGA doesn't call your manhood into
> question, nor does it inhibit your ability to do very fast
> stuff (far too fast for a CPU) elsewhere on the FPGA.
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.
Nice, that you Jonathan suggest soft-core cpu
i been wondering some times already why someone does
ever want to send uart data using a statemachine.
for my februrary issue i did some research about FPGA
vendor small soft-core cpus
funnily the winner seems to be Actel CoreABC, it has
most choices to finetune the core, lots of commands
are optional, data width is programmable, externel
bus width is progrmmable, index loop counter
is optional with variable width, instruction widht is
also variable (well the fixed part is 6 bits + depend
on parameters), the rom generator for hard (logic
tile mapped) uses "dont cares" to make the rom
smaller. It is also the ONLY small soft-core that
is COMPLETLY integrated with the IDE, small
systems can be generated without writing single
line of hdl code, just mouse click in the smart
design, and enter the asm instructions in the
embedded editor.
uart hello ("TEST...",13,10);
takes 398 actel versatiles or 206 spartan-3
slices (would be smaller if using bram rom)
also nice with coreABC is the standard
APB bus so can use APB peripherals:)
of course picoblaze or some other core
are not so much more complicated, and
defenetly a recommended way todo
small serial port code
Antti
Article: 138318Make sure you have include your vhdl/verilog files in your plb_usb_link_v1_20a.pao file and include plb_usb_link.ngc in plb_usb_link_v1_20a.ngo file in data folder. set these options in your mpd file OPTION STYLE = MIX OPTION RUN_NGCBUILD = TRUEArticle: 138319
On Feb 15, 9:27=A0pm, luudee <rudolf.usselm...@gmail.com> wrote: > On Feb 16, 2:13=A0am, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > > > yes > > one > > suggesion > > > ALWAYS before using stl(xxxx) in your code, > > take KNOWN GOOD WORKING example code first. > > > \EDK\sw\XilinxProccessorIPlib\drivers\intc_v1_11_a\examples > > \xintc_example.c > > > would be the file to test out first. > > if that works, then proceed from that code step by step to the code > > you want > > > if that doesnt work, then fix your system until it works or open a > > webcase > > > Antti > > Yeah, I should have probably mentioned that I wasted several > hours trying to get the XINTC API to work. Basically I had > *exactly* the same results with it. I thought I was doing > something wrong, and decided to go to the lower level. That's > when I found out that no matter what I do, it *does* get my > interrupt, BUT does not execute my handler, but apparently > is taking the reset vector ... > > I have traced this problem now for two days, and I am certain > that I set everything up the way EDK and User docs suggest. > I can poll the ISR register (and disable microblaze interrupt) > and see the interrupts happen ... > > Thanks, > rudi 1) if the original sample code did not work, then there was no reason to try "low level method".. you really just wasted time next: 2) run EDK/BSB select some board, select MB, no cache, 64K BRAM, UART lite, INTC, no EXT RAM build it. do not make any changes to the code except UCF file run INTC self test and demo code 3) if [2] did not work, then get some Xilinx own board and use 100% xilinx EDK reference system as base for testing AnttiArticle: 138320
Hi Jonathan, Thanks for your help ... > >The input is SAT Tuner. Clock output is invalid if transponder is not fo= und. > >In other case the input is parallel port for parallel transport stream. > > I don't understand this. =A0I thought you said it was to be > hot-swappable. =A0 Yes, the hot-swappable is used for external input, parallel port, when not using an internal tuner. The Tuner is an option. > What do you mean by "Clock output is invalid"? The clock may be random sweep and the duty cycle not is 50%. > How do you know if the "transponder is not found"? The tuner can indicate if there is a valid transponder. > >I have made some change on code. > > =A0process (ce, clk, rst) > > =A0begin > > =A0if ce =3D '1' then > > Do you REALLY intend that reset should be > disabled if "ce" is false? =A0The code you > presented doesn't match the standard > synchronous template. =A0It is conventional > to use > > =A0 process(clock, reset) > =A0 begin > =A0 =A0 if reset =3D '1' then > =A0 =A0 =A0 ...... reset actions ...... > =A0 =A0 elsif rising_edge(clock) then > =A0 =A0 =A0 if ce =3D '1' then > =A0 =A0 =A0 =A0 ..... clocked actions enabled by ce ...... > =A0 =A0 =A0 end if; > =A0 =A0 end if; > =A0 end process; Yes. Thanks. I know some VHDL, I wrote something, but some things I did not clear. Asked for help to ask someone who knows more than me. > > =A0 =A0resync(0) <=3D flag; > > =A0 =A0resync(1) <=3D resync(0); > > =A0 =A0resync(2) <=3D resync(1); > > Good idea, but this is even better: > > =A0 =A0resync <=3D resync(1 downto 0) & flag; > > I didn't use arrays in my example code because I did > not know how familiar you are with VHDL. =A0The array > solution is much better. OK ... :-) ... > > =A0-- USEFUL DATA PROCESSING: > > =A0process(ce, clk, rst) > > =A0begin > > =A0 if ce =3D '1' then > > Same question about this use of "ce". OK ... I replace the code ... > > =A0 =A0 if new_data =3D '1' then > > =A0 =A0 =A0we_int <=3D '1'; > > =A0 =A0 =A0dout_int <=3D din_int; > > =A0 =A0 else > > =A0 =A0 =A0we_int <=3D '0'; > > =A0 =A0 =A0dout_int <=3D dout_int; > > =A0 =A0 end if; > > Looks good to me. =A0Maybe it's even easier - > could you use "new_data" directly as a > write-enable for the FIFO? Yes. Good idea ... try as I have said ... Thanks. Kappa.Article: 138321
Hi Jonathan, This is a review ... library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity synchronizer is port ( ce : in std_logic; clk : in std_logic; rst : in std_logic; dclk : in std_logic; din : in std_logic_vector (7 downto 0); dout : out std_logic_vector (7 downto 0); vout : out std_logic ); end synchronizer; architecture Behavioral of synchronizer is -- Internal Signal signal flag : std_logic; signal new_data : std_logic; signal resync : std_logic_vector(2 downto 0); signal din_int : std_logic_vector(7 downto 0); begin -- INPUT CLOCK DOMAIN: Use it to capture -- the data, and toggle a flag signal process (dclk, rst) begin if rst = '1' then flag <= '0'; din_int <= (others => '0'); elsif rising_edge(dclk) then flag <= not flag; din_int <= din; end if; end process; -- FPGA CLOCK DOMAIN: Detect the flag change, -- and use it to create a data-enable signal. -- The flag must be resynchronised and delayed -- by a chain of at least 2 flip-flops; 3 is better. process (ce, clk, rst) begin if rst = '1' then resync <= (others => '0'); new_data <= '0'; elsif rising_edge(clk) then if ce = '1' then resync <= resync(1 downto 0) & flag; new_data <= resync(2) xor resync(1); end if; end if; end process; --Your main FPGA logic should now take the contents --of "data_register" on every clock cycle when "new_data" --is asserted.... -- USEFUL DATA PROCESSING: process(ce, clk, rst) begin if rst = '1' then dout <= (others => '0'); vout <= '0'; elsif rising_edge(clk) then if ce = '1' then if new_data = '1' then dout <= din_int; vout <= '1'; else vout <= '0'; end if; end if; end if; end process; end Behavioral; I did not understand this step: > > if new_data = '1' then > > we_int <= '1'; > > dout_int <= din_int; > > else > > we_int <= '0'; > > dout_int <= dout_int; > > end if; > Looks good to me. Maybe it's even easier - > could you use "new_data" directly as a > write-enable for the FIFO? I have to put "din_int" directly to the FIFO and use "new_data" to "we"? Thanks. Kappa.Article: 138322
Currently i am doing my final year project on
xilinx cpld 9572
How do we can access registers in this cpld using vhdl .......
Article: 138323Hi everyone. I've been designing for spartan3 for the last few years but I'm just starting on a virtex 5 project. I am surprised at the incredible lack of decoupling XILINX now recomend. Does anyone has experience of following the XILINX recomendations? I accept that the FPGA will work fine but I'm wondering at the amount of noise injected back into the PCB. The FPGA is a logic engine to a processor sitting right alongside it whose engineers don't yet understand SI or PDS at all with no GND pins near the power pins. Any thoughts appreciated. ColinArticle: 138324
very useful tool to discuss timing. I have download it and use it! On Feb 15, 9:10=A0pm, timinganalyzer <timinganaly...@gmail.com> wrote: > Hi All, > > A new beta version of the TimingAnalyzer is available. =A0 Since it > taking much longer than expected to finish the program, =A0a few changes > have occurred. > > 1) There is only one version now that includes all the features that > are functional to this point. =A0You can download and use without any > restrictions. > > 2) =A0A new license simply says that the TimingAnalyzer will always be > completely free to use with no limitations for personal and academic > use. =A0 There will be a one time charge for commercial use when the > final release occurs. =A0Expected cost will be very low compared to the > competition. > > www.timing-diagrams.com > > As always, =A0feedback and suggestions are welcome. =A0This way, =A0you c= an > shape the look and feel of the TimingAnalyzer. > > Regards, > Dan
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