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> >Hi kadhiem_ayob > >I'm interested, but why interpolate for 66 ? I do not understand. > >Kappa. **************************** please refer to my above post. I have assumed you want an upsampling rate of 66/7. The idea applies to any other exact ratio or non-exact decimal digits Tell me what is your data rate. I know you want to lift it up to 140. KadhiemArticle: 136576
Hi Mark, Thanks for your response, You seem to be the only expert in this metter. Well you are right about the DDK and Visual - it doesnt work that good together. Honestly I do not understand how to use the HID in windows. why cant I use bulk transfer in windows? And why does the buffer is 128B? do you have a Visual sample project? what about the NIOS side SW? I am relying on Altera's SW, are there any modifications needed? Really thanks, I an having some difficulties ere since I am a HW man... so thanks again, GuyArticle: 136577
>DAC = 140 MHz >FPGA = 140 MHz >Sample time : 66MHz / 7 > >Kappa. ******************************************** So you need to upsample by [140/(66/7)] = 140 * 7/66 = 70 * 7/33 = 490/33 Thus I = 490, D = 33 step(1) coefficient design (most difficult) The total taps should be a multiple of 490 e.g. 490 * 8 = 3920 (this implies 490 subfilters (polyphases) each of 8 taps. design any low pass FIR filter of your choice, let passband ripple be minimum, let it cutoff to remove first image and further. This depends on your maximum signal frequency(fmax) and remember the I = 490 so the cutoff of the filter must be assuming this Fs as 1 hence your Fmax will move 1/490 with respect to new Fs. Note also that the D of 33 will move your Fmax back 33 times towards Fs. Try Matlab function upfirdn to design your filter correctly You may increase the number of taps per polyphase instead of 8 to improve filtering but the number of polyphases of 490 must stay. step(2)Implement in FPGA First: break up your taps sequentially into 8 sections each having 490 taps and store in 8 memory blocks. section (1) to contain first 490 taps, section (2) the next 490 taps and so on... Second: you will need a delay line of 8 stages for the input. Third: use a free running modulo adder(0 ~ 498) running on 140MHz, increment by 33. The adder will address all the 8 blocks at every value. At overflow ONLY advance the input and delay stages by one sample only. i.e. generate your enable from this overflow signal by one sample of 140MHz -convolve the taps and stages at every clock of 140 and produce an output. An important issue here is to synchronise input with polyphases. When the input starts it must convolve with polyphases in the right order starting from first(not wrap up) and this is meant at the multipliers. Else the filter will distort your signal. I hope it is clear ... If it is difficult let me know kadhiemArticle: 136578
>Third: >use a free running modulo adder(0 ~ 498) running on 140MHz, increment by >33. I mean 0 ~ 499 sorry kadhiemArticle: 136579
>>Third: >>use a free running modulo adder(0 ~ 498) running on 140MHz, increment by >>33. > >I mean 0 ~ 499 sorry > >kadhiem > ********************* Well still wrong ?? old age it should read 0 ~ (490-1) -- I won't take further risk kadhiemArticle: 136580
Hi kadhiem_ayob > So you need to upsample by [140/(66/7)] = 140 * 7/66 = 70 * 7/33 = 490/33 > > Thus I = 490, D = 33 There is a possibility that this filter comes in a Spartan 3A DSP 1800 ? > step(1) coefficient design (most difficult) > > The total taps should be a multiple of 490 e.g. 490 * 8 = 3920 > (this implies 490 subfilters (polyphases) each of 8 taps. > design any low pass FIR filter of your choice, let passband ripple be > minimum, let it cutoff to remove first image and further. This depends on > your maximum signal frequency(fmax) and remember the I = 490 so the cutoff > of the filter must be assuming this Fs as 1 hence your Fmax will move > 1/490 > with respect to new Fs. Note also that the D of 33 will move your Fmax > back > 33 times towards Fs. > > Try Matlab function upfirdn to design your filter correctly > You may increase the number of taps per polyphase instead of 8 to improve > filtering but the number of polyphases of 490 must stay. % Parameter interpolator I = 490; D = 33; % 490 subfilter of 8 taps N = 8 * I; % Filter coefficient h = fir1(N, 1/I, kaiser(N+1, 8)); > step(2)Implement in FPGA > First: > break up your taps sequentially into 8 sections each having 490 taps and > store in 8 memory blocks. section (1) to contain first 490 taps, section > (2) the next 490 taps and so on... > > Second: > you will need a delay line of 8 stages for the input. > > Third: > use a free running modulo adder(0 ~ 498) running on 140MHz, increment by > 33. > The adder will address all the 8 blocks at every value. > At overflow ONLY advance the input and delay stages by one sample only. > i.e. generate your enable from this overflow signal by one sample of > 140MHz > > -convolve the taps and stages at every clock of 140 and produce an > output. > > An important issue here is to synchronise input with polyphases. When the > input starts it must convolve with polyphases in the right order starting > from first(not wrap up) and this is meant at the multipliers. Else the > filter will distort your signal. I need a bit of time ... > I hope it is clear ... It is very clear, I thought it was easier. > If it is difficult let me know Is difficult, but let me think a little. Thanks. Kappa.Article: 136581
Hi Kappa, Before commiting to the design, you will need to look at other options: -If you are resource limited then you can use a CIC filter (Tools can generate a CIC for you). This only needs few adders. The drawback is the passband droop of CIC which is similar to that of running average filter and needs a correcting filter(inverse sinc). - you can factorise 490/33 right down to prime numbers e.g. [49 x 5 x2]/[3 x 11] and design multistage but this complicates it further and only makes sense for a DSP software platform. In fpga you may prefer 245/33 stage then x2 stage. kadhiemArticle: 136582
hi all i am designing the code for AES system as system works on 128bit data and 128 bit of key i am ready with all module which work on data path of 128 bits but i want a input to external entity in the form of 32bit as input text as 32 bit data input simillerly key input is 32 bit and output is 32 bit. so all this should come inside with clock cycles and output should work after internal logic is over and output with clock synchronus way. so i need help in this regard if some buddy help me please i will be greatful to him/her for kind help. example code as entity core is port ( clk : in std_logic; textIn : in std_logic_vector (31 downto 0); keyIn : in std_logic_vector(31 downto 0); textOut : out std_logic_vector(31 downto 0) ); architecture rtl of core is signal -------------------- begin process(clk) variable ----------for registers-------- begin if(clk='1' and clk'event ) then variable as per case statement end process; end rtl; please do somebuddy help me. as my logic not working here as i tried alot. thanks alotArticle: 136583
"wallra" <khamitkar.ravikant@gmail.com> wrote in message news:6affbc00-f8dd-44e5-a215-1499138b2018@w39g2000prb.googlegroups.com... > hi all > i am designing the code for AES system > as system works on 128bit data and 128 bit of key > i am ready with all module which work on data path of 128 bits > but i want a input to external entity in the form of 32bit > as input text as 32 bit data input simillerly key input is 32 bit and > output > is 32 bit. > so all this should come inside with clock cycles and output should > work after internal logic > is over and output with clock synchronus way. > so i need help in this regard if some buddy help me please > i will be greatful to him/her for kind help. > You have two basic choices to go forward 1. Run the external interfaces at 4x clock speed of the internal AES logic so that the 32 bit I/O has enough bandwidth to keep up with the 128 bit AES. 2. Add flow control signals to throttle the data while you manipulate into the bit widths required for the I/O. Depending on the clock frequency you expect this thing to run at, option #1 is likely the easier of the two to implement but this approach runs out of gas pretty quickly since I/O to an off chip device is generally slower than internal logic, depending on how that logic is written. In any case, it might work for you. Option #2 is the method that will give you longer term knowledge of controlling data paths in general. Looking at your entity for 'core' I don't see any signals to indicate when either 'textin', 'keyIn' or 'textout' are actually valid, thus implying (perhaps) that they are valid on each and every clock cycle which I find that rather difficult to believe. For flow control you need at a minimum - Some form of command signal from a master. - Some form of status signal from a target. You also need to understand the concept of master/target, which is simply that the thing that generates the command is the 'master', the thing that generates the status is the 'target', which way the data is flowing is not relevant. For more background on this I refer you to Altera's Avalon bus specification or the Wishbone specification as examples that you would do well to follow (personally I prefer Avalon). Once you've got that down, then you will have an understanding of why all your components should have flow control logic right from the git-go. Assuming that your AES core had flow control signals then the issues you have regarding 32->128 conversions would be easily handled as well. What you need on the front end is a module that takes 32 bit input and converts it into 128 bits. Conceptually this is very easy, you need 4 consecutive inputs to make it up. On the back end you do the opposite; for every input of 128 bits you now have four consecutive outputs that can be produced. Once you understand and implement flow control logic, you'll see why these '4 consecutive' things do not need to occur on four consecutive clock cycles (although they certainly could, the flow control logic would handle this). So what you need to develop is a 32->128 bit module and a 128->32 bit module. If you think about it, you should realize that these are inverse functions of each other which means that when you cascade these modules, the second one undoes what the first one does. Design these two modules, and cascade them in a testbench and insure that they do indeed work as intended. In order to design these two in the first place you'll have to have some form of flow control which is the reason I had for mentioning it right up front. Test these two extensively, modifying the external flow control signals in your testbench in random fashions. Also try making an even longer chain (i.e. 32->128->32->128->32->128....->32) and verify that the output data stream does in fact exactly match the input stream after whatever the clock cycle latency of the chain happens to be. Also notice that the two pieces you need to develop can be done so totally independent of the AES function that is your ultimate goal. Now you need to tackle putting the appropriate flow control signals into the AES module. This is a good thing, it means you're developing code in a reusable manner and are breaking the problem down into completely independent sub-functions that can be individually tested and verified. Once you've added the flow control to AES and tested that it still works properly in a stand-alone manner with the 128 bit interfaces, now you're ready to connect them to the two modules that you developed for converting word sizes. If you've throughly tested each of the three modules then you'll likely find that when you glue them together and test them, that you won't find many issues with the bigger system. Again, this is a good thing. Lest you be put off by what flow control means, in a nutshell it is simply: - Commands are only generated by 'master' - A command is simply 'read' or 'write'. - Status is generated only by the 'target'. - A target device, in response to a command from a master, can set an output signal 'wait'. - A master must retain its current command if it is receiving a 'wait' from the target. A particular component can have multiple interfaces, being 'master' on some, 'target' on others. It is the interface of a component that does not change, a particular component is simply a collection of interfaces. For example, for 'core' maybe the interface that recieves 'keyIn', 'core' should be a master, but for the interface that receives 'textIn' and the one that generates 'textout' should be targets. I'm not suggesting that for your design they should be this way, just that they could be. The thing is that the input key and the data you're encrypting with that key as well as the output of the module probably do need to be their own separate interfaces with their own set of flow control so that the whole thing can be encrypting at the maximum possible speed without any spillover between using the wrong key or having to wait for things to 'flush through' before starting a new encryption. When all is said and done, you'll find that flow control logic generally is not very expensive in terms of logic resources if you choose the proper master and targets. It is also the only method that you can use to throttle data streams of different bandwidths. Good luck on your design Kevin JenningsArticle: 136584
Guy_FPGA wrote: > Honestly I do not understand how to use the HID in windows. why cant I > use bulk transfer in windows? You use the same code as the sample HIDCLIENT in the DDK. It's just a matter of getting the right headers and libraries from the DDK into your Visual C project. Bulk transfer is another kettle of fish. You need the bulkusb.sys driver but again, you can use a project from either Visual C or the DDK to communicate once you have the headers/libraries. > And why does the buffer is 128B? > what about the NIOS side SW? I am relying on Altera's SW, are there > any modifications needed? That seems like a NIOS-side problem to me. Can't help there sorry as I've never used the NIOS USB stuff. > do you have a Visual sample project? The code I write was done several years ago (hence the sketchy details) and I don't own the IP for it, so I can't redistribute it, sorry. But it's really just a matter of moving your DDK code to Visual C and getting the right headers/libraries - the code itself should work as-is. Or maybe the headers/libs were in the Platform SDK??? I can't recall. :( I'll see if I can dig anything else up... Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 136585
Mark McDougall wrote: > I'll see if I can dig anything else up... In the HID project, I have the following additional library files... usbd.lib hid.lib setupapi.lib Under VC++ Tools->Options->Projects->Directories, includes $(VCInstallDir)include $(VCInstallDir)atlmfc\include $(VCInstallDir)PlatformSDK\include\prerelease $(VCInstallDir)PlatformSDK\include $(FrameworkSDKDir)include C:\WINDDK\2600.1106\inc ...and for library files... $(VCInstallDir)lib $(VCInstallDir)atlmfc\lib $(VCInstallDir)PlatformSDK\lib\prerelease $(VCInstallDir)PlatformSDK\lib $(FrameworkSDKDir)lib C:\WINDDK\2600.1106\lib\wxp\i386 Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 136586
"Jonathan Bromley": > [..] > and got exactly what I wanted, a 5-bit adder with a carry in. Ok, but the problem in question was: How to write a 4 bit up/down counter with carry out, using a carry chain. xst recognizes constants passed to adders, detects it is an inc/dec-operation, and for some reason puts this logic into LUTs instead of using the carry chain. Gruss Jan BrunsArticle: 136587
Hai,
Distributed Dual-port RAM with asynchronous read:
module raminfr (clk, we, a, dpra, di, spo, dpo);
input clk;
input we;
input [4:0] a;
input [4:0] dpra;
input [3:0] di;
output [3:0] spo;
output [3:0] dpo;
reg [3:0] ram [31:0];
always @(posedge clk)
begin
if (we)
ram[a] <= di;
end
assign spo = ram[a];
assign dpo = ram[dpra];
endmodule
I have to generate the above RAM using ACTEL smartgen.
I need to know the equivalent actel smartgen RAM of the above
distributed dual port RAM with asynchronous read ..I tried smartgen's
two port and dual port RAM both are not equivalent..
Can u pls suggest the change i need to do in two port and dual port
RAM of ACTEL to achieve the Distributed Dual port RAM with
asynchronous read...Do Actel has RAM with asynchronous read?Is it
possible?
regards,
rajesh
Article: 136588Mike Treseler wrote: > abe wrote: >> does anybody have a clear opinion about code generators ( c-> vhdl , >> matlab-> vhdl, etc..) that are around? Are they really irreplaceable >> in complex applications (i.e DSP) as the vendors say? > > My only clear opinion is that > many code generators create very ugly text. > > I have used python and maple to work out the math > before I write my own code, and it seems plausible > to me that something like the matlab -> hdl products > *might* be practical. > I just haven't seen or heard any direct evidence. > Have you looked at MyHDL (www.myhdl.org) ? You might be able to get python test code and vhdl/verilog generation from the same source.Article: 136589
wallra <khamitkar.ravikant@gmail.com> wrote in news:6affbc00-f8dd-44e5- a215-1499138b2018@w39g2000prb.googlegroups.com: > hi all > i am designing the code for AES system > as system works on 128bit data and 128 bit of key > i am ready with all module which work on data path of 128 bits > but i want a input to external entity in the form of 32bit > as input text as 32 bit data input simillerly key input is 32 bit and > output > is 32 bit. > so all this should come inside with clock cycles and output should > work after internal logic > is over and output with clock synchronus way. > so i need help in this regard if some buddy help me please > i will be greatful to him/her for kind help. > > example code > > as > entity core is > port ( clk : in std_logic; > textIn : in std_logic_vector (31 downto 0); > keyIn : in std_logic_vector(31 downto 0); > textOut : out std_logic_vector(31 downto 0) > ); > architecture rtl of core is > signal -------------------- > begin > process(clk) > variable ----------for registers-------- > begin > if(clk='1' and clk'event ) then > variable as per case statement > end process; > end rtl; > > please do somebuddy help me. > as my logic not working here > as i tried alot. > thanks alot In addition to all that KJ said in his post, you should know in advance what type of "mode" you are using. Please read all of http://en.wikipedia.org/wiki/Block_cipher_modes_of_operation for details. The important information is whether feedback has been used, as this will place constraints on the latency of your implementation. Modes with feedback are CBC, CFB, OFB, etc. Modes without feedback are CTR, etc. (and ECB, but you never use that 'cause it isn't safe for most applications). The modes with feedback are less prone to injection attacks, etc. (Please refer to http://en.wikipedia.org/wiki/Malleability_(cryptography) ) Your AES-128 calculation has 12 rounds. (BTW, AES-256 has 14 rounds.) Your AES engine is likely to need multiple clocks to produce 128 bits of output. This number will vary with implementation, but it is likely to be 6 (2 rounds per clock) or 12 (1 round per clock). FPGA implementations that use block rams for the SBoxes typically can't to better than 1 round per clock. (BTW, the newer FPGAs with wider input LUTs are much better for making SBOXes out of logic. Thank you X and A!) As an experiment, I once unrolled fully an AES-256, so that it did all 14 rounds in one clock. Performance was really bad, as there was just too much logic for the placer to converge on a good solution. > i am ready with all module which work on data path of 128 bits This implies that your datapath is gapped (e.g. the data is only valid every N clocks), or that the AES engine is running at a much faster clock rate than the datapath. Does this match your understanding? Regards, AllanArticle: 136590
On 22 Nov., 18:38, "kadhiem_ayob" <kadhiem_a...@yahoo.co.uk> wrote: > >DAC = 140 MHz > >FPGA = 140 MHz > So you need to upsample by [140/(66/7)] = 140 * 7/66 = 70 * 7/33 = 490/33 There is an alternative, that might be better or worse than Kadhiems proposal, depending on your application: You can do sin(x)/x interpolation. Your 140MHz DAC clock runs periodically through 490 positions relative to your sample clock, so you need 490 coefficient sets resulting in one coefficient BRAM per Multiplier. You than compute Y[t1] = c(i)(-n)*X[t2-n] + .... + c(i)(n)*X[t2+n] where i cycles through 0...479. n will determine the quality of the result and is application dependent (in theory it must be infinite) t1 is the time position in your output sequence and is incremented by one every clock cycle. t2 is the time position in your input sequence and must be incremented 33 times in 490 clock cycles. You can have the times at which t2 must be incremented stored in the coefficent RAM as well (490x1 RAM), or compute them on the fly using Bresenhams line drawing algorithm. The coeficients are sin(x)/x with x being the relative position of the DAC clock to the input clock. Kolja SulimmaArticle: 136591
Hi, Have you had a look at the new FMC standard (VITA 57)? It looks extremely promising as nowadays many designs are based on a simple FPGA with variations on the front pannel. Sofar I have only seen FMC developments for high perfomance plataforms based on Virtex5, but I feel that a great benefit would appear when using a flexible low budget carrier with flexible low cost front pannels. Check this article for quick intro to VITA 57 http://www.vmecritical.com/articles/id/?3575 What do you think? Cheers pabloArticle: 136592
Hello all, does anyone any experience using the opb2wb bridge and the can core from opencores?. I've already installed the opb2wb bridge in xilinx edk but I would like to know how to interface the can core with this opb2wb bridge. Once this bridge is installed I would like how to work with this bridge. Thanks in advanceArticle: 136593
palvarez <pabloalvarezsanchez gmail.com> wrote: > <snipped spam> > What do you think? I think you are just another Google Groups cross-posting spammer, especially considering this is your only post to USENET. > > Cheers > > pablo > > > > > > Path: nlpi059.nbdc.sbc.com!nlpi062.nbdc.sbc.com!prodigy.com!nlpi057.nbdc.sbc.com!prodigy.net!border1.nntp.dca.giganews.com!nntp.giganews.com!postnews.google.com!t11g2000yqg.googlegroups.com!not-for-mail > From: palvarez <pabloalvarezsanchez gmail.com> > Newsgroups: comp.arch.fpga,sci.electronics.design > Subject: FMC/VITA 57 > Date: Mon, 24 Nov 2008 08:34:24 -0800 (PST) > Organization: http://groups.google.com > Lines: 21 > Message-ID: <0fffe0e3-6b4a-4b16-a5b7-055b9999b65c t11g2000yqg.googlegroups.com> > NNTP-Posting-Host: 137.138.192.48 > Mime-Version: 1.0 > Content-Type: text/plain; charset=ISO-8859-1 > Content-Transfer-Encoding: 7bit > X-Trace: posting.google.com 1227544465 8496 127.0.0.1 (24 Nov 2008 16:34:25 GMT) > X-Complaints-To: groups-abuse google.com > NNTP-Posting-Date: Mon, 24 Nov 2008 16:34:25 +0000 (UTC) > Complaints-To: groups-abuse google.com > Injection-Info: t11g2000yqg.googlegroups.com; posting-host=137.138.192.48; posting-account=g1u9fAoAAACpGZst4vQSI70Y1Alv9CUN > User-Agent: G2/1.0 > X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 7.0; Windows NT 5.1; .NET CLR 1.1.4322; .NET CLR 2.0.50727; InfoPath.1),gzip(gfe),gzip(gfe) > Bytes: 1682 > Xref: prodigy.net comp.arch.fpga:149478 sci.electronics.design:944982 > X-Received-Date: Mon, 24 Nov 2008 11:34:25 EST (nlpi059.nbdc.sbc.com) > -- The first big front wheel rollerblades. http://www.flickr.com/photos/27532210 N04/2565924423/ Google Groups is destroying the USENET archive. From rgaddi@technologyhighland.com Mon Nov 24 09:52:23 2008 Path: flpi142.ffdc.sbc.com!flph199.ffdc.sbc.com!prodigy.com!flph200.ffdc.sbc.com!prodigy.net!bigfeed.bellsouth.net!bigfeed2.bellsouth.net!news.bellsouth.net!news.glorb.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local02.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Mon, 24 Nov 2008 11:52:23 -0600 Date: Mon, 24 Nov 2008 09:52:23 -0800 From: Rob Gaddi <rgaddi@technologyhighland.com> Newsgroups: comp.arch.fpga Subject: Re: Student FPGAs Message-Id: <20081124095223.631f7ad9.rgaddi@technologyhighland.com> References: <gg6m8r$egl$1@aioe.org> <49280fe2$1@news.uni-ulm.de> Organization: Highland Technology, Inc. X-Newsreader: Sylpheed 2.5.0 (GTK+ 2.10.14; i686-pc-mingw32) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Lines: 31 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 66.117.134.49 X-Trace: sv3-6mFg3WeMjQGW+1JcjuJjw7oi8qZRVIPaXAIlGd/KCtmopiFzgBIUdhBevFEmIvkqvPhhBqTd2ZQxQo1!Fu11P535CLyat5VDA8Sl01/ECZV3VuOjbtiqNsSYzSR0smz5jiqmaYyeC8fiG9URkdDtLKk3mv3T!4awYtjX710r9i+TX6Eg= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: prodigy.net comp.arch.fpga:149481 X-Received-Date: Mon, 24 Nov 2008 12:52:23 EST (flpi142.ffdc.sbc.com) On Sat, 22 Nov 2008 14:57:52 +0100 Lorenz Kolb <lorenz.kolb@uni-ulm.de> wrote: > Philipp wrote: > > Hi > > > > I am just wondering if there are any other companies out there that > > provide like Xilinx a univerity programm where a student can get a > > board for free or for very low cost? Especially a Virtex V board > > would be interesting to explore. > > > > Cheers, > > Philipp > > Well it's not a student-board, though in terms of cost (compared to > typical costs) Avnet has a Virtex-5FXT Evaluation board for "only" 395 > $. > > That's quite cheap for that sort of board. > > Regards, > > Lorenz Really?? From the last time I price checked any of the V5s, at that price you could buy the eval boards, desolder, reball, and still turn a profit. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 136594
On 24 nov, 18:31, John Doe <j...@usenetlove.invalid> wrote: > palvarez <pabloalvarezsanchez gmail.com> wrote: > > <snipped spam> > > What do you think? > > I think you are just another Google Groups cross-posting spammer, > especially considering this is your only post to USENET. I am just using google groups as I could have used any other news reader. I do not know what is wrong with it.Article: 136595
Rob Gaddi wrote: > On Sat, 22 Nov 2008 14:57:52 +0100 > Lorenz Kolb <lorenz.kolb@uni-ulm.de> wrote: [...] >> Well it's not a student-board, though in terms of cost (compared to >> typical costs) Avnet has a Virtex-5FXT Evaluation board for "only" 395 >> $. [...] > Really?? From the last time I price checked any of the V5s, at that > price you could buy the eval boards, desolder, reball, and still turn a > profit. Amazingly, it's true: http://www.em.avnet.com/evk/home/0,4534,CID%253D46471%2526CCD%253DUSA%2526SID%253D32214%2526DID%253DDF2%2526LID%253D32232%2526BID%253DDF2%2526CTP%253DEVK,00.html?SUL=virtex5fxt-evl They'll even knock off another buck if you order more than 100 of them :) If the URL doesn't work, it's part number AES-V5FXT-EVL30-G. The FPGA is an XC5VFX30T-1FFG665, which Avnet sells at $500 a pop. I'm not sure if this one is supported by Webpack, though (I know only a small number of Virtex devices are supported, but I can't find a list anywhere), so you may also need to spend another ~2.5 kilobucks to get Foundation. If I'd found this one when I was shopping (ended up with the Spartan 3E Starter Kit) it'd have been very tempting. Of course, now that the Australian dollar has tanked, it's a little more than I'd like to spend, but for those getting paid in greenbacks I'd say it's a killer deal. -- Michael Brown Add michael@ to emboss.co.nz ---+--- My inbox is always openArticle: 136596
paas <pabloalvarezsanchez@gmail.com> wrote: > John Doe <j...@usenetlove.invalid> wrote: >> palvarez <pabloalvarezsanchez gmail.com> wrote: >> > <snipped spam> >> > What do you think? >> >> I think you are just another Google Groups cross-posting spammer, >> especially considering this is your only post to USENET. > > I am just using google groups as I could have used any other news > reader. I do not know what is wrong with it. Are you nym-shifting?Article: 136597
...Makes it a perfect choice ,by using this script as an -how to do it script- for getting vectors from a relative fast unit level functional simulation for a full chip functional or a gate-level one. http://bknpk.no-ip.biz/incremental_backup/vcd_extract.htmlArticle: 136598
Anyone know what kind of latitude you have for the input frequency of the IDELAYCTRL primitive? I'm looking at implementing a LVDS link with a 2:1 DDR (so 4:1) at 156.25MHz. From xapp860 it looks like 200MHz works, but I'd rather use a DCM to generate the value from the 156.25MHz instead of bringing in a 200MHz clock signal from the outside. Thanks RonArticle: 136599
On Nov 24, 3:15=A0pm, Pinhas <bk...@hotmail.com> wrote: > ...Makes it a perfect choice ,by using this script as an -how to do it > script- for getting vectors from a relative fast unit level functional > simulation for a full chip functional or a gate-level one. > > http://bknpk.no-ip.biz/incremental_backup/vcd_extract.html Avast! finds a virus if I follow that link...
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