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In article <38F911C1.6DE83C7F@ids.net>, Ray Andraka <randraka@ids.net> wrote: > > Nope, modelsim is pretty much just a simulator. > .... > > Synthesis (VHDL/verilog to netlist with logic primitives) > Synplicity Exemplar (leonardo) FPGA express > > Place and Route > from the FPGA vendors. > I have a question then : what are the file formats used as input to the place & route softwares (or what are usual file format output for synthesys software) ?Article: 22051
"Eric GAUDET" <egaudet@exoffice.com> wrote in message news:bNksTh0p$GA.107@news.thrunet.com... > I have a question then : what are the file formats used as input to the place & > route softwares (or what are usual file format output for synthesys software) ? Generally EDIF (*.EDF -- electronic data interchange format) or, for Xilinx, XNF (*.XNF -- Xilinx netlist format) files. Both are ASCII readable forms of netlists, similar to what you'd have a schematic capture program produce for a PCB layout program. And as such, the program (synthesis tool) of the EDIF files has to know the correct names of the "primitives" (LUTs, RAMs, I/O buffers, etc.) that are used by the particular FPGA that's being targeted. The difference between synthesis tools is often in how well it's been "targeted" for a particular manufacturer's architecture; that is, how "smart" it is about building higher level structures such as adders and multipliers using primitives specific to a given manufacturer. Some of the (often less expensive) synthesis tools (e.g., Metamor) use a more generic architecture model, and therefore the quality of results is not always as high as, e.g., Synplify with Xilinx FPGAs. ---Joel KolstadArticle: 22052
Announcement and Second Call for Papers
2000 MAPLD International Conference
Kossiakoff Conference Center
The Johns Hopkins University - Applied Physics Laboratory
11100 Johns Hopkins Road
Laurel, Maryland 20723-6099
September 26-28, 2000
The 3rd annual Military and Aerospace Applications of
Programmable Devices and Technologies International Conference
will address devices, technologies, usage, reliability, fault
tolerance, radiation susceptibility, and applications of
programmable devices and adaptive computing systems in military
and aerospace systems. The program will consist of oral and
poster technical presentations and industrial exhibits. The
majority of the conference is open to US and foreign
participation and is unclassified. There will be one
classified session at the secret level, for U.S. citizens only.
For conference information, please see the Programmable
Technologies Web Site (http://rk.gsfc.nasa.gov) or the
conference www home page at:
http://rk.gsfc.nasa.gov/richcontent/MAPLDCon00/MAPLDCon00.html
Abstracts are being solicited in all aspects of the use of
programmable elements, devices, and systems for military and
aerospace applications. These include: PALs, FPGAs, PROMs,
Programmable Substrates, FPIC, Programmable Analog Circuits,
adaptive computing systems and related technologies.
Invited speakers for the conference include:
Keynote Address:
Henry Spencer - SP Systems
"Faster, Better, but Most Important, Much Much Cheaper"
History Invited Talk:
Eldon Hall, MIT Instrumentation Lab
"The Apollo Guidance Computer - A Designer's View"
Dinner Speaker:
Dr. Thomas Jones, NASA Astronaut Office
"ISS: The Exploration Proving Ground"
Lloyd Massengill, Vanderbilt University
"Single Event Modeling on Emerging Commercial Technologies"
AIAA Invited Talk:
James Kinnison, Johns Hopkins University/Applied Physics Lab
"System Level Radiation Tolerance"
http://rk.gsfc.nasa.gov/richcontent/MAPLDCon00/InvitedSpeakers00.html
contains abstracts for the invited speakers. Several invited
talks will be added as some details are being finalized.
Conference proceedings will be published and will consist of all
presentations (oral and poster) as well as written papers. Papers
may be submitted in one of two categories: "Select" or "Contributed."
Select papers will be subject to a peer review and will be published
in a special edition of the AIAA Journal of Spacecraft and Rockets as
well as the conference proceedings. Contributed papers will be
subject to a less stringent review.
We are again including tours this year. Guided tours will be
given at the NASA Goddard Space Flight Center, the National Security
Agency's National Cryptologic Museum, and the Applied Physics
Laboratory. For additional tour information, please see:
http://rk.gsfc.nasa.gov/richcontent/MAPLDCon00/Tours.htm
Conference topics include (but are not limited to) the following:
System on a Chip
Advanced Devices, Technologies, and Software and Their
Impact on Critical System Reliability
Programmable Technologies and State-of-the-Art Devices and
Programmable Elements
Low-Power Design Techniques
High-Speed Design Techniques
Arithmetic and Signal Processing
Adaptive Computing Systems
Evolvable Hardware
Radiation Effects, Device Reliability and Element
Characteristics
Device Architecture, Performance, and Capabilities
Applications and Novel Techniques for Military and
Spaceflight Circuits.
Use of COTS Devices in the Military and Spaceflight Environment
Testing and Analysis Techniques
Software Tools for Design/Analysis - HDLs, Synthesis, Design
Entry Systems
Translation from High Level Languages
Intellectual Property
Advanced Packaging including Known-Good-Die, MCMs, and
Chip-scale packaging.
Military Applications
Aeronautics and Space Applications
Encryption Systems
Experience and "Lessons Learned" from Mission Experience
The conference is sponsored by:
NASA Goddard Space Flight Center
JHU/Applied Physics Laboratory
National Security Agency
NASA Electronics Radiation Characterization Project
Military & Aerospace Programmable Logic Users Group
American Institute of Aeronautics and Astronautics
IEEE Aerospace & Electronic Systems Society (AESS)
For more information see http://rk.gsfc.nasa.gov or contact:
Richard Katz - Conference Chair
NASA Goddard Space Flight Center
rich.katz@gsfc.nasa.gov
Tel: (301) 286-9705
Alan W. Hunsberger - Conference Co-Chair
National Security Agency
awhunsb@afterlife.ncsc.mil
Tel: (301) 688-0245
Ann Darrin - Conference Co-Chair
Johns Hopkins University
Applied Physics Laboratory
ann.darrin@jhuapl.edu
Tel: (240) 228-4952
Tanya Vladimirova - Conference Co-Chair
University of Surrey
T.Vladimirova@ee.surrey.ac.uk
+44(0)1483 879137
Abstracts should be approximately 2 pages long and are due
June 9, 2000. Please send abstracts to
maplug@pop700.gsfc.nasa.gov. If your abstract is in an
attached file, please name the file in the following format:
LastName_A.ext - where last name is the name of the first
author - e.g., Katz_A.txt. Please include first author
information (name, affiliation, phone number, and email
address) as well as whether an open or classified presentation
is desired. Additionally, please specify whether you will be
submitting your paper for a peer-reviewed publication or a
symposium publication. All abstracts should be unclassified
when sent over email. If you can not submit an unclassified
abstract, please contact Alan Hunsberger.
Industrial exhibit reservations should be sent to
maplug@pop700.gsfc.nasa.gov and should include company name
and contact information (phone and email). Please see
http://rk.gsfc.nasa.gov/richcontent/MAPLDCon00/Industrial_Exhibits.htm
for additional information.
Technical Committee
===================
Ray Andraka The Andraka Group
Neil Bergmann Queensland University of Technology
Ben Cohen Hughes Aircraft/Raytheon Systems Company
Lew Cohn Defense Threat Reduction Agency
Marty Fraeman Johns Hopkins University
Creigh Gordon Air Force Research Laboratory/VSSE
Sandi Habinc European Space Agency
David Hepner US Army Research Laboratory
Brad Hutchings Brigham Young University
Ralph Kohler Air Force Research Laboratory
Ken LaBel NASA Goddard Space Flight Center
Thomas D. Milnes Johns Hopkins University
John McHenry National Security Agency
Robert Reed NASA Goddard Space Flight Center
Michael Regula Dornier Satellitensysteme GmbH
Hans Tiggeler University of Surrey
Frank R. Stott Jet Propulsion Laboratory
Tanya Vladimirova University of Surrey
Jing Yuan Jet Propulsion Laboratory
Article: 22053<!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> In my design I have two microcontrollers that have to talk to each other at the same time using independent clock. I have a solution for this but I believe there is a standard (possibly more efficient) way to accomplish this. Does any one out there can help me with this design? <br>Thanks, <br>tz <p>Peter Alfke wrote: <blockquote TYPE=CITE>At Xilinx, we use the name "asynchronous FIFO" for a FIFO with <br>completely independent write and read clocks. Such a FIFO bridges the <br>gap between different clock domains. <br>There is no need to synchronize such a FIFO. It does the <br>synchronization. <p>A "synchronous FIFO" would use the same clock for write and read. Such a <br>design is a trivial subset of the more general asynchronous case. <p>Sorry if we confused you by our nomenclature. <p>Peter Alfke, Xilinx Applications <br>============================================= <br>Taras Zima wrote: <p>> I am looking for a way to synchronizes an asynchronous FIFO. The <br>> verilog module of FIFO was generated by Xilinx Core Generator. I am <br>> using Spartan XL FPGA family. Does any one can point me to a site <br>> with information on this topic? <br>> Thanks, <br>> tz</blockquote> </html>Article: 22054
You can add a very complet product in your list: "FPGA ADVANTAGE" from Mentor ( www.mentor.com ): "FPGA ADVANTAGE" = 1. HDL design entry : Renoir 2. Synthesis: Leonardo Spectrum (Exemplar, partner of Mentor) 3. Simulation: Modelsim (ModelTech, partner of Mentor) Very good package ... I am very happy to use it. Laurent Ray Andraka a écrit : > Nope, modelsim is pretty much just a simulator. > > Here's the some of what's what, but by no means a complete list > > Schematic capture: > Viewlogic > Aldec (foundation) > Orcad > > HDL design entry > Aldec > others > > simulation > Aldec (VHDL and soon verilog) > modelsim (VHDL/verilog) > viewlogic (great for schematics, weak for vhdl, no vhdl93 support) > > Synthesis (VHDL/verilog to netlist with logic primitives) > Synplicity > Exemplar (leonardo) > FPGA express > > Place and Route > from the FPGA vendors. > > You'll need something from each category (HDL entrya nd schematic fall under > the same category). The simulator and synthesis tools have text editors and > debug features in them, but they are not very good for design entry. Veribest > is, I think a formal verification tool so it is an additional piece. Only the > FPGA place and route tools generate the bitstreams for the part. Altera has a > schematic and hdl facility built into their maxplus tools, but it locks you > into that device and toolset. You can generally mix VHDL and schematic at the > input of the FPGA tools, but you will have to instantiate one or the other > into your top level to get it all to play nice. > > Vasant Ram wrote: > > > Hey all. > > > > I have a few questions on on the VHDL/FPGA software that is available. > > > > I've heard of several packages like ModelSim, FPGA Express, Leonardo > > Spectrum, VeriBest, etc. > > > > What I want to know is to these tools produce files that you can use to > > directly program into a part? Also do they allow free-mixing of VHDL code > > and schematic capture like Altera's Max+Plus II (where you can make a .GDF > > of AHDL/VHDL code and then use it in schematic entry)? > > > > The design flow as I know it goes something like: > > > > Come up with an idea > > > > Start a new project > > > > Write the VHDL / Schematic entry / State Machines / Verilog > > > > Fix all the errors to satisfaction so it compiles > > > > After it compiles, use a "waveform editor" and apply input stimuli and > > look at timing etc. > > > > Repeat above steps if timing isn't satisfactory > > > > Recompile > > > > When finished, take output file and program to part > > > > Granted I skipped a lot of important steps (timing constraints, etc) but > > does one tool do all of these? From what I've seen on the many products' > > websites, the are generally 4 components to the software package: > > > > A) VHDL & Schematic capture > > B) Compiling > > C) Simulating (looking at waveforms) > > D) Programming part? > > > > As for the last step however, I've always been led to believe that > > something like ModelSim can be used to do all the work up to coming up > > with the program for the part which has to be done by the part vendors' > > Place & Route tool? > > > > Thanks for any clarification, > > Vasant. > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://users.ids.net/~randrakaArticle: 22055
On Mon, 17 Apr 2000 01:37:29, Laurent Gauch <laurent.gauch@aps-euro.com> wrote: > You can add a very complet product in your list: > > "FPGA ADVANTAGE" from Mentor ( www.mentor.com ): > > "FPGA ADVANTAGE" = > 1. HDL design entry : Renoir > 2. Synthesis: Leonardo Spectrum (Exemplar, partner of Mentor) > 3. Simulation: Modelsim (ModelTech, partner of Mentor) > > Very good package ... I am very happy to use it. Ok, how is this different (looking for views from the experts here) than the Synplicity package? Synplify (entry and synthesis), HD Analyst (logic/schematic view), and ModelSim seems to be very similar. Synplify came highly recommended to me and I have some very good support, so I bought it. However, I think this is an area that would be ripe for comparison. None of this stuff is cheap (so neither of us are likely to change horses), but it might help to air out the differences so others will choose the right tools. ...and at the same time prod the tool developers into improving their tools. Frankly, I'm just competant with Synplify (and FPGA design) to get me in real trouble. This is changing fast, however. ..thanks in large part to reading the discussions in this group. ---- Keith R. Williams krw@attglobal.netArticle: 22056
When will the timing(speed files)for Virtex-EM
be available on the Xilinx download web page?
All they have available now are the speed files
for the Virtex-E.
remove the "_nospamm_" from the return address
thanks,
steve martindell
'smartind@home.com'
<or> 's-martindell@ti.com'
Article: 22057I've just started programming in VHDL on a Xilinx Virtex XCV300 chip using Foundation Express 2.1. I'm trying to write a program that will do some handshaking with an external chip connected to the FPGA. The chips data sheet says I need to do something like the following: 1) set pin WCLK low 2) after 5 ns, set pin C1 high 3) after 4 ns, set pin C2 low. etc ... Any suggestions? Is there a standard way to do such things in Foundation Express? I had planned to use the various VHDL delay statements, but none of them seem to be supported. I thought this would be simple until I realized that a large part of VHDL is not supported by Foundation Express (possibly for good reason, I don't know). It seems to me, the FPGA could not possibly produce a delay shorter than the clock period anyway (is that correct?), so do people just use the rising edge of the clock to do handshaking? ThanksArticle: 22058
"David A Hand" <hand@corestar-corp.com> wrote in message news:38FAB2D4.F900B05B@corestar-corp.com... > The chips > data sheet says I need to do something like the following: > > 1) set pin WCLK low > 2) after 5 ns, set pin C1 high > 3) after 4 ns, set pin C2 low. Are these times minimums delays? This is rather important. What kind of device is it anyway? Something common like a memory, or just some weird ASIC or other PLD that you've been asked to interface to? > Any suggestions? Is there a standard way to do such things in Foundation > Express? Not really -- as you've discovered, "wait for xxx ns" statements are not synthesizable in VHDL (or any HDL, by any synthesizer), because there's no way to map such a request into real hardware. It sounds like you'd benefit from reading a good book on VHDL synthesis. The FAQ has a whole bunch of them listed. For something good at the low- to mid-level, take a look at "VHDL for Logic Synthesis" by Andrew Rushton. "The Designers Guide to VHDL" by Peter Ashenden also gets a lot of recommendations around here, although I personally don't have a copy and therefore can't comment on it. > It seems to me, the FPGA could not possibly produce a delay shorter than > the clock period anyway (is that correct?), so do people just use the > rising edge of the clock to do handshaking? Yes, or sometimes both clock edges if necessary. And keep in mind that, depending on what clock frequencies you have available and how slow they are, some FPGAs can do internal clock doubling or quadrupling for you. If you absolutely have to, you can sit down and write asynchronous state machines to do handshaking. This is not for the faint of heart; it can take a very long time to be absolutely sure that you don't have any race conditions that'll destroy your handshaking sequence. And you still can't get precise delays, all you can get is an order of execution with certain bounds on the execution time. (Most people who are out there creating large asynchronous designs are after power reduction and not so much execution speed. Clock nets take a lot of power in a big IC.) ---Joel KolstadArticle: 22059
Hi, The f/16 is from external source, so I believe the safest way is to have it synchronized with f , have full handshake and suffer some delay.... I simply don't have that experience to ensure everything works fine if I don't use the safest method. Illan, Thanks for all your ideas man.... i'll keep them in mind in my future designs if I happen to encounter the similar deisgn problem again :-))) MK <iglasner@zumanetworks.com> wrote in message news:8d2hti$7q9$1@nnrp1.deja.com... > Hi, > > you mention that you have low freq which are f/16, IF this low freq > is generate from the base freq (f) than you might not need the > syncronizer at all BUT here come the tricky quesiton, how do you > generate the low freq ? > > if you have a counter/devider than depend on the way you designed this > devide, if you design is such as that both posedge of the low freq and > high freq are togther (a cascade DFF as a simple counter therfore will > not do) than when you send a signla from the low freq to the high the > signal not need to have any "handling" HOWEVER when you send from the > high to the low than you must hold it for few clock so it will still be > active when the low freq finaly get to the posedge. (if you also use > negedge of clock somewhere you will need that also both negedge of the > clock will be on the same time). > > BTW the "suffer" of clock delay is expected as after all you sample it > twice in the syncronizer. > > also you might consider not a full-handshake incase you are certain > that the other module "saw" the signla, and in this case you can de- > active the signal as soon as you belive it is ok. > > unless you are limited due to number of FF/gates I belive this will > work also in higher frequance, what you might consider doing but is all > depend on your desing is that you might consider adding a fifo, or > maybe make the data passing as burst mode meaning that when you ask to > read the data you also tell how many read you want to do in this read > (the how many will be treated as data and not need to be syncronized) > and than you can get few block of data but again it is all just an > idea's and it all depoend on your design. > > have a nice day > > Illan > > In article <8d0qfd$d19$1@coco.singnet.com.sg>, > "MK Yap" <mkyap@REMOVE.ieee.org> wrote: > > Hi! > > > > I have a few modules that works in this way... > > In_module which works at .. say 33Mhz( f), out_module at ard 2MHz ( > f/16). I > > have synchornized the out_module to in_module and the warning goes > away... > > and yup! The simulation result is now correct :-)) > > but I suffer some delay(1-2 clk cycles) in sending data... :-( > > > > There is another out2_module that works at much higher speed, (max > f/3 or > > 11MHz). I believe my method no longer works since the delay (1-2 clk > cycles) > > is intolerable in this case... Does yer method work in this case? > > > > btw, in Synplify, I managed to design all my modules to work at, say > all > > >70Mhz. But when I use schematic to interconnect the modules in > max+plus2 > > (use fast logic synthesis), after compilation, the max frequency drops > > drastically to ard 40MHz.... is there any way to improve the final max > > frequency close to 70MHz?? > > > > Thanks Iglasner & Christian for sharing yer experiences... They're > useful > > for novice like me :-) > > > > Regards > > MK > > > > <iglasner@zumanetworks.com> wrote in message > > news:8cvpj6$51g$1@nnrp1.deja.com... > > > Hi, > > > > > > You ommite the clock frequance of the 2 clock's (or maybe more ?) > > > you are talking about as well as are the infomation delay is > crusial or > > > can you wait a clock or two. > > > > > > according to the above there are few way to approch the problem. > > > > > > as an example assume you have a data stored in module1 work with > clk1 > > > in few buffers and you want to read a certain buffer to a module2 > that > > > work in clk2 > > > > > > than a general sulotion will be that module2 will prepare the buffer > > > number he want to read and than will rais a single saying he want to > > > read. > > > > > > this read signal you will pass through syncronizer (to clk1) to > module1 > > > domain and than module1 will look and see the address which is > > > already "long ago" stable. > > > > > > module1 will than put the data and will rais a signal saying data is > > > ready. > > > > > > this data is ready signal will also be syncronize (to clk2) and when > > > module2 see it the data is already stable, and can be "used safely". > > > > > > than module 2 pulldown the read and as soon as mosule 1 see that the > > > read signal is pulldown he pulldown the data is ready signal. > > > > > > this is just one way (usually called full-handshake) and there are > many > > > other. > > > > > > have a nice day > > > > > > Illan > > > > > > > > > In article <8cu1mq$3v1$1@coco.singnet.com.sg>, > > > "MK Yap" <mkyap@REMOVE.ieee.org> wrote: > > > > Hi all, > > > > > > > > For my design, there is a global clock, some input signals, some > > > output > > > > signals (clocked by external source). > > > > > > > > When input signals come in(synchronized by global clock), the > central > > > > controller will collect, organize, manipulate & store in buffer. > > > > The output port interface portion will at intervals (ctrl by > external > > > clk) > > > > request data from buffer. > > > > During my design, I encounter hundreds of design warning by > > > max+plus2 (i'm > > > > using synplify vhdl sythesizer) saying sth like this > > > > "Design Dr warning: flipflop or synchronous memory 'q_data_7' > > > receives data > > > > that is synchronized by another clock at flipflop or synchronous > > > memory > > > > 'subc_datareq' " > > > > & > > > > "Design Dr warning: inverting delay chain starting at primitive > > > > 'cntr_1_lut_5' feeds primitive 'statemachine_cntr_i_0' " > > > > > > > > & my project fails to work during timing simulation. > > > > Can somebody pls shed some light on how to properly design a > multiple > > > clock > > > > system that meets all setup time, hold time....??? > > > > or is there any good reference that stress on this area of design? > > > > > > > > Any help is much appreciated. Thanks in advance. > > > > > > > > Rgds > > > > MK > > > > > > > > > > > > > > > > > Sent via Deja.com http://www.deja.com/ > > > Before you buy. > > > > > > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 22060
Hi, does anybody out there know how to force a Xilinx-IOB (XC4000 or Virtex) to add an pull-up resistor to an input pad when using Synopsys' VHDL-entry tools for the design? I've tried using the Synopsys command "set_pad_type -pullup ..." but the compiler seems to ignore that. The resulting .sedif-netlist contains a normal IBUF at the pin but no pull-up resitor. I've searched for a Xilinx attribute or similar to tell the corresponding IOB to swith on its pull-up but didn't find anything of that type. Also, several VHDL-constructs like adding a PULLUP- and an IBUF-component to a port and setting a "dont_touch" on them failed, I always got a simple IBUF in my netlist. What can I do to force the resulting IOB to switch on it's pull-up? TIA Jens P.S. I'm using Synopsys_1998_08 and Xilinx M1.5i (I know, these aren't the newest tools but it's not up to me to install newer versions)Article: 22061
Hi, I was suprised when I read your mail because I used Synopsys too and it's work !! (I've just verified in Xilinx Editor and I see the pull up when I edit the IOB : the pull-up box is checked). "My method" is to use pull-up component perhaps your mistake is the connection ? My example : "C_PULLUP1: pulldown port map(O => Signal_A_Pull); Signal_A_Pull <= I_Signal_A;" where "Signal_A_Pull " is a local signal (from the architecture declarative part) and "I_Signal_A" a signal form the port of entity You'll have a warning from Synopsys : "The net I_Signal_A has more than one driver (FPGA-CHECK-10) but you can safely ignore it. "Jens Hildebrandt" <hil@e-technik.uni-rostock.de> a écrit dans le message news: 38FAE7F4.A881C8D@e-technik.uni-rostock.de... > Hi, > does anybody out there know how to force a Xilinx-IOB (XC4000 or Virtex) > to add an pull-up resistor to an input pad when using Synopsys' > VHDL-entry tools for the design? > I've tried using the Synopsys command "set_pad_type -pullup ..." but the > compiler seems to ignore that. The resulting .sedif-netlist contains a > normal IBUF at the pin but no pull-up resitor. I've searched for a > Xilinx attribute or similar to tell the corresponding IOB to swith on > its pull-up but didn't find anything of that type. Also, several > VHDL-constructs like adding a PULLUP- and an IBUF-component to a port > and setting a "dont_touch" on them failed, I always got a simple IBUF in > my netlist. > What can I do to force the resulting IOB to switch on it's pull-up? > > TIA > Jens > > > P.S. I'm using Synopsys_1998_08 and Xilinx M1.5i (I know, these aren't > the newest tools but it's not up to me to install newer versions)Article: 22062
In article <8cn88v$8kv$1@nnrp1.deja.com>, <karenwlead@my-deja.com> wrote: >Hi All, > >After how many cycles the virtex clkdll reaches the stability state > This is specified in the Virtex datasheet in the DLL timing parameter section (page 39). It varies with the input frequency. Ed McGettigan --Article: 22063
Dear Gentle Persons, I need a paper, book report or some other reference that addresses the nature and hopefully the percentage of failures that are experienced in modern FPGA's. The only studies I have are so old, that FPGA's didn't exist when they were done. Does anyone have a reference. Note I am looking for non design errors, that happen after the part has been tested in the installed environment. Robert Posey MuddyArticle: 22064
In article <ee6b563.0@WebX.sUN8CHnE>, Craig Niple <Craig.Niple@med.ge.com> wrote: >Does anyone know of an ABEL to VHDL translator? The Xilinx Foundation 2.1i software has a utility called XPORT that can convert ABEL to Verilog and VHDL. Ed McGettigan --Article: 22065
My choice of desing tools include: Active-HDL (design entry in VHDL and simulation - back annotation simulation also) Leonardo Spectrum (synthesis) Whatever Fitter Tool you need depending on what FPGA/CPLD you are using (Xilinx, Altera, Lattice, Actel, etc.. etc..) For the money, you can't beat what you get for the Active-HDL package. Download the trial version and check it out. www.aldec.com Vasant Ram <12111_1vasantr6_32_3@utdallas.edu> wrote in message news:8daq6h$auj$1@news.utdallas.edu... > Hey all. > > I have a few questions on on the VHDL/FPGA software that is available. > > I've heard of several packages like ModelSim, FPGA Express, Leonardo > Spectrum, VeriBest, etc. > > What I want to know is to these tools produce files that you can use to > directly program into a part? Also do they allow free-mixing of VHDL code > and schematic capture like Altera's Max+Plus II (where you can make a .GDF > of AHDL/VHDL code and then use it in schematic entry)? > > The design flow as I know it goes something like: > > Come up with an idea > > Start a new project > > Write the VHDL / Schematic entry / State Machines / Verilog > > Fix all the errors to satisfaction so it compiles > > After it compiles, use a "waveform editor" and apply input stimuli and > look at timing etc. > > Repeat above steps if timing isn't satisfactory > > Recompile > > When finished, take output file and program to part > > Granted I skipped a lot of important steps (timing constraints, etc) but > does one tool do all of these? From what I've seen on the many products' > websites, the are generally 4 components to the software package: > > A) VHDL & Schematic capture > B) Compiling > C) Simulating (looking at waveforms) > D) Programming part? > > As for the last step however, I've always been led to believe that > something like ModelSim can be used to do all the work up to coming up > with the program for the part which has to be done by the part vendors' > Place & Route tool? > > Thanks for any clarification, > Vasant.Article: 22066
Hi. Has anyone come across the following errors when using generics using Aldec-HDL 3.6? I have written many vhdl entities and component declarations that I have placed in a package file. I then use a top level file to instantiate the components I need. All components use generics for the port widths and internal paths, including the top-level block since it will be used in an even bigger design later on. (Some components have nested components which also use generics). When I try to simulate the design in Aldec-HDL 3.6, it compiles without any errors or warnings, but it cannot elaborate the entity when it needs to begin the simulation. It's strange because when I synthesize it using synplfy, I get all the correct port widths and internal data path widths. I am targetting Altera flex10k (but this should not matter in Aldec-HDL since I do not use anything from Altera, just pure VHDL). The exact errors from Aldec-HDL are: ELBREAD: Error: Internal: elb_obj.cpp, 4287. ELBREAD: Error: Elaboration process completed with errors. Design: Error: Elaboration failed I have narrowed down the components that may be causing the errors, but their code seems correct (one is a mux, the other is a comparator). I even tried using numerical values throught the whole design for the generics, but the problem persists. It doesn't seem like a vhdl design error, but more like some kind of tool error (a bug?). If anyone might know what could be causing this error, I would greatly appreciate your help. Thanks in advance. NestorArticle: 22067
Hi, Do you really plan to draw the stimulus ? unless you are synthesis a very simple logic (and even than) I must wonder why using "drawing" ? why not writing a test bench just as you write your code, it is faster and also much more flexable, not to mention that if the code is a it more than few gates the coverage of your "drawing" is most likely very poor/limited so I would strongly suggest you use test bench to test your code and put a side the "drawing". Also once you get the netlist with and withut the timing you van verify that you synthesis tool "understood" you by using again the same test bench (sometime few modification are needed depend on how you wrote you test bench) to verify it. and so on ... have a nice day Illan In article <8daq6h$auj$1@news.utdallas.edu>, Vasant Ram <12111_1vasantr6_32_3@utdallas.edu> wrote: > Hey all. > > I have a few questions on on the VHDL/FPGA software that is available. > > I've heard of several packages like ModelSim, FPGA Express, Leonardo > Spectrum, VeriBest, etc. > > What I want to know is to these tools produce files that you can use to > directly program into a part? Also do they allow free-mixing of VHDL code > and schematic capture like Altera's Max+Plus II (where you can make a .GDF > of AHDL/VHDL code and then use it in schematic entry)? > > The design flow as I know it goes something like: > > Come up with an idea > > Start a new project > > Write the VHDL / Schematic entry / State Machines / Verilog > > Fix all the errors to satisfaction so it compiles > > After it compiles, use a "waveform editor" and apply input stimuli and > look at timing etc. > > Repeat above steps if timing isn't satisfactory > > Recompile > > When finished, take output file and program to part > > Granted I skipped a lot of important steps (timing constraints, etc) but > does one tool do all of these? From what I've seen on the many products' > websites, the are generally 4 components to the software package: > > A) VHDL & Schematic capture > B) Compiling > C) Simulating (looking at waveforms) > D) Programming part? > > As for the last step however, I've always been led to believe that > something like ModelSim can be used to do all the work up to coming up > with the program for the part which has to be done by the part vendors' > Place & Route tool? > > Thanks for any clarification, > Vasant. > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 22068
Joel, Thanks for the help. The timings are in fact minimum delays. The chip is a DAC that generates sine wave outputs. I need to load 5 bytes to tell it what frequency and so forth. Since I'm running at 100 Mhz, using the clock will give me 10 ns. My fear is, some day they will have 1 Ghz FPGA's and all my code will break. I'll look into the books you mention. The ones I have just describe the language and ignore some of the more practial aspects. As a side note: do you recommend VHDL over Verilog? Thanks, Dave Hand Joel Kolstad wrote: > "David A Hand" <hand@corestar-corp.com> wrote in message > news:38FAB2D4.F900B05B@corestar-corp.com... > > The chips > > data sheet says I need to do something like the following: > > > > 1) set pin WCLK low > > 2) after 5 ns, set pin C1 high > > 3) after 4 ns, set pin C2 low. > > Are these times minimums delays? This is rather important. What kind of > device is it anyway? Something common like a memory, or just some weird > ASIC or other PLD that you've been asked to interface to? > > > Any suggestions? Is there a standard way to do such things in Foundation > > Express? > > Not really -- as you've discovered, "wait for xxx ns" statements are not > synthesizable in VHDL (or any HDL, by any synthesizer), because there's no > way to map such a request into real hardware. > > It sounds like you'd benefit from reading a good book on VHDL synthesis. > The FAQ has a whole bunch of them listed. For something good at the low- to > mid-level, take a look at "VHDL for Logic Synthesis" by Andrew Rushton. > "The Designers Guide to VHDL" by Peter Ashenden also gets a lot of > recommendations around here, although I personally don't have a copy and > therefore can't comment on it. > > > It seems to me, the FPGA could not possibly produce a delay shorter than > > the clock period anyway (is that correct?), so do people just use the > > rising edge of the clock to do handshaking? > > Yes, or sometimes both clock edges if necessary. And keep in mind that, > depending on what clock frequencies you have available and how slow they > are, some FPGAs can do internal clock doubling or quadrupling for you. > > If you absolutely have to, you can sit down and write asynchronous state > machines to do handshaking. This is not for the faint of heart; it can take > a very long time to be absolutely sure that you don't have any race > conditions that'll destroy your handshaking sequence. And you still can't > get precise delays, all you can get is an order of execution with certain > bounds on the execution time. (Most people who are out there creating large > asynchronous designs are after power reduction and not so much execution > speed. Clock nets take a lot of power in a big IC.) > > ---Joel KolstadArticle: 22069
use an entry in your project ucf file (I think this only works with foundation 2.1): NET "MYNET1" PULLUP; # define a pullup NET "MYNET2" PULLDOWN; # define a pulldown NET "MYNET3" KEEPER; # define a weak keeper I think the latter only works on Virtex. Matt "Jens Hildebrandt" <hil@e-technik.uni-rostock.de> wrote in message news:38FAE7F4.A881C8D@e-technik.uni-rostock.de... | Hi, | does anybody out there know how to force a Xilinx-IOB (XC4000 or Virtex) | to add an pull-up resistor to an input pad when using Synopsys' | VHDL-entry tools for the design? | I've tried using the Synopsys command "set_pad_type -pullup ..." but the | compiler seems to ignore that. The resulting .sedif-netlist contains a | normal IBUF at the pin but no pull-up resitor. I've searched for a | Xilinx attribute or similar to tell the corresponding IOB to swith on | its pull-up but didn't find anything of that type. Also, several | VHDL-constructs like adding a PULLUP- and an IBUF-component to a port | and setting a "dont_touch" on them failed, I always got a simple IBUF in | my netlist. | What can I do to force the resulting IOB to switch on it's pull-up? | | TIA | Jens | | | P.S. I'm using Synopsys_1998_08 and Xilinx M1.5i (I know, these aren't | the newest tools but it's not up to me to install newer versions)Article: 22070
try to visit http://www.geocities.com/SiliconValley/Pines/6639/ip/memory_cores.html it may help you Taras Zima wrote: > I am looking for a way to synchronizes an asynchronous FIFO. The > verilog module of FIFO was generated by Xilinx Core Generator. I am > using Spartan XL FPGA family. Does any one can point me to a site > with information on this topic? > Thanks, > tzArticle: 22071
Hi all. I do a fair amount of CPLD (Xilinx XC9500 series) design with the Xilinx Foundation (got 2.1i right now) series of software. Whenever I run the synthesis part (the fitter), it seems that all the GUI is doing is running a program called 'hitop' with a bunch of command line options. The syntax isn't to hard to figure out. Anyway, I often try to cram as much crap as possible into these little chips, and I often end up without enough resources, either pterms or macrocells (usually because of flops). Of course, if I suspect that I can fit the design in the chip, I like to play with the all the various settings used by the compiler, which reside in the implementation's directory, in the *.ctl file. So.... I've been thinking that it shouldn't be too hard to write a PERL (or some other language) script to modify the file for particular settings, then run hitop (w/ appropriate command line opts), store the results, and iterate over a range of parameter values. Seems simple enough, and I've started the pseudo code, I'm just wondering if I'm duplicating the wheel here. ie, has anybody done this? RussArticle: 22072
"Rémi SEGLIE" wrote: > > Hi, > > I was suprised when I read your mail because I used Synopsys too and it's > work !! (I've just verified in Xilinx Editor and I see the pull up when I > edit > the IOB : the pull-up box is checked). > > "My method" is to use pull-up component perhaps your mistake is the > connection ? > > My example : > > "C_PULLUP1: pulldown port map(O => Signal_A_Pull); > > Signal_A_Pull <= I_Signal_A;" > > where "Signal_A_Pull " is a local signal (from the architecture declarative > part) and "I_Signal_A" a signal form the port of entity > You'll have a warning from Synopsys : "The net I_Signal_A has more than one > driver (FPGA-CHECK-10) but you can safely ignore it. > <snip> "Your method" was my starting point and because it didn't work (with my Virtex-design) I started looking for other methods. The PULLUPs dissapear after invoking Synopsys' "compile"-command although I have set a "dont_touch" on them. What is your target architecture and which Synopsys/Xilinx-Versions do you use? JensArticle: 22073
This is a multi-part message in MIME format.
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Russell,
There is a command-line program called xflow in the Xilinx 2.1i
release. It not only allows you to kick off batch runs but also gives you
access to all switches of the sub-programs like hitop. To use this program,
open a DOS-box or UNIX shell and CD to your project. Type in one of the
folloowing lines (the one that best suites your goals):
xflow -p <part_to_target> -fit balanced.opt -norun <design_name>
xflow -p <part_to_target> -fit speed.opt -norun <design_name>
xflow -p <part_to_target> -fit density.opt -norun <design_name>
This will place in your directory one of the three .opt files you specified
above. Open that file in an editor and view/change the options set for the
run. After the .opt file is set to your satisfaction, run the previous
command without the -norun option. This will kick off the run with your
specified options.
Should be easier than it sounds.
Hopefully that will do what you want without too mcuh effort on your part.
Note: You can also run this program with FPGAs however the switch is
-implement rather than -fit.
-- Brian
Russell Brinkmann wrote:
> Hi all. I do a fair amount of CPLD (Xilinx XC9500 series) design with
> the
> Xilinx Foundation (got 2.1i right now) series of software. Whenever I
> run the
> synthesis part (the fitter), it seems that all the GUI is doing is
> running a
> program called 'hitop' with a bunch of command line options. The syntax
> isn't
> to hard to figure out.
>
> Anyway, I often try to cram as much crap as possible into these little
> chips,
> and I often end up without enough resources, either pterms or macrocells
>
> (usually because of flops).
>
> Of course, if I suspect that I can fit the design in the chip, I like to
> play
> with the all the various settings used by the compiler, which reside in
> the
> implementation's directory, in the *.ctl file.
>
> So.... I've been thinking that it shouldn't be too hard to write a PERL
> (or
> some other language) script to modify the file for particular settings,
> then run hitop (w/ appropriate command line opts), store the results,
> and
> iterate over a range of parameter values.
>
> Seems simple enough, and I've started the pseudo code, I'm just
> wondering if
> I'm duplicating the wheel here. ie, has anybody done this?
>
> Russ
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n:Philofsky;Brian
tel;work:1-800-255-7778
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url:http://www.xilinx.com
org:Xilinx, Inc.;Software Marketing
adr:;;2100 Logic Dr.;San Jose;CA;95124;USA
version:2.1
email;internet:brianp@xilinx.com
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--------------A3B2443457DEDDAD310CBE46--
Article: 22074
David A Hand wrote in message <38FBBEBD.9714FB5@corestar-corp.com>...
>The timings are in fact minimum delays. The chip is a DAC that generates
sine
>wave outputs. I need to load 5 bytes to tell it what frequency and so
forth.
>Since I'm running at 100 Mhz, using the clock will give me 10 ns.
All you need to do is have a state machine that asserts strobe 1 on the
first tick, then strobe 2 on the second, then strobe 3 on the third (if
that's what's required). Each tick will be 10 ns apart, which meets your
requirements.
>My fear is,
>some day they will have 1 Ghz FPGA's and all my code will break.
Just because the FPGA *can* run at 1 GHz doesn't mean you have to run it
that fast.
>As a side note: do you recommend VHDL over Verilog?
You don't want to go there ...
-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"Money is property; it is not speech."
-- Justice John Paul Stevens
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