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In article <8f95h7$4t4$1@news.netpower.no>, >Prof. Andrew Tanenbaum refers to a binary semaphore named "mutex" in >Operating Systems Design and Implementation [...] in 1987. To play OED, I see a similar usage in chapter 1 of D. Comer, "Operating System Design: The XINU approach", copyright 1984. --Article: 22451
David Brown wrote: > > Johan Kwisthout wrote in message <3917fdf7.20732581@obsserver>... > >On Mon, 08 May 2000 22:30:04 -0400, Jerry Avins <jya@ieee.org> wrote: > > > >>Result of check: I asked a CS friend (he has a masters degree and is > >>active in the profession) if he knew or could guess what a mutex is. He > >>had a vague memory that it is a species of mosquito. > >> > >>Jerry > > > >Funny, I study CS in the Netherlands and the theory of operation > >systems (like synchronisation algorithms, multitasking theory) was > >part of the first half of the bachalors program, dealing with > >semaphores, mutexes, critical regions, producers/consumers, deadlocks > >etcetera. Guess it depends on the university where you're studying... > > > > It certainly does. Some universities and courses will cover things like > Windows programming, which does not really have anything to do with CS, but > which looks good to PHBs for later employment. Are you implying, that mutex is MS-speak ? It isn't (although the ingrates do use the term .... there should be a law .... ;-) RennieArticle: 22452
PeterS wrote: > > > >The original system of semaphores, for signalling, used flags. A > >semaphore is simply a signal, as is a flag, flags are not necessarily > >binary, originally semaphore, the method of singalling, each with > >different context sensitive meaning. > > Hmmm, interesting sentence. Wonder what it means ;-) > > Chains of simple signal flags were also used to "post" entire messages from > the rigging > of sailing ships (like Nelson's "England expects this day..." signal at > Trafalgar), > but there was nothing, I guess to stop anyone else (ie no interlock) putting > up a > message from their own rigging, which is why I dislike the interchangeable > use of > "flag" and "semaphore". I agree absolutely. IMO, clarity is not served by overloading existing terms with new meanings. Sometimes, it is simply necessary to create a new word to describe a specific concept. RennieArticle: 22453
Carsten,
If you're receiving a single LVDS stream with embedded clock/data, perhaps NRZ encoding, you're probably out of luck. Conventional wisdom says you need a PLL to recover the clock, and the Virtex DLLs are not PLLs.
Gee, maybe you could build a tapped delay line (by the way, that's what a DLL is) and come up with a method for adjusting the tap, as well as feeding a clock-like signal to the DLL. Good luck, it's probably patentable.
I have a similar requirement (fiber-optic transceiver interface) and I use an external serializer/deserializer which also performs clock recovery and NRZ encoding/decoding.
Marc
Article: 22454Hi I have an unusual request: we have a DataIO programmer that can't program our Altera PROMs. We don't want to invest in an other programmer so we are looking for someone/a company/anything else who owns an Altera programmer near us (Courbevoie, France) who could program the PROMs for us. Thanks in advance -- Nicolas MATRINGE DotCom S.A. Conception electronique 16 rue du Moulin des Bruyeres Tel 00 33 1 46 67 51 11 92400 COURBEVOIE Fax 00 33 1 46 67 51 01 FRANCEArticle: 22455
This is a multi-part message in MIME format. --------------6521A72644FB2885DB29B885 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit > As for software, the Kanda and Atmel packages come with some, for the > Xess one I would also have to spend another $100 for the Foundation > student edition. Buying the Xilinx Student Edition gives you a $30 discount on the XS40 Board. Also, the new version of the Xilinx Student Edition may offer some additional price restructuring whenever it appears. > > > ** so, first question: any known "gotcha's" with the above alternatives? > [ISTR a recent hint that the Atmel software was weak in one respect - > it is noticeable that their web site seems to say almost nothing about > its functionality - and the low cost version of Foundation doesn't > include VHDL?] The Xilinx Student Edition version of Foundation supports Verilog, VHDL, and schematics. > > Are there other reasonable options? I assume you checked all the boards listed at http://www.optimagic.com? -- || Dr. Dave Van den Bout XESS Corp. (919) 387-0076 || || devb@xess.com 2608 Sweetgum Dr. (800) 549-9377 || || http://www.xess.com Apex, NC 27502 USA FAX:(919) 387-1302 || --------------6521A72644FB2885DB29B885 Content-Type: text/x-vcard; charset=us-ascii; name="devb.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Dave Vanden Bout Content-Disposition: attachment; filename="devb.vcf" begin:vcard n:Vanden Bout;Dave tel;fax:(919) 387-1302 tel;work:(919) 387-0076 x-mozilla-html:FALSE url:http://www.xess.com org:XESS Corp. adr:;;2608 Sweetgum Drive;Apex;NC;27502;USA version:2.1 email;internet:devb@xess.com title:FPGA Product Manager x-mozilla-cpt:;-16464 fn:Dave Vanden Bout end:vcard --------------6521A72644FB2885DB29B885--Article: 22456
William LenihanIii wrote in message <3917CA27.73DFB646@earthlink.net>...
>I have some shift registers in a Xilinx Virtex design and between the
>synthesis tool (FPGA Compiler II) and the Xilinx Alliance P&R (2.1i), it
>is placing these shift registers inside the Look-up tables, not in the
>'regular' registers in the slices/CLBs -- which is where I need them
>since they are acting as pipeline registers to help break up the long
>travel time from one side of the chip to the other -- and forcing them
>inside a "SRL16" of one CLB isn't going to do that.
>Is there a way of coaxing the synthesis and/or P&R tool to put shift
>registers in a resource of the designers' choosing (without manual
>instantiation of SRL16's vs. FDCE's)?
The shift registers are in the LUTs? Pardon me but it seems as if your
shift register is not registered! A snippet of your code would be helpful
here.
-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"A sufficiently advanced technology is indistinguishable from magic"
--Arthur C. Clarke
Article: 22457Tomasz Brychcy wrote: > Hello, > > What's synthesisable model (verilog) is better: > > 1) model which contains only nets. > 2) model which contains only registers. > > Both models are exactly the same. > > Thanks for each reply > > tbrychcy@sensor.ime.pz.zgora.pl If I have understood your question correctly, you ask which of the following synthesizable codes is better: input a, b; output c; wire c = a ^ b; or assign c = a ^ b; The other one input a, b; output c; reg c; always @(a or b) c = a ^ b; Well, this is asynchronous logic. Synchronous logic can be only designed with registers. So, a design which can be modelled with either net or reg can be only an asynchronous logic. Asynchronous logic causes big delays in an FPGA anyway. So both of the codes doesn't change much in the RTL synthesis. But from simulation point of view, wire modelling is faster to simulate in Verilog-XL (accelerated assignments?). Are you really trying to design asynchronous logic in FPGA? Utku -- I feel better than James Brown.Article: 22458
Bill Williams wrote: > > Clearly your friend has a bright future at Microsoft. Does Microsoft have a bright future? My friend is a competent and pretty well rounded programmer. His strong point is adaptability, and I imagine that if he were to start a project involving separate threads, he would know what a mutex is pretty quickly. (When I showed him the explanations posted here, he said "Oh, that. Yeah.") But I fear that his confusion of mutex with culex foreshadows a dim future as a naturalist, should he change his profession. Jerry -- Engineering is the art of making what you want from things you can get. -----------------------------------------------------------------------Article: 22459
> During place&route the following message appears:
> Warning: Illegal memory cell name "scfifo_1_8_on_on"
> Error: can't find design file "scfifo_1_8_on_on"
>
> If I use only Maxplus 2 everything works fine.
>
> Is it possible to use megafunctions created with MaxPlus 2 any how?
> How can I use these functions with Leonardo?
Hi,
What is missing is that Exemplar does not know what that module that you
just created is. What you have to do is make a small addition to that file
that MaxPlus2 just created for you.....And that change is to use the
black_box tag. And, a good idea is to put this black box "module" above the
megafuction module to ensure the compile sees it first.
However, I'm a verilog guy, so you will have to port this to VHDL....
Example:
module megafunction(
foo,
bar); /*exemplar synthesis black_box
input foo;
output bar;
endmodule
module megafunction_name(
bunch of stuff
);
more stuff
megafunction megafunction (foo,bar);
//probably some tags "LPM_" for instance
endmodule
Email me if you want more assistance
Xanatos
Article: 22460Problem is resolved, messag can be deleted! My clock-signal did not meet de specs of the input-clock the Xilinx needs. The clock-signal has got a relative great offset. With TTL no problem, but with CMOS (FPGA) problem.Article: 22461
Andy Peters wrote:
The shift registers are in the LUTs? Pardon me but it seems as if your
> shift register is not registered! A snippet of your code would be helpful
> here.
>
For Virtex parts an LUT can be configured as a Shift register in much the same
way as it can be configured as a sync. RAM. See the SRL16xx components in the
lib guide.
One crude way of stopping an SRL being inferred would be to add a reset term,
which they don't support.
reg [7:0] sr;
always @(posedge clk)
if (rst)
sr <= 0;
else
sr <= {sr_din, sr[6:1]};
Article: 22462Does anyone know which Spartan II devices are or will be supported by Foundation base express?Article: 22463
Anyone know what Spartan II device are (or will be) supported by Foundation Base Express.Article: 22464
Anyone know what Spartan II device are (or will be) supported by Foundation Base Express.Article: 22465
Which data IO do you have? I have the 2900 and it programs altera proms no problem....sometimes you have to get software updates for new chips though. (and I'm not in france) In article <39183CFE.DA0A3D5A@dotcom.fr>, Nicolas Matringe <nicolas@dotcom.fr> wrote: > Hi > I have an unusual request: we have a DataIO programmer that can't > program our Altera PROMs. We don't want to invest in an other programmer > so we are looking for someone/a company/anything else who owns an Altera > programmer near us (Courbevoie, France) who could program the PROMs for > us. > Thanks in advance > -- > Nicolas MATRINGE DotCom S.A. > Conception electronique 16 rue du Moulin des Bruyeres > Tel 00 33 1 46 67 51 11 92400 COURBEVOIE > Fax 00 33 1 46 67 51 01 FRANCE > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 22466
Anthony Ellis - LogicWorks wrote: > > Does anyone know which Spartan II devices are or will be supported by > Foundation base express? This is a very good question. But I think it may have been answered already. I seem to remember that someone said it is the same parts that are supported as Virtex devices. But I think there are some new smaller versions of the Spartan II parts like the XC2S15 and the XC2S30 that don't exist as Virtex parts. So it would be nice to get a list from Xilinx. Anyone from Xilinx care to answer? -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 22467
Anyone have any experience with the EETools Topmax universal device programmer? I recently bought a Needham's EMP-20 but returned it and paid a little more for an EETools Topmax for the following reasons: - low voltage device support: the EMP-20 only supports devices down to 5V while the Topmax also supports 3.3/2.7/1.8V (EETools doesn't mention 1.8V support on their web site but the AMD AM29SL800/AM29SL160 1.8V devices are listed in their software). I emailed EETools to suggest listing 1.8V support. - family modules: I experienced the family modules and wanted to avoid the hassle. Didn't want to bother with looking for and having the right family module installed every time I program a device. There are currently 29 family modules for the EMP-20 so I'll be spending an additional ~$400 if I wanted support for all devices. The Topmax have programmable pin drivers and doesn't require family modules. Not having to buy and the convenience and time saved with not having to deal with family modules ever is worth more than the ~$400 price difference between the two units. - device support: The EMP-20 currently supports 1530 devices, EMP-30 with 2245 devices and Topmax with 3356 devices. - frequency of software updates: EMP-20 and EMP-30 software last updated 3/27/200. Topmax last updated 5/4/200 with at least 3 updates within the last two weeks or so when I started researching device programmers. - DOS and Windows support: EMP-20 supports DOS and Windows 95/98, EMP-30 supports DOS and Windows 9X/NT4/NT2000, Topmax supports DOS and Windows 9X/NT4/NT2000. Didn't have any problems running either in a DOS box under Windows 98 SE with ECP/EPP printer port mode setting. EMP-30 has Windows version of software but is listed as beta with fewer devices support than DOS version. Topmax also has Windows software version with same revision number as DOS software (haven't tried). - software ease of use: EMP-20 requires manual look-up of devices. Topmax can search by typing in a few letters of manufacturer and/or part number. Topmax also supports auto device ID on some devices and testing of memory and logic ICs. Edge goes to Topmax software. - quality of construction: EMP-20 has plastic case with internal fan. Case wasn't flush underneath with slight bulging at one corner. Topmax has metal case with no fan. Topmax wins with better construction, better simpler design for low heat with no fan to rattle and break down. - power supply: EMP-20 has external wall plug. Topmax has internal PS which is a little more convenient (no "Dang, I forgot the wall plug"). - additional features: Topmax has removable adapter module, RJ-45 port to interface optional EPROM/EEPROM/flash emulator - support: Both Needham's and EETools are local Northern California based companies. Did a search of the newgroups with good things said about both companies' support. Both companies answer with a live person when calling by phone. I've sent emails to EETools and got a response within a few days. I haven't requested for a new device support but they both seem willing to help. I also considered some other companies but narrowed down to one with the best combination of price, device support, software updates, support and if it's a local company. For support, consider a local company with local engineering support to better support you. Advantech LabTool-48 $1295, slightly higher price, good device support, pin drivers (doesn't require family modules), supports devices down to 3.3V, frequent and recent software updates, not a local company, support unknown BP Micro BP-1400 $8995, very good device support, pin driver (doesn't require family modules), supports devices down to 2.7V, frequent and recent software updates, nearly fell out of my chair when they replied to my email with the price quote (yes, that's $8995), local company EETools Topmax $879-995, to be fair I list prices that are publicly available, I managed to get mine for $850, pin drivers (doesn't require family modules), good device support, supports devices down to 2.7V (looks like it also does 1.8V), frequent and recent software updates, local company Needham's EMP-30 $895-995, requires inconvenient family modules but all available family modules included at time of purchase, supports devices down to 1.8V, fairly recent software updates, good support, local company Needham's EMP-20 $429-449, requires inconvenient family modules as an additional purchase (3 included, additional family modules $50 for 3), fairly recent software updates, supports devices to 5V, good support, local company, if you plan to program a lot of devices you're better off with the EMP-30 or go with a different manufacturer Xeltek Super Pro III $650-695, good price, good device support, pin drivers (doesn't require family modules), fairly recent software updates, some negative posts regarding support (support questionable), seems like they stop supporting a unit when it gets replaced by a newer model, not a local companyArticle: 22468
In article <39166E98.1124CA2B@ieee.org>,
Jerry Avins <jya@ieee.org> wrote:
> Rennie Allen wrote:
> >
> > OneStone wrote:
> > >
> > > 1. You list Binary Semaphore and the even less known term mutex yet omit
> > > the simplest term which is a flag or flag bit.
> >
> > Mutex is an "even less known term" than binary semaphore ? You must
> > move in very different circles than I. The pthreads standard (for which
> > there are at least three popular book titles) mentions little else in
> > the way of mutual exclusion mechanisms, besides mutexes; besides, what
> > could be a better name for a mutual exclusion mechanism than mutex ?
> >
> > Rennie
>
> I'm hardly a CS expert, but I know a few and I'll check with them. I've
> been dealing with semaphores (though I mostly call them flags) for
> years, but I heard of "mutex" for the first time in this thread.
same here. i called those things a "handshake flag" but someone at
Eventide told me in 1993 that them critters are called semafers.
--
r b-j
pbjrbj@viconet.com a.k.a. robert@audioheads.com
a.k.a. robert@wavemechanics.com
"Don't give into the Dark Side. Boycott intel and microsoft."
Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 22469
www.opencores.org has three boards of varying complexity and
www.optimagic.com has links to a number of dev.board manufacturers.
ray
myself <myself@magma.ca> wrote in message
news:39181fe5.1681331@news.magma.ca...
> Hi does anyone have a simple schematic for a Xilinx fpga board.
>
> perhaps the 4000 series fpga and a power supply, clock and some i/o &
> or connectors?
>
> I will be buying the student edition book and sw when the new version
> comes out in July. I think there are schematics for there demo board
> in the book, but i would like to design a pcb to test out some designs
> now.
>
> p.s. I use "pads power pcb" but can import most ascii files schmatic
> and or PCB. or with a word or pdf file I could create my own schematic
> and pcb.
>
> Thanks any help is appreciated.
>
> My email address if it is easyer to send there is "martinb@magma.ca"
>
Article: 22470
On 9 May 2000 16:03:13 GMT, lied@w-lied1.ih.lucent.com (Robert Lied)
wrote:
>In article <8f95h7$4t4$1@news.netpower.no>,
>>Prof. Andrew Tanenbaum refers to a binary semaphore named "mutex" in
>>Operating Systems Design and Implementation [...] in 1987.
>
>To play OED, I see a similar usage in chapter 1 of
>D. Comer, "Operating System Design: The XINU approach", copyright 1984.
"Structured Concurrent Programming with Operating Systems
Applications," Holt et. al., 1978
I suspect the term is even older than that.
Regards,
-=Dave
--
The opinions expressed in this post are my own and do not
represent the views of CyberOptics Corporation.
Change is inevitable. Except from a vending machine.
Article: 22471Try www.aps-euro.com : stand-alone board, PC104 boards, ISA board. Laurent myself a écrit : > Hi does anyone have a simple schematic for a Xilinx fpga board. > > perhaps the 4000 series fpga and a power supply, clock and some i/o & > or connectors? > > I will be buying the student edition book and sw when the new version > comes out in July. I think there are schematics for there demo board > in the book, but i would like to design a pcb to test out some designs > now. > > p.s. I use "pads power pcb" but can import most ascii files schmatic > and or PCB. or with a word or pdf file I could create my own schematic > and pcb. > > Thanks any help is appreciated. > > My email address if it is easyer to send there is "martinb@magma.ca"Article: 22472
Hi all, I am a novice user of the Altera software and I am stuck with a design that I run through Quartus 2000.03 and I get an error during compilation: clock skew is greater then data delay, ciruit will not function. If this is trivial, I apologize, but I could not find a solution via Altera's atlas db website. I am using an EDIF from the Leonardo Specturm 1999.1j synthesis tool as input. The clock with the problem is the only clock I am constraining with the Quartus software. To fix this, do I have to use a certain global clock buffer in my VHDL or do I need to locate the clock pin, or something else? I am not locating any IO pins yet. Any suggestions are appreciated. Don M.Article: 22473
Synplify infers the SRL16 or SRL16e if there is no reset term. These, as you know, use the LUT as a 16 bit shift register in the VIrtex devices. Put a reset term on the shift register to keep it out of the LUT. If you don't use the reset term, connect it to a dummy signal and keep that from getting optimized out in synthesis by putting a syn_keep attribute on the dummy signal. William LenihanIii wrote: > I have some shift registers in a Xilinx Virtex design and between the > synthesis tool (FPGA Compiler II) and the Xilinx Alliance P&R (2.1i), it > is placing these shift registers inside the Look-up tables, not in the > 'regular' registers in the slices/CLBs -- which is where I need them > since they are acting as pipeline registers to help break up the long > travel time from one side of the chip to the other -- and forcing them > inside a "SRL16" of one CLB isn't going to do that. > > Is there a way of coaxing the synthesis and/or P&R tool to put shift > registers in a resource of the designers' choosing (without manual > instantiation of SRL16's vs. FDCE's)? > > -- > ======================== > William Lenihan > lenihan3we@earthlink.net > ========================Article: 22474
If you look at the FPGA architectural features as they apply to a computer design, I think you'd wind up settling on the Xilinx architectures. First, you'll probably want a fast carry chain so that you can do fast arithmetic with minimal logic. That rules out pretty much everyone except Xilinx, Altera and Lucent. I haven't seen any commercial boards with Lucent, so bye bye Lucent. Xilinx has a capability of using a LUT (a four input look-up table which is the basis of the FPGA architecture) as a small RAM or shift register. This makes for very compact register files, pipeline delays, reordering queues etc. In Altera, each bit of storage chews up another logic element unless you use the buld memories. Also, Altera's carry logic structure is not as powerful as the Xilinx structure, which means you will probably need two levels of logic for real-world arithmetic vs 1 level of logic in Xilinx. If you want it small, you could always go to a bit serial design. A pretty decent bit serial scientific calculator will fit in an XCS-05 Andy Holt wrote: > This is the sort of thing I would expect to be an FAQ, but there doesn't > seem to be one for this group. > > I have been thinking about "playing" with an FPGA both from the view of > learning about an interesting-looking technology and with the hope of > constructing an emulation of a '60s mainframe (more about this later). > > I am looking for advice on low-cost ways of doing this (Let's say price > ceiling of about £200 [$300]). It seems that I am going to need two main > things: > * A package of software. > * A prototyping/evaluation board. > > Taking the second of these first there seem to be few choices available > (without paying lots of $$$) - > > The most obvious seems to be the XS40 from Xess using the Xilinx 4000 > series devices. (http://www.xess.com) > > Less expensive with more features on board is the Atmel FPGA Starter Kit > from Kanda (http://www.kanda.com) > > If I qualify for the special deal (I am a member of staff at a > University), the Altera Design Laboratory Package looks very > attractively priced - if I can't get the deal it is likely to be too > expensive. (http://www.altera.com) > > The only other low-priced boards available seem to be the Australian > ones from Burch Electronic Designs (http://www.burched.com.au) that were > recently advertised on this group. However they seem to be very "bare" > and more designed for building real-world prototypes than for learning. > All versions also come with FPGAs of minimal capacity (almost certainly > too small for my "big" project). > > As for software, the Kanda and Atmel packages come with some, for the > Xess one I would also have to spend another $100 for the Foundation > student edition. > > ** so, first question: any known "gotcha's" with the above alternatives? > [ISTR a recent hint that the Atmel software was weak in one respect - > it is noticeable that their web site seems to say almost nothing about > its functionality - and the low cost version of Foundation doesn't > include VHDL?] > Are there other reasonable options? > > The other main question I have concerns estimating how big an FPGA I > would need for the mainframe emulation. I assume that the "usable gate" > counts for all devices tend to be as much marketing as technical > statements. I have detailed (but only "almost complete") descriptions of > the logic design for the mainframe that I am interested in (ICT 1905 - > aka FP6000) and I can be reasonably confident that it has less than 6000 > gates including FPU ... probably less than 4000 without. Is this likely > to fit in a "10000 gate" FPGA?, a "20000 gate" one, or whatever? > > More questions later :-) > > Andy Holt > Systems Consultant > City University > London, England > andyh@city.ac.uk
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