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Threads Starting Oct 2000
26018: 00/10/01: Muzaffer Kal: multi-input adders in virtex ?
26020: 00/10/01: Ray Andraka: Re: multi-input adders in virtex ?
26022: 00/10/01: Muzaffer Kal: Re: multi-input adders in virtex ?
26026: 00/10/01: Ray Andraka: Re: multi-input adders in virtex ?
26028: 00/10/01: Muzaffer Kal: Re: multi-input adders in virtex ?
26037: 00/10/01: Jamie Lokier: Re: multi-input adders in virtex ?
26039: 00/10/01: Ray Andraka: Re: multi-input adders in virtex ?
26032: 00/10/01: <erika_uk@my-deja.com>: Re: multi-input adders in virtex ?
26040: 00/10/01: Ray Andraka: Re: multi-input adders in virtex ?
26052: 00/10/02: <erika_uk@my-deja.com>: Re: multi-input adders in virtex ?
26058: 00/10/02: Ray Andraka: Re: multi-input adders in virtex ?
26064: 00/10/02: Jan Gray: Re: multi-input adders in virtex ?
26071: 00/10/03: Keith R. Williams: Re: multi-input adders in virtex ?
26202: 00/10/08: Austin Franklin: Re: multi-input adders in virtex ?
26213: 00/10/09: Keith R. Williams: Re: multi-input adders in virtex ?
26226: 00/10/09: Austin Franklin: Re: multi-input adders in virtex ?
26251: 00/10/10: Keith R. Williams: Re: multi-input adders in virtex ?
26117: 00/10/04: <ed.moore@snellwilcox.com>: Re: multi-input adders in virtex ?
26203: 00/10/08: Austin Franklin: Re: multi-input adders in virtex ?
26038: 00/10/01: K.J. Seefried III: Migrating PAL/TTL design to FPGA
26041: 00/10/01: rickman: Re: Migrating PAL/TTL design to FPGA
26044: 00/10/02: Jim Granville: Re: Migrating PAL/TTL design to FPGA
26042: 00/10/01: Rami: Begineer
26045: 00/10/01: Vincent J. Mooney: CASES 2000 Advanced Program
26047: 00/10/01: Netscape User: GPIO on AVNET Xilinx FPGA board? any cables?!?
26048: 00/10/01: Muzaffer Kal: Re: GPIO on AVNET Xilinx FPGA board? any cables?!?
26049: 00/10/01: David Forbes: Re: GPIO on AVNET Xilinx FPGA board? any cables?!?
26056: 00/10/02: Rick Filipkiewicz: Re: GPIO on AVNET Xilinx FPGA board? any cables?!?
26095: 00/10/03: Netscape User: Re: GPIO on AVNET Xilinx FPGA board? any cables?!?
26051: 00/10/02: Sherdyn: Programming Cypress Graphics Clock Generator
26065: 00/10/02: Steve Wiseman: Re: Programming Cypress Graphics Clock Generator
26080: 00/10/03: Sherdyn: Re: Programming Cypress Graphics Clock Generator
26053: 00/10/02: Vipan Kakkar: Multiplication
26059: 00/10/02: Ray Andraka: Re: Multiplication
26165: 00/10/06: Vipan Kakkar: Re: Multiplication
26170: 00/10/06: Ray Andraka: Re: Multiplication
26057: 00/10/02: Jan Gray: "Xilinx Adds FPGA Support to Free Web Design Tools"
26060: 00/10/02: rickman: Re: "Xilinx Adds FPGA Support to Free Web Design Tools"
26066: 00/10/02: Rick Filipkiewicz: Re: "Xilinx Adds FPGA Support to Free Web Design Tools"
26079: 00/10/03: Nicolas Matringe: Re: "Xilinx Adds FPGA Support to Free Web Design Tools"
26081: 00/10/03: Jerry English: Re: "Xilinx Adds FPGA Support to Free Web Design Tools"
26061: 00/10/02: Andy Peters: Synthesis failures
26067: 00/10/02: Andy Peters: Re: Synthesis failures
26068: 00/10/02: rickman: Re: Synthesis failures
26069: 00/10/03: Jim Granville: Re: Synthesis failures
26072: 00/10/02: rickman: Re: Synthesis failures
26087: 00/10/03: Andy Peters: Re: Synthesis failures
26086: 00/10/03: Andy Peters: Re: Synthesis failures
26074: 00/10/02: Qian Zhang: Xilinx Demo Board
26078: 00/10/03: Christophe Heyert: Re: Xilinx Demo Board
26082: 00/10/03: Martin Schoeberl: JVM processor
26084: 00/10/03: Jan Gray: Re: JVM processor
26085: 00/10/03: Jan Gray: Re: JVM processor
26110: 00/10/04: Richard Meester: Re: JVM processor
26113: 00/10/04: Jan Gray: Re: JVM processor
26116: 00/10/04: Jan Gray: Re: JVM processor
26088: 00/10/03: <erika_uk@my-deja.com>: Pwr/Gnd ( again)
26092: 00/10/03: Ray Andraka: Re: Pwr/Gnd ( again)
26108: 00/10/04: <erika_uk@my-deja.com>: Re: Pwr/Gnd ( again)
26115: 00/10/04: Ray Andraka: Re: Pwr/Gnd ( again)
26138: 00/10/05: <erika_uk@my-deja.com>: Re: Pwr/Gnd ( again)
26141: 00/10/05: Ray Andraka: Re: Pwr/Gnd ( again)
26150: 00/10/05: <husby@my-deja.com>: Re: Pwr/Gnd ( again)
26093: 00/10/04: <korthner@inf.furukawa.co.jp>: Xilinx Licensing.
26098: 00/10/03: rickman: Re: Xilinx Licensing.
26107: 00/10/04: Marc Reinert: Re: Xilinx Licensing.
26111: 00/10/04: Jerry English: Re: Xilinx Licensing.
26118: 00/10/04: Andy Peters: Re: Xilinx Licensing.
26119: 00/10/04: bob elkind: Re: Xilinx Licensing.
26122: 00/10/04: rickman: Re: Xilinx Licensing.
26124: 00/10/04: bob elkind: Re: Xilinx Licensing.
26145: 00/10/05: Peter Alfke: Re: Xilinx Licensing.
26125: 00/10/05: Rick Filipkiewicz: Re: Xilinx Licensing.
26129: 00/10/05: Kent Orthner: Re: Xilinx Licensing.
26143: 00/10/05: rickman: Re: Xilinx Licensing.
26161: 00/10/06: Rick Filipkiewicz: Re: Xilinx Licensing.
26099: 00/10/04: J.L. Mitchell: test
26100: 00/10/03: Qian Zhang: Urgent How to generate BitFile
26102: 00/10/04: ±è¾ç·¡_YLKIM: [Req] Schematic for using Xilinx XC4000E Series.
26103: 00/10/03: Dexin Li: test
26104: 00/10/04: Pauric Hennessy: Category : virtex e I/O bank contention
26121: 00/10/04: Rick Filipkiewicz: Re: Category : virtex e I/O bank contention
26130: 00/10/05: <nishioka@my-deja.com>: Re: Category : virtex e I/O bank contention
26131: 00/10/05: <nishioka@my-deja.com>: Re: Category : virtex e I/O bank contention
26157: 00/10/05: Alun: Re: Category : virtex e I/O bank contention
26105: 00/10/04: Felicia: Xilinx FPGA Modules: Delays & Ha
26106: 00/10/04: <gabriel_t@my-deja.com>: Boundary Scan and LVDS in Virtex E
26127: 00/10/05: Kent Orthner: Re: Boundary Scan and LVDS in Virtex E
26167: 00/10/06: <gabriel_t@my-deja.com>: Re: Boundary Scan and LVDS in Virtex E
26112: 00/10/04: Daniel Nilsson: pci host
26146: 00/10/05: Iwo Mergler: Re: pci host
26178: 00/10/06: Steve Rencontre: Re: pci host
26152: 00/10/05: Steve Rencontre: Re: pci host
26162: 00/10/06: <sulimma@my-deja.com>: Re: pci host
26419: 00/10/15: Austin Franklin: Re: PCI host
26425: 00/10/16: Nicolas Matringe: Re: PCI host
26120: 00/10/05: Allan Herriman: DLL unlocking
26123: 00/10/04: bob elkind: Re: DLL unlocking
26139: 00/10/05: <news@rtrussell.co.uk>: Re: DLL unlocking
26128: 00/10/05: S. Ramirez: Re: DLL unlocking
26136: 00/10/05: <eml@riverside-machines.com.NOSPAM>: Re: DLL unlocking
26147: 00/10/05: Austin Lesea: Re: DLL unlocking
26219: 00/10/09: Allan Herriman: Re: DLL unlocking
26132: 00/10/04: Michael Fluet: 3DES VHDL
26134: 00/10/05: Mike Johnson: Re: 3DES VHDL
26135: 00/10/05: <eml@riverside-machines.com.NOSPAM>: Re: 3DES VHDL
26133: 00/10/05: Martin.J Thompson: Re: Simon , decoupling caps
26137: 00/10/05: Hchen: Xilinx BoardScope
26144: 00/10/05: Phil James-Roxby: Re: Xilinx BoardScope
26142: 00/10/05: Anders=?iso-8859-1?q?_Bostr=F6m?=: Re: Xilinx par tool version 3.2i triggers wine bug
26149: 00/10/05: Andy Peters: Final word on the inverted RAM write clock problem
26151: 00/10/05: Alastair Allen: PhD studentship
26156: 00/10/05: Domagoj: Non-standard vhdl expressions
26168: 00/10/06: <eml@riverside-machines.com.NOSPAM>: Re: Non-standard vhdl expressions
26175: 00/10/06: Jonathan Bromley: Re: Non-standard vhdl expressions
26176: 00/10/06: Rick Filipkiewicz: Re: Non-standard vhdl expressions
26185: 00/10/07: Domagoj: Re: Non-standard vhdl expressions
26238: 00/10/09: <eml@riverside-machines.com.NOSPAM>: Re: Non-standard vhdl expressions
26245: 00/10/10: Domagoj: Re: Non-standard vhdl expressions
26158: 00/10/05: Tom Hicks: Simultaneous Switching question
26159: 00/10/05: Gary Cook: Altera Internal Error
26164: 00/10/06: JPC: Re: Altera Internal Error
26182: 00/10/08: Fairbairn Family: Re: Altera Internal Error
26184: 00/10/07: <s_sharma@my-deja.com>: Re: Altera Internal Error
26421: 00/10/16: Leonid Shvarzberg: Re: Altera Internal Error
26426: 00/10/16: Gary Cook: Re: Altera Internal Error
26163: 00/10/06: Dines Justesen: Floorplanning
26166: 00/10/06: Maciek Kudla: Problem Foundation 3.1 sp 3
26188: 00/10/07: <gazit@my-deja.com>: Re: Problem Foundation 3.1 sp 3
26239: 00/10/09: Yenni Totong: Re: Problem Foundation 3.1 sp 3
26171: 00/10/06: Marc Reinert: programm Xilinx FPGAs via JTAG
26174: 00/10/06: Nicolas Matringe: Re: programm Xilinx FPGAs via JTAG
26177: 00/10/06: Rick Filipkiewicz: Re: programm Xilinx FPGAs via JTAG
26189: 00/10/07: <rotemg@mysticom.com>: Re: programm Xilinx FPGAs via JTAG
26201: 00/10/08: Austin Franklin: Re: program Xilinx FPGAs via JTAG
26180: 00/10/06: <sfeldman@my-deja.com>: Re: programm Xilinx FPGAs via JTAG
26183: 00/10/07: <s_sharma@my-deja.com>: Re: programm Xilinx FPGAs via JTAG
26186: 00/10/08: David R Brooks: Re: programm Xilinx FPGAs via JTAG
26220: 00/10/09: Marc Reinert: Re: programm Xilinx FPGAs via JTAG // so far, so good
26221: 00/10/09: <rotemg@mysticom.com>: Re: programm Xilinx FPGAs via JTAG // so far, so good
26222: 00/10/09: Marc Reinert: Re: programm Xilinx FPGAs via JTAG // so far, so good
26242: 00/10/09: <rotemg@mysticom.com>: Re: programm Xilinx FPGAs via JTAG // so far, so good
26224: 00/10/09: <mpeattie@my-deja.com>: Re: programm Xilinx FPGAs via JTAG // so far, so good
26173: 00/10/06: <brian13074@my-deja.com>: Project Leader, Architecture Modeling
26179: 00/10/06: Andy Peters: Re: Project Leader, Architecture Modeling
26181: 00/10/07: Rick Filipkiewicz: Re: Project Leader, Architecture Modeling
26232: 00/10/09: Andy Peters: Re: Project Leader, Architecture Modeling
26275: 00/10/10: <husby@my-deja.com>: Headhunter, The Game (Re: Project Leader, Architecture Modeling)
26187: 00/10/07: <mike_login@my-deja.com>: TMS320C54x interface
26195: 00/10/08: Barry Schneider: Long Island Verilog and VHDL people wanted!!
26196: 00/10/07: Bob Perlman: Re: Long Island Verilog and VHDL people wanted!!
26200: 00/10/08: Rick Filipkiewicz: Re: Long Island Verilog and VHDL people wanted!!
26288: 00/10/10: Barry Schneider: Re: Long Island Verilog and VHDL people wanted!!
26296: 00/10/10: Bob Perlman: Re: Long Island Verilog and VHDL people wanted!!
26231: 00/10/09: Andy Peters: Re: Long Island Verilog and VHDL people wanted!!
26204: 00/10/08: Jerry English: Foundation iSE and Coregen limited devices
26205: 00/10/08: Steve Dewey: Analogue FPGAs ?
26225: 00/10/09: Hawker: Re: Analogue FPGAs ?
26227: 00/10/09: rickman: Re: Analogue FPGAs ?
26228: 00/10/09: Hawker: Re: Analogue FPGAs ?
26237: 00/10/09: Theron Hicks: Re: Analogue FPGAs ?
26229: 00/10/09: S. Ramirez: Re: Analogue FPGAs ?
26319: 00/10/11: K. C. Lee: Re: Analogue FPGAs ?
26328: 00/10/11: rickman: Re: Analogue FPGAs ?
26391: 00/10/13: K. C. Lee: Re: Analogue FPGAs ?
26230: 00/10/09: Andy Peters: Re: Analogue FPGAs ?
26258: 00/10/10: rk: Re: Analogue FPGAs ?
26279: 00/10/10: Andy Peters: Re: Analogue FPGAs ?
26291: 00/10/10: rk: Re: Analogue FPGAs ?
26313: 00/10/11: Andy Peters: Re: Analogue FPGAs ?
26316: 00/10/11: S. Ramirez: Re: Analogue FPGAs ?
26329: 00/10/11: rickman: Re: Analogue FPGAs ?
26346: 00/10/12: Andy Peters: Re: Analogue FPGAs ?
26363: 00/10/13: rickman: Re: Analogue FPGAs ?
26247: 00/10/10: <bob_42690@my-deja.com>: Re: Analogue FPGAs ?
26216: 00/10/08: yihua xu: Help me! the limit of a signal's drive capacity
26218: 00/10/09: Joel Kolstad: Re: Help me! the limit of a signal's drive capacity
26223: 00/10/09: Patrick Schulz: BIST: Testing embedded RAMs
26283: 00/10/10: Adrian Dunn: Re: Testing embedded RAMs
26301: 00/10/11: Patrick Schulz: Re: Testing embedded RAMs
26240: 00/10/09: Anurag Tiwari: 68000 vhdl model
26243: 00/10/09: Jan Gray: Re: 68000 vhdl model
26257: 00/10/10: Rissa Tero: Re: 68000 vhdl model
26278: 00/10/10: Edward L. Hepler: Re: 68000 vhdl model
26256: 00/10/10: Angel: Re: 68000 vhdl model
26244: 00/10/09: rickman: ModelSim XE/Starter speed issues
26248: 00/10/10: <bob_42690@my-deja.com>: Re: ModelSim XE/Starter speed issues
26255: 00/10/10: rickman: Re: ModelSim XE/Starter speed issues
26259: 00/10/10: Dines Justesen: Re: ModelSim XE/Starter speed issues
26274: 00/10/10: rickman: Re: ModelSim XE/Starter speed issues
26455: 00/10/16: Geezer: Re: ModelSim XE/Starter speed issues
26466: 00/10/17: Dines Justesen: Re: ModelSim XE/Starter speed issues
26467: 00/10/17: Dines Justesen: Re: ModelSim XE/Starter speed issues
26264: 00/10/10: Georg Heinrich, Student: Difference FPGA Compiler 1/2 from SYNOPSYS
26270: 00/10/10: Mark Rawlings: Computer Architecture emulator on a Xilinx chip
26304: 00/10/11: Utku Ozcan: Re: Computer Architecture emulator on a Xilinx chip
26271: 00/10/10: George Koukouras: Delay locked loop in a Spartan II
26300: 00/10/11: George Koukouras: Re: Delay locked loop in a Spartan II
26277: 00/10/10: <tbrychcy@my-deja.com>: Setup error
26282: 00/10/10: Tim Boescke: Bidirectional IO with ispDesignEXPERT
26286: 00/10/10: Michael Barr: ANNOUNCE: Bibliography Update!
26294: 00/10/10: Steve Su: Modular Exponentiation
26295: 00/10/11: Muzaffer Kal: Re: Modular Exponentiation
26306: 00/10/11: bubba: Re: Modular Exponentiation
26299: 00/10/11: news tin: palasm
26308: 00/10/11: Dan Kuechle: Re: palasm
26317: 00/10/11: S. Ramirez: Re: palasm
26315: 00/10/12: Jim Granville: Re: palasm
26330: 00/10/11: John Larkin: Re: palasm
26355: 00/10/12: bob elkind: Re: palasm
26378: 00/10/13: Andy Peters: Re: palasm
26390: 00/10/14: S. Ramirez: Re: palasm
26424: 00/10/16: Klaus Falser: Re: palasm
26453: 00/10/16: S. Ramirez: Re: palasm
26445: 00/10/16: Andy Peters: Re: palasm
26354: 00/10/13: news tin: Re: palasm
26410: 00/10/15: Peter: Re: palasm
26413: 00/10/15: M. Simon: Re: palasm
26302: 00/10/11: Georg Heinrich: Constraints in FPGA Comp. II
26307: 00/10/11: Lars: LUT to CLB assignment
26311: 00/10/11: Steven Derrien: Re: LUT to CLB assignment
26333: 00/10/12: Dines Justesen: Re: LUT to CLB assignment
26339: 00/10/12: <eml@riverside-machines.com.NOSPAM>: Re: LUT to CLB assignment
26439: 00/10/16: Ray Andraka: Re: LUT to CLB assignment
26310: 00/10/11: Jon Seddon: FPGA PCB design examples
26414: 00/10/15: M. Simon: Re: FPGA PCB design examples
26312: 00/10/11: Stuart J Adams: Xilinx FDN Express vs. Base Express ??
26350: 00/10/12: Mark Harvey: Re: Xilinx FDN Express vs. Base Express ??
26318: 00/10/12: Igal K.: LCELL in MAX+plusII
26320: 00/10/11: Andy Peters: Xilinx, Altera stocks take dumps!
26325: 00/10/11: Netscape User: Re: Xilinx, Altera stocks take dumps!
26337: 00/10/12: EKC: Re: Xilinx, Altera stocks take dumps!
26334: 00/10/12: anand kuriakose: Category : Subject:Floorplanning
26335: 00/10/12: Lars Rzymianowicz: Re: Category : Subject:Floorplanning
26340: 00/10/12: <eml@riverside-machines.com.NOSPAM>: Re: Category : Subject:Floorplanning
26343: 00/10/12: rickman: Re: Category : Subject:Floorplanning
26345: 00/10/12: Walter Haas: Re: Category : Subject:Floorplanning
26336: 00/10/12: alten: Category : Subject
26351: 00/10/12: Caleb Hess: Long filenames in Express schematic editor
26381: 00/10/13: Andy Peters: Re: Long filenames in Express schematic editor
26352: 00/10/12: Jeff Tong: PCB board simulation - Need basic help!
26364: 00/10/13: Uwe: How to functionally simulate Xilinx Cores in my design ?
26380: 00/10/13: Andy Peters: Re: How to functionally simulate Xilinx Cores in my design ?
26365: 00/10/13: Franz Hollerer: VHDL synthesis with synopsys
26366: 00/10/13: Steven Derrien: Re: VHDL synthesis with synopsys
26367: 00/10/13: Georg Heinrich: Re: VHDL synthesis with synopsys
26368: 00/10/13: Steven Derrien: Re: VHDL synthesis with synopsys
26369: 00/10/13: Lars: const coeff multiplier w/ LUTs
26371: 00/10/13: Dines Justesen: Re: const coeff multiplier w/ LUTs
26373: 00/10/13: Phil James-Roxby: Re: const coeff multiplier w/ LUTs
26492: 00/10/18: <eml@riverside-machines.com.NOSPAM>: Re: const coeff multiplier w/ LUTs
26377: 00/10/13: Peter Alfke: Re: const coeff multiplier w/ LUTs
26437: 00/10/16: Ray Andraka: Re: const coeff multiplier w/ LUTs
26370: 00/10/13: Brendan Lynskey: CRC calculation
26375: 00/10/13: <eml@riverside-machines.com.NOSPAM>: Re: CRC calculation
26372: 00/10/13: giuseppe: PROM 17512
26440: 00/10/16: Rascal: Re: PROM 17512
26483: 00/10/18: giuseppe: R: source PROM 17512
26491: 00/10/18: Rascal: Re: source PROM 17512
26514: 00/10/18: Tom Burgess: Re: source PROM 17512
26516: 00/10/18: Tom Burgess: Re: source PROM 17512
26374: 00/10/13: jean-francois hasson: 5V compatible Virtex
26384: 00/10/13: Uwe: Re: 5V compatible Virtex
26386: 00/10/13: Alun: Re: 5V compatible Virtex
26387: 00/10/13: Keith R. Williams: Re: 5V compatible Virtex
26389: 00/10/13: Jonas Thor: Re: 5V compatible Virtex
26393: 00/10/14: Muzaffer Kal: Re: 5V compatible Virtex
26397: 00/10/14: Rick Filipkiewicz: Re: 5V compatible Virtex
26493: 00/10/18: <eml@riverside-machines.com.NOSPAM>: Re: 5V compatible Virtex
26506: 00/10/18: Rick Filipkiewicz: Re: 5V compatible Virtex
26561: 00/10/20: Grumps: Re: 5V compatible Virtex
26431: 00/10/16: Grumps: Re: 5V compatible Virtex
26435: 00/10/16: Ray Andraka: Re: 5V compatible Virtex
26436: 00/10/16: Kent Orthner: Re: 5V compatible Virtex
26447: 00/10/16: Ray Andraka: Re: 5V compatible Virtex
26441: 00/10/16: Grumps: Re: 5V compatible Virtex
26460: 00/10/17: Kent Orthner: Re: 5V compatible Virtex
26463: 00/10/17: Ray Andraka: Re: 5V compatible Virtex
26468: 00/10/17: Kent Orthner: Re: 5V compatible Virtex
26376: 00/10/13: <mbzbcm@aol.com>: AOL - TIME WARNER MERGER! Tell the F.C.C. what you think! 7734
26382: 00/10/13: Joe: ModelTech's VHDL Vsim and Xilinx's old XACT place/route
26388: 00/10/13: James S.: clk'event
26392: 00/10/14: S. Ramirez: Re: clk'event
26401: 00/10/14: Mike Harris: Re: clk'event
26433: 00/10/16: Ray Andraka: Re: clk'event
26394: 00/10/14: <andrew_f66@my-deja.com>: Sinusoidal PWM on a Xilinx FPGA
26500: 00/10/18: Santiago de Pablo: Re: Sinusoidal PWM on a Xilinx FPGA
26395: 00/10/14: <andrew_f66@my-deja.com>: Sinusoidal PWM on Xilinx FPGA
26400: 00/10/14: Mike Harris: Re: Sinusoidal PWM on Xilinx FPGA
26404: 00/10/14: rickman: Re: Sinusoidal PWM on Xilinx FPGA
26408: 00/10/15: Jim Granville: Re: Sinusoidal PWM on Xilinx FPGA
26423: 00/10/16: Ulf Samuelsson: Re: Sinusoidal PWM on Xilinx FPGA
26438: 00/10/16: Ray Andraka: Re: Sinusoidal PWM on Xilinx FPGA
26396: 00/10/14: Christof Paar: CHES 2001 Workshop
26399: 00/10/14: Tom St Denis: Re: CHES 2001 Workshop
26448: 00/10/16: Mike Rosing: Re: CHES 2001 Workshop
26449: 00/10/16: Tom St Denis: Re: CHES 2001 Workshop
26450: 00/10/16: Tom St Denis: Re: CHES 2001 Workshop
26398: 00/10/14: Stuart J Adams: DLL's Spread Spectrum Compatible ??
26407: 00/10/15: Jonas Thor: Re: DLL's Spread Spectrum Compatible ??
26411: 00/10/15: Hal Murray: Re: DLL's Spread Spectrum Compatible ??
26418: 00/10/15: Mark Harvey: Re: DLL's Spread Spectrum Compatible ??
26420: 00/10/15: Lessard: business opportunity
26427: 00/10/16: Eric Montreal: Asynchronous pulse generation with Spartan.
26428: 00/10/16: Eric Montreal: Asynchronous pulse generation with Spartan.
26443: 00/10/16: rickman: Re: Asynchronous pulse generation with Spartan.
26465: 00/10/17: Eric Montreal: Re: Asynchronous pulse generation with Spartan.
26469: 00/10/17: rickman: Re: Asynchronous pulse generation with Spartan.
26557: 00/10/20: Eric Montreal: Mailbox (was "Asynchronous pulse generation with Spartan.")
26560: 00/10/20: Philip Freidin: Re: Mailbox (was "Asynchronous pulse generation with Spartan.")
26566: 00/10/20: Eric Montreal: Re: Mailbox (was "Asynchronous pulse generation with Spartan.")
26477: 00/10/18: Rick Filipkiewicz: Re: Asynchronous pulse generation with Spartan.
26429: 00/10/16: <e97bjli@thn.htu.se>: Low power cpld?
26432: 00/10/16: Laurent Gauch: Re: Low power cpld?
26451: 00/10/17: Jim Granville: Re: Low power cpld?
26434: 00/10/16: Sten Sogaard: Sporadic Error: ERROR:JTag - Illegal character ?
26444: 00/10/16: =?iso-8859-1?Q?J=F6rg?= Ritter: ordered list
26462: 00/10/17: Kent Orthner: Re: ordered list
26470: 00/10/17: Peter Alfke: Re: ordered list
26471: 00/10/17: Tom: Has anyone done a biquad filter in xilinx FPGAs?
26473: 00/10/17: Neil Franklin: VHDL vs Verilog
26474: 00/10/17: Ray Andraka: Re: VHDL vs Verilog
26475: 00/10/17: Muzaffer Kal: Re: VHDL vs Verilog
26476: 00/10/17: Ray Andraka: Re: VHDL vs Verilog
26479: 00/10/18: Muzaffer Kal: Re: VHDL vs Verilog
26481: 00/10/18: Ray Andraka: Re: VHDL vs Verilog
26586: 00/10/21: <erika_uk@my-deja.com>: Re: VHDL vs Verilog
26591: 00/10/21: Ray Andraka: Re: VHDL vs Verilog
26538: 00/10/19: Andy Peters: Re: VHDL vs Verilog
26568: 00/10/20: Brian Drummond: Re: VHDL vs Verilog
26480: 00/10/18: Kent Orthner: Re: VHDL vs Verilog
26478: 00/10/17: Gary Spivey: Backannotated Simulation of Annapolis Microsystems Starfire
26485: 00/10/18: peter: scripting with xilinx tools (foundation) ????
26515: 00/10/18: Petter Gustad: Re: scripting with xilinx tools (foundation) ????
26517: 00/10/18: Dave Vanden Bout: Re: scripting with xilinx tools (foundation) ????
26518: 00/10/18: Brian Philofsky: Re: scripting with xilinx tools (foundation) ????
26533: 00/10/19: <erika_uk@my-deja.com>: Re: scripting with xilinx tools (foundation) ????
26534: 00/10/19: Brian Philofsky: Re: scripting with xilinx tools (foundation) ????
26486: 00/10/18: Marc Reinert: Virtex-E and ADC
26501: 00/10/18: Newsbrowser: Re: Virtex-E and ADC
26502: 00/10/18: Marc Reinert: Re: Virtex-E and ADC
26601: 00/10/21: Netscape User: Re: Virtex-E and ADC
26488: 00/10/18: Franz Hollerer: Q: Xilinx unified libraries and synthesis
26489: 00/10/18: Kent Orthner: Re: Q: Xilinx unified libraries and synthesis
26498: 00/10/18: Ray Andraka: Re: Q: Xilinx unified libraries and synthesis
26537: 00/10/19: Andy Peters: Re: Q: Xilinx unified libraries and synthesis
26490: 00/10/18: Nicolas Matringe: Virtex pull-up/down resistors question
26499: 00/10/18: Ray Andraka: Re: Virtex pull-up/down resistors question
26504: 00/10/18: Nicolas Matringe: Re: Virtex pull-up/down resistors question
26494: 00/10/18: Michael Boehnel: F3.1i, Win2k, LMACs
26496: 00/10/18: Marc Reinert: Re: F3.1i, Win2k, LMACs
26497: 00/10/18: Michael Boehnel: Re: F3.1i, Win2k, LMACs
26503: 00/10/18: Nicholas Weaver: Stupid Virtex Trick...
26505: 00/10/18: Paul Smith: Spartan II ?
26507: 00/10/18: Ray Andraka: Re: Spartan II ?
26524: 00/10/19: Harjo Otten: Re: Spartan II ?
26828: 00/10/31: Leon Heller: Re: Spartan II ?
26829: 00/10/31: Paul Smith: Re: Spartan II ?
26853: 00/11/01: Rick Filipkiewicz: Re: Spartan II ?
26873: 00/11/02: <eml@riverside-machines.com.NOSPAM>: Re: Spartan II ?
27558: 00/11/28: Nick Bruty: Re: Spartan II ?
26508: 00/10/18: <p25486@my-deja.com>: Off subjuct, VHDL question
26511: 00/10/18: Ray Andraka: Re: Off subjuct, VHDL question
26520: 00/10/19: Kent Orthner: Re: Off subjuct, VHDL question
26521: 00/10/19: Ray Andraka: Re: Off subjuct, VHDL question
26509: 00/10/18: Seb C: two complement multiplier
26512: 00/10/18: Ray Andraka: Re: two complement multiplier
26510: 00/10/18: Juergen Otterbach: XILINX Download cable with USB
26513: 00/10/18: Ray Andraka: Re: XILINX Download cable with USB
26643: 00/10/23: Juergen Otterbach: Re: XILINX Download cable with USB
26648: 00/10/23: Ray Andraka: Re: XILINX Download cable with USB
26675: 00/10/24: Joel Kolstad: Re: XILINX Download cable with USB
26685: 00/10/25: Gary Watson: Re: XILINX Download cable with USB
26519: 00/10/18: Edwin: Off Subject- FPGA Jobs Available
26528: 00/10/19: <yuryws@my-deja.com>: UCF question
26529: 00/10/19: Vincent Jachetta - Multidyne: FPGA DESIGNER LONG ISLAND
27017: 00/11/07: Jeremy Cooke: Re: FPGA DESIGNER LONG ISLAND
26530: 00/10/19: <yuryws@my-deja.com>: UCF Question
26531: 00/10/19: <yuryws@my-deja.com>: UCF Question
26573: 00/10/20: Andy Peters: Re: UCF Question
26578: 00/10/20: <yuryws@my-deja.com>: Re: UCF Question
26580: 00/10/20: Andy Peters: Re: UCF Question
26581: 00/10/20: <yuryws@my-deja.com>: Re: UCF Question
26587: 00/10/21: Magnus Homann: Re: UCF Question
26611: 00/10/22: rickman: Re: UCF Question
26612: 00/10/22: Magnus Homann: Re: UCF Question
26613: 00/10/22: rickman: Re: UCF Question
26616: 00/10/22: Magnus Homann: Re: UCF Question
26617: 00/10/22: rickman: Re: UCF Question
26625: 00/10/23: Magnus Homann: Re: UCF Question
26620: 00/10/23: Ray Andraka: Re: UCF Question
26621: 00/10/23: <yuryws@my-deja.com>: Re: UCF Question
26657: 00/10/23: rickman: Re: UCF Question
26680: 00/10/25: <yuryws@my-deja.com>: Re: UCF Question
26744: 00/10/26: rickman: Re: UCF Question
26768: 00/10/27: Andy Peters: Re: UCF Question
26771: 00/10/27: <yuryws@my-deja.com>: Re: UCF Question
26638: 00/10/23: Andy Peters: Re: UCF Question
26681: 00/10/25: <yuryws@my-deja.com>: Re: UCF Question
26697: 00/10/25: Andy Peters: Re: UCF Question
26532: 00/10/19: Yu Chen: How safe is the algorithm implemented with FPGA?
26535: 00/10/19: Nicholas Weaver: Re: How safe is the algorithm implemented with FPGA?
26540: 00/10/19: Ray Andraka: Re: How safe is the algorithm implemented with FPGA?
26542: 00/10/19: Nicholas Weaver: Re: How safe is the algorithm implemented with FPGA?
26556: 00/10/20: Jan Gray: Re: How safe is the algorithm implemented with FPGA?
26562: 00/10/20: <kolja@prowokulta.org>: Re: How safe is the algorithm implemented with FPGA?
26687: 00/10/25: <eml@riverside-machines.com.NOSPAM>: Re: How safe is the algorithm implemented with FPGA?
26691: 00/10/25: <eml@riverside-machines.com.NOSPAM>: Re: How safe is the algorithm implemented with FPGA?
26696: 00/10/25: Nicholas Weaver: Re: How safe is the algorithm implemented with FPGA?
26745: 00/10/26: rickman: Re: How safe is the algorithm implemented with FPGA?
26748: 00/10/27: Jim Granville: Re: How safe is the algorithm implemented with FPGA?
26751: 00/10/27: Nicholas Weaver: Re: How safe is the algorithm implemented with FPGA?
26698: 00/10/25: Philip Freidin: Re: How safe is the algorithm implemented with FPGA?
26699: 00/10/25: Nicholas Weaver: Re: How safe is the algorithm implemented with FPGA?
26701: 00/10/25: Keith R. Williams: Re: How safe is the algorithm implemented with FPGA?
26702: 00/10/25: Nicholas Weaver: Re: How safe is the algorithm implemented with FPGA?
26710: 00/10/25: <eml@riverside-machines.com.NOSPAM>: Re: How safe is the algorithm implemented with FPGA?
26712: 00/10/25: Nicholas Weaver: Re: How safe is the algorithm implemented with FPGA?
26723: 00/10/26: <eml@riverside-machines.com.NOSPAM>: Re: How safe is the algorithm implemented with FPGA?
26732: 00/10/26: Ray Andraka: Re: How safe is the algorithm implemented with FPGA?
26704: 00/10/25: Brian Dipert: Re: How safe is the algorithm implemented with FPGA?
26719: 00/10/25: Philip Freidin: Re: How safe is the algorithm implemented with FPGA?
26722: 00/10/26: <eml@riverside-machines.com.NOSPAM>: Re: How safe is the algorithm implemented with FPGA?
26735: 00/10/26: Steve Rencontre: Re: How safe is the algorithm implemented with FPGA?
26709: 00/10/25: <eml@riverside-machines.com.NOSPAM>: Re: How safe is the algorithm implemented with FPGA?
26711: 00/10/25: Nicholas Weaver: Re: How safe is the algorithm implemented with FPGA?
26706: 00/10/25: Ray Andraka: Re: How safe is the algorithm implemented with FPGA?
26769: 00/10/27: Peter Alfke: Re: How safe is the algorithm implemented with FPGA?
26814: 00/10/31: Reinoud: Re: How safe is the algorithm implemented with FPGA?
26700: 00/10/25: Steve Rencontre: Re: How safe is the algorithm implemented with FPGA?
26703: 00/10/25: Nicholas Weaver: Re: How safe is the algorithm implemented with FPGA?
26741: 00/10/26: <kolja@prowokulta.org>: Re: How safe is the algorithm implemented with FPGA?
26570: 00/10/20: Ulf Samuelsson: Re: How safe is the algorithm implemented with FPGA?
26572: 00/10/20: Nicholas Weaver: Re: How safe is the algorithm implemented with FPGA?
26579: 00/10/20: Ulf Samuelsson: Re: How safe is the algorithm implemented with FPGA?
26653: 00/10/23: Yu Chen: Re: How safe is the algorithm implemented with FPGA?
26656: 00/10/23: Philip Freidin: Re: How safe is the algorithm implemented with FPGA?
26663: 00/10/24: Nicholas Weaver: Re: How safe is the algorithm implemented with FPGA?
26672: 00/10/24: Ray Andraka: Re: How safe is the algorithm implemented with FPGA?
26714: 00/10/25: <kolja@prowokulta.org>: Re: How safe is the algorithm implemented with FPGA?
26536: 00/10/19: Dan: DS2401 security from pirating an FPGA
26541: 00/10/19: Ray Andraka: Re: DS2401 security from pirating an FPGA
26549: 00/10/20: Dan: Hay Ray -
26594: 00/10/21: luigi funes: Re: Hay Ray -
26554: 00/10/19: rickman: Re: DS2401 security from pirating an FPGA
26563: 00/10/20: Ray Andraka: Re: DS2401 security from pirating an FPGA
26599: 00/10/21: Eric Montreal: Re: 12C508 / SX20 / AVR security from pirating an FPGA
26539: 00/10/19: Walter Haas: PCI Core : Clock Problem
26544: 00/10/19: Carl Rohrer: Re: PCI Core : Clock Problem
26553: 00/10/20: <yuryws@my-deja.com>: Re: PCI Core : Clock Problem
26642: 00/10/23: Walter Haas: Re: PCI Core : Clock Problem
26543: 00/10/19: Tom Burgess: CoolRunner news :(
26574: 00/10/20: Andy Peters: Re: CoolRunner news :(
26576: 00/10/20: Tom Burgess: Re: CoolRunner news :(
26582: 00/10/21: Jim Granville: Re: CoolRunner news :(
26583: 00/10/20: Tom Burgess: Re: CoolRunner news :(
26596: 00/10/21: Peter: Re: CoolRunner news :(
26595: 00/10/21: Peter: Re: CoolRunner news :(
26618: 00/10/22: Peter Alfke: Re: CoolRunner news :(
26692: 00/10/25: Peter: Re: CoolRunner news :(
26770: 00/10/27: Peter Alfke: Re: CoolRunner news :(
26776: 00/10/28: Peter: Re: CoolRunner news :(
26782: 00/10/29: Stuart Adams: Re: CoolRunner news :(
26795: 00/10/29: Peter: Re: CoolRunner news :(
27121: 00/11/11: Steve Fair: Re: CoolRunner news :(
26987: 00/11/06: P: Re: CoolRunner news :(
26991: 00/11/07: Jim Granville: Re: CoolRunner news :(
27494: 00/11/24: P: Re: CoolRunner news :(
26545: 00/10/19: Edwin: Very Lucrative FPGA Jobs
26548: 00/10/20: Austin Franklin: Re: Very Lucrative FPGA Jobs
26550: 00/10/20: Ray Andraka: Re: Very Lucrative FPGA Jobs
26551: 00/10/20: S. Ramirez: Re: Very Lucrative FPGA Jobs
26603: 00/10/22: Adrian Dunn: Re: Very Lucrative FPGA Jobs
26565: 00/10/20: Ron Huizen: Re: Very Lucrative FPGA Jobs
26567: 00/10/20: Magnus Homann: Re: Very Lucrative FPGA Jobs
26798: 00/10/30: S. Ramirez: Re: Very Lucrative FPGA Jobs
26804: 00/10/30: Magnus Homann: Re: Very Lucrative FPGA Jobs
26577: 00/10/20: <husby@my-deja.com>: Re: Very Lucrative FPGA Jobs
26635: 00/10/23: Austin Franklin: Re: Very Lucrative FPGA Jobs
26647: 00/10/23: Theron Hicks: Re: Very Lucrative FPGA Jobs
26650: 00/10/23: Austin Franklin: Re: Very Lucrative FPGA Jobs
26799: 00/10/30: S. Ramirez: Re: Very Lucrative FPGA Jobs
26546: 00/10/20: Domagoj: Virtex E development boards
26564: 00/10/20: Jerry English: Re: Virtex E development boards
26575: 00/10/20: Steven K. Knapp: Re: Virtex E development boards
26547: 00/10/19: Edwin: FPGA Designers Wanted!!!!!
26552: 00/10/20: Recruit Express: Off subject-FPGA DESIGNERS for new PDA start up in San Jose
26555: 00/10/20: <yuryws@my-deja.com>: Any takers for "UCF Question" posted 10/19/2000?
26558: 00/10/20: Andreas Kirchgraber: DSP-Core C31
26569: 00/10/20: Steven Derrien: "Number of logic levels" in xilinx PAR reports
26571: 00/10/20: Ray Andraka: Re: "Number of logic levels" in xilinx PAR reports
26584: 00/10/21: Barry Schneider: Looking for ASIC,FPGA Designers
26585: 00/10/21: Muzaffer Kal: xilinx floor planner issues
26590: 00/10/21: Ray Andraka: Re: xilinx floor planner issues
26607: 00/10/22: <erika_uk@my-deja.com>: Re: xilinx floor planner issues
26615: 00/10/22: Ray Andraka: Re: xilinx floor planner issues
26637: 00/10/23: Steve Rencontre: Re: xilinx floor planner issues
26645: 00/10/23: Muzaffer Kal: Re: xilinx floor planner issues
26806: 00/10/30: Kate Meilicke: Re: xilinx floor planner issues
26588: 00/10/21: Yves Le Henaff: SPROM size problem
26589: 00/10/21: Russ.Shaw: Cheapy FPGA sw
26592: 00/10/21: Ray Andraka: Re: Cheapy FPGA sw
26605: 00/10/22: Mark Harvey: Re: Cheapy FPGA sw
26636: 00/10/23: Ulf Samuelsson: Atmel FPGA tools (was Re: Cheapy FPGA sw)
26654: 00/10/24: eng: Re: Atmel FPGA tools (was Re: Cheapy FPGA sw)
26593: 00/10/21: Rob Finch: Xilinx 4000 reset
26602: 00/10/21: Duane: Re: Xilinx 4000 reset
26614: 00/10/22: Ray Andraka: Re: Xilinx 4000 reset
26597: 00/10/21: sriley: foundation 3.1 crash
26598: 00/10/21: Al Dev: CPU Design HOWTO v2.0 - To design, test and manufacture CPUs
26600: 00/10/21: sriley: reusing macros in F3.1i
26606: 00/10/22: llandre: SoC: Triscend vs Atmel FPSLIC
26608: 00/10/22: Dave Vanden Bout: Re: SoC: Triscend vs Atmel FPSLIC
26609: 00/10/22: <info@seriousmonkey.com>: - Major automotive website
26610: 00/10/22: Tony Burch: ANN: Make use of your XC4000 chips with a low cost kit
26619: 00/10/22: <jesse@jumboprawn.net>: QuickLogic programmer(s) for sale
26622: 00/10/23: Emanuele Russo: implementing a memory
26682: 00/10/25: <yuryws@my-deja.com>: Re: implementing a memory
26716: 00/10/25: Ulf Samuelsson: Re: implementing a memory
26623: 00/10/23: Rob Finch: PCB's for re-casting the form factor of a QFP
26624: 00/10/23: Russ.Shaw: Re: PCB's for re-casting the form factor of a QFP
26626: 00/10/23: Mike H.: Re: PCB's for re-casting the form factor of a QFP
26628: 00/10/23: Daniel Nilsson: SV: PCB's for re-casting the form factor of a QFP
26630: 00/10/23: Dave Vanden Bout: Re: SV: PCB's for re-casting the form factor of a QFP
26627: 00/10/23: Steven Derrien: Typical toggle rates for power estimation ...
26633: 00/10/23: Ray Andraka: Re: Typical toggle rates for power estimation ...
26634: 00/10/23: Steven Derrien: Re: Typical toggle rates for power estimation ...
26640: 00/10/23: Ray Andraka: Re: Typical toggle rates for power estimation ...
26629: 00/10/23: Dan: How secure from pirates is a Quick Logic part ?
26658: 00/10/23: David Forbes: Re: How secure from pirates is a Quick Logic part ?
26678: 00/10/24: Dan: Thanks for the info David
26631: 00/10/23: Dan: RS422 interfacing to a FPGA ?
26639: 00/10/23: Andy Peters: Re: RS422 interfacing to a FPGA ?
26649: 00/10/23: Dan Kuechle: Re: RS422 interfacing to a FPGA ?
26660: 00/10/23: Eric Smith: Re: RS422 interfacing to a FPGA ?
26666: 00/10/24: Jim Granville: Re: RS422 interfacing to a FPGA ?
26693: 00/10/25: Peter: Re: RS422 interfacing to a FPGA ?
26644: 00/10/23: Eric Smith: Re: RS422 interfacing to a FPGA ?
26646: 00/10/23: Dan: Eric and Andy Thanks for help
26632: 00/10/23: Peter Lang: log2 function in VHDL
26694: 00/10/25: Ray Andraka: Re: log2 function in VHDL
26715: 00/10/25: Ulf Samuelsson: Re: log2 function in VHDL
26725: 00/10/26: Peter Lang: Re: log2 function in VHDL
26641: 00/10/23: Recruit Express: Off subject-WIRELESS H/W S/W - pre IPO - San Jose
26651: 00/10/23: Yu Chen: [2]How safe is the algorithm implemented with FPGA?
26652: 00/10/23: Don Teeter: Specifying pin in design file
26655: 00/10/24: Kang Liat Chuan: Re: Specifying pin in design file
26659: 00/10/24: EMF: New PACT 50 GOP Reconfigurable Processor
26661: 00/10/23: Eric Smith: Re: New PACT 50 GOP Reconfigurable Processor
26664: 00/10/24: Philip Freidin: Re: New PACT 50 GOP Reconfigurable Processor
26670: 00/10/24: Steve Rencontre: Re: New PACT 50 GOP Reconfigurable Processor
26673: 00/10/24: Ray Andraka: Re: New PACT 50 GOP Reconfigurable Processor
26662: 00/10/24: Frank Z.F Xie: How to reduce Tco?
26676: 00/10/24: Rick Filipkiewicz: Re: How to reduce Tco?
26677: 00/10/24: Ray Andraka: Re: How to reduce Tco?
26665: 00/10/24: Nicolas Matringe: Xilinx configuration: JTAG and SPROM
26667: 00/10/24: Etienne Racine: Re: Xilinx configuration: JTAG and SPROM
26752: 00/10/27: Bill Lenihan: Re: Xilinx configuration: JTAG and SPROM
27154: 00/11/13: Walter Welwarsky: Re: Xilinx configuration: JTAG and SPROM
26668: 00/10/24: Steven Sanders: Virtex Dual Port RAM simulation failure in Modelsim
26674: 00/10/24: Ray Andraka: Re: Virtex Dual Port RAM simulation failure in Modelsim
26669: 00/10/24: Franz Hollerer: timing simulation with Xilinx and Fusion/SpeedWave
26720: 00/10/26: Uwe: Re: timing simulation with Xilinx and Fusion/SpeedWave
26755: 00/10/27: Franz Hollerer: Re: timing simulation with Xilinx and Fusion/SpeedWave
26729: 00/10/26: Klaus Falser: Re: timing simulation with Xilinx and Fusion/SpeedWave
26754: 00/10/27: Franz Hollerer: Re: timing simulation with Xilinx and Fusion/SpeedWave
26671: 00/10/24: Markus Michel: IOBUF's replaced by IBUF's
27094: 00/11/10: Andrea Sorio: Re: IOBUF's replaced by IBUF's
26679: 00/10/24: jeung joon ee: ultra low cost Evaluation boards
26683: 00/10/25: Saqib: Polynomial transform based 2D-DCT
26684: 00/10/25: Dan: Design theft story in EDN. New security ?
26686: 00/10/25: Rick Filipkiewicz: Re: Design theft story in EDN. New security ?
26690: 00/10/25: Ray Andraka: Re: Design theft story in EDN. New security ?
26695: 00/10/25: Nicholas Weaver: Re: Design theft story in EDN. New security ?
26705: 00/10/25: Brian Dipert: Re: Design theft story in EDN. New security ?
26724: 00/10/26: <eml@riverside-machines.com.NOSPAM>: Re: Design theft story in EDN. New security ?
26734: 00/10/26: Brian Dipert: Re: Design theft story in EDN. New security ?
26688: 00/10/25: <gazit@my-deja.com>: 155Mhz DDR in a programmable logic
26707: 00/10/25: Pete Dudley: Re: 155Mhz DDR in a programmable logic
26773: 00/10/27: Scott Schlachter: Re: 155Mhz DDR in a programmable logic
26785: 00/10/29: <gazit@my-deja.com>: Re: 155Mhz DDR in a programmable logic
26689: 00/10/25: Stephen Lohning: Jtag programing 18V02 prom
26713: 00/10/25: Arthur Yang: Re: Jtag programing 18V02 prom
26708: 00/10/25: Muzaffer Kal: ROC (reset on configuration) on Virtex ?
26717: 00/10/25: Ray Andraka: Re: ROC (reset on configuration) on Virtex ?
26718: 00/10/25: <no.email.address.entered@none444.yet>: New Web Hosting - $3.95 for 35Mb/CGI/Your Domain and 2Gb Monthly Traffic !!!
26721: 00/10/26: korg: Fpga vs. ASIC
26731: 00/10/26: Ray Andraka: Re: Fpga vs. ASIC
26737: 00/10/26: Peter: Re: Fpga vs. ASIC
26759: 00/10/27: <spam@gustad.com>: Re: Fpga vs. ASIC
26762: 00/10/27: Peter: Re: Fpga vs. ASIC
26939: 00/11/03: Ashok Chotai: Re: Fpga vs. ASIC
26783: 00/10/29: ALOK SAHOO: Re: Fpga vs. ASIC
26784: 00/10/29: ALOK SAHOO: Re: Fpga vs. ASIC
26786: 00/10/29: Elmar Haneke: Re: Fpga vs. ASIC
26726: 00/10/26: Peter Lang: How to Compile a hierarchical VHDL Design to a LIB?
26727: 00/10/26: .-: hebben eengoedkoop bordje
26728: 00/10/26: Rob Finch: Using GSR Xilinx 4k
26736: 00/10/26: Andy Peters: Re: Using GSR Xilinx 4k
26730: 00/10/26: chsw: what's meaning?
26740: 00/10/26: Ray Andraka: Re: what's meaning?
26743: 00/10/26: chsw: Re: what's meaning?
26733: 00/10/26: Steven Derrien: High fan out CE signal.
26739: 00/10/26: Ray Andraka: Re: High fan out CE signal.
26761: 00/10/27: Steven Derrien: Re: High fan out CE signal.
26765: 00/10/27: Ray Andraka: Re: High fan out CE signal.
26777: 00/10/28: <erika_uk@my-deja.com>: Re: High fan out CE signal.
26780: 00/10/29: Rick Filipkiewicz: Re: High fan out CE signal.
26810: 00/10/30: Ray Andraka: Re: High fan out CE signal.
26812: 00/10/30: Rick Filipkiewicz: Re: High fan out CE signal.
26815: 00/10/31: Ray Andraka: Re: High fan out CE signal.
26823: 00/10/31: <erika_uk@my-deja.com>: Re: High fan out CE signal.
26825: 00/10/31: Ray Andraka: Re: High fan out CE signal.
26831: 00/10/31: Andy Peters: Re: High fan out CE signal.
26833: 00/10/31: Ray Andraka: Re: High fan out CE signal.
26838: 00/10/31: Andy Peters: Re: High fan out CE signal.
26957: 00/11/05: rickman: Re: High fan out CE signal.
26969: 00/11/06: Ray Andraka: Re: High fan out CE signal.
26979: 00/11/06: Hal Murray: Re: High fan out CE signal.
26839: 00/10/31: Andy Peters: Re: High fan out CE signal.
26846: 00/11/01: Ray Andraka: Re: High fan out CE signal.
26840: 00/10/31: Andy Peters: Re: High fan out CE signal.
26841: 00/10/31: Andy Peters: Re: High fan out CE signal.
26848: 00/10/31: Phil Hays: Re: High fan out CE signal.
26738: 00/10/26: Gary Spivey: Leonardo vs. FPGA Compiler 2
26753: 00/10/27: Bill Lenihan: Re: Leonardo vs. FPGA Compiler 2
26742: 00/10/26: Atlas: Excellent Opportunity ASIC Engineers CA International Relocation
26767: 00/10/27: Andy Peters: Re: Excellent Opportunity ASIC Engineers CA International Relocation
26797: 00/10/29: <husby@my-deja.com>: Re: Excellent Opportunity ASIC Engineers CA International Relocation
26877: 00/11/02: Jerry English: Re: Excellent Opportunity ASIC Engineers CA International Relocation
26746: 00/10/27: Barry Schneider: Long Island Verilog and VHDL people wanted!!
26766: 00/10/27: Andy Peters: Re: Long Island Verilog and VHDL people wanted!!
26779: 00/10/29: Barry Schneider: Re: Long Island Verilog and VHDL people wanted!!
26811: 00/10/30: Ray Andraka: Re: Long Island Verilog and VHDL people wanted!!
26817: 00/10/31: Barry Schneider: Re: Long Island Verilog and VHDL people wanted!!
26818: 00/10/31: Ray Andraka: Re: Long Island Verilog and VHDL people wanted!!
26819: 00/10/31: Barry Schneider: Re: Long Island Verilog and VHDL people wanted!!
26747: 00/10/27: William: 890622@itri.org.tw
26749: 00/10/26: Netscape User: Xilinx Spartan2 and VirtexE availability
26778: 00/10/28: Anthony C: Re: Xilinx Spartan2 and VirtexE availability
26789: 00/10/29: doug: Re: Xilinx Spartan2 and VirtexE availability
26750: 00/10/26: Bob Perlman: Lazio Promises End to Long Island FPGA Crisis
26756: 00/10/27: Muzaffer Kal: Re: Lazio Promises End to Long Island FPGA Crisis
26757: 00/10/27: Magnus Homann: Re: Lazio Promises End to Long Island FPGA Crisis
26758: 00/10/27: Renzo Venturi: Re: Lazio Promises End to Long Island FPGA Crisis
26763: 00/10/27: Brian Drummond: Re: Lazio Promises End to Long Island FPGA Crisis
26760: 00/10/27: <news@rtrussell.co.uk>: Using previous version as floorplan (2.1i vs 3.1i)
26764: 00/10/27: Ray Andraka: Re: Using previous version as floorplan (2.1i vs 3.1i)
26822: 00/10/31: <news@rtrussell.co.uk>: Re: Using previous version as floorplan (2.1i vs 3.1i)
26826: 00/10/31: Ray Andraka: Re: Using previous version as floorplan (2.1i vs 3.1i)
26772: 00/10/27: SongWei: why?
26774: 00/10/27: chsw: why?
26775: 00/10/28: Muzaffer Kal: death of rloc ?
26781: 00/10/29: Rick Filipkiewicz: Re: death of rloc ?
26794: 00/10/29: rickman: Re: death of rloc ?
26865: 00/11/01: Satnam Singh: Re: death of rloc ?
26867: 00/11/01: Muzaffer Kal: Re: death of rloc ?
26796: 00/10/29: <husby@my-deja.com>: Re: death of rloc ?
26866: 00/11/01: Satnam Singh: Re: death of rloc ?
26787: 00/10/29: T.Koyama: Webpack Error?
26790: 00/10/29: Alex Sherstuk: Re: Webpack Error?
26802: 00/10/30: Tadaaki Koyama: Re: Webpack Error?
26788: 00/10/29: Jim Patterson: help on a simple ALU
26791: 00/10/29: Srinivasan Venkataramanan: Re: help on a simple ALU
26792: 00/10/29: Jim Patterson: Re: help on a simple ALU
26849: 00/11/01: news: Re: help on a simple ALU
26861: 00/11/01: Colin Marquardt: Re: help on a simple ALU
27025: 00/11/07: Qian Zhang: Re: help on a simple ALU
26793: 00/10/29: JoeG: I need some VHDL/Synthesis Design BOOK recommendations!!
26864: 00/11/01: Manfredo: Re: I need some VHDL/Synthesis Design BOOK recommendations!!
26800: 00/10/30: Quin: Undergraduate PLD Studies
26801: 00/10/29: David Forbes: Re: Undergraduate PLD Studies
26809: 00/10/30: Petter Gustad: Re: Undergraduate PLD Studies
26816: 00/10/31: S. Ramirez: Re: Undergraduate PLD Studies
26807: 00/10/30: Austin Franklin: Re: Undergraduate PLD Studies
26803: 00/10/30: chsw: why?
26805: 00/10/30: Mark Hillers: ChipScope, MultiLINX and NT
26808: 00/10/30: Richard Chidester: WebPACK ISE V3.2i is available for immediate download!
26824: 00/10/31: Santiago de Pablo: Re: WebPACK ISE V3.2i is available for immediate download!
26836: 00/10/31: Richard Chidester: Re: WebPACK ISE V3.2i is available for immediate download!
26813: 00/10/30: Qian Zhang: Xilinix Foundation Question
26827: 00/10/31: Colm Clancy: Re: Xilinix Foundation Question
26820: 00/10/31: Matthew Fettke: Virtex Hardware Verification
26821: 00/10/31: Bong-Jin Seo: The Xilinx Design tools for the customly designed SRAM-based FPGA
26830: 00/10/31: Petter Gustad: Alliance under Linux?
26835: 00/10/31: Jamie Sanderson: Re: Alliance under Linux?
26837: 00/10/31: S. Ramirez: Re: Alliance under Linux?
26842: 00/10/31: Andy Peters: Re: Alliance under Linux?
26844: 00/11/01: S. Ramirez: Re: Alliance under Linux?
26845: 00/10/31: Curtis Fischaber: Re: Alliance under Linux?
26852: 00/11/01: Steve Rencontre: Re: Alliance under Linux?
26868: 00/11/01: S. Ramirez: Re: Alliance under Linux?
26858: 00/11/01: Andy Peters: Re: Alliance under Linux?
26859: 00/11/01: Duane: Re: Alliance under Linux?
26870: 00/11/02: Zoltan Kocsi: Re: Alliance under Linux?
26874: 00/11/02: <eml@riverside-machines.com.NOSPAM>: Re: Alliance under Linux?
26916: 00/11/03: Jamie Lokier: Re: Alliance under Linux?
26920: 00/11/03: Ray Andraka: Re: Alliance under Linux?
26940: 00/11/04: Simon Gornall: Group behaviour (was: Alliance under Linux)
26941: 00/11/04: Ray Andraka: Re: Group behaviour (was: Alliance under Linux)
26943: 00/11/04: Muzaffer Kal: Re: Group behaviour (was: Alliance under Linux)
26966: 00/11/06: Zoltan Kocsi: Re: Alliance under Linux?
27117: 00/11/11: Kasper Pedersen: Re: Alliance under Linux?
27119: 00/11/11: Duane: Re: Alliance under Linux?
26929: 00/11/03: Simon Gornall: Re: Alliance under Linux?
26942: 00/11/04: Muzaffer Kal: Re: Alliance under Linux?
26945: 00/11/04: Simon Gornall: Re: Group behaviour (was: Alliance under Linux)
26951: 00/11/04: <eml@riverside-machines.com.NOSPAM>: Re: Alliance under Linux?
26871: 00/11/02: Zoltan Kocsi: Re: Alliance under Linux?
26847: 00/10/31: Duane: Re: Alliance under Linux?
26856: 00/11/01: Uwe Bonnes: Re: Alliance under Linux?
26860: 00/11/01: Duane: Re: Alliance under Linux?
26904: 00/11/03: Rick Filipkiewicz: Re: Alliance under Linux?
26925: 00/11/03: Duane: Re: Alliance under Linux?
26949: 00/11/04: Duane: Re: Alliance under Linux?
26934: 00/11/04: Zoltan Kocsi: Re: Alliance under Linux?
26950: 00/11/04: Petter Gustad: Re: Alliance under Linux?
26954: 00/11/04: Eric Smith: Re: Alliance under Linux?
26958: 00/11/05: rickman: Re: Alliance under Linux?
26959: 00/11/05: Duane: Re: Alliance under Linux?
26832: 00/10/31: S. Ramirez: Alliance 3.2i
26834: 00/10/31: Ray Andraka: Re: Alliance 3.2i
26851: 00/11/01: Gary Cook: Re: Alliance 3.2i
26915: 00/11/03: Andreas Koch: Re: Alliance 3.2i
26843: 00/10/31: Andy Peters: Re: Alliance 3.2i
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