Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Ray Andraka <ray@andraka.com> wrote: >I don't think there is such a thing as neutral ground when it comes to that >subject. It is more like religion. That said, I use VHDL because it gives me >more control for getting the design to exactly what I want. It is more verbose >than verilog, and can be more difficult to master (according to some). However, >it has the controls I need to be able to do placement from within the code, and >use it as a generator as opposed to for synthesis. As of last year, you >couldn't do everything I needed with verilog. Ray, would you like to expand little bit on what things VHDL does better for you ?Article: 26476
user attributes let me put INIT=, TNM, and RLOCs on instantiated primitives so I can generate optimized macros that I know will do the logic the way I want it everytime regardless of what the synthesizer wants to do. Last I looked, there was no way of doing that in Verilog. Muzaffer Kal wrote: > > Ray Andraka <ray@andraka.com> wrote: > > >I don't think there is such a thing as neutral ground when it comes to that > >subject. It is more like religion. That said, I use VHDL because it gives me > >more control for getting the design to exactly what I want. It is more verbose > >than verilog, and can be more difficult to master (according to some). However, > >it has the controls I need to be able to do placement from within the code, and > >use it as a generator as opposed to for synthesis. As of last year, you > >couldn't do everything I needed with verilog. > > Ray, > would you like to expand little bit on what things VHDL does better > for you ? -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26477
Eric Montreal wrote: > Hi, > > My question is about safely generating an asynchronous pulse to reset > a single D latch in a Spartan FPGA, (and I know this is frowned upon, > with good reasons). > > More specifically, I need to duplicate the main function offered with > the discrete 74F552 chip : > http://www-us6.semiconductors.com/acrobat/datasheets/74F552_2.pdf > > This chip is a bidirectional registered transceiver with "Data Ready" > flag and parity. > > It's all very easy, except for the OEBR & OEAS input that clear the flag on > it's rising edge by internally generating a short asynchronous reset pulse > for the flag latch. > > The "ugly" trick they show in the schematic (bottom of page 5) diagram is a NAND > gate whose 2 inputs are driven by both a true and a (heavily loaded) inverted > signal, thus creating the transient condition during the time between when the > uninverted input goes high and when the inverted input goes low (propagation > delay in the inverter). Could you do something simpler OEBR_async_reset = out & OEBR_q; outFF_async_reset = out & ~OEBR_q; The advantage of this approach is that it works if the sequence is right, independent of timing. In effect a tiny piece of self-timed logic.Article: 26478
I am using an Annapolis Microsystems Starfire board and having that classic difficulty where the behavioral simulation works and the chip doesn't. So, trying the backannotated simulation, I ran into a few difficulties. First, the ports on the pex module were a record in the behavioral simulation and an array post synthesis. Figured out how they were mapped, but now I am having a problem in that the Global_Reset line is not working in the gate-level simulation. Before I go hacking there code to try and pull the line out to the upper level, has anybody else done a gate-level simulation with an Annapolis Microsystems board and do you have a methodology for making it work? Cheers, Gary spivey@rincon.comArticle: 26479
Ray Andraka <ray@andraka.com> wrote: >user attributes let me put INIT=, TNM, and RLOCs on instantiated primitives so I >can generate optimized macros that I know will do the logic the way I want it >everytime regardless of what the synthesizer wants to do. Last I looked, there >was no way of doing that in Verilog. I think it would be synthesizer specific but I think you can do this with xc_props and xc_rloc properties with Synplify. Muzaffer http://www.dspia.comArticle: 26480
Someone on one of these newsgroups had this to say about a month ago: (Apologies for lack of reference, and probable misquote) Verilog was written by hardware people with no real knowledge of how to write a programming language, and had to be banged around quite a bit before it was really useful. VHDL was written by programming language peeople with no real knowledge of hardware, and had to be banged around quite a bit before it was really useful. -KentArticle: 26481
xc_rlocs doesn't work worth beans for synplicity VHDL. Last year it wasn't there for Verilog, but I have no confidence it would be any better. Nevertheless, with user attributes in VHDL, you've at least got a fighting chance of it working with someone else's tools too. Muzaffer Kal wrote: > > Ray Andraka <ray@andraka.com> wrote: > > >user attributes let me put INIT=, TNM, and RLOCs on instantiated primitives so I > >can generate optimized macros that I know will do the logic the way I want it > >everytime regardless of what the synthesizer wants to do. Last I looked, there > >was no way of doing that in Verilog. > > I think it would be synthesizer specific but I think you can do this > with xc_props and xc_rloc properties with Synplify. > > Muzaffer > http://www.dspia.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26482
Ray Andraka wrote: > The > floorplanning it does is about equivalent to using area constraints in the > graphical floorplanner. The graphical floorplanner does not work well with synthesized design. When a behavioral design is synthesized, the registers and RAMs often have repeatable names and gates (LUTS and muxes) often do not. With a repeatable name, the floorplan will work mostly unchanged if the design needs to be respun. Synthesized logic often does not have repeatable names. If the gates are floorplanned, with the graphical floorplanner, the floorplan may need to be redone for every resynthesis. The alternative to this is to map out the logic into FMAPs by hand, as I have done and as you do, which is ok as long as the block is widely reusable, isn't very complex, and has little risk of change. Or at least one of those. If the FMAPs are mapped out by hand, they can have repeatable names and can be floorplanned many different ways. > Agreed, it does do some additional optimization on RTL > level coding based on the more accurate timing it gets from floorplanning. > However, the marketing stuff tells me they get an average of 25% improvement > over a design with __Absolutely_no_floorplanning__. Thing is you can get that > much improvement pretty easily without the extra optimization, or at most with > an iteration through the timing analyzer to see where the critical path is and > fix it. The gain from floorplanning clearly varies a lot from design to design. I've seen some small designs that can't gain anything from floorplanning (other than from a reasonable pinout). -- Phil HaysArticle: 26483
A manufacturer of serial PROM (or Eprom or EEprom) 17C512 DIP 8pin, usable to configure FPGA similar to Xilinx XC17c512LPD8C but 5V not 3.3V. GiuseppeArticle: 26484
The area constraints in 3.1 do work reasonably well with a hierarchical design. As for the naming of stuff, the part that does not keep the same name from run to run on the synthesizer is the inferred combinatorial logic. Flip-flops tend to keep the names (I label everything) if you label your processes. If you follow good high speed FPGA design so that your logic is mostly 1 level, then you can get away with floorplanning the flip-flops and leaving the luts off. The tools will often do a reasonable job at putting the luts next to the associated flip-flops. The first time through the floorplanner, it helps to put the luts down to get the connectivity, but pick the automatically named ones back up before saving the floorplan. I find it pretty rare for a design to not get faster by at least 15-20% with floorplanning. The larger the design the more the gains, also the denser the design the higher the gains. Datapath especially seems to benefit...I've seen instances where floorplanning has improved a design by over 70%. Basically, my rule of thumb is if it is something special for this design and there is only one or two copies of this macro, I'll do the floorplanning in the GUI. Much anything more, I'll embed RLOCs in the code. Hierarchy is the biggest help for reuse, rapid design and floorplanning. The big designs tend to be made up of the same smaller pieces as the small designs, so it is very rare that I have to start a floorplan from scratch. One last thing, I run into people from time to time that tell me that you can't do million + gate designs this way (using Rlocs and fmaps). The proof is in the pudding, though. It is a quite successful flow for me. I figure I've done well over 10 million Virtex gates in the last 8 months, the majority of those are being clocked over 100 MHz and every one of them is in a -4 (slow) part. Yes, all of those designs have been floorplanned, and all but one have RLOCs and FMAPs embedded in the code. Phil Hays wrote: > > Ray Andraka wrote: > > > The > > floorplanning it does is about equivalent to using area constraints in the > > graphical floorplanner. > > The graphical floorplanner does not work well with synthesized design. When a > behavioral design is synthesized, the registers and RAMs often have repeatable > names and gates (LUTS and muxes) often do not. With a repeatable name, the > floorplan will work mostly unchanged if the design needs to be respun. > Synthesized logic often does not have repeatable names. If the gates are > floorplanned, with the graphical floorplanner, the floorplan may need to be > redone for every resynthesis. The alternative to this is to map out the logic > into FMAPs by hand, as I have done and as you do, which is ok as long as the > block is widely reusable, isn't very complex, and has little risk of change. Or > at least one of those. If the FMAPs are mapped out by hand, they can have > repeatable names and can be floorplanned many different ways. > > > Agreed, it does do some additional optimization on RTL > > level coding based on the more accurate timing it gets from floorplanning. > > However, the marketing stuff tells me they get an average of 25% improvement > > over a design with __Absolutely_no_floorplanning__. Thing is you can get that > > much improvement pretty easily without the extra optimization, or at most with > > an iteration through the timing analyzer to see where the critical path is and > > fix it. > > The gain from floorplanning clearly varies a lot from design to design. I've > seen some small designs that can't gain anything from floorplanning (other than > from a reasonable pinout). > > -- > Phil Hays -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26485
Hi, As an asic designer, I used altera components for prototyping (realtime functional verification of subblocks) in the past. Currently (new job), we are using the Xilinx environment. With the Altera (quartus) tool, I was able to completely script (tcl) the synthesis flow. Just run a few scripts (like synopsys) to do the job. No interactive stuff, no display stuff ! Automatisation and batch runs, a real need in a good design flow ! But how about scripting in the foundation toolset ? Is it not possible ? And what about the Alliance toolset ? Synplify as precompiler, perfect (synplify does support scripting) but I would like to script the total flow. So, after desparately surfing the Xilinx website, is there anybody who knows how to do scripting with the Xilinx tools ? regards, PeterArticle: 26486
Has anybody a good solution to connect a ADC (e. g. AD9054A 200Ms / I've got a free sample:-) to a Virtex-E FPGA. I'm sorry, I've no concept of the analog part of my circuit. Do I have to put a amplifier etc. in front of my analog input. Has anybody a made a similar design? I'll be happy if anybody has some useful hints - thank U MarcArticle: 26487
Aloha!
"S. Ramirez" wrote:
>
> Scott,
> Is there a list of errata for this core?
> -Simon Ramirez, Consultant
> Synchronous Design, Inc.
One obvious, though pretty easily fixed problem is the use of alias, which
isn't supported by several tools.
--
Med vänlig hälsning, Yours
Joachim Strömbergson - Alltid i harmonisk svängning
---------------- Ericsson Microwave Systems AB -----------------
Joachim Strömbergson http://www.ericsson.se/microwave
ASIC System on Silicon engineer, nice to CUTE animals.
* Opinions above, expressed or implicit, are strictly personal *
------------- Spamfodder: regeringen@regeringen.se -------------
Article: 26488Hi! I want to use the Xilinx unified libraries for a design but I have trouble to synthesize the design. FPGA: Xilinx Virtex XCV50 VHDL synthesis tool: Synopsys FPGA Express 3.3.0.4517 (comes with Viewlogic) Xilinx Software: Xilinx Alliance Series 2.1i I managed to simulate the design using UNISIM. I believe I also need this library for synthesis. Is this true? I tried to analyse the vhdl files for the UNISIM library with FPGA express. But I failed to analyse unisim_VPKG.vhd. FPGA Express stops with errors: VITALTABLESYMBOLTYPE is not declared. (VSS-575) (FPGA-dm-hdlc-unknown) What I am doing wrong? I read the Xilinx "Synthesis and Simulation Design Guide". But I can't get the STARTBUF example to work. I looked at the UNISIM vhdl sources where I found some translation_off and translation_on pragmas. Thus I think unisim is thought for synthesis too. Which means I must manage to build the unisim library with FPGA express. Right? Thx Franz Hollerer -- Institut fuer Hochenergiephysik Nikolsdorfer Gasse 18 1050 Wien Austria Tel: (+43-1)5447328/50Article: 26489
Hi, Franz. Franz Hollerer <hollerer@hephy.oeaw.ac.at> writes: > I want to use the Xilinx unified libraries for a design but I have > trouble to > synthesize the design. > > FPGA: Xilinx Virtex XCV50 > VHDL synthesis tool: Synopsys FPGA Express 3.3.0.4517 (comes with > Viewlogic) > Xilinx Software: Xilinx Alliance Series 2.1i > > I managed to simulate the design using UNISIM. I believe I also need > this library for synthesis. Is this true? No, it's not true. The 'Sim' in Unisim is "Simulation" (which unfortunately rhymes with 'syn' for 'synthesis'.) The Unisim libraries are for simulation only. When you analyze your files that contain primitives, the synth tool just uses a reference to that block. And then, when you try to place'n'route the design, the PnR recognises the primitive for what it is, and uses a real component in the FPGA. HTH, Kent.Article: 26490
Hi I was wondering if the pull-up (or pull-down) resistors in the Virtex IOBs could be used as output pull-up. The schematics in the datasheet shows the resistors directly connected to the pad but the text only mentions them in the "Input path" chapter. Anyway, I still can add an external resisotr... -- Nicolas MATRINGE IPricot European Headquarters Conception electronique 16 rue du Moulin des Bruyeres Tel +33 1 46 67 51 11 F-92400 COURBEVOIE - FRANCE Fax +33 1 46 67 51 01 http://www.IPricot.com/Article: 26491
giuseppe ha scritto nel messaggio <8sjfla$k8q$1@fe2.cs.interbusiness.it>... : :A manufacturer of serial PROM (or Eprom or EEprom) 17C512 DIP 8pin, usable :to configure FPGA similar to Xilinx XC17c512LPD8C but 5V not 3.3V. : I, too, have searched for something like that a few moths ago. Presently there seem to be no devices equivalent to Xilinx serial PROMs.Article: 26492
On Fri, 13 Oct 2000 10:15:52 -0600, Phil James-Roxby <phil.james-roxby@xilinx.com> wrote: >Lars wrote: >> >> Hi everybody! >> >> In my design I have to implement a couple of 8x8 bit multipier. One coefficient is constant. >> Since I have to change this constant coefficient in runtime (partial reconfig. of the Virtex chip) the easiest way would be a implementation just with LUTs (so I know the exact location of the LUTs and can change them). Has somebody an idea how I can handle this?? >> >> Thank you! >> >> Lars > >Four options... Or the somewhat less-taxing option 4(b) - Coregen now does this for you. I think you need the newest Coregen update from the website, which includes the dynamic KCM. EvanArticle: 26493
On Sat, 14 Oct 2000 11:12:09 +0100, Rick Filipkiewicz <rick@algor.co.uk> wrote: >Jonas Thor wrote: > >> Hello! >> >> I have a follow up question. Do you know of any 3.3V <-> 5V integrated >> translaters around? I can do the translation with a few discrete >> componentents but I rather use a IC. Any hints??? >> >> / Jonas >> > >The best way is to use parts generically called ``QuickSwitch'' from the >company that first made them [now owned by IDT]. These are basically a bunch >of pass transistors that have the characteristic that the resistance >increases as the voltage on the driving size approaches the device's VCC. In >effect they clamp the output side to about VCC - 0.7. For our 3.3V conversion >we power the 5V parts from a 3.9V supply. You can now get 3.3V versions which >we are about to use in the same way to get LVTTL <-> SSTL2 conversion. > >These parts have the huge advantage that they add almost no delay - about >250ps or so - in the transition range of 0 -> 3.0V where Ron stays at about >10R. > >The best place to look for this stuff is probably Pericom's web site. Also, the additional power supply is easier than it might seem. You can just use a diode to drop your 5V to ~4.3V, and power your QuickSwitch off that. I prefer an active diode, ie. a transistor and a resistor. You can get 8-bit bidirectional switching with just a transistor, a resistor, and something cheap like a QS3244. EvanArticle: 26494
Hi! I have a problem with using F3.1i under Win2k. We have an university license working with a license manager. The environmental setting for the license server location is set correctly. When I open a project at startup (logged in as a normal user) I get the following error messages: Lmacs: The Record Manager or Request is inactive : Pcm: Libraries access error When I am logged in as an administrator everything works correctly. I followed Xilinx solution #7417 (for F2.1i; Windows NT) and changed the write permissions and ini-files, but without success. It has to be a problem concerning permissions, but where? Hope to get some suggestions. MichaelArticle: 26495
Hi, May i also know how to get the free core that U mention? thank you. Post or send to martinb@magma.ca thanks martinArticle: 26496
Try to set the LM_LICENSE_FILE variable when You're locked in as user. -- and reboot before starting the PM! Marc Michael Boehnel schrieb: > Hi! > > I have a problem with using F3.1i under Win2k. We have an university > license working with a license manager. The environmental setting for > the license server location is set correctly. When I open a project at > startup (logged in as a normal user) I get the following error messages: > > Lmacs: The Record Manager or Request is inactive > : > Pcm: Libraries access error > > When I am logged in as an administrator everything works correctly. > > I followed Xilinx solution #7417 (for F2.1i; Windows NT) and changed the > write permissions and ini-files, but without success. > > It has to be a problem concerning permissions, but where? > > Hope to get some suggestions. > > MichaelArticle: 26497
I have set the LM_LICENSE_FILE in the user environment and rebooted the system - without success. I get the same error message. Thanks anyway, Michael Marc Reinert wrote: > Try to set the LM_LICENSE_FILE variable when You're locked in as user. > -- and reboot before starting the PM! > > Marc > > Michael Boehnel schrieb: > > > Hi! > > > > I have a problem with using F3.1i under Win2k. We have an university > > license working with a license manager. The environmental setting for > > the license server location is set correctly. When I open a project at > > startup (logged in as a normal user) I get the following error messages: > > > > Lmacs: The Record Manager or Request is inactive > > : > > Pcm: Libraries access error > > > > When I am logged in as an administrator everything works correctly. > > > > I followed Xilinx solution #7417 (for F2.1i; Windows NT) and changed the > > write permissions and ini-files, but without success. > > > > It has to be a problem concerning permissions, but where? > > > > Hope to get some suggestions. > > > > MichaelArticle: 26498
No, you don't want to use unisims for synthesis. They should be black boxed so that the synthesis passes the declaration to the fpga tools. look at your tool manual for black box syntax. For synplicity, a black box will be inferred with a warning if there is no entity for the component. To suppress the warnings, attach a syn_black_box VHDL attribute to the component. Franz Hollerer wrote: > > Hi! > > I want to use the Xilinx unified libraries for a design but I have > trouble to > synthesize the design. > > FPGA: Xilinx Virtex XCV50 > VHDL synthesis tool: Synopsys FPGA Express 3.3.0.4517 (comes with > Viewlogic) > Xilinx Software: Xilinx Alliance Series 2.1i > > I managed to simulate the design using UNISIM. I believe I also need > this library for synthesis. Is this true? > > I tried to analyse the vhdl files for the UNISIM library with FPGA > express. > But I failed to analyse unisim_VPKG.vhd. FPGA Express stops with errors: > > VITALTABLESYMBOLTYPE is not declared. (VSS-575) > (FPGA-dm-hdlc-unknown) > > What I am doing wrong? I read the Xilinx "Synthesis and Simulation > Design Guide". But I can't get > the STARTBUF example to work. > I looked at the UNISIM vhdl sources where I found some translation_off > and translation_on > pragmas. Thus I think unisim is thought for synthesis too. Which means I > must manage to > build the unisim library with FPGA express. Right? > > Thx > Franz Hollerer > > -- > Institut fuer Hochenergiephysik > Nikolsdorfer Gasse 18 > 1050 Wien > Austria > > Tel: (+43-1)5447328/50 -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26499
They do pull up outside the part, but they are too weak to be considered a reliable pullup for additional pins tied to the net. Use an external pull-up if you have other components on the net. (the Virtex pull up value is in the 100's of K ohms). Nicolas Matringe wrote: > > Hi > I was wondering if the pull-up (or pull-down) resistors in the Virtex > IOBs could be used as output pull-up. > The schematics in the datasheet shows the resistors directly connected > to the pad but the text only mentions them in the "Input path" chapter. > Anyway, I still can add an external resisotr... > -- > Nicolas MATRINGE IPricot European Headquarters > Conception electronique 16 rue du Moulin des Bruyeres > Tel +33 1 46 67 51 11 F-92400 COURBEVOIE - FRANCE > Fax +33 1 46 67 51 01 http://www.IPricot.com/ -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.com
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z