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You can also find various FPGA boards on the OptiMagic site at ... http://www.optimagic.com/boards.html -- Steve Knapp "Domagoj" <domagoj@engineer.com> wrote in message news:8snvmv$fld$1@bagan.srce.hr... > Hi, > I'm looking for Virtex E development boards. I had a look on > http://www.xilinx.com/products/protoboards/protoboards.htm > but couldn't find any company offering what I'm looking for. > > Any recomendations ? > > Thanks. Regards, > > ------------------------------------------- > - Domagoj - > - Domagoj@engineer.com - > ------------------------------------------- > > >Article: 26576
The tragedy is the loss of the only "true" zero operating power (well okay, <75 microamps) low-density PLD in a socketable low-tech package. The "zero-power" Lattice parts draw much, much more (55-100 mA) in non-standby mode. The best substitute for low-power apps looks to be the XCR3032XLPC44. Leftover logic can be used to implement a simple random "executive decision maker" bonus feature :) BTW, a less tersely worded version of the announcement can be found here: http://www.xilinx.com/products/coolpld/custnotice.htm regards, tom Andy Peters wrote: > > I like how the recommended replacement for the 22V10 is the 9536. OK, > so the replacement chip has three times the amount of logic. > > What if I don't need all of that logic? > > I guess Lattice/Vantis still does 22V10s and 16V8s. > > -- a Tom Burgess -- Digital Engineer Dominion Radio Astrophysical Observatory P.O. Box 248, Penticton, B.C. Canada V2A 6K3Article: 26577
Ron Huizen <rhuizen@bittware.com> wrote: > I wonder if he knows what PLD stands for? Probably not. The sad thing is, if he actually finds someone for this job (even though he didn't even say where the job is) he will make a 25% to 33% commission. I don't understand why companies don't post these themselves. Why not skip the middleman? Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26578
OFFET IN BEFORE together with OFFSET IN AFTER would be required. Unfortunately the tools do not allow the usage of both of the above constraints simultaneously, when they are applied to the same net(s). In addition, PERIOD constraint would have to be specified for CLK net. Unfortunately, for that constraint to be understood by the tools I would need to have more then one level of registers clocked by CLK. In my design, the data coming from outside gest clocked by CLK and then reclocked by another clock CLK2, so I only have a single level of regs. clocked by CLK :( In article <8sps1t$pjr$1@noao.edu>, Andy Peters <"apeters <"@> n o a o [.] e d u> wrote: > yuryws@my-deja.com wrote: > > > > Need to create UCF constraints to cover the following scenario: > > > > 1. 16 bits are being clocked on the falling edge of CLK. > > 2. 16 bits are being clocked on the rising edge of CLK. > > 3. Data is valid 6 ns before and 6 ns after every CLK edge. > > 4. Shortest time between CLK edges is 25 ns. > > 5. Data and the clock come into Xilinx (Spartan XL) through input pads. > > 6. CLK is fed through a non-clock pad. > > > > So, the circuit is: > > > > CLK @ non-clock pad---IBUF---BUFGLS--->FF > > Data @ pad------------IBUF-------------FF > > Put a period constraint of 25 ns on CLK. > > Put an OFFSET constraint on the data pins. > > -- a > ---------------------------- > Andy Peters > Sr. Electrical Engineer > National Optical Astronomy Observatory > 950 N Cherry Ave > Tucson, AZ 85719 > apeters (at) n o a o [dot] e d u > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26579
> > > As people have pointed out, there is no 100% solution to protection. > > You can make it harder. The FPSLIC AVR+FPGA will soon come out in a > > multichip package where the configurator is inside the package > > without visibility of the bitstream. You can program the part and > > you can erase the part. Not sure how verification works though! > > >While it is not perfect, you cannot easily read the contents without > >opening up the package and even then you have to use advanced equipment. > > One observation: Opening up and probing a set of leads on a > multichip module should be easier than opening up and probing for a > set of eeprom bits or write once or laser programmed ROM bits within a > single chip. True, as I said it is not perfect, just protects agains the average hacker. You pay a lot for getting EEPROM on an FPGA, since you add a significant amount of mask layers to the die. You also tend to use larger geometries if you add EEPROM. Logic gates are a lot slower etc, You dont want to build an FPGA in EEPROM technology. > I'd personally wonder about the reason for the multichip > module format, it seems like pretty expensive and exotic packaging. > -- Nope, it is not so expensive to do multichip package. Some quad OPamps from other companies are actually multichip packages. The BGA technology that is used lends itself to Multichip packaging very nicely. Best regards, ulf at atmel dot com The contents of this message is intended to be my private opinion and may or may not be shared by my employer Atmel SwedenArticle: 26580
yuryws@my-deja.com wrote: > > OFFET IN BEFORE together with OFFSET IN AFTER would be required. > Unfortunately the tools do not allow the usage of both of the above > constraints simultaneously, when they are applied to the same net(s). Perchance, are you trying to use double-data-rate SDRAMs? In any case, if I was trying to do what you're trying to do, I'd have the FPGA clock running at twice the external interface rate. Register the inputs (in the IOB's flops) with the 2x clock. Then, use some kinda clever logic to run the "rising edge clocked" data through one data path (for instance), and the "falling edge clocked" stuff through another. The external (1x) clock could be used as a gate or something. > In addition, PERIOD constraint would have to be specified for CLK net. > Unfortunately, for that constraint to be understood by the tools I > would need to have more then one level of registers clocked by CLK. In > my design, the data coming from outside gest clocked by CLK and then > reclocked by another clock CLK2, so I only have a single level of regs. > clocked by CLK :( For that case, you'll need to set up an FF-to-FF constraint. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d uArticle: 26581
Registering the inputs in IOB Flops will only take care of one set of those flops (Rising or Falling edge only), which I happen to do anyway, except I do use the externally fed CLK to do that. The other set of FFs is that from CLBs. The reason for all of these problems is that data is only valid for 6ns before and 6ns after each clock edge. I suppose Double data rate SDRAMs operate in a similar manner. This design is for a uDMA controller. I do just what you described as far as FF-FF constraints are concerned instead of PERIOD constraint. In addition my internal clock running at 2.5 times the shortest side of the externally fed clock is used fo detecting the edges and doing some clever stuff with it. The problem is that I can not tolerate the absolulte difference in propagation time between clock_PAD -> FF and data_PAD -> FF of more then 6 ns, in addition the propagation time on clock or data path to FF can not exceed 25 ns. From what I see the Xilinx PAR tools do not have enough controls to allow for specifying such a situation. What I have been doing so far is constrain the prop time (clock -> FF) and (data -> FF) to 6 ns, which does work, but the tools have a very difficult time meeting the constratint. -- Yury Wolf, Senior Digital Design Engineer / RealTime Data In article <8sq81p$18vj$1@noao.edu>, Andy Peters <"apeters <"@> n o a o [.] e d u> wrote: > yuryws@my-deja.com wrote: > > > > OFFET IN BEFORE together with OFFSET IN AFTER would be required. > > Unfortunately the tools do not allow the usage of both of the above > > constraints simultaneously, when they are applied to the same net (s). > > Perchance, are you trying to use double-data-rate SDRAMs? > > In any case, if I was trying to do what you're trying to do, I'd have > the FPGA clock running at twice the external interface rate. Register > the inputs (in the IOB's flops) with the 2x clock. Then, use some kinda > clever logic to run the "rising edge clocked" data through one data path > (for instance), and the "falling edge clocked" stuff through another. > The external (1x) clock could be used as a gate or something. > > > In addition, PERIOD constraint would have to be specified for CLK net. > > Unfortunately, for that constraint to be understood by the tools I > > would need to have more then one level of registers clocked by CLK. In > > my design, the data coming from outside gest clocked by CLK and then > > reclocked by another clock CLK2, so I only have a single level of regs. > > clocked by CLK :( > > For that case, you'll need to set up an FF-to-FF constraint. > > -- a > ---------------------------- > Andy Peters > Sr. Electrical Engineer > National Optical Astronomy Observatory > 950 N Cherry Ave > Tucson, AZ 85719 > apeters (at) n o a o [dot] e d u > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26582
Tom Burgess wrote: > > The tragedy is the loss of the only "true" zero operating power > (well okay, <75 microamps) low-density PLD in a socketable low-tech package. The Atmel ATF22V10CQZ has 5uA typ static Idd, 25uA max. So, they will give longer static battery life than Coolrunner, but for mA/MHz the coolrunner was the best. The ATF750, which has twice the logic ( smart enough to do an i2c slave ) has 130uA Static Idd. It is still in DIP24, so is easy to teach/prototype with. For 5V systems, it is easier to use an ATF1502/1504, which is pin compatible with XCR5032/5064, and has 5uA static Idd, than redesign the PCB to a single sourced pin out, with higher Idd. We have migrated designs from XVR5032 to ATF1500/1502, but that was done for EMC reasons. -jg -- ======= 80x51 Tools & PLD IP Specialists ========= = http://www.DesignTools.co.nzArticle: 26583
Jim Granville wrote: <snipped> > > Tom Burgess wrote: > > > > The tragedy is the loss of the only "true" zero operating power > > (well okay, <75 microamps) low-density PLD in a socketable low-tech package. > > The Atmel ATF22V10CQZ has 5uA typ static Idd, 25uA max. > So, they will give longer static battery life than Coolrunner, but > for mA/MHz the coolrunner was the best. > Thanks for the info - had not kept track of Atmel's PLD parts. This looks like another pseudo zero-power part, i.e. it cycles power to the PLD core on every input transition to get near-zero idle current. I'm not too keen on the thought of a ~100 mA power glitch source near sensitive analog circuitry - bypassing and filtering can only do so much ... Seems like only Philips had an inherently low power simple PLD. regards, -- Tom Burgess Digital Engineer Dominion Radio Astrophysical Observatory P.O. Box 248, Penticton, B.C. Canada V2A 6K3Article: 26584
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Article: 26585hi everyone, Today I spent a couple of hours looking at placement of micro-controller occupying almost 50% of a virtex 800. One thing I couldn't figure out how to do is to annotate a critical path from the timing analyzer onto the floorplan. I looked at the online help and the online description I could find was to open a timing file and add individual nets by using the Find command in the floorplan tool. Is this really the only way ? I was expecting a much more automated way to do this. Basically selecting a number of paths in the timing analyzer would just select all the nets involved in the placement by unique colors. Another problem is that some of the nets in the path have multiple destinations, i.e. one register output seems to go to 3 different FGs but only one of these paths is on the critical path so after ctrl-selecting a couple of lines in the critical path, you are really not sure what is the critical path anymore. Is there way to get around this ? I think Altera's way of linking critical paths to placement is much nicer. Muzaffer http://www.dspia.comArticle: 26586
could you do even FMAP. do those attributes work with FPGA EXPRESS ? In article <39ED0316.F754252C@andraka.com>, Ray Andraka <ray@andraka.com> wrote: > xc_rlocs doesn't work worth beans for synplicity VHDL. Last year it wasn't > there for Verilog, but I have no confidence it would be any better. > Nevertheless, with user attributes in VHDL, you've at least got a fighting > chance of it working with someone else's tools too. > > Muzaffer Kal wrote: > > > > Ray Andraka <ray@andraka.com> wrote: > > > > >user attributes let me put INIT=, TNM, and RLOCs on instantiated primitives so I > > >can generate optimized macros that I know will do the logic the way I want it > > >everytime regardless of what the synthesizer wants to do. Last I looked, there > > >was no way of doing that in Verilog. > > > > I think it would be synthesizer specific but I think you can do this > > with xc_props and xc_rloc properties with Synplify. > > > > Muzaffer > > http://www.dspia.com > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com or http://www.fpga-guru.com > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26587
yuryws@my-deja.com writes: > Registering the inputs in IOB Flops will only take care of one set of > those flops (Rising or Falling edge only), which I happen to do anyway, > except I do use the externally fed CLK to do that. > > The other set of FFs is that from CLBs. The reason for all of these > problems is that data is only valid for 6ns before and 6ns after each > clock edge. > > I suppose Double data rate SDRAMs operate in a similar manner. This > design is for a uDMA controller. > > I do just what you described as far as FF-FF constraints are concerned > instead of PERIOD constraint. In addition my internal clock running at > 2.5 times the shortest side of the externally fed clock is used fo > detecting the edges and doing some clever stuff with it. > > The problem is that I can not tolerate the absolulte difference in > propagation time between clock_PAD -> FF and data_PAD -> FF of more > then 6 ns, in addition the propagation time on clock or data path to FF > can not exceed 25 ns. > > From what I see the Xilinx PAR tools do not have enough controls to > allow for specifying such a situation. What I have been doing so far is > constrain the prop time (clock -> FF) and (data -> FF) to 6 ns, which > does work, but the tools have a very difficult time meeting the > constratint. I have also tried to specify min and max Tco and Tsetup with both Xilinx and Altera. The tools can't handle this, and I think this will become more and more of a problem. It would also be nice to be able to cnostraint Toskew for a set of outputs. The tools are not good enough for this, atr leats they weren't six months ago. Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 26588
Hello, We have a design with a Spartan II 50K gates. The SPROM we have is XC17S50XL (which is the one we should use). Unfortunately we still have the Foundation 2.1i and it doesn't manage this SPROM. We chosed a larger one in the PROM file formater (XC1701L). As the register informations are not stored in the file, this shouldn't be a problem. But the SPROM file contains a header with some information about size and checksum. Has someone already developped a piece of software to adapt the SPROM files (or an idea to solve this problem) ? By the way, it seems the configuration register in a XC17S50 is located at byte 0x10000 (our dataIO wants to write the config there and when we read a blank XC17S50 we see "01" at this address), but the stream is 0x11110 bytes long ! So do we have to skip this address (shift the bytes ) ? PS: Do not buy a DataIO Chipwriter. It burns the ALTERA EPC1441, there are a lot of signature mismatch, there is a poor support. The XC17S50 is given as not supported on the web site, but the software support it (But we toasted two XC17S50 at this time, the programmer can't read it after programming the chip !). Thanks.Article: 26589
Hi all, Is there any entry level tools for fpgas such as atmel at40k05? The free IDS6 tool from atmel is a bit too crappy. I don't mind buying a tool, but the budget isn't open ended... -- ******************************************* * Russell Shaw, B.Eng, M.Eng(Research) * * email: russell@webaxs.net * * Victoria, Australia * *******************************************Article: 26590
THat's about all there is. In the timing report, make note of the CLB locations in the critical path. Armed with those, go into the floorplanner and zoom in on the first CLB in the path, and select the element (S0 is the right half, s1 is the left half of the CLB, F/X is on the bottom of the slice G/Y is the top half. THe loaction down to the BEL is displayed in the lower right side of the display. Once you select the first location, then zoom back out and you can select the second. That one will be easier to find, as it is one of the ones with a ratsnest going to it. Tell Xilinx that you'd like to see the timing paths get back annotated to the floorplanner. (use the on-line tech support or hotline to submit a query as to how to do it). The more people they see using part of a tool or requesting a feature, the higher they move it on the to-do list. Floorplanner has historically taken a bottom position on their priority list because they seem to think the only ones who use it are for the "%5 designs from hell". Muzaffer Kal wrote: > > hi everyone, > Today I spent a couple of hours looking at placement of > micro-controller occupying almost 50% of a virtex 800. One thing I > couldn't figure out how to do is to annotate a critical path from the > timing analyzer onto the floorplan. I looked at the online help and > the online description I could find was to open a timing file and add > individual nets by using the Find command in the floorplan tool. Is > this really the only way ? I was expecting a much more automated way > to do this. Basically selecting a number of paths in the timing > analyzer would just select all the nets involved in the placement by > unique colors. > Another problem is that some of the nets in the path have multiple > destinations, i.e. one register output seems to go to 3 different FGs > but only one of these paths is on the critical path so after > ctrl-selecting a couple of lines in the critical path, you are really > not sure what is the critical path anymore. Is there way to get around > this ? > I think Altera's way of linking critical paths to placement is much > nicer. > > Muzaffer > > http://www.dspia.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26591
Well...be careful there. FMAP is a funny component. If you have declare the output as an output, the tools will complain that there are two nodes driving. If declaring it as an input, inout or buffer requires changing the primitive, and I haven't had luck getting that modified primitive all the way through the tools flow, at least not with synplicity. Admittedly, I haven't pursued it much since I got a working flow using the synplicity xc_fmap attribute. erika_uk@my-deja.com wrote: > > could you do even FMAP. > do those attributes work with FPGA EXPRESS ? > In article <39ED0316.F754252C@andraka.com>, > Ray Andraka <ray@andraka.com> wrote: > > xc_rlocs doesn't work worth beans for synplicity VHDL. Last year it > wasn't > > there for Verilog, but I have no confidence it would be any better. > > Nevertheless, with user attributes in VHDL, you've at least got a > fighting > > chance of it working with someone else's tools too. > > > > Muzaffer Kal wrote: > > > > > > Ray Andraka <ray@andraka.com> wrote: > > > > > > >user attributes let me put INIT=, TNM, and RLOCs on instantiated > primitives so I > > > >can generate optimized macros that I know will do the logic the > way I want it > > > >everytime regardless of what the synthesizer wants to do. Last I > looked, there > > > >was no way of doing that in Verilog. > > > > > > I think it would be synthesizer specific but I think you can do this > > > with xc_props and xc_rloc properties with Synplify. > > > > > > Muzaffer > > > http://www.dspia.com > > > > -- > > -Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com or http://www.fpga-guru.com > > > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26592
For design entry or for place and route? For design entry, you are kinda stuck using one of the fully capable tools (not a seat crippled so it works for only one vendor's stuff). THose are usually more $. If you are schematic based, I'd recommend innoveda (formerly viewlogic). If HDL based, you'll need to pick a synthesis tool that supports atmel (I know synplicity does, I'm not sure any of the others do). For the place and route, you are stuck with Atmel's IDS software. It is a stepchild of the crappy figaro stuff. My sympathies. "Russ.Shaw" wrote: > > Hi all, > > Is there any entry level tools for fpgas > such as atmel at40k05? > > The free IDS6 tool from atmel is a bit > too crappy. I don't mind buying a tool, > but the budget isn't open ended... > > -- > ******************************************* > * Russell Shaw, B.Eng, M.Eng(Research) * > * email: russell@webaxs.net * > * Victoria, Australia * > ******************************************* -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26593
I have a signal 'reset' in my design used to reset the state of various registers and counters. Is there a way of generating a reset signal internally ? I looked at using the STARTUP symbol and it looks to me like I could use Q4, but how do I configure this (Q4 vs Q1) there doesn't seem to be any option. Alternately is there a way I can specify initial register settings ? I am using student edition F1.5 software. Thanks RobArticle: 26594
Dan ha scritto nel messaggio ... >My timing verification idea was not clear. > >I suggest reading the stream over and over again repeatedly at different >speeds to search for the failure speed. The DS2401 has a maximum speed in >the 16.3Kbps range. If you can read the stream at 120% of max bandwidth then >it must be a copy in a faster device. > >A pirate would not think about replicating the bandwidth >Just how robust is this timing security method ? It is no secure. The timings of all Dallas 1-Wire devices are based on internal RC and then they are subjected to wide tolerances. For my experience, I tested devices functioning at 200% of the max nominal speed. LuigiArticle: 26595
Typical of Xilinx - buy a competitor then close it down. I now have to redesign some boards!!!! >Discontinuation notice here: >http://www.xilinx.com/partinfo/notify/pdn0007.htm > >Looks like everything but the XPLA3 family goes. >Last time buy April 27/01. Peter. -- Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y. Please do NOT copy usenet posts to email - it is NOT necessary.Article: 26596
A lot of the time, an AVR running at 10MHz will do the job nicely :) I now have the task of replacing a P3Z22V10 and a P5Z22V10 (containing two state machines) with something else. The P5Z is not really power-limited; I could use a normal 22V10, but the P3Z one needs to be <2mA with a 1MHz clock. Both are in PLCC-28. >> The tragedy is the loss of the only "true" zero operating power >> (well okay, <75 microamps) low-density PLD in a socketable low-tech package. > >The Atmel ATF22V10CQZ has 5uA typ static Idd, 25uA max. >So, they will give longer static battery life than Coolrunner, but >for mA/MHz the coolrunner was the best. > >The ATF750, which has twice the logic ( smart enough to do an i2c slave >) >has 130uA Static Idd. >It is still in DIP24, so is easy to teach/prototype with. > >For 5V systems, it is easier to use an ATF1502/1504, which is pin >compatible >with XCR5032/5064, and has 5uA static Idd, than redesign the PCB to a >single >sourced pin out, with higher Idd. > >We have migrated designs from XVR5032 to ATF1500/1502, but that was done >for >EMC reasons. Peter. -- Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y. Please do NOT copy usenet posts to email - it is NOT necessary.Article: 26597
The tool has died on two separate computers. It cannot open schematic capture tool, it cannot find its server, it cannot implement a design, etc. Further, the database is missing files from time to time. I suspect this occurs during archiving/restoring. Re-installing the tool does not help either. My next step is to overhaul both the desktop and the laptop. There may be a problem with library manager. The older foundation tools had a problem with btrieve and its associated dll's. But there is no fix for F3.1i. One thought is a conflict with Lotus Notes and/or some Windriver software. Does anyone have these or similar problems? TIA -Sue Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26598
Hello: The CPU Design HOWTO version 2.0 is released. This document gives a bird's eyeview on design, test and manufacturing of CPUs. It is located at http://www.aldev.8m.com or at http://aldev.webjump.com Bookmark this url and circulate to your friends.. Let me know suggestions and I will add those.. al devArticle: 26599
Hi, I'm not (by far !) a security expert, but to protect a FPGA based design, I think I would rather look at dirt cheap devices such as 12C508 (well under $1) that can offer much more than DS2401 for such applications. These chips can be field programmed for uniqueness and configured with internal osc, thus they exactly require zero external components for lowest possible cost/space (8 pins SO and you can use ceramic/xtal if more precise timing is needed). Depending on the application they can be programmed not only to be part of a security checking scheme, but also a part of the function itself or offer a higher level communication link between the FPGA and external world (app dependant). Some higher end 12Cxxx serie processors offer on chip A/D conversion, or EEPROM for storing parameters, this could be used in some apps too. Scenix processors are a bit more expensive, but can provide much greater functionnality since they have a very capable 50/75 Mhz 8 bits processor core tuned for fastest interrupt response time. Onchip analog brownout detector & medium speed comparator can also be real handy to have. close coupling these low priced "all in one" processors with a FPGA to perform low to medium speed functions in software could end up allowing the use of the next lower density FPGA, thus more than absorbing their cost. Basic SPI variant serial communication protocol that can be used between the two parts. This is also likely to consume much less FPGA ressources than what's needed to implement the timing based 1 wire interface to the DS2401. Another benefit is that the interface can be as customized as needed and only transmit encrypted data between the FPGA and the processor for better protection. Same can certainly be said about the AVR processors, but lately, the hardest part seems to be getting your hands on them unless you need them after Q2 2001. http://www.scenix.com/ http://www.microchip.com/10/lit/pline/picmicro/index.htm http://www.atmel.com/atmel/products/prod23.htm --- No protection is perfect, but for many applications the cost/protection/added features combination certainly make them an interresting option. However, I don't exactly know how much protecton these processor can offer to a reverse engineering effort (what is the "protection bit" worth ?). What I mean is that copying bitstream is child's play, functionnally duplicating DS2401 is already likely to stop a casual copycat, Guessing the whole function of a one chip microcontroller is only likely to appeal the most determined fringe. except for very sensitive apps, estimating how often such efforts are undertaken could help draw the line between reasonable measures and counter productive paranoļa. my 0.02 (I'm from Canada, so in facts, its more like a 0.01 ;-) Eric. ------------------------------------------------------------------------------------------ Dan wrote: > Hi, > > This security method can be broken by replicating the serial number. > > How much more secure would it be to not only check the serial number but > also check the timing. For example: read it a bit too slow and a bit too > fast and expect it to fail. If it passes, it must be a copy stored in some > other device with different timing ? > > Does every purchaser of the DS2401 get a unique number ?? How could this be > ?? > > If I buy 100 and later buy another 100 how will they have the same serial > number ?? > > How would they know how many to produce with each number ? > > Makes it sound like each one is unique. This means every FPGA board must be > reprogrammed to look for a unique number. Is this the case ? > > Dan
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