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Rick Filipkiewicz a écrit dans le message <3A1E817E.60874415@algor.co.uk>... Hi Rick. >This is not necessary - its perfectly o.k. to use a single combinatorial OE >control from inside the CLB matrix. Its just slower, which won't matter if clock >period is relaxed. The registered tri-state FF is really only required for very >high clock rates or for situations where one driver is being turned off and >another turned on in the same clock period and you are not worried by 1 or 2nsec >of contention. In fact, Frank was worried by a 10 ns tco, so, i believed that he wanted to achieve something like less than 5 ns. But why using a CLB FF when you can use several ENBFFs. These ENBFF are on the chip even if you don't want to use them, anf if you choose to use them, you will save a CLB FF ;-)))) In both cases, the routing is the same. If you choose the ENBFFs, your tco won't depend on your routing, and it will always be the same even if your Virtex is completely full. It's like INFFs and OUTFFs, i see no good reason for not using them when it is possible. -- J-P GOGLIO GETRIS S.A. 13 Chemin des Prés 38240 Meylan France Tel : (+33) 4 76 18 52 10 E-mail : goglio@getris.comArticle: 27501
Why power down? Most modern FPGAs that I have seen have very low static power, if they are not driving any DC loads. "Very low power consumption" is a relative term, of course. Does that mean 1 mA? 1 uA? Quicklogic also has quick power-on times. Note that "quick" is also a relative term, and is not zero for antifuse technologies that are currently in production. There's also the Gatefield/Actel FPGA - higher densities and reprogrammable and non-volatile. No external memories needed. Or how about something like Chip Express or one of the other vendors that can handle small quantities of ASICs - which should get you lower power consumption, no configuration time, and most definitely non-volatile. For "minimum" power, an ASIC might be the best way to go. rk Michael Strothjohann wrote: > > Ohps, > you are looking for a (real) low power -, > fast -, big resources - > FPGA. I would add : low cost . > anyone have them ? please, mail me too. > Xilinx (Philips) CoolRunner CPLDs are fast and > low power, ok, small recources, so > what about an actel-FPGA in fuse technology, > powered when you need it, > so stand-by-power is low, > and no configuration phase is needed, > when you switch it on. > Your application sounds like you have to > use other components like memory etc etc. . > what about the *total* power needed ? > > Steve Nordhauser schrieb: > > > I have a complex video processing application - wavelet or DCT > > compression in an FPGA for a 1Kx1K 30 frame per second video > > stream. I need very low power consumption. Ideally, I would like > > to leave the FPGA powered down until I need it, but it would have > > to be ready in under 100mSec. > > > > I've only worked with the Xilinx FPGAs and was wondering if > > someone out there with a more varied background could point me > > in the right direction. I need enough resources and speed to do > > the algorithm, but at minimum power. > > > > As an aside, anyone out there with compatible experience or can > > point me towards a web site for real-time, high resolution compression? > > > > Thanks, > > Steve NordhauserArticle: 27502
I have a very strange problem where NGDBUILD is erroring out complaining that it can't find FFs I've specified even though I know they are there & have the right names. Here's the simple situation: module dram dram ( .... input [31:0] dd_in; // DRAM data input output [NN:0] dram_out; // DRAM data output + some other stuff .... ) ... reg [31:0] reg_dd_in; always @(clk) if (clken) reg_dd_in <= dd_in; assign dram_out[31:0] = reg_dd_in; .... endmodule What I want to do is put a multicycle delay contraint on some of the registered DRAM data paths: TIMEGRP DRAMDD = FFS(dram/reg_dd_in*); TIMESPEC TSFOO = FROM DRAMDD TO NonCPUFFs ``clk period'' * 2; What happens is the NGDBUILD complains that it cannot find any FFs matching the name ``dram/reg_dd_in*''. o Removing the offending timespec, going through to MAP and then doing an XDL dump I can *see* the FFs with precisely these names nestling happily in the IOBs. o There are other TNM_NET type timegroups that should and do show these FFs in their BEL lists in the PCF. o I can work around the problem by putting these constraints in the PCF and all is well. Note that I don't synthesise all together but I've got a top level module that instantiates all the others including ``dram''. NGDBUILD then acts as a linker. Anybody seen this before ? Any ideas ? I'm running 2.1iSP6 [Until recently I've only been running SP5 ... I wonder if I should try stepping back]Article: 27503
> Yes, skew is the difference between the arrival time of two signals, but again, it's the same clock net with the same driver that's have the skew problem. How can one part of one net have a maximum Tpd and another part of that same net have a minimum? Enough so that it makes a big difference, like in the ns range? > > And yes, on chip routing is slow. It's all capacitive loading of the entire net plus the gate of the receiver(s). That is not in dispute at all. > > What I'm saying is that skew on a signal net that is driven by a single driver can only come from the differences in propagation delay, or buffering elements in between. If all elements get their clock from a single clock net, how can there be skew in the range they are reporting? I think there are two issues here. One is what's actually happening inside the chip and the other is what the tools are telling you and/or how to work around them. I'm not a silicon wizard, but I don't think any numbers based on FR4 are interesting for this discussion. Inside a chip, the resistance of the wires is significant, especially with occasional pass transistors or buffers. If you want a board analogy, you should be thinking about something like driving an address bit for a bank of DRAMs. The distributed capacitance has a big influence on the propagation time. In terms of the tools, Xilinx has decided that they don't want to talk about min delays and hold time. That works fine for the main clock nets where they guarantee that the worse case skew is less than the min prop time. (You have to look around to find where they say that.) There are app notes that discuss min delays for some of the older Xilinx families. I haven't seen anything similar for the newer families, but I haven't been looking. The reasoning hasn't changed but the numbers (scale factors) might be slightly different. As others have said, you are asking for troubles if you are using local routing for clocks. I'd try hard to do something else. The reason isn't so much that you can't make it work, but rather than you won't get a lot of help from Xilinx. They have decided that their party line is a simple synchronous design clocked by the main clocks. A clock enable on a faster clock is one approach. Another is to split your feedback paths into two stages, clocking each stage on alternate clocks. (Perhaps implemented with rising and falling edges.) -- These are my opinions, not necessarily my employers. I hate spam.Article: 27504
Philip Freidin wrote: > > On 22 Nov 2000 00:49:48 GMT, sac62513@saclink3.csus.edu (Don Teeter) wrote: > > >Concerning XC4000E series. > > > >To activate the internal oscillator all I need is to include the OSC4 > >symbol in the schematic, as the documentation states. Correct? > >I have done this yet seen no evidence that the clock is running. > > What evidence were you looking for? Test design is an 8-bit Johnson counter at 15Hz such that I should see the sequence repeat twice per second. Outputs drive LEDs, have verified this electrically with static signals. Looks great in sim but it just doesn't run for real. > Nope. Just plonk it down and connect to it. Did you check that the > instance was in the EDIF file? what about the MAP trimming report? Yes. Thanks for your input.Article: 27505
Hal Murray wrote: <snip> > > There are app notes that discuss min delays for some of the older > Xilinx families. I haven't seen anything similar for the newer families, > but I haven't been looking. The reasoning hasn't changed but the numbers > (scale factors) might be slightly different. > In fact you can get the min numbers for some of the families and the trce timing analyser has a -min flag *but* these numbers are always late wrt product introduction. The Virtex min values are available but not the Virtex-E. > > As others have said, you are asking for troubles if you are using > local routing for clocks. I'd try hard to do something else. The > reason isn't so much that you can't make it work, but rather than you > won't get a lot of help from Xilinx. They have decided that their > party line is a simple synchronous design clocked by the main clocks. > That fine & I think - apart from those brave souls into self-timed design - we all agree with this. However its a bit like apple pie, mother & the flag [U.K stereotype =~ the queen & warm beer] fine in theory but imperfect in practice. The original poster's question could be re-phrased as what do you do when the pie and mother have run out and the flag's obscured by fog ? Xilinx's answer is <<< helpful. Also: I repeat - if their ``party line'' is simple synchronous design then (1) They find a way of increasing the number of global clocks for bigger devices. (2) Find a way of making the secondary networks accessible @ the HDL level.Article: 27506
> Its worse than I thought. Firstly stepping back to the SP5 version of NGDBUILD didn't make any difference. Secondly this problem can happen almost silently. If the FFs NGDBUILD can't find don't reduce the timegrp to 0 then only a warning is produced - not an error. O.k. I should be more careful about checking through the zillions of warnings to pick out the real ones *BUT* there's one case where even this won't help: If the UCF timegrp spec uses a wildcard on a vectored signal and NGDBUILD can find some but not all of the FFs. In my case it the spec contained: .../saved_size* saved_size is a 5 bit vector but NGDBUILD missed saved_size[4] and continued silently on. For me this is not really too dangerous most of the time since the majority of the timespecs are multi-cycled easing up of the basic period one. However if the timespec's job is to tighten the timing then there's potential for trouble. The one place I *do* tighten specs is on clock domain changing FFs! Since I can't find any mention of this in the answers db has it propagated into 3.x ?Article: 27507
MiroTech Microsystems Inc (www.mirotech.com) has two PCI based boards that use the PLX9080 as the PCI bridge. Support for Win95, Win98, WinNT 4.0 and Windows 2000 is provided. And PCI performance of up to 110MB/s :) MF "Christian Werner" <cwerner@informatik.hu-berlin.de> wrote in message news:Pine.GSO.4.02.10011221458100.4926-100000@rock... > Hi! > > I'm looking for Virtex prototyping boards with a PCI-interface. > > The PCI-interface shold be controlled by a seperate chip, so that the FPGA > does not need to provide the functionality for the PCI-Bus. > > Is there anybody who has some (good or bad) experiences with such a board > and can give me any hints which board I should buy? > > As I don't know much about PCI-programming I would appreciate a board > that is shipped with ready-to-use PCI-drivers for Linux and/or Windows and > some examples how to use them. > > Thanks in advance, > > Christian Werner >Article: 27508
hello: when i have synthesis my project in Windows NT on the platform of the pc,i plan to simulate with NC-VERILOG in Solaris 2.6 platform.how do i? Can the library of the xilinx Foundation 2.1i of the pc be used in NC-VERILOG in the Solaris?Article: 27509
non riesco a configurare , mi causa un errore irreversibile! Help!Article: 27510
Has someone an idea : We use a Data IO Chipwriter Portable ($1500) for Xilinx 3.3 V SPROMs. But this programmer use 5 volts to program them ! (Xilinx makes smart devices, but not enough to resist Data IO programmers ). Is there a way to modify the library or the algorithm (or have Data IO people read a Xilinx datasheet (just some help : page 6 of Spartan SPROMs pdf, for 3.3 V devices the absolute maximum is 4 Volts !!))...Article: 27511
Hi,
I am new to vhdl/FPGA design, I am designing a FIFO who's read and
write ports operate on different clocks at different frequencies. I am
keeping track of how full/empty the FIFO is by using a counter that
increments during a write and decrements during a read. This presents a
problem as when a read and write occur simultaneously the counter will not
function correctly.
How do I solve this, should I adopt a different approach to keep a count to
generate the full and half full flags ?
Thanks
J
Article: 27512Xilinx has several APP notes on FIFOs. I think you are asking for trouble if you have one counter and expect it to be valid on two separate clock domains. What I usually try to do is find some trick that lets me simplify things for my particular use. Here is one handwaving example. The write side needs to know if the FIFO is full so it can avoid writing any more and/or set an error flag. The read side needs to know if the FIFO is empty so it doesn't read too much. Put the counter on the read side. Each write, send a write-pulse through a synchronizer to bump the counter. Generate an almost-full signal and send that back to the write side through another synchronizer. The "almost" part needs to be big enough so that the almost-full signal will get back to the write side in time to stop writing before the FIFO really does get full. Getting the write pulse through a synchronizer is easy if the receive side clock is significantly faster. Toggle a FF each write, run that through a pair of synchronizing FFs and watch it on the receive side. Each toggle is a write. -- These are my opinions, not necessarily my employers. I hate spam.Article: 27513
Herbert Kleebauer wrote: >Greetings, > > > I've been curious about how many gates it takes to achieve > >a simple & small MPU, (such as a Z80 for example). The cpu's can take a rather large # of gates because of logic decoding. Remember in ASIC's a wide gate is cheap and a ALU is not. The roles are reversed in FPGA's. > >Essentially, I have an XC4005XL FPGA, and am writing the pieces of this pie > >out, and they come up 500 gates a piece (Program Counter, > >Address Registers, Data Registers.) 500 gates is more than a ample for small to mid sized RISC machines, providing you have dual ported memory on your FPGA. Design also can give you about a 2:1 ratio in logic cells on some kinds of logic. Using Altera's 10k10 (single ported memory) a simple 24 bit CISC using TTL macro's uses 526 clb's. The same design tailored for FPA logic is about 20% faster and smaller. Remember to save some room for routing. > As an exercise for our students we have developed and implemented a > 16 bit minimal processor. The processor can address 64 kByte and > supports hardware interrupts. It is built with 65 flip-flops and > about 250 gates. The documentation and schematics can be found at > > ftp://137.193.64.130/pub/mproz/ This is a nice small CPU. I just wish more people would design more MID-sized CPU's as small instruction sets are a pain to program in. They also hide most weakness a FPGA architecture may have, like poor multiplexer logic. A 12 bit CPU with ADD,AND,XOR,JUMP,JZERO,DEPOSIT AND CLEAR,CALL,RETURN instructions and single accumulator may route well into XYZ's fpga but going to 16 bits could cause routing congestion and slow the cpu down by 25%. Ben. -- "We do not inherit our time on this planet from our parents... We borrow it from our children." "Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchukArticle: 27514
"j" <j@j.com> wrote in message news:8vrkt0$fk8$1@uranium.btinternet.com... > Hi, > I am new to vhdl/FPGA design, I am designing a FIFO who's read and > write ports operate on different clocks at different frequencies. I am > keeping track of how full/empty the FIFO is by using a counter that > increments during a write and decrements during a read. This presents a > problem as when a read and write occur simultaneously the counter will not > function correctly. > How do I solve this, should I adopt a different approach to keep a count to > generate the full and half full flags ? > > Thanks > > J > > I have just finished a roll-your-own FIFO. I addressed the problem you mention by using two separate counters. One points to read addresses and the other points to write addresses. The counters each have their own enables and clocks, and these need not be synchronized with each other. The counters are incremented only, never decremented. If the depth of your FIFO is a power of 2, counter rollover is not a problem. Otherwise, you will need to reset your counter when the last address is reached. The empty, full, and almost full (or half full) flags will be implemented using comparators. I hope this is of some help. Good Luck, Frank MadisonArticle: 27515
rk wrote: > > Greg Neff wrote: > > > > In article <8uuvue$8iq$1@news.utdallas.edu>, > > V Ram <ipickledthefigsmyeslf@mrbourns.com> wrote: > > (snip) > > Anyone > > > use ViewDraw? > > > > Yes, we use ViewDraw. I have been told that you can mix VHDL and > > schematics with ViewLogic, but I have never tried it. You probably > > need to generate an EDIF netlist out of the synthesis tool, and build a > > schematic symbol wrapper for the netlist. > > Hi Greg, > > I *think* you can do that with Viewlogic if you have the fancier > simulator that can mix the VHDL and the Viewlogic netlists. I don't > have that license, just regular Viewsim, so I'm not sure, haven't > actually tried it myself. Here's what it says in the help file: > > In addition to stand alone VHDL analysis > and simulation, Workview Office also supplies > ViewSim the Workview Office gate-level digital > simulator and VCS for Windows. You use ViewSim > to simulate schematic-based digital designs. > VCS for Windows is the Workview Office Verilog > simulator. You use VCS to simulate Verilog designs. > > You can use each of these simulators independent > of each other or you can use them in conjunction > with one another, this is Workview Office Digital > Fusion. With Digital Fusion you can concurrently > simulate designs containing any combination of > Verilog, VHDL, and/or logic primitives. > > rk Yes, you need the program called "FUSION" which hooks schematic and vhdl outputs together. A good way of doing this is do make a symbol for the "component" for the vhdl and then place it in the schematic. There are two ways of doing this: one with the symbol wizard which I hate, because I hardly got it to work or the program called v2sym or something like that. It is a dos-based command line program found in ...viewlogic\bin I think. Basically you need to make a symbol that is EXACTLY representive of your VHDL port. I am not sure how that works with Generics, I never tried it with them. What I did find useful was being able to do back-annotated simulations in a testbed. Where the VHDL in the symbol was compiled and routed and had timing data in it. There is an option on a symbol that says what type of symbol it is in Viewdraw. Select VHDL model then tell it where to find the model. -Kip kip@netgate.netArticle: 27516
"rk" <stellare@nospamplease.erols.com> wrote in message news:3A1E9646.30F677A1@nospamplease.erols.com... > > > > If I was using local routing for clocks in what appears to > > be your situation _and_ the rate wasn't too high I'd be > > inclined to impliment using master-slave FF structures (as > > long as it was only for small blocks :) . Dull but > > effective. > > A simple solution is to, as long as the frequency isn't too high and the > duty cycle not too bad, simply have the flip-flops that are sequentially > adjacent be clocked off opposite edges of the high-skew clock> <snip> That's master slave in my book :) DaveArticle: 27517
Hi, chsw wrote: > > hello: > when i have synthesis my project in Windows NT on the platform of the pc,i plan to simulate > with NC-VERILOG in Solaris 2.6 platform.how do i? Well, if you have your target library in Verilog format, try and compile that Verilog file(s) with NC-Verilog on UNIX. > Can the library of the xilinx Foundation 2.1i > of the pc be used in NC-VERILOG in the Solaris? If you are talking about "compiled" library, as far as I know no EDA tool can "understand" (or read) the compiled database of another EDA tool (it may also be true for the same family of tools but different versions). And what you are asking is "across platforms".. Just impossible - I feel (:- HTH, Srini -- Srinivasan Venkataramanan (Srini) ASIC Design Engineer, Chennai (Madras), IndiaArticle: 27518
Andy,
Thanks so much. This was exactly what I needed to get this working right.
What is this about the Ashenden book? I am not familiar with this reference.
Andy Peters wrote:
> Theron Hicks wrote:
> >
> > I have a ROM generated in coregen that I would like to place in my
> > system. How do I use the coregen template from the language tools?
> > Several places in the instructions in the template are not especially
> > clear. For example what is the intent of the
> > -- synopsys translate_off
> > and
> > -- synopsys translate_on
> > comments in the template.
>
> Those are pragmas that tell the synthesis tool to ignore code between
> translate_off and translate_on. In this case, they are used because
> Synopsys does not understand configurations. The synthesis tool just
> creates a black box for the ROM that the P+R tools fill in. However, to
> simulate, something must be there.
>
> > Where exactly do I place the configuration snippet?
>
> At the end of the source file.
>
> > -- synopsys translate_off
> >
> > for all : rom256x8 use entity
> > XilinxCoreLib.C_MEM_SP_BLOCK_V1_0(behavioral)
> > generic map(
> > c_has_en => 0,
> > c_rst_polarity => 1,
> > c_clk_polarity => 1,
> > c_width => 8,
> > c_has_do => 1,
> > c_has_di => 0,
> > c_en_polarity => 1,
> > c_has_we => 0,
> > c_has_rst => 0,
> > c_address_width => 8,
> > c_read_mif => 1,
> > c_depth => 256,
> > c_pipe_stages => 0,
> > c_mem_init_radix => 16,
> > c_default_data => "FF",
> > c_mem_init_file => "rom256x8.mif",
> > c_we_polarity => 1,
> > c_generate_mif => 0);
> > end for;
> >
> > -- synopsys translate_on
> >
> > What is the intent of these lines?
>
> The configuration indicates which entity/architecture pair are used "for
> all" instantiations of the component rom256x8. In this case, all
> instantiations of rom256x8 pull a component called C_MEM_SP_BLOCK_V1_0
> out of the XilinxCoreLib, and it uses the architecture called
> behavioral. In addition, generics are supplied.
>
> > --
> > -- <Insert LIBRARY Declaration here>
> > --
> > -- configuration <cfg_my_design> of <my_design> is
> > -- for <my_arch_name>
> > -- <Insert CONFIGURATION Declaration here>
> > -- end for;
> > -- end <cfg_my_design>;
> > --
> > -- If this is not the top-level design then in the next level up, the
> > following text
> > -- should appear at the end of that file:
> > --
> > -- configuration <cfg> of <next_level> is
> > -- for <arch_name>
> > -- for all : <my_design> use configuration <cfg_my_design>;
> > -- end for;
> > -- end for;
> > -- end <cfg>;
> > --
> > How do I fill in the various blanks?
> > Does anyone have an example of code with a functioning coregen part in
> > it?
>
> See example below! Assume the code is in a source file called fifo.vhd.
>
> library ieee;
> use ieee.std_logic_1164.all;
>
> entity fifo is
> port ( );
> end entity fifo;
>
> architecture fifo_arch of fifo is
>
> signal ....
>
> -- CORE dual-port RAM:
> component dpram16d16w is
> port ( ... );
> end component dpram16d16w;
>
> begin
>
> u1 : dpram16d16w
> port map ( ... );
>
> end architecture fifo_arch;
>
> -- configuration only needed for simulation:
> -- synopsys translate_off
> library XilinxCoreLib;
>
> configuration cfg_fifo of fifo is
> for fifo_arch
> for all : dpram16d16w use entity XilinxCoreLib.dpramVHT(behavioral)
> generic map ( ... );
> end for; -- all
> end for; -- fifo arch
> end configuration cfg_fifo;
> -- synopsys translate_on
>
> Now, assume the following is in the next-higher-level code. This could
> be your test bench for the fifo module, or it could be the next
> hierarchy level of your chip design. Call this file top_level.vhd.
>
> library ieee;
> use ieee.std_logic_1164.all;
>
> entity top_level is
> port ( ... );
> end entity top_level;
>
> architecture top_level_arch is
>
> -- we want a fifo:
> component fifo is
> port ( ... );
> end component fifo;
>
> begin
>
> u1 : fifo
> port map ( ... );
>
> end architecture top_level_arch;
>
> -- synopsys translate_off
> configuration cfg_top_level of top_level is
> for top_level_arch
> for all : fifo
> use configuration work.cfg_fifo;
> end for; -- all fifo
> end for; -- top-level-arch
> end configuration cfg_top_level;
> -- synopsys translate_on
>
> The secret here is that you must write a configuration if a lower-level
> component uses a configuration.
>
> Yeah, wouldn't it be nice if Xilinx' documentation didn't suck so hard
> here? You should read the Ashenden book's section on configurations.
>
> -- a
> ----------------------------
> Andy Peters
> Sr. Electrical Engineer
> National Optical Astronomy Observatory
> 950 N Cherry Ave
> Tucson, AZ 85719
> apeters (at) n o a o [dot] e d u
>
> "It is better to be silent and thought a fool,
> than to send an e-mail to the entire company
> and remove all doubt."
Article: 27519fred wrote: > > "rk" <stellare@nospamplease.erols.com> wrote in message > news:3A1E9646.30F677A1@nospamplease.erols.com... > > > > > > If I was using local routing for clocks in what appears > to > > > be your situation _and_ the rate wasn't too high I'd be > > > inclined to impliment using master-slave FF structures > (as > > > long as it was only for small blocks :) . Dull but > > > effective. > > > > > A simple solution is to, as long as the frequency isn't > too high and the > > duty cycle not too bad, simply have the flip-flops that > are sequentially > > adjacent be clocked off opposite edges of the high-skew > clock> > <snip> > That's master slave in my book :) Hmmm ... *usually* for master-slave flip-flops one uses latches for each of the two parts. Using a simple clock - clockbar strategy with no minimum delay between latches makes the circuit sensitive to skew. By using two edge-triggered flip-flops and opposite edge clocking, then the circuit is insensitive to skew (but sensitive to duty cycle) and let's the problem of making good flip-flops rest on the manufacturer's shoulders. Of course, definitions are always hard to agree on. A few years ago we debated the meaning of the word "is". Today we debate the meaning of the word "vote" and we all now know what "chad" is. :-) Have a good day! rk p.s. I have made, in FPGAs, lots of master-slave flip-flops out of latches (for experimental purposes). I have also, again for experimental purposes, made shift registers of positive edge-triggered flip-flops on local clocks - *carefully* managing skew. Have trouble shot many circuits (fortunately none of them mine) where skew wasn't managed carefully and the circuits failed.Article: 27520
Zhen Luo wrote: > > Thanks for the replies for my previous posting. They are really helpful. > Here are more questions about general aspects of configurable computing. > > I think most FPGA designers today go for the HDL synthesis and automatic > placement and routing approach. And in this process, designers would try to > include the hard macros like Xilinx cores in their design to improve the > overall performance. However, one of my reviewers believed most designers > for commercial products would probably still go for manual placement and > routing. This probably depends on the market. If you're designing high end boxes that will sell for $100K then time to market is probably most important, devices will be spec'd that the designer is _sure_ can cope with the design and the tools will be left to do a 'good enough' job. (80% of designs?) If you're designing a product that is pushing the technology, or a _very_ high volume product where every penny counts then time will be spent getting highest possible performance or squeezing the design into the smallest possible design.(20% of designs?). > Secondly, I state that configurable computing shortens the development cycle > by comparison to ASIC design. However, one of my reviewers argue that ASIC > design can also be done in a comparable time frame through design > automation. I'd say that's rubbish if you're doing any sort of 'one off' design. Nial.Article: 27521
Ahh...you guys are classic.. Well, I understand the validity of the master-slave architecture, but I'm sorry when I'm coding in HDL, I would like to try and get above trying to split my domains into posedge and negedge designs. Not only that, wouldn't this design have to run at twice the speed, because now I only have 1/2 the clock cycle for my logic to complete (posedge to negedge)? And hand placing even a portion of a multi-million gate design? Unless it's less than 100 gates, then fuh-get it :) I am loving the clock enable signal though. My 5th clock is a 50MHz clock, which comes out of a DLL as a /2 of a 100MHz clock, which of course is on a global resource. If the USELOWSKEWLINES doesn't work, I'll try this. Thanks again for all your help. Cheers, WallyArticle: 27522
Asynchronous FIFOs are quite possibly one of the most difficult modules to implement. In order to get water-mark flags to work properly (half-full, etc) you really need to use gray codes. The Xilinx app notes describe this well. But unless you get deep into the design and get a good feel for all of the asynchronous nuances of your FIFO, you will likely have problems. Xilinx followed their app notes in creating their Asynchronous FIFO core generator. I have used it in several implementations with great success. I would suggest checking it out if you want a quick and simple solution.Article: 27523
Zhen, Xilinx has access the to world class fab facilities, with the world's best processes (such as: http://www.xilinx.com/prs_rls/ibmpartner.htm ). The transistors are no better, nor worse, than Intel's. Intel does have one advantage: they can operate their processor at any voltage they want. Thus, if it doesn't quite melt down at 1.875 Vdv, they are free to operate there --- they make the motherboards! Xilinx must remain compatible with all of the other IC's in the system, and thus may not choose to operate off its own custom power supply. There are other limitations on why the FPGA Clock speed can not be as fast as the microprocessor which are related to architecture. Regardless, the massive parallelism in FPGAs allows for solving many compute problems 200X faster than the fastest processors. See the Xtreme DSP(tm) announcement. It is no coincidence that Xilinx FPGAs are being used in cellular basestations for 3G and beyond. http://www.xilinx.com/prs_rls/xtremedsp.htm As for IO, we are already moving ahead with serial IO technologies to break that bottle neck (see aquisition of RocketChips: http://www.xilinx.com/prs_rls/rocketchips.htm Austin Zhen Luo wrote: > Hi, guys > > I am writing my thesis now and one of my reviewers had a different view > about FPGA clock rate. I felt FPGA could not achieve the general-purpose > processor like clock rate (> 1GHz right now) because FPGA's structure and > its components (like SRAM-based look-up table, programmable wiring > switchbox) are just not fit for high clock rate. My reviewer pointed out > that FPGAs couldn't achieve the general-purpose processor like clock rate > because they had to be cost-effective. If Xilinx had a foundry like intel > did and they would go all for the clock speed, they could make it to the > similar range. I think there is some truth in it, but I still don't think > FPGA could be that fast even if they do so. > > I would really like to hear your thoughts on this. Meanwhile, I also have a > question, why is the I/O clock rate of Xilinx chips much slower than their > internal clock rate? Would that finally become the bottleneck for improving > the overall clock rate for FPGA applications? > > Also, since the clock rate on FPGA varies between applications, let's just > assume that we have a design that is highly pipelinable, like an > array-multiplier. > > Thanks! > > -- ZhenArticle: 27524
rk, I will be using the FPGA for real-time compression in a battery operated camera. Most of the time, (hours) the user will just be looking around. When they activate the shutter (maybe halfway down) autofocus kicks in, the FPGA wakes up and is ready to compress video. I can handle about 1-2Watts during compression but the standby power should be around 1mW or so. I agree on the ASIC side, although I am bothered by the lack of field upgradability. There are always improvements going on in compression algorithms. I would like to be able to reprogram the camera with new algorithms. This is not a consumer device, by the way. Thanks, Steve The Gatefield/Actel answer might be perfect. I'll check them out. rk wrote: > Why power down? Most modern FPGAs that I have seen have very low static > power, if they are not driving any DC loads. > > "Very low power consumption" is a relative term, of course. Does that > mean 1 mA? 1 uA? > > Quicklogic also has quick power-on times. Note that "quick" is also a > relative term, and is not zero for antifuse technologies that are > currently in production. > > There's also the Gatefield/Actel FPGA - higher densities and > reprogrammable and non-volatile. No external memories needed. > > Or how about something like Chip Express or one of the other vendors > that can handle small quantities of ASICs - which should get you lower > power consumption, no configuration time, and most definitely > non-volatile. For "minimum" power, an ASIC might be the best way to go. > > rk -- Steve Nordhauser Director of New Product Development Imaging Systems IEM, Inc. 60 Fourth Ave. Albany, NY 12202-1924 digital@nycap.rr.com http:/www.iem.net Phone: (518) 449-5504x21 Fax: (518) 449-5567
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