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hi, I think this paper would be helpful to some people here and interesting for most. Interesting read. Available at : http://www.xilinx.com/labs/satnam/death_of_the_rloc.pdf Muzaffer http://www.dspia.comArticle: 26776
>The 22V10 was invented at AMD ( not MMI ) in 1980 ( I worked there at that >time ). >The design is thus 20 years old. We can today pack far more functionality, >sophistication, and performance into a small piece of silicon. >We would prefer you to migrate your design to integrate more of the total >functionality into a CoolRunner or an FPGA. >Why should we first break our wafer into thousands almost invisible specks of >silicon, put each of them in a 24-pin package, so that you then reassemble >them on an expensive pc-board? Nobody benefits from that. >Whoever sells such tiny integrated circuits is not in the silicon business, >but rather in the plastics, leadframe, handling, marking, and shipping >business, where it is extremely difficult to reduce cost and remain >profitable. >Moore's law does not apply to a 22V10. Of course I can see where you are coming from - selling cheap devices is not Xilinx's business aim and that's the end of it. However it remains that a 22V10 is a good solution to many applications. I have done a lot of XC3k design, mostly for mixed-tech ASIC prototyping, over the past 10 years, and have always examined the possibility of a FPGA or a CPLD in the numerous products which I have designed. I was never able to use one because of one thing or another; the low-power FPGAs (3k, 4k etc) are too expensive for all "cheap" products, there is the issue of a separate config chip (or using an even more expensive alternative), and CPLDs all draw far too much static power. The Philips 22V10, almost zero power, was a great solution at the right price, about $2 (1k+). If you can do an FPGA for that price, or even $3, with on-chip config FLASH, then I will eat my words. Peter. -- Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y. Please do NOT copy usenet posts to email - it is NOT necessary.Article: 26777
hi ray, i don't see what do you mean by << The only viable solution I have found is to pipeline the CE's in a distribution tree. >> me i duplicate the CE generator In article <39F86C52.36F7F1BD@andraka.com>, Ray Andraka <ray@andraka.com> wrote: > Nope, That's one of the problems with the VIrtex architecture. They tell you > to use the "low skew routing resource" ie secondary clock network for this, but > I find it is way too slow compared to the speed of designs I can do in the > part. The only viable solution I have found is to pipeline the CE's in a > distribution tree. > > Steven Derrien wrote: > > > > Hello, > > > > I was wondering if it is possible to use a Virtex BUFG buffer to drive a > > non clock signal ( in my case it is a CE signal with a very heavy > > fan-out (all DFF CE ports)) > > > > Steven > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com or http://www.fpga-guru.com > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26778
try www.avnet.com "Netscape User" <your_namel@email_address.net> wrote in message news:39F8F4E4.8EFF0A78@email_address.net... > Is it just me, or are the Spartan2/VirtexE parts in short supply? > I've checked several distributors, and while they do have *some* parts > in stock, more parts are listed as 'ASK' or 'NOT AVAIL.' > > Yet visiting Xilinx's page, Xilinx would still have you believe the $10 > for 100,000k gates is just around the corner. $10 if you can find it?Article: 26779
Andy,
I'm sorry if your situation makes you so skeptical. This is job
is real and the work environment is great. Sometimes we do have deadlines
so some of us put in extra time. (paid) We use either Verilog and VHDL
whichever is dictated by our customer at the time. We feel if you only know
one language we can help you learn the other fast enough. Lastly, Synthesis
is only part of the job we do. We have synthesis knowledge and will teach a
worthwhile candidate. At this point in time good engineers with limited
experience with ASICS need to be grown from good FPGA design engineers.
Best of Luck,
Barry
"Andy Peters n o a o [.] e d u>" <"apeters <"@> wrote in message
news:8tcqfk$177a$1@noao.edu...
> Barry Schneider wrote:
> >
> > I am presently working at a ASIC consulting company and we have a huge
> > backlog of
> > work. We need help and will pay well. We have a great office and have
> > very flexible hours. We are looking for Verilog and/or VHDL
experience.
> > Synthesis and/or Mixed Signal a plus. If you are interested in a Good
Job
> > e-mail me at barry61s@optonline.com
>
> Waitaminit.
>
> "Flexible hours"? I guess that means, "arrive at dawn, leave sometime
> before 9 pm."
>
> "Verilog and/or VHDL experience"? Which one? Does that mean I get to
> use VHDL, even if every other engineer in the place is a Verilogger?
>
> "Synthesis and/or Mixed Signal a plus"? Seems to me that an ASIC
> position would REQUIRE synthesis experience.
>
> -- a
> ----------------------------
> Andy Peters
> Sr. Electrical Engineer
> National Optical Astronomy Observatory
> 950 N Cherry Ave
> Tucson, AZ 85719
> apeters (at) n o a o [dot] e d u
>
> "It is better to be silent and thought a fool,
> than to send an e-mail to the entire company
> and remove all doubt."
Article: 26780Ray Andraka wrote: > Nope, That's one of the problems with the VIrtex architecture. They tell you > to use the "low skew routing resource" ie secondary clock network for this, but > I find it is way too slow compared to the speed of designs I can do in the > part. The only viable solution I have found is to pipeline the CE's in a > distribution tree. > > Steven Derrien wrote: > > > > Hello, > > > > I was wondering if it is possible to use a Virtex BUFG buffer to drive a > > non clock signal ( in my case it is a CE signal with a very heavy > > fan-out (all DFF CE ports)) > > > > Steven Unusually Ray's no quite right here. I was using this trick to make the domain crossing between the main system clock and a 1/2 speed clock formed by a divide by 2 FF followed by a BUFG [The ASIC Vendor coudn't emulate Virtex's div2 DLL output]. What happens is that you get a warning in MAP and the delay from the BUFG output to the CE inputs is very much longer than the delay to the clock inputs BUT o Its still not huge. I've just knocked up a test case that shows it to be 1.8-2.6 nsec against the CLK input delay of 0.59 nsec. o Its still bounded in that most of the routing is along the global clock lines so that even CE inputs a long way from the global buffer have well controlled delays. In the end I had to remove this for the ASIC since the Vendor couldn't [... or wouldn't - I'm still not sure which] allow clock tree connections to CE inputs. I then used Synplify's automatic register replication mechanism to do the fanout from a duplicate of the BUFG input but it was still a lot more hassle. Of course even though it works at present Xilinx might always, in their infinite wisdom, change it from a warning to an error.Article: 26781
Muzaffer Kal wrote: > hi, > I think this paper would be helpful to some people here and > interesting for most. Interesting read. Available at : > http://www.xilinx.com/labs/satnam/death_of_the_rloc.pdf > > Muzaffer > > http://www.dspia.com Yes, nice article, but why the hell do Xilinx make me download 2MB+ for 8 pages!!! and I've got a 128KBit ISDN - I hate to think what its like on a modem ?Article: 26782
> The Philips 22V10, almost zero power, was a great solution at the > right price, about $2 (1k+). If you can do an FPGA for that price, or > even $3, with on-chip config FLASH, then I will eat my words. The XCR3064XL-10VQ44C is only $3.20 -- StuartArticle: 26783
What is the difference between FPGA and CPLD , please let me know/.Article: 26784
What is a RealTime System .Single line defination please.Article: 26785
Scott, I did looked at Xapp200 (Very well documented code !). The thing is 155MHz seems to be very aggressive (despite the half- duplex nature of my application) and I was just wondering if anyone had ever implemented similar design before. Thanks for your response, Rotem. > Rotem, > You've probably already done this, but just in case, you might want to go > to Xilinx's web site and download the application note XAPP200: > "Synthesizable 1.6 GBytes/s DDR SDRAM Controller". (www.xilinx.com, click > on "Products", then "Application Notes", then "Virtex"). This was written > for the Virtex and Spartan-II families targeting 100MHz DDR SDRAM, and it > could be potentially implimented with even higher performance in the > Virtex-E family (though I'm not sure of the actual performance achievable, > and 155 will be aggressive...). Recently we've added both VHDL and > Verilog reference designs that you can download as well (with links right > next to the one for the app note). Hope this helps, > -Scott S. Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26786
On Sun, 29 Oct 2000 00:35:00 -0700, "ALOK SAHOO" <alokworld@yahoo.com> wrote: >What is a RealTime System .Single line defination please. System operation at time-constraints, e.g. "answer to an interrupt must be given in an certain amount of time"Article: 26787
Hello. I downloaded Webpack 3.2i and installed. I tried Sparutan2 compile, but Error happened. Error Massege is >The XML Parser environment is incorrectly set up, preventing it from >finding its text transcoding files. Nomally these will be located >via the ICU_DATA environment variable, or located relative to the >XML4C2 DLL(or SharedLib).) Please check your installation. >EXEWRAP detected a return code of '9999' from program 'ngdbuild' I'm using Window98 Japanese Version. What do I do? T.Koyama.Article: 26788
Just starting at the VHDL so be gentle. I am doing a simple ALU for my class. Having trouble with the various types in VHDL. I am trying to do a case statement on the control input (opcode). When I get to the code that says to add, subtract, and, or, etc. I get errors. The errors are usually type mismatches. It seems like some operations (add, subtract) what the inputs to be integers while other operations (and, or) what them to be bit_vectors or std_logic_vectors. How can I do this? I have tried several different things and can't get it going. I know this is simple and I am just missing something (I hope). Thanks a bunch. -- Jim Patterson jpatters@stny.rr.comArticle: 26789
Avnet has 80 parts listed, all of which are out of stock and only one of which has a lead time listed. Depending on whether you are buying or getting an engineering sample, it is 12 or 17 weeks. Peter, are these chips going to be real soon? "Anthony C" <anthony.crawford2@sympatico.ca> wrote in message news:0NHK5.398036$1h3.10712829@news20.bellglobal.com... > try www.avnet.com > > > "Netscape User" <your_namel@email_address.net> wrote in message > news:39F8F4E4.8EFF0A78@email_address.net... > > Is it just me, or are the Spartan2/VirtexE parts in short supply? > > I've checked several distributors, and while they do have *some* parts > > in stock, more parts are listed as 'ASK' or 'NOT AVAIL.' > > > > Yet visiting Xilinx's page, Xilinx would still have you believe the $10 > > for 100,000k gates is just around the corner. $10 if you can find it? > > >Article: 26790
This is a known XILINX software bug, related to Windows "International Settings". XILINX AnswerDatabase record #10223 http://support.xilinx.com/techdocs/10223.htm recommends to submit support request and to obtain a patch. I've done that, and obtained bug fix. Regards, Alex Sherstuk "T.Koyama" <basaro@fa2.so-net.ne.jp> wrote in message news:8thahc$45n$1@news.gao.ne.jp... > Hello. > > I downloaded Webpack 3.2i and installed. > I tried Sparutan2 compile, but Error happened. > > Error Massege is > >The XML Parser environment is incorrectly set up, preventing it from > >finding its text transcoding files. Nomally these will be located > >via the ICU_DATA environment variable, or located relative to the > >XML4C2 DLL(or SharedLib).) Please check your installation. > >EXEWRAP detected a return code of '9999' from program 'ngdbuild' > > I'm using Window98 Japanese Version. > > What do I do? > > T.Koyama. > > >Article: 26791
Hi, It is quite difficult to comment unless you post your code. From what I can understand from your posting is that "you are missing the correct libraries" to do proper "arithmetics". You should be using LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; -- If the later is supported by your tool Hope this helps a bit. Else please post your code. Regards, Srini In article <T4XK5.99848$JS3.15201591@typhoon.nyroc.rr.com>, "Jim Patterson" <jpatters@stny.rr.com> wrote: > Just starting at the VHDL so be gentle. I am doing a simple ALU for my > class. Having trouble with the various types in VHDL. I am trying to do a > case statement on the control input (opcode). When I get to the code that > says to add, subtract, and, or, etc. I get errors. The errors are usually > type mismatches. It seems like some operations (add, subtract) what the > inputs to be integers while other operations (and, or) what them to be > bit_vectors or std_logic_vectors. How can I do this? I have tried several > different things and can't get it going. I know this is simple and I am > just missing something (I hope). Thanks a bunch. > > -- > Jim Patterson > jpatters@stny.rr.com > > -- Srinivasan Venkataramanan ASIC Design Engineer Chennai, India Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26792
You are correct. I dug through the FAQ and saw the info on the libraries. I added the numeric_std and now it compiles! Thanks for your response. -- Jim Patterson jpatters@stny.rr.com Srinivasan Venkataramanan <srinivasan_v@my-deja.com> wrote in message news:8thpgt$rql$1@nnrp1.deja.com... > Hi, > It is quite difficult to comment unless you post your code. From what > I can understand from your posting is that "you are missing the correct > libraries" to do proper "arithmetics". > > You should be using > > LIBRARY IEEE; > USE IEEE.STD_LOGIC_1164.ALL; > USE IEEE.NUMERIC_STD.ALL; > > -- If the later is supported by your tool > > > Hope this helps a bit. Else please post your code. > > Regards, > Srini > > In article <T4XK5.99848$JS3.15201591@typhoon.nyroc.rr.com>, > "Jim Patterson" <jpatters@stny.rr.com> wrote: > > Just starting at the VHDL so be gentle. I am doing a simple ALU for > my > > class. Having trouble with the various types in VHDL. I am trying > to do a > > case statement on the control input (opcode). When I get to the code > that > > says to add, subtract, and, or, etc. I get errors. The errors are > usually > > type mismatches. It seems like some operations (add, subtract) what > the > > inputs to be integers while other operations (and, or) what them to be > > bit_vectors or std_logic_vectors. How can I do this? I have tried > several > > different things and can't get it going. I know this is simple and I > am > > just missing something (I hope). Thanks a bunch. > > > > -- > > Jim Patterson > > jpatters@stny.rr.com > > > > > > -- > Srinivasan Venkataramanan > ASIC Design Engineer > Chennai, India > > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 26793
I already have: 1) Ashenden's "Designers guide to VHDL" 2) Stefan Sjoholm & Lindh's "VHDL for designers" 3) Douglas Smith's "HDL Chip Design" 4) Kurup & Abbasi's "Logic synthesis using Synopsys" I am looking for a couple of recommendations on books w/ some state of the art examples/techniques in VHDL design and synthesis. I currently use ModelTech's VHDL compiler/simulator and Synopsys' Design Analyzer/FPGA compiler. Cost is no object and I am familiar w/ the VHDL faq book list. Thanks in advance...Article: 26794
Rick Filipkiewicz wrote: > > Muzaffer Kal wrote: > > > hi, > > I think this paper would be helpful to some people here and > > interesting for most. Interesting read. Available at : > > http://www.xilinx.com/labs/satnam/death_of_the_rloc.pdf > > > > Muzaffer > > > > http://www.dspia.com > > Yes, nice article, but why the hell do Xilinx make me download 2MB+ for > 8 pages!!! and I've got a 128KBit ISDN - I hate to think what its like > on a modem ? Xilinx seems to let marketing into a lot of things that they provide on the web. I can't say that this document is full of "pretty" graphics or other large objects, since I am still waiting for it to download. But I have seen documents that were primarily technical, such as the High Volume Packages document (2 pages), that are many, many bytes, full of very complex "pretty" pictures and very slow to draw in Acrobat. There is no real reason to do this, Xilinx just seems to be rather loosely controlled internally. Perhaps someday they will get a better idea of how to produce data for engineers... -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 26795
> The XCR3064XL-10VQ44C is only $3.20 In what country, and volume?? An old 3064? They are obsolete now. Peter. -- Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y. Please do NOT copy usenet posts to email - it is NOT necessary.Article: 26796
Of course an easier experiment is to remove the rlocs from your existing designs and find that all of them perform much worse or can't be routed at all. The same goes for mapping directives. Muzaffer Kal <muzaffer@dspia.com> wrote: > I think this paper would be helpful to some people here and > interesting for most. Interesting read. Available at : > http://www.xilinx.com/labs/satnam/death_of_the_rloc.pdf Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26797
Skip the middleman- Go directly to the LSI-logic web site: http://idealcareers.lsilogic.com/joblist.html Or the Mint technology web site: http://www.mint-tech.com/ Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26798
Come on Magnus, don't you now that he knew this? This is part of his poking fun at the guy! -Simon Ramirez, Consultant Synchronous Design, Inc. "Magnus Homann" <d0asta@mis.dtek.chalmers.se> wrote in message news:ltg0lrr55t.fsf@mis.dtek.chalmers.se... > Ron Huizen <rhuizen@bittware.com> writes: > > > Essential Skills: > > > Power PC > > Power PC? I never thought of that as a marketable skill, although I > > guess have years of experience plugging in my PC. > > He probably meant PowerPC, as in MPC7400(*). > Homann > Magnus Homann, M.Sc. CS & E > d0asta@dtek.chalmers.seArticle: 26799
Austin,
This is very typical -- for headhunters and managers to ask the world
but only want people with 2-3 years experience. What they really mean to
say is that they want a fully qualified engineer like yourself to do the
work, but they only want to pay a junior engineer salary.
-Simon Ramirez, Consultant
Synchronous Design, Inc.
P.S. I can teach a junior engineer to know what FPGA stands for and charge
only one man-week of time. Let me know if you come across anyone interested
in learning this very important skill.
"Austin Franklin" <austin@dark88room.com> wrote in message
news:01c03d35$06251b30$2c0bf7a5@drt1...
> > > 3 years experience in the industry
>
> This is actually the one that gets me...a whole three years experience,
and
> they expect them to be able to do all this other stuff...I'd be impressed
> if the guy knew what FPGA stood for with 3 years experience (in the
> industry, of course ;-)
>
> Their expectations are, to say the least, bizarre...at least in my book.
>
>
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