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Authors (A)
a:
48720: 02/10/23: data sheets for tda5247ht
58068: 03/07/14: Re: free downloadable VLSI softwares
78047: 05/01/24: Re: How does a SDRAM controller work?
118168: 07/04/18: Question about Xilinx ISE (problem with signals trimming)
118202: 07/04/19: Re: Question about Xilinx ISE (problem with signals trimming)
A Al-Sabagh:
28455: 01/01/13: Re: CHES 2001 --- 2nd CFP
A Beaujean:
68487: 04/04/06: Fast Carry Chains in Xilinx SpartanII FPGA's
68575: 04/04/08: Re: Need help with using inout (bi-dir) in VHDL for Xilinx FPGA
68844: 04/04/20: Re: Configurating multiple devices(FPGA and CPLD) with different Vccs through the JTAG
69061: 04/04/26: Re: Xilinx XC9500 CPLD Wired-OR; Wired-ND
69180: 04/04/29: Behaviour of Xilinx FPGA pins during Slave Serial Download.
69220: 04/04/30: Re: Fast Carry Chains in Xilinx SpartanII FPGA's
71210: 04/07/12: Re: extending a signal pulse
71254: 04/07/13: Re: dots during P&R, ISE
72887: 04/09/07: Re: how to get the data from ADC
72966: 04/09/09: Problem with HELP after installation of Webpack ISE
73452: 04/09/21: Re: XST vhdl adder with carry out : broken carry chain
73469: 04/09/22: Problem with Xilinx Webpack documentation
73567: 04/09/24: Re: Problem with Xilinx Webpack documentation
74750: 04/10/18: Re: which xilinx CPLD to select?
79620: 05/02/22: Spartan3 Power Supply Circuits
79674: 05/02/22: Re: Spartan3 Power Supply Circuits
80346: 05/03/04: Re: SR latches in Xilinx devices?
80364: 05/03/04: Re: VHDL Instantiation
80802: 05/03/11: Re: Global Reset paths
80951: 05/03/15: Re: Global Reset paths
81280: 05/03/21: Re: TPS75003 for FPGAs
A Benkrid:
17980: 99/09/20: test
A Day & A Knight:
64335: 03/12/29: Re: This design contains an RPM macro bm_0 which is to be automatically placed, but it contains TBUF elelements that are not allowed during automatic placement of RPMs?
64370: 03/12/31: Re: This design contains an RPM macro bm_0 which is to be automatically placed, but it contains TBUF elelements that are not allowed during automatic placement of RPMs?
64391: 04/01/01: Question on partial reconfiguration flow...Must use EDIF flow?
64418: 04/01/03: Re: Question on partial reconfiguration flow...Must use EDIF flow?
64424: 04/01/04: Complicated clocking in an FPGA.
A E Lawrence:
30469: 01/04/09: Re: Handel-C
A person:
18254: 99/10/10: 1.8V FPGA
20326: 00/02/04: Re: Conditional compilation in VHDL?
27615: 00/11/29: Re: Virtex ROM ques.
27616: 00/11/29: Re: Synplify Benchmarks
A Random Mike:
42012: 02/04/12: Re: ChipScope Speed
64168: 03/12/18: Re: CRC-32 in spatan-3
a s:
151023: 11/03/01: Count bits in VHDL, with loop and unrolled loop produces different results
151030: 11/03/01: Re: Count bits in VHDL, with loop and unrolled loop produces
151044: 11/03/01: Re: Count bits in VHDL, with loop and unrolled loop produces
151046: 11/03/01: Re: Count bits in VHDL, with loop and unrolled loop produces
151058: 11/03/02: Re: Count bits in VHDL, with loop and unrolled loop produces
A sharp:
9970: 98/04/18: General Purpose Interface
A William Sloman:
6928: 97/07/09: Re: fast scopes: how?
7132: 97/08/04: Re: digitizer design, high speed
A.:
22689: 00/05/18: Traning for Nallatech??
A. Abellard:
68457: 04/04/05: Problem for CNA/CAN conversion
68475: 04/04/06: Problem for DAC/ADC conversion (Stratix EP1S25 Development Board)
A. Alsolaim:
23881: 00/07/13: HELP!! Nallatech Virtex Board.
A. Chemeris:
35836: 01/10/19: About BLIF
A. de Boer:
35604: 01/10/11: Tool qualification for airborne hardware, DO-254
A. dhermies:
29748: 01/03/07: Re: Programming a CPLD
A. Graevinghoff:
1143: 95/05/04: Re: AT&T ORCA data book
A. I. Khan:
30802: 01/04/30: Need info : Training on ASIC/FPGA
31105: 01/05/11: Implementation Of LUT in Vertex-E
31416: 01/05/22: How to handle/store partial product in Core generator ?
34385: 01/08/23: Why this mismatches in simulation and sysnthesis results ?
34646: 01/09/01: How to connect a clock to a non-clock pad ?
35342: 01/09/30: Re: How to fix the hold time violation (clock skew>data skew) in
A. Karen Alfke:
49991: 02/11/27: Re: question about PCB traces for FPGA board... ?
50003: 02/11/27: Re: Frequency multiplier with digital h/w
50005: 02/11/27: Re: question about PCB traces for FPGA board... ?
50016: 02/11/28: Re: question about PCB traces for FPGA board... ?
50018: 02/11/28: Re: Asynchronous FIFOs using Handel-C?
50021: 02/11/28: Re: Metastability in FPGAs
50023: 02/11/28: Re: question about PCB traces for FPGA board... ?
50032: 02/11/28: Re: Metastability in FPGAs
50049: 02/11/29: Re: System Generator and 18x18 multipliers
50050: 02/11/29: Re: programmable FSM
50055: 02/11/29: Re: Metastability in FPGAs
50070: 02/11/30: Re: programmable FSM
50071: 02/11/30: Re: Asynchronous FIFOs using Handel-C?
50077: 02/11/30: Re: Asynchronous FIFOs using Handel-C?
A. Karen Rowe:
38026: 01/12/31: Re: Actel 54sx series clock doubler
A. Karttunen:
98064: 06/03/04: Re: Spartan 3 Expansion Board
A. Kasd:
10472: 98/05/20: XC300 ROM
A. M. G. Solo:
91903: 05/11/16: Call For Papers: 2006 PDPTA, ICAI, SERP + more (28 joint conferences); Las Vegas, USA, June 2006
A. Nelson:
47324: 02/09/23: Re: fpga eval kits
47325: 02/09/23: writing across a column in an SDRAM
47346: 02/09/24: Re: writing across a column in an SDRAM
A. Omondi:
A. P. Richelieu:
88845: 05/08/30: Re: FPGA Development Board Wish List
A. Shakuntala:
530: 94/12/22: Data compression schemes using FPGAs
690: 95/02/07: PLDshell:waveform conversion to PS format
A. Spanias:
4200: 96/09/25: CDMA DSP
11204: 98/07/24: CALL FOR PAPERS - INDUSTRY DSP FORUM AT ICASSP -99
A. Tillmann:
10628: 98/06/06: Over 900 semiconductor links!
A.C.Rochat:
7005: 97/07/22: Re: VHDL Synthesis in Xilinx Foundation Series
7090: 97/07/30: Re: VHDL Synthesis in Xilinx Foundation Series
A.D.:
94834: 06/01/18: Re: [RANT] Webpack 8.1 editor totally messed up ?
95301: 06/01/22: Re: Xilinx Partial Reconfiguration add-on module
102154: 06/05/11: Re: [Newbie] 64-point complex FFT with 32 bit floating-point representation
106770: 06/08/18: Problem with "don't care"
113340: 06/12/11: Partial reconfiguration
113390: 06/12/12: Re: Partial reconfiguration
124062: 07/09/11: PCI byte enalbes in read cycles
124094: 07/09/12: Re: PCI byte enalbes in read cycles
124130: 07/09/12: Re: PCI byte enalbes in read cycles
124161: 07/09/13: Re: PCI byte enalbes in read cycles
124162: 07/09/13: Re: PCI byte enalbes in read cycles
130673: 08/03/30: Re: ISE 10.1 - Initial experience
a.j.:
44693: 02/06/27: 32KHz oscilator in CPLD
44868: 02/07/03: Re: 32KHz oscilator in CPLD
<a.osama@ic.ac.uk>:
833: 95/03/09: FPGA related papers
834: 95/03/09: RE: FPGA Custom Computing Machine
835: 95/03/09: RE: Bit serial multipliers in FPGAs
A.P.Richelieu:
161064: 19/01/30: ARM + FPGA CPU Module running Yocto Linux?
161068: 19/01/30: Re: ARM + FPGA CPU Module running Yocto Linux?
161069: 19/01/30: Re: ARM + FPGA CPU Module running Yocto Linux?
161072: 19/01/30: Re: ARM + FPGA CPU Module running Yocto Linux?
161074: 19/01/30: Re: ARM + FPGA CPU Module running Yocto Linux?
161076: 19/01/30: Re: ARM + FPGA CPU Module running Yocto Linux?
161078: 19/01/30: Re: ARM + FPGA CPU Module running Yocto Linux?
161079: 19/01/30: Re: ARM + FPGA CPU Module running Yocto Linux?
161081: 19/01/30: Re: ARM + FPGA CPU Module running Yocto Linux?
161084: 19/01/30: Re: ARM + FPGA CPU Module running Yocto Linux?
161097: 19/02/01: Re: ARM + FPGA CPU Module running Yocto Linux?
161098: 19/02/01: Re: ARM + FPGA CPU Module running Yocto Linux?
161099: 19/02/01: Re: ARM + FPGA CPU Module running Yocto Linux?
161100: 19/02/01: Re: ARM + FPGA CPU Module running Yocto Linux?
161101: 19/02/01: Re: ARM + FPGA CPU Module running Yocto Linux?
161104: 19/02/02: Re: ARM + FPGA CPU Module running Yocto Linux?
161107: 19/02/02: Re: ARM + FPGA CPU Module running Yocto Linux?
161145: 19/02/05: Re: Is it possible to implement Ethernet on bare metal FPGA, Without
161179: 19/02/15: Re: Altera Cyclone replacement
161239: 19/03/19: Xilinx M1 Pad file
161284: 19/03/22: Re: High-level synthesis
161290: 19/03/23: Re: High-level synthesis
161293: 19/03/24: Re: High-level synthesis
161324: 19/03/28: Re: Replaceme EPROM by CPLD/FPGA
161334: 19/03/29: Re: Replaceme EPROM by CPLD/FPGA
161336: 19/03/30: Re: Replaceme EPROM by CPLD/FPGA
161337: 19/03/30: Re: Replaceme EPROM by CPLD/FPGA
161339: 19/03/30: Re: Replaceme EPROM by CPLD/FPGA
a.palmieri:
1072: 95/04/25: Re: Sunrise ???
1091: 95/04/26: Re: Is anybody using FPGA's to do PCI interfaces?
1704: 95/08/18: Simulation not matching lab results
A.Tillmann:
12007: 98/09/23: Over 1000 semiconductor links!
13979: 99/01/05: Over 1100 semiconductor links!
A.Williams:
6810: 97/06/30: Re: Programming Xilinx 3k/4k in C ?
A.y:
63556: 03/11/25: area constraints
63597: 03/11/25: Re: area constraints
63598: 03/11/25: Re: area constraints
63645: 03/11/27: Re: area constraints
63674: 03/11/27: Re: area constraints
64290: 03/12/25: Re: Problems with Xilinx ISE6.1i P&Rs for Virtex II
a0-0b:
79271: 05/02/16: Xilinx RPM in Makefile?
79307: 05/02/17: Re: Xilinx RPM in Makefile?
79330: 05/02/17: Re: Xilinx RPM in Makefile?
<a12@a.a>:
6945: 97/07/13: $$$$ LOAN BUSINESS, EASY MONTHLY INCOME, NO BRAINER $$$$
<a1734@dis.ulpgc.es>:
17752: 99/08/30: Problem with VHDL in MAX+Plus II / Flex10k
<a19@a.a>:
6944: 97/07/13: $$$$ NEW SYSTEM, BETTER THAN "ADD ME TO YOUR MAILING LIST" $$$
A1A Computer Professionals:
29892: 01/03/15: Archive of Electronic Engineering jobs incl: ASIC,DSP,VHDL,FPGA,RF etc..
30275: 01/03/30: Unlimited Jobs for Electronic Engineering jobs incl: ASIC,DSP,VHDL,FPGA,RF etc..
30657: 01/04/21: Unlimited Jobs for Electronic Engineering jobs incl: ASIC,DSP,VHDL,FPGA,RF etc..
30967: 01/05/05: Unlimited Jobs for Electronic Engineering jobs incl: ASIC,DSP,VHDL,FPGA,RF etc..
a2zasics:
63778: 03/12/03: Hold violation and PLL
63913: 03/12/08: Hold violations
<a7yvm109gf5d1@netzero.com>:
115478: 07/02/12: Re: Building Coaxial transmission line on PCB?
125850: 07/11/06: Re: not totally repulsive
151862: 11/05/25: Re: PCI Express Cable
<a@z.com>:
17794: 99/09/04: Re: synthesis comparion between Synplify and FPGA express
18092: 99/09/29: Re: Looking for substitute for XC17*** Xilinx Prom
18895: 99/11/20: Re: Virtex: Getting flip-flops into the pads
18896: 99/11/20: Re: Xilinx FPGA Editor...does it really work?
18932: 99/11/22: Re: Why not Lucent ORCA FGPAs?
19507: 99/12/28: Re: xilinx help *desperately* needed
20350: 00/02/07: Re: Count 1's algorithm...
20382: 00/02/08: Re: Conditional compilation in VHDL?
20480: 00/02/11: Re: Simulation problem
20481: 00/02/11: Re: Xilinx error message
20482: 00/02/11: Re: Master/Serial mode for Virtex
20484: 00/02/11: Re: Xilinx Virtex Reset
20485: 00/02/11: Re: ROL VHDL operator.. need help!
20495: 00/02/11: Re: Master/Serial mode for Virtex
20559: 00/02/14: Re: Post-synthesis simulation in Foundation Express
20829: 00/02/23: Re: Installing Xilinx Foundation on PC
20830: 00/02/23: Re: Xchecker schematic?
20864: 00/02/24: Re: Xchecker schematic?
21387: 00/03/21: Re: Clock nets using non-dedicated resources
21526: 00/03/24: Re: No- FPGA openness
22314: 00/05/04: Re: How to Prevent theft of FPGA design
22311: 00/05/04: Re: How to connect JTAG to XCS10pc84 FPGA device
a_darabiha:
38197: 02/01/08: Core Generator
38530: 02/01/16: Re: Core Generator
38532: 02/01/16: Image Processing on FPGAs. Dose System Generator help??
38533: 02/01/16: SysGen on PC / Unix ?
41750: 02/04/06: Re: Simulator for xilinx Cores?
<a_maier@my-deja.com>:
18776: 99/11/14: configure_flex10k30e_jtag_jam
18948: 99/11/22: Re: configure_flex10k30e_jtag_jam
18949: 99/11/22: Re: Altera JAM
18950: 99/11/22: Re: [Q] End-goal: porting ISA design to PCI. Which PLD to learn?
A_Smith:
69924: 04/05/24: HSTL and Virtex 2
AA:
157202: 14/11/03: Quartus II TCL or Command line
aa55:
80594: 05/03/09: Re: Good, affordable verilog simulator
80993: 05/03/16: Re: Which HDL?
80994: 05/03/16: Re: Tri-Stae Bus
<aa@mail.pt>:
30811: 01/04/30: New sites 8994
AAA:
93165: 05/12/14: D FLIP -FLOP
93170: 05/12/15: Re: D FLIP -FLOP
93382: 05/12/21: HOW IS GREY BOX VERIFICATION DONE
93770: 05/12/30: TCL SCRIPT AND VHDL DESIGN
93958: 06/01/03: Re: TCL SCRIPT AND VHDL DESIGN
101077: 06/04/25: VERIFICATION AND TESTPLAN
aaf:
20733: 00/02/19: Lattice Download Cable
Aage Farstad:
3654: 96/07/09: jul9-test
4482: 96/11/04: ORCA Configuration
5213: 97/01/31: Steven K. Knapp - no such article
aan.woodz@gmail.com:
96993: 06/02/14: Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?
100929: 06/04/21: Using another crystal oscillator..
AAP3:
37513: 01/12/13: datapath schematic editor
37549: 01/12/14: Re: datapath schematic editor
37696: 01/12/19: MIPS or MOPS?
<aaps@erols.com>:
6476: 97/05/27: Re: Cheap way to develop for FPGAs?
6489: 97/05/28: Re: Cheap way to develop for FPGAs?
6490: 97/05/28: Re: Best way to learn VHDL?
6505: 97/05/29: Re: Cheap way to develop for FPGAs?
6733: 97/06/20: Re: APS-X84 - recommended?
6732: 97/06/20: Re: Help: Interfacing a Xilinx 4k to a microprocessor
6756: 97/06/24: Re: FPGA prototype board
6778: 97/06/26: Re: FPGA prototype board
Aare Tali:
33888: 01/08/07: Spartan-2 and homemade parallel cable
34444: 01/08/24: Spartan II JTAG configuration
34858: 01/09/11: Re: Spartan II JTAG configuration
37649: 01/12/18: WebPack blows up CPLDs?
38938: 02/01/28: Spartan-2E data sheet (ds077_x.pdf)
39473: 02/02/11: Spartan Program/Verify
39513: 02/02/12: Re: Spartan Program/Verify
39535: 02/02/12: Re: Spartan Program/Verify
39827: 02/02/20: KEEP constraints on std_logic_vector
39895: 02/02/21: Re: FPGA: JTAG CABLE
51678: 03/01/18: Re: Support for older Virtex
58841: 03/08/02: Re: Design fits XC9536 but not XC9536XL
58842: 03/08/02: Re: Design fits XC9536 but not XC9536XL
59224: 03/08/12: Re: Design fits XC9536 but not XC9536XL
<aarodriguez@amper.es>:
81716: 05/03/30: Program flash memory XC18V01 from FPGA
Aaron:
76180: 04/11/27: Disable Global Buffer
100660: 06/04/14: C# and Spartan 3 Starter Kit
115762: 07/02/19: How to get the area/time results without IO mapping
146711: 10/03/26: Re: Xilinx Spartan6 Virtex6 Rollout
aaron:
41412: 02/03/27: Re: Core Generator and Modelsim XE
49455: 02/11/12: Re: HDL vs RTL
49456: 02/11/12: Re: HDL vs RTL
Aaron A. Cohn:
3808: 96/08/05: !! Semiconductor SuperSite.Net
Aaron Bongard:
31759: 01/06/05: selection of software for xilinx devices
Aaron Chen:
122434: 07/07/27: V5 Differential Select I/O
Aaron Curtin:
110715: 06/10/20: Reversing SPI shift out order on Microblaze design
110973: 06/10/26: OPB to SPI clock frequency ratio
110984: 06/10/26: Re: OPB to SPI clock frequency ratio
110990: 06/10/26: Re: OPB to SPI clock frequency ratio
110992: 06/10/26: Re: OPB to SPI clock frequency ratio
111648: 06/11/07: Microblaze FPU and IEEE754 single precision number format
Aaron Eberhart:
39617: 02/02/14: Create a bit stream (BIT file) from an NCD file?
39618: 02/02/14: Logiblox cells not connected in ISE4.1 HDL project
41425: 02/03/27: Re: Logiblox cells not connected in ISE4.1 HDL project
Aaron Ferrucci:
671: 95/02/02: Re: "on-fly" reprogrammable devices/research
70586: 04/06/21: Re: C Header files for User Design Logic in the Nios.
70700: 04/06/23: Re: C Header files for User Design Logic in the Nios.
Aaron Holtzman:
8582: 98/01/10: Xilinx PCI cores
26034: 00/10/01: Re: FPGA development on the cheap?
148132: 10/06/22: Re: Xilinx BULLSHITIX-8, when?
148233: 10/06/30: Re: Xilinx BULLSHITIX-8, when?
Aaron Nabil:
31497: 01/05/28: Want to buy: Old copy of ABEL, Synario or ViewPLD
31524: 01/05/29: Re: Want to buy: Old copy of ABEL, Synario or ViewPLD
Aaron Quantz:
5387: 97/02/12: Re: Serial Communication Controller Design
5486: 97/02/19: Re: Xilinx or Altera?
6041: 97/04/07: Re: Pentium Pro Worth it for Altera Max Plus?
6510: 97/05/29: Re: VHDL PCI FPGA Implementation
7258: 97/08/19: Re: MaxPlusII from Altera.
7508: 97/09/18: Re: 6809 discontinued
7888: 97/10/27: Re: Internal tri-state emulation.
Aaron Robins:
3347: 96/05/17: *Prototyping* <?>
Aaron Spink:
5319: 97/02/06: Re: DES Challenge
Aaron T. Smith:
3010: 96/03/13: ORCA Fpgas
Aaron Wohl:
922: 95/03/30: FAQ/getting started/cheap?
aaron123:
148655: 10/08/13: How to use VIO and core inserter at the same time.
148664: 10/08/16: Re: How to use VIO and core inserter at the same time.
148671: 10/08/17: Re: How to use VIO and core inserter at the same time.
148695: 10/08/17: Re: How to use VIO and core inserter at the same time.
<aaronburgess@ieee.org>:
18119: 99/10/01: Implementing a LFSH in Xilinx XC9500 series
<AaronDBenson@gmail.com>:
98335: 06/03/08: Connect USB device to Spartan 3 FPGA
Aart van Beuzekom:
59096: 03/08/08: Upgrading OS or WebPack
59160: 03/08/11: Re: Upgrading OS or WebPack
59334: 03/08/15: Re: Upgrading OS or WebPack
60109: 03/09/05: Writing a Xilnx testbench
61118: 03/09/29: Counting ones
61119: 03/09/29: Re: Counting ones
61131: 03/09/29: Re: Counting ones
61201: 03/09/30: Re: Counting ones
61202: 03/09/30: Re: Counting ones
Aarul Jain:
73056: 04/09/13: Newbie question systemc
73351: 04/09/20: Re: Newbie question systemc
73389: 04/09/21: Re: Newbie question systemc
Aashish Malhotra:
103828: 06/06/12: Re: PCI Express - Root Complex ?
104121: 06/06/19: Re: PCI Express - Root Complex ?
105367: 06/07/20: Re: PCIe: use 8*x1 PHY devices to form x8
aayush:
97387: 06/02/21: Communication between FPGA and PC with ethernet card
97775: 06/02/27: communication b/w ethernet and fpga
Ab Ran:
58636: 03/07/29: DCM delays in the TRCE report.
58668: 03/07/30: Re: DCM delays in the TRCE report.
abbas:
137832: 09/01/30: LUT design / Transmission gates or pass transistors?
Abbes Amira:
70764: 04/06/27: Short Course by Dr. Abbes Amira:Accelerating Matrix Algorithms on Reconfigurable Hardware for Image and Signal Processing Applications
Abbs:
91975: 05/11/18: synthesis
92038: 05/11/20: Re: synthesis
92076: 05/11/21: Re: synthesis
92800: 05/12/07: VERIFICATION AND TESTING
92868: 05/12/08: Re: VERIFICATION AND TESTING
93126: 05/12/14: Re: VERIFICATION AND TESTING
Abby:
60173: 03/09/06: VGA display
60179: 03/09/07: Re: VGA display
60299: 03/09/10: Re: VGA display
60300: 03/09/10: Re: VGA display
60301: 03/09/10: Re: VGA display
154330: 12/09/30: Need Terasic LTM Module
Abby Brown:
145684: 10/02/18: Re: using an FPGA to emulate a vintage computer
145691: 10/02/18: Re: using an FPGA to emulate a vintage computer
145728: 10/02/21: Re: using an FPGA to emulate a vintage computer
146820: 10/03/29: Free VHDL or Verilog Simulator
146930: 10/04/02: Re: Free VHDL or Verilog Simulator
151189: 11/03/14: Alternative To Altera's Cyclone III Starter Board
151340: 11/03/25: Re: Alternative To Altera's Cyclone III Starter Board
ABC:
103410: 06/06/01: rise/fall clock edge constraint
111572: 06/11/06: Re: Formal Logic Equivalent Check (LEC)
112931: 06/12/01: Re: Can I see the detail timing parameter by Quartus II tools?
ABCDEF:
67531: 04/03/13: Re: ANN: new Pulsonix version 3 PCB software released
67535: 04/03/13: Re: ANN: new Pulsonix version 3 PCB software released
abd_elhamid_:
158022: 15/07/10: Calculate dynamic power at fmax in Quartus
Abdar Kerpal:
23115: 00/06/14: PAR Times for XILINX Foundation Express Student Edition 1.5
23122: 00/06/14: Re: PAR Times for XILINX Foundation Express Student Edition 1.5
23138: 00/06/15: Re: PAR Times for XILINX Foundation Express Student Edition 1.5
Abdelhak Zoubir:
3128: 96/04/09: Available Research Assistant positions
3588: 96/07/02: ISSPA 96
Abdelmajid:
71106: 04/07/08: runing a bootloader on a Virtex II Pro Board???
abdsamad benkrid:
29310: 01/02/13: test
Abdul Nizar:
66441: 04/02/19: Multiple PicoBlaze/Bus access
Abdul S Khan:
23174: 00/06/16: 386 Chipset Example
Abdulla873:
157682: 15/01/27: Instantiating Components or Using Generate statements
157683: 15/01/27: Re: Send a pulse across clocks
AbdulMoeed:
53271: 03/03/09: Re: VHDL & FPGA Design tools
abdulqadir alaqeeli:
18315: 99/10/14: Virtex Board
AbdulraHman Lomax:
11569: 98/08/24: Re: professional autorouters
11576: 98/08/25: Re: professional autorouters
abe:
136478: 08/11/18: opinion about various code generators
136495: 08/11/19: Re: USB JTAG
abeaujean@gillam-fei.be:
84089: 05/05/12: Re: High radix multiplier
86388: 05/06/27: Spartan ii Slave Serial programming
88684: 05/08/25: Altera ByteBlaster II vs ByteBlaster MV
88964: 05/09/01: Strange behaviour while trying to program MAX II CPLD's
89077: 05/09/05: Reprogramming one MAXII EPM1270 vs security bit set
89941: 05/09/30: Re: vhdl state maching problem
91859: 05/11/15: Rise time/fall time for Spartan3 clock inputs
91863: 05/11/15: Re: Rise time/fall time for Spartan3 clock inputs
91895: 05/11/16: Re: Rise time/fall time for Spartan3 clock inputs
91896: 05/11/16: Re: Rise time/fall time for Spartan3 clock inputs
Abednego:
21158: 00/03/08: ModelSim 2.1i ?
Abernathey Family:
45428: 02/07/23: Re: spiral / waterfall /watersluice : Which are your methods?
<abgoyal@gmail.com>:
86819: 05/07/07: Re: EDK 6.3, Xilinx ML40x ML402, XBD files
87132: 05/07/16: virtex 4 configuration error
88745: 05/08/27: infering a BRAM block for a dual ported ROM
88843: 05/08/29: Re: infering a BRAM block for a dual ported ROM
93121: 05/12/14: Re: ISE WebPack 8.1i
95169: 06/01/21: EDK 8.1, Finally!
95179: 06/01/21: Re: EDK 8.1, Finally!
96520: 06/02/05: Re: VGA and framebuffer interface (Waste of BlockRAM)
<abhayjoshi@my-dejanews.com>:
11276: 98/08/01: ASIC DESIGN Services/Manpower/Consultancy Available - Anybody keen ?
11398: 98/08/10: Looking for a Sr. ASIC DESIGN Engineer / Consultant
Abhi:
124218: 07/09/14: add_file -verilog +define ..... filename.v
130207: 08/03/17: Xilinx interview questions
abhi:
89890: 05/09/29: CPLD program editing
Abhijeet:
36046: 01/10/26: Synplicity Ver. 7.0 Mapper Error
Abhijeet A Chachad:
3704: 96/07/18: Re: why? internal error in VSS when simulting
Abhijit:
52792: 03/02/21: Re: parameters in ANSI-style Verilog port maps
Abhijit K. Deb:
32834: 01/07/10: Re: Problem with resolution functions
Abhijit Patait:
36084: 01/10/28: Re: qpsk clock recovery
Abhimanyu Rastogi:
32790: 01/07/09: FLEX EPF8452A
32937: 01/07/12: ne one knows wat this AHDL code is doing??
33040: 01/07/16: How to set an AHDL query pattern
33642: 01/08/01: Err with this AHDL code
33647: 01/08/01: Re: Err with this AHDL code
33684: 01/08/02: Re: Err with this AHDL code
33914: 01/08/08: Why doesn't DFF stroes the value from the previous clock
33958: 01/08/09: this code doesn't work properly
33999: 01/08/10: Re: newbie help needed
34336: 01/08/21: How does For Loop works in AHDL
34362: 01/08/22: Re: How does For Loop works in AHDL
34368: 01/08/22: Re: How does For Loop works in AHDL
34576: 01/08/29: Urgent Please
34618: 01/08/31: Timing delay problem
Abhinav:
59302: 03/08/14: Modelsim : Error code 3601
Abhinav Kumar:
5968: 97/04/01: Help on file format
Abhishek Ghate:
44394: 02/06/19: Info required on SPI3
abhishek kumar:
144969: 10/01/17: DCM
abhishek tara:
65641: 04/02/03: how to get a vendor id of a pci
<abica@my-deja.com>:
25520: 00/09/13: Re: Accessing internal signals and ports for writing to a file using testbench
abigael:
49722: 02/11/19: switch block architecture for fpga
abilashreddy@yahoo.com:
84431: 05/05/18: Why do VHDL gate level models simulate slower than verilog
abirov:
160191: 17/08/04: Re: minimal HDMI pins to send video ?
160199: 17/08/04: Re: minimal HDMI pins to send video ?
<abirov@gmail.com>:
158369: 15/10/24: ML405 Xilinx ISE 14.7
158370: 15/10/24: ERROR:MapLib:30 - LOC constraint P11 on vga_b_out<1> is invalid: No
158377: 15/10/25: Re: ML405 Xilinx ISE 14.7
158378: 15/10/25: Re: ERROR:MapLib:30 - LOC constraint P11 on vga_b_out<1> is invalid:
158379: 15/10/25: Re: ML405 Xilinx ISE 14.7
158380: 15/10/25: Re: ERROR:MapLib:30 - LOC constraint P11 on vga_b_out<1> is invalid:
158381: 15/10/25: Re: ERROR:MapLib:30 - LOC constraint P11 on vga_b_out<1> is invalid:
158425: 15/11/19: ERROR:HDLParsers:409 .... at left hand side. Please help
158428: 15/11/23: Re: ERROR:HDLParsers:409 .... at left hand side. Please help
158429: 15/11/23: Re: vga in virtex 4
158430: 15/11/23: Re: ERROR:HDLParsers:409 .... at left hand side. Please help
158431: 15/11/23: Re: ML403 board - VGA schematics - wrong pins
158433: 15/11/23: Re: ML403 board - VGA schematics - wrong pins
158565: 15/12/27: Re: ERROR:HDLParsers:409 .... at left hand side. Please help
158575: 16/01/05: hamsterworks + lauriVosandi + X = Error
158578: 16/01/05: Re: hamsterworks + lauriVosandi + X = Error
158581: 16/01/06: Re: hamsterworks + lauriVosandi + X = Error
158588: 16/01/08: Re: hamsterworks + lauriVosandi + X = Error
158597: 16/01/19: Re: hamsterworks + lauriVosandi + X = Error
159237: 16/09/06: Ob Screen Display from video coming from OV7670
159586: 17/01/05: VHDL I2c burst read
159588: 17/01/05: Re: VHDL I2c burst read
159589: 17/01/05: Re: VHDL I2c burst read
159593: 17/01/14: Re: VHDL I2c burst read
159621: 17/01/21: VHDL, how to convert sensor data to Q15
159690: 17/02/03: Re: VHDL, how to convert sensor data to Q15
159692: 17/02/06: Re: VHDL, how to convert sensor data to Q15
159693: 17/02/06: Re: VHDL, how to convert sensor data to Q15
159756: 17/02/24: Master Xilinx FPGA like Jtag bridge.
159757: 17/02/24: Re: Master Xilinx FPGA like Jtag bridge.
159758: 17/02/24: Re: Master Xilinx FPGA like Jtag bridge.
159767: 17/02/25: Re: Master Xilinx FPGA like Jtag bridge.
159879: 17/04/13: Re: Master Xilinx FPGA like Jtag bridge.
160161: 17/06/22: Re: FPGA input pin connection to receive MIPI CSI-2
160189: 17/08/03: minimal HDMI pins to send video ?
160192: 17/08/03: Re: minimal HDMI pins to send video ?
160193: 17/08/03: Re: minimal HDMI pins to send video ?
160198: 17/08/04: Re: minimal HDMI pins to send video ?
160203: 17/08/04: Re: minimal HDMI pins to send video ?
160633: 18/06/06: Stepper motor controller
160672: 18/09/22: Strange thing, my FPGA HDMI output cannot work with cheap chinese
160678: 18/09/25: Re: Strange thing, my FPGA HDMI output cannot work with cheap chinese
160679: 18/09/25: Re: Strange thing, my FPGA HDMI output cannot work with cheap chinese
160682: 18/09/28: Re: Strange thing, my FPGA HDMI output cannot work with cheap chinese
160761: 18/11/18: Re: Strange thing, my FPGA HDMI output cannot work with cheap chinese
160762: 18/11/18: who knows how to make 480P HDMI output in VHDL code ?
161426: 19/08/11: Bayer Pattern to RGB VHDL CODE
161427: 19/08/11: Re: Bayer Pattern to RGB VHDL CODE
161550: 19/11/29: SOS ! Raspberry PI - HDMI - TMDS Hamsterwork HDMI INPUT = not work ?
161551: 19/11/29: Re: SOS ! Raspberry PI - HDMI - TMDS Hamsterwork HDMI INPUT = not
161552: 19/11/29: Re: SOS ! Raspberry PI - HDMI - TMDS Hamsterwork HDMI INPUT = not
161562: 19/11/29: Re: SOS ! Raspberry PI - HDMI - TMDS Hamsterwork HDMI INPUT = not
Ablaz7:
157083: 14/09/27: Re: ICAP attached to Microblaze on Virtex 2-pro..
ableton:
48939: 02/10/27: Communication question : looking for a simple schematic to implement a Biphase mark encoder ?
48940: 02/10/27: Communication question : looking for a simple schematic to implement a Biphase mark encoder ?
48941: 02/10/27: Communication question : looking for a simple schematic to implement a Biphase mark encoder ?
48954: 02/10/28: Communication question : looking for a simple schematic to implement a Biphase mark encoder ?
ABloke:
52377: 03/02/07: Annapolis Microsystems Wildcard
53212: 03/03/06: Re: Annapolis Microsystems Wildcard
62165: 03/10/21: Re: Blocks RAM in HandelC
ABP:
25471: 00/09/12: hardware compatibility and patent infringement
<abp_00@my-deja.com>:
23143: 00/06/15: Work as a freelance FPGA engineer
<abpebmm@ponymail.com3188801885>:
Abraham Henry Vlok:
35065: 01/09/20: Clockin on rising AND falling edge
35072: 01/09/20: Re: Clockin on rising AND falling edge
Abraham Roth:
17205: 99/07/08: fpga 10k50 and up prototype with a/d d/a
abright52:
113497: 06/12/14: Virtex-II Pro: Reading/Writing data with Compact Flash
113649: 06/12/18: Re: Virtex-II Pro: Reading/Writing data with Compact Flash
113650: 06/12/18: Re: Virtex-II Pro: Reading/Writing data with Compact Flash
113796: 06/12/21: Re: Virtex-II Pro: Reading/Writing data with Compact Flash
114265: 07/01/09: Re: Virtex-II Pro: Reading/Writing data with Compact Flash
ABS:
92309: 05/11/27: VLSI Processor Cores
93106: 05/12/13: J Tag Protocol
93167: 05/12/15: Re: J Tag Protocol
97573: 06/02/23: configuring Hardware
97577: 06/02/23: Re: configuring Hardware
Abs:
101184: 06/04/26: Re: Modelsim Simulation
ac:
52146: 03/02/03: Re: Static Timing Analysis
52223: 03/02/04: Re: xilinx virtex II floorplanning
ac-ic:
38163: 02/01/07: I2C/SPI implementation on FPGA
<ac@cd.com>:
11492: 98/08/19: Porn spamming
11603: 98/08/26: Re: Porn spamming
ACA:
6423: 97/05/23: Re: Glitches in timing simulation of Xilinx FPGAs with Synopsys
acbel:
8687: 98/01/20: bypass for 68 pin PLCC
Acceed See:
81687: 05/03/30: Coregen to generate a ROM of 32X1500 using LUT to construct multiplexer.
82461: 05/04/13: Re: CCD and Graphics - which FPGA?
82776: 05/04/18: Re: salary ballpark please guys
82777: 05/04/18: Re: Hobby or job? (FPGA User's groups anyone?)
82871: 05/04/19: How do I convert binary data from Agilent logic analyzer 16702 into plain text?
82878: 05/04/19: What is the cause of a "can not see clock" problem in logic analyser?
82879: 05/04/19: Re: What is the cause of a "can not see clock" problem in logic analyser?
82934: 05/04/20: Some signals became ? and missing on the simvision, why?
83147: 05/04/25: Re: New FPGA Development Board
83204: 05/04/26: Re: New FPGA Development Board
83205: 05/04/26: Re: How do I convert binary data from Agilent logic analyzer 16702 into plain text?
Acci:
86159: 05/06/22: Re: DC vhdl question
Acciduzzu:
70553: 04/06/20: XST: Inferring dual-port RAM from VHDL with BlockRAM
70566: 04/06/21: Re: XST: Inferring dual-port RAM from VHDL with BlockRAM
70612: 04/06/22: Re: XST: Inferring dual-port RAM from VHDL with BlockRAM
acd:
102658: 06/05/18: V5 and carry lookahead
113213: 06/12/08: Re: Recursive component instantiation
114310: 07/01/11: Re: EDIF generation from C
116863: 07/03/20: Wanted: container classes for reconfigurable computing
124197: 07/09/14: Physical Design Contribution to FPGA/CPLD success
124212: 07/09/14: Re: Physical Design Contribution to FPGA/CPLD success
124325: 07/09/18: Population Count circuit
124332: 07/09/18: Re: Population Count circuit
139786: 09/04/13: Low-cost Altera FPGA roadmap
139793: 09/04/14: Re: Low-cost Altera FPGA roadmap
140457: 09/05/13: XML for LUT+FF netlist representation in (academic) tools
153497: 12/03/14: Re: Internal BUS design: MUX or OR-GATE?
153742: 12/05/04: FPGA and Package-on-Package
155672: 13/08/02: Parallella-16 lowest-cost xilinx zynq kit
157041: 14/09/05: Re: Know any good public FPGA projects to contribute to?
ACD:
139402: 09/03/28: partitions and incremental design with xilinx ISE
139403: 09/03/28: Re: Where to find a xc6200 xilinx fpga?
Ace:
116803: 07/03/18: Re: FPGA vs. GPP anyone?
117303: 07/03/27: Confuse on Spartan speed
117304: 07/03/27: Re: is edk 8.1 availabe for download
117349: 07/03/28: Re: Confuse on Spartan speed
117352: 07/03/28: Re: Confuse on Spartan speed
120368: 07/06/05: XILINX IPCore
121648: 07/07/10: SystemC in modeling HW/SW
123548: 07/08/29: Where is Command Reg and Status Reg as mentioned in PCI system architecture (Mindshare) in generated pci32 core?
123611: 07/08/30: Re: Where is Command Reg and Status Reg as mentioned in PCI system architecture (Mindshare) in generated pci32 core?
<ace.shikha@gmail.com>:
100513: 06/04/10: reading vhdl files
acetylcholinerd@gmail.com:
89650: 05/09/21: Xilinx Spartan-3
89652: 05/09/21: Re: Xilinx Spartan-3
89665: 05/09/21: Re: Xilinx Spartan-3
89687: 05/09/22: Re: Xilinx Spartan-3
92927: 05/12/09: XC4VFX12 -- availability?
93245: 05/12/16: How to simulate Virtex-4 PPC, MAC, etc. ?
94113: 06/01/05: Virtex-4 FX12 EMAC with ISE WebPack
AchatesAVC:
132635: 08/06/04: Using ethernet on a Xilnx board (Help appreciated)
132643: 08/06/04: Re: Using ethernet on a Xilnx board (Help appreciated)
Achim Gratz:
2289: 95/11/17: Re: Xilinx Configuration Memory Hacking
2366: 95/11/24: Re: Xilinx Configuration Memory Hacking
2845: 96/02/16: Re: New Reconfigurable Computing Threads.
2861: 96/02/19: Re: New Reconfigurable Computing Threads.
3385: 96/05/23: Re: Evolvable HW
3626: 96/07/05: RE: Sanity check for 100K gate DSP FPGA project
6545: 97/06/02: Re: New Reconfigurable Computing newsgroup?
6565: 97/06/03: Re: New Reconfigurable Computing newsgroup?
6604: 97/06/05: Re: New Reconfigurable Computing newsgroup?
7165: 97/08/08: Re: Price of Serial EPROM is Outrageous - Better Explanation
7569: 97/09/23: Re: Lattice Synario and ISPLSI1048
7719: 97/10/07: Re: FPGA multiprocessors
7775: 97/10/14: Re: I looked up Altera in an Italian dictionary.....
9003: 98/02/13: Re: Why altera CPLDS are slow to power-up?
9031: 98/02/16: Re: Why altera CPLDS are slow to power-up?
9243: 98/03/04: Analog crossbar switch matrix IC?
9460: 98/03/15: [SUMMARY] Analog crossbar switch matrix IC?
10264: 98/05/08: Re: Low power FPGA design
10320: 98/05/12: Re: Low power FPGA design
11010: 98/07/10: Re: high-speed place and route
11027: 98/07/12: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
11029: 98/07/13: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
11073: 98/07/17: Re: Shift Invarient Bit Transform
11248: 98/07/30: Re: Asynchronous Building Blocks?
11660: 98/08/29: Re: CPLD/FPGA software
11676: 98/08/31: Re: CPLD/FPGA software
11752: 98/09/07: Re: Altera 10K20 Register File Implementation??
12723: 98/10/26: Re: gray code counter in a Xilinx fpga???
14256: 99/01/22: Re: Free max+plus ll simulator on win95
14479: 99/02/01: Re: Off topic DRAM/SIMM question....
14683: 99/02/11: Re: Supercomputer uses 280 Xilinx FPGAs
14704: 99/02/12: Re: Xilinx de-compiler
14751: 99/02/15: Re: Xilinx de-compiler
14808: 99/02/18: Re: "Altera FreeCore Library" back on the web
15221: 99/03/15: Re: Possible problem with die shrink of xc4010
15497: 99/03/26: Re: xilinx virtex parallel download from SUN
15812: 99/04/15: Re: Obsolete Xilinx series - how to use them?
15835: 99/04/16: Re: craig
39323: 02/02/06: Pseudorandom Bitstream
39356: 02/02/07: Re: Pseudorandom Bitstream
39407: 02/02/08: Re: Pseudorandom Bitstream
39503: 02/02/12: Re: Pseudorandom Bitstream
39533: 02/02/12: Re: Pseudorandom Bitstream
39550: 02/02/13: Re: Pseudorandom Bitstream
39583: 02/02/13: Re: Pseudorandom Bitstream
39602: 02/02/14: Re: SpartanXL & VHDL -- free software?
39739: 02/02/18: Re: Pseudorandom Bitstream
45961: 02/08/12: Re: Fun FPGA system
46103: 02/08/19: Re: Xilinx tools: which one? Esp. schematic
53849: 03/03/25: Re: Increased Wafer yield by row adjusted placement
53890: 03/03/26: Re: Increased Wafer yield by row adjusted placement
Achlys:
32949: 01/07/12: Xilinx BRAM failures
32967: 01/07/13: Re: Xilinx BRAM failures
33152: 01/07/18: Re: Xilinx BRAM failures
<achomyn@madge.com>:
18280: 99/10/12: Re: Token-Ring MAC in FPGA?
acidocinico:
92930: 05/12/09: re:Job available... 2 projects
-ackNnak-:
28839: 01/01/26: Re: Advice on FPGA board.
28840: 01/01/26: Re: Encryption is supported in new Virtex II but.....
<aclegg1986@googlemail.com>:
123881: 07/09/06: Is it possible to perform gate level simulation on a design without a reset?
123990: 07/09/10: Re: Is it possible to perform gate level simulation on a design without a reset?
123999: 07/09/10: Re: Is it possible to perform gate level simulation on a design without a reset?
acm:
69374: 04/05/09: Re: Easypath question (was "Hard-tocopy" rant)
ACM/PDW Treasurer:
5619: 97/03/01: ISPD-97 Advance Pgm & Registration: (April 14-16, Napa CA)
5703: 97/03/08: ISPD-97 (final week for early registration)
5795: 97/03/16: ISPD-97 (Important Announcement RE Hotel & Registration)
6113: 97/04/13: ISPD-97 Registration FULL
Acquisition Systems:
4407: 96/10/24: New PCI Reconfigurable Hardware available
4761: 96/12/12: Re: ASICs Vs. FPGA in Safety Critical Apps.
<acrawfor29@gmail.com>:
138541: 09/02/26: Re: Fm digital baseband demodulation
138628: 09/03/02: Re: Fm digital baseband demodulation
Acromag Web Surfer:
8400: 97/12/12: Xilinx Configuration Problem
ACS Tran:
11182: 98/07/23: AD: Reading Secured Devices
actela:
73331: 04/09/19: Re: Would flash/antifuse-based vendors be more likely to disclose
73332: 04/09/19: Re: FPGA with PCI interface for video processing?
73333: 04/09/19: How intimidating is Xilinx's EDK?
73534: 04/09/23: Xilinx ISE and Verilog $signed/$unsigned tasks?
ACTELFAE:
6440: 97/05/24: Re: Anyone using Actel software?
Active Tools Corporation:
6380: 97/05/20: Use your networked computers for large scale simulations
Active Tools Inc:
8983: 98/02/12: Software available for parallel execution of CAD software
<acushing@doble.com>:
22357: 00/05/05: Re: Bidirectional bus
Ad:
102153: 06/05/11: Re: sqrt(a^2 + b^2) in synthesizable VHDL?
102157: 06/05/11: Re: sqrt(a^2 + b^2) in synthesizable VHDL?
102245: 06/05/12: Re: JTAG tutorial
102321: 06/05/15: Re: safety critical applications with FPGAs/CPLDs
102330: 06/05/15: Re: pull-ups and jtag questions
102337: 06/05/15: Re: pull-ups and jtag questions
102429: 06/05/16: Re: safety critical applications with FPGAs/CPLDs
102679: 06/05/19: Re: FPGA Configuration Question
Ad Verschueren:
1993: 95/09/29: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
2700: 96/01/25: Re: How Big Chips Will Be Designed In The Not Too Distant Future
2732: 96/01/31: Re: How Big Chips Will Be Designed In The Not Too Distant Future
12721: 98/10/26: Re: Schematic entry?
12775: 98/10/29: Re: Schematic entry?
12847: 98/11/02: Re: Schematic entry?
51585: 03/01/16: Re: SChematic design approach compared to VHDL entry approach
51685: 03/01/19: Re: SChematic design approach compared to VHDL entry approach
51730: 03/01/20: Re: SChematic design approach compared to VHDL entry approach
53024: 03/02/28: Re: IBUF : Pullup Resistors
54851: 03/04/20: Found signed Verilog multiply in Webpack 5.2 ??
54868: 03/04/21: Re: Found signed Verilog multiply in Webpack 5.2 ??
59959: 03/09/02: Re: Complex digital ICs visual simulation?
60143: 03/09/05: Re: Schematic simulation and then FPGA programming?
ada:
97088: 06/02/16: DDR SDRAM Controller
97111: 06/02/16: Re: DDR SDRAM Controller
97184: 06/02/18: Re: DDR SDRAM Controller
97292: 06/02/20: Re: DDR SDRAM Controller
97428: 06/02/22: Re: DDR SDRAM Controller
97459: 06/02/22: Re: DDR SDRAM Controller
98133: 06/03/06: Re: DDR SDRAM Controller
98254: 06/03/07: Re: DDR SDRAM Controller
98643: 06/03/14: Re: DDR SDRAM Controller
98658: 06/03/14: Re: DDR SDRAM Controller
98740: 06/03/15: Re: DDR SDRAM Controller
100438: 06/04/09: Re: DDR SDRAM Controller
<ada_sri@my-deja.com>:
18477: 99/10/26: Looking for ASIC designers
Adam:
59850: 03/08/29: Re: Xilinx Foundation Series F2.1i + win2k
61857: 03/10/14: How to program an XC5210
61894: 03/10/14: Re: How to program an XC5210
64528: 04/01/06: Simulating multi-chip design
64533: 04/01/07: Re: AFX BG560 board
65078: 04/01/20: Re: AFX BG560 board
65886: 04/02/09: Virtex 2 Fastest MUX performance
66608: 04/02/24: Fast Single-ended I/O
72641: 04/08/27: Modelsim: ROM initialisation
72778: 04/09/01: Re: Modelsim: ROM initialisation
76792: 04/12/12: PLLs on biphase mark signals
76861: 04/12/15: Re: PLLs on biphase mark signals
83676: 05/05/05: Re: Newbie VHDL/FPGA question
Adam Anderson:
6881: 97/07/06: Re: Smart Card Design and Interface. How?
Adam Biniszkiewcz:
17714: 99/08/26: F 1.5
Adam Biniszkiewicz:
9732: 98/04/02: Re: Altera Bitblaster or Byteblaster??
10764: 98/06/17: Re: VHDL testbench in Maxplus2
12335: 98/10/09: Re: VHDL'93 in MaxPlus
12334: 98/10/09: Re: VHDL'93 in MaxPlus
Adam Donlin:
22556: 00/05/12: SpartanXL config. via XC18V00?
Adam Elbirt:
7776: 97/10/14: Re: I looked up Altera in an Italian dictionary.....
30017: 01/03/20: RC5 implementations
36284: 01/11/05: Help with Synplify Warning
36294: 01/11/05: Re: Help with Synplify Warning
38370: 02/01/12: Quick question regarding IEEE-TVLSI and IEEE-Computer
45889: 02/08/09: Re: AES (rijndael) Ip core
51080: 02/12/30: Xilinx Gate Counts
94724: 06/01/17: Getting Gate Counts from Quartus
94760: 06/01/17: Re: Getting Gate Counts from Quartus
Adam Goldman:
104142: 06/06/20: Re: Xilinx ISE S/W Install kernel version "mismatch"
Adam Hawes:
27079: 00/11/10: Re: Linux/Unix code to drive Xilinx download cable
37670: 01/12/19: Re: SPI interface in VHDL
Adam J. Elbirt:
6593: 97/06/04: The Advanced FPGA Design Demonstration at DAC
6623: 97/06/06: Re: Actel Designer Series 3.1 and NT 4.0?
7088: 97/07/30: Re: Where is Actel's www?
8834: 98/01/30: Re: VHDL vs schematics
10597: 98/06/04: graphical edif writer
14002: 99/01/06: VHDL Bit String Literals
14280: 99/01/22: Array Usage in VHDL Question
15463: 99/03/24: FPGA Express Synthesis Problem
15483: 99/03/25: Re: FPGA Express Synthesis Problem
15735: 99/04/10: Anyone Use SpeedWave? Help with Simulation Problem
15767: 99/04/12: Re: Viewlogic FPGA Express vs Xilinx FPGA Express....any difference?
15968: 99/04/23: Using Embedded RAM in Xilinx Virtex Chips
15975: 99/04/23: Re: Using Embedded RAM in Xilinx Virtex Chips
15976: 99/04/24: Re: Xilinx FPGA eval board
15980: 99/04/24: Re: Using Embedded RAM in Xilinx Virtex Chips
16390: 99/05/19: Xilinx M1.5 Crash
16393: 99/05/19: Re: Xilinx M1.5 Crash
16395: 99/05/20: Re: Xilinx M1.5 Crash
16411: 99/05/20: Re: Xilinx M1.5 Crash
16418: 99/05/20: Re: Xilinx M1.5 Crash
17369: 99/07/22: Embedded RAM in Virtex Chips
17568: 99/08/10: Re: VHDL OPTIMIZATION FOR FPGA's: (Anyone have suggestions?)
17867: 99/09/14: Re: ACTEL Viewlogic Problem
18037: 99/09/24: Re: Help for viewlogic73!
18706: 99/11/08: Re: PLD Quesiton
18915: 99/11/21: Re: Why not Lucent ORCA FGPAs?
21058: 00/03/04: Xilinx Tools Question
21060: 00/03/05: Re: Xilinx Tools Question
Adam Krolnik:
1820: 95/09/06: ABEL language software
Adam Megacz:
65919: 04/02/10: Acquiring a Pilchard or TKDM board
66409: 04/02/18: Re: Can FPGA bootstrap itself?
69426: 04/05/11: Re: One issue about free hardware
70058: 04/05/31: solderless breadboard + fpga + smt-adaptable socket?
70103: 04/06/02: FPPTA?
70281: 04/06/11: Re: Virtex4: I don't understand their thinking....
72034: 04/08/06: Re: Xilinx Spartan-3 Supply Issues?
72242: 04/08/12: Attention Xilinx: command line tools would be useful [Was: Re:
72771: 04/09/01: Re: Announcing JOLT - Yet Another Xilinx Programming Tool
73753: 04/09/29: Re: Would flash/antifuse-based vendors be more likely to disclose
73084: 04/09/13: Would flash/antifuse-based vendors be more likely to disclose
73258: 04/09/16: Re: Would flash/antifuse-based vendors be more likely to disclose
73310: 04/09/18: Re: Would flash/antifuse-based vendors be more likely to disclose
73311: 04/09/18: Re: Statix II vs. Virtex 4
73093: 04/09/14: Re: Would flash/antifuse-based vendors be more likely to disclose
74553: 04/10/13: Re: JBits and Spartan
74682: 04/10/15: What was the first FPGA?
76729: 04/12/09: Re: Open source FPGA EDA Tools
77765: 05/01/16: asynchronous logic on Actel Axcelerator?
85860: 05/06/17: comp.arch.fpga.<mfr>
85957: 05/06/19: damage Atmel AT40k/AT94k with wrong bitstream?
85958: 05/06/19: Re: comp.arch.fpga.<mfr>
85997: 05/06/20: Re: damage Atmel AT40k/AT94k with wrong bitstream?
86353: 05/06/26: Re: damage Atmel AT40k/AT94k with wrong bitstream?
86801: 05/07/06: for sale: two spartan-3 dev boards, $50 each (normally $100)
89281: 05/09/09: future of antifuse fpgas?
89294: 05/09/11: Re: future of antifuse fpgas?
89335: 05/09/12: Re: future of antifuse fpgas?
89485: 05/09/16: Re: Version Control Software (darcs recommended)
89765: 05/09/25: Re: jbits
89784: 05/09/26: Re: jbits & reverse engineering
90098: 05/10/04: Re: EasyPath, demystified
90108: 05/10/04: Re: EasyPath, demystified
91169: 05/10/31: the wretched state of FPGA marketing literature
91563: 05/11/08: Re: What does the IP in IPCORE stand for? (say "gateware" instead)
95927: 06/01/27: Re: Actel Fusion
95945: 06/01/27: Re: Xilinx ....
95942: 06/01/27: Re: Spartan 3, V4 and reconfig, both static and dynamic
96515: 06/02/05: Re: FPGA ogg Vorbis/Theora player
97118: 06/02/16: state-of-the-art schematic generation? [Was: SCHEMATICS ... ]
100416: 06/04/08: Re: Compiler to FPSLIC
100491: 06/04/10: Atmel FPSLIC
100532: 06/04/11: Re: Atmel FPSLIC
100907: 06/04/20: cheapest board (of any sort) with an Atmel At94k40 FPSLIC on it?
101873: 06/05/08: Re: FPGA-based hardware accelerator for PC
103374: 06/05/31: clockless arbiters on fpgas?
103952: 06/06/15: Re: clockless arbiters on fpgas?
103953: 06/06/15: Re: clockless arbiters on fpgas?
103954: 06/06/15: anybody doing self-timed/asynchronous on post-jbits xilinx parts?
103962: 06/06/15: Re: clockless arbiters on fpgas?
103964: 06/06/15: Re: clockless arbiters on fpgas? [here's how it's done in ASICs]
103966: 06/06/15: Re: clockless arbiters on fpgas? [here's how it's done in ASICs]
103997: 06/06/16: Re: clockless arbiters on fpgas?
103999: 06/06/16: Re: clockless arbiters on fpgas? [here's how it's done in ASICs]
104000: 06/06/16: Re: clockless arbiters on fpgas?
117704: 07/04/07: raggedstone + xc3sprog?
117721: 07/04/08: Re: raggedstone + xc3sprog? (solution and PHY question)
117755: 07/04/09: Re: raggedstone + xc3sprog? (solution and PHY question)
118461: 07/04/26: one extra slipway board from fccm
118990: 07/05/08: Re: FPGA software quality - how low can it go ?!
119571: 07/05/22: Re: Atmel release Metal Programmable Cell Fabric uC ARM9
119862: 07/05/28: Re: Atmel FPSLIC users out there?
122412: 07/07/27: completely open source fpga toolchain
122529: 07/07/30: Re: completely open source fpga toolchain
124885: 07/10/09: Re: Open-Source VHDL Synthesis for FPSLIC?
124886: 07/10/09: Re: Low-level FPGA programming?
125973: 07/11/10: Re: Why dynamic partial reconfiguration is still not there?
Adam Przybyla:
74261: 04/10/06: Re: embedded linux on FPGA?
Adam Sedziwy:
956: 95/04/03: Test
Adam Seychell:
8028: 97/11/10: FPGA basics please ?
8179: 97/11/26: FPGAs for hobbyist, HELP
Adam Zilinskas:
3041: 96/03/19: Re: SYNARIO tool for CPLD and FPGA ?
<adam.taylor@selex-sas.com>:
121442: 07/07/04: Re: Rocket IO clocking
121443: 07/07/04: Re: Rocket IO clocking
121996: 07/07/17: Re: chipscope PLB IBA - how to get meaningful labels on signals?
<adam_hawes@dingoblue.net.au>:
27575: 00/11/29: Virtex bitstream generation
<Adam_Rose@mentor.com>:
110573: 06/10/18: Re: Synopsys's VMM and Mentor's AVM
AdamE:
115389: 07/02/08: Question Regarding Look-Up Tables and Access Time/Levels of Logic
115402: 07/02/09: Re: Question Regarding Look-Up Tables and Access Time/Levels of Logic
116632: 07/03/14: Xilinx Netlist
116697: 07/03/15: Re: Xilinx Netlist
<adamjone@purdue.edu>:
17035: 99/06/26: Virtex JTAG readback
17111: 99/07/01: Re: Virtex JTAG readback
adamk:
144644: 09/12/21: Re: Please help, Xilinx FIFO problem!
<adamou@gmail.com>:
105433: 06/07/22: KASUMI source code in VHDL
AdamRose:
111791: 06/11/10: Re: SystemVerilog not use Mail-box directly in VMM and AVM ?
Adams:
22612: 00/05/13: See if this code can work.
22615: 00/05/14: Re: Altera Schematic
adams:
21953: 00/04/09: JTAG PROBLEM
AdamS:
78027: 05/01/23: What's difference of low/high level driver in Xilinx MicroBlaze?
78058: 05/01/23: Re: What's difference of low/high level driver in Xilinx MicroBlaze?
78127: 05/01/25: What's new in MicroBlaze 3.00a?
78251: 05/01/27: EDK--If I'm not using a vendor's board
78315: 05/01/28: Re: What's new in MicroBlaze 3.00a?
78319: 05/01/29: How to change the font in EDK's text editor?
88735: 05/08/26: Phase Offset in Xilinx DDS Core
88736: 05/08/26: Re: i need some help ASAP !!! (DLL - Spartan-IIE)
88748: 05/08/27: Re: Phase Offset in Xilinx DDS Core
88909: 05/08/31: Re: usb and xc95
88914: 05/08/31: Problems on Xilinx FIR Core
89068: 05/09/04: coe file of Xilinx MAC FIR core??
adarsh:
37551: 01/12/14: Re: Dual-port ram templates
adarsh arora:
53662: 03/03/19: free downloadable VLSI softwares
Adarsh Kumar Jain:
63875: 03/12/07: Can you be more Specific ? My XST User Guide does not say that
63881: 03/12/07: Re: Block RAM simulation VII
64736: 04/01/12: V2Pro Rocket IO Primitive- Parameter and Port Settings
64866: 04/01/15: Virtex 2 Pro : Rocket IO Simulation Problem
64941: 04/01/16: so nobody knows how to simulate Rocket IO using Active HDL ?
64972: 04/01/16: Re: Block RAM
65033: 04/01/19: Rocket IO Transceiver : Loss of Sync Signal Always high
65104: 04/01/20: Re: RocketIO evaluation
65105: 04/01/20: Re: RocketIO evaluation
66283: 04/02/16: Configuring Multiple V2Pros with Same Bitstream
66330: 04/02/17: Re: Configuring Multiple V2Pros with Same Bitstream
66758: 04/02/26: Done Pin Remains Low after JTAG Configuration of V2Pro
66836: 04/02/27: Re: Done Pin Remains Low after JTAG Configuration of V2Pro
67467: 04/03/12: Re: Issues in Rocket I/O
68490: 04/04/06: Some RocketIOs in V2Pro - Output XXXX
68687: 04/04/14: Rocket IO : How to put K Characters on LSB of Output Data
69279: 04/05/04: Stratix - Virtex2Pro Co-Simulation using modelsim !
70159: 04/06/07: Rocket IO Timing Problem : sometimes miss Half Word
70161: 04/06/07: Rocket IO : Sensitivity to RefClk Phase
71199: 04/07/12: Same bitstream files give different behavior.
74566: 04/10/14: ChipScope Pro : Data Samples and No of Trigger Occurences
74567: 04/10/14: Same Bitstream: Different Performance
74569: 04/10/14: Xilinx 6.2sp3: Post Place and Route Modelsim6.0 Simulation Crashes
75995: 04/11/22: Re: RocketIO success?
76314: 04/11/30: Xilinx V2Pro Resource Utilisation Estimation
76316: 04/11/30: 99% Utilisation !
85419: 05/06/09: Re: Can I use a 18k ram as 2 single-port ram?
85427: 05/06/09: Re: Can I use a 18k ram as 2 single-port ram?
85795: 05/06/16: Re: Synplify vs XST...
86133: 05/06/22: FPGAs and JTAG
90033: 05/10/03: Re: Xilinx ISE 7.1i Portability Error
Addie Tang:
8841: 98/02/01: Re: How to design 3-staged pipelined multiplier in VHDL for Xilinx 4000XL
27177: 00/11/14: Re: Synopsys VSS and XilinxCorelib weirdness
44895: 02/07/05: Re: Fixed point arithmetic
Adel:
45066: 02/07/11: What open core MAC to choose?
adetaylor:
39184: 02/02/03: Using Refinate to compare EDIF files and verify/create BOM
adi:
131340: 08/04/20: Re: Virtex 4 DCM problem
<adikisela@gmail.com>:
159417: 16/10/25: Re: Platform Cable USB II in Windows 7 not Found (ISE 13.4)
adiles:
146794: 10/03/29: Great Public and Private undergraduate/graduate schools for Comp Arch
Aditi:
146430: 10/03/17: FPGA's with on-chip PROM?
146630: 10/03/24: PROM for Spartan 6 FPGA
146633: 10/03/24: Re: PROM for Spartan 6 FPGA
146674: 10/03/25: Re: PROM for Spartan 6 FPGA
146731: 10/03/26: Version of Xilinx ISE for Spartan 6 FPGAs
146787: 10/03/28: Re: Version of Xilinx ISE for Spartan 6 FPGAs
146963: 10/04/05: Multi-function pins in Spartan-6
147388: 10/04/25: Spartan 6 FPGA decoupling cap pattern diagram
147439: 10/04/27: Re: Spartan 6 FPGA decoupling cap pattern diagram
149566: 10/11/05: PCI Parallel port detection in XILINX
149584: 10/11/08: Re: PCI Parallel port detection in XILINX
150114: 10/12/14: Xilinx Flash PROM and Config rate for Spartan 6 FPGA
150115: 10/12/14: Xilinx Flash PROM and Config rate for Spartan 6 FPGA
151249: 11/03/17: Reg DCM_CLKGEN primitive for Spartan-6
Aditya:
22915: 00/06/02: Altera
98237: 06/03/07: Re: Asynchronous FIFO design question
Aditya Dua:
61999: 03/10/16: wireless test board
<adityaishwar1994@gmail.com>:
159073: 16/07/25: Re: Xilinx Platform cable USB and impact on linux without windrvr
ADM:
11228: 98/07/28: UK Graduate required as Sales Engineer
<admbarnett@gmail.com>:
130708: 08/03/30: Writing to DDR RAM on Virtex II Pro Board on PLB Bus
admin:
46410: 02/08/28: discrepancies in Xilinx xapp253, DDR SDRAM controller.
47102: 02/09/17: Re: Viewing internal signals during Post route simulation.
48498: 02/10/18: Re: Locating IOBs with shared routing resources in VirtexII.
48499: 02/10/18: Re: Locating IOBs with shared routing resources in VirtexII.
48519: 02/10/18: Job opening for FPGA design engineer
0000-Admin(0000):
1823: 95/09/07: Re: How to: dual port memory
1822: 95/09/07: Re: HW VIDEO ALGORITHMS
1824: 95/09/07: Re: Repost: VHDL Source for 5x5 Image convolver in ORCA FPGA
1826: 95/09/07: Re: Question about intro. Xilinx software
1825: 95/09/07: Re: verilog to fpga ?
1827: 95/09/07: Re: pci board design guide
1828: 95/09/07: Re: SDRAM memory control
1836: 95/09/07: Re: HW VIDEO ALGORITHMS (Dyslexia Strikes Again!)
1861: 95/09/11: Re: Looking for Scan-Path-Insertion-Too
1862: 95/09/11: Re: Looking for Scan-Path-Insertion-Too
Adnan:
109349: 06/09/25: Help required regarding PCI Master core
109397: 06/09/26: Re: Help required regarding PCI Master core
109535: 06/09/28: Re: Help required regarding PCI Master core
109717: 06/10/04: Re: Help required regarding PCI Master core
109755: 06/10/05: Re: Help required regarding PCI Master core
111437: 06/11/02: Re: Help required regarding PCI Master core
111453: 06/11/03: Re: Help required regarding PCI Master core
111686: 06/11/08: Re: Help required regarding PCI Master core
117363: 07/03/29: Regarding connecting two Ethernet Mac Phy
120113: 07/06/01: Regarding multiple write problem in opencores pci bridge
<adnan.aziz@gmail.com>:
91905: 05/11/16: complexity of arithmetic
<adnan.kuleta@gmail.com>:
154390: 12/10/22: Re: USB Cables again
Adolfo Mora:
47076: 02/09/16: ISE 4.2i: Some bugs in ECS, State CAD Modelsim_XE.
adria.bofill:
12013: 98/09/24: shareware
Adrian:
36828: 01/11/21: Viewing generated VHDL
36854: 01/11/21: Re: Viewing generated VHDL
36855: 01/11/21: Creating a jitter free clock
36949: 01/11/27: Re: Creating a jitter free clock
43303: 02/05/18: Re: Driving high speed external devices from an FPGA
43305: 02/05/18: Signal Fan-out
71639: 04/07/26: New WinFilter Digital Filter design freeware tool release available.
71872: 04/08/03: Re: Best tool(s) for filter float->fixed->VHDL flow?
89334: 05/09/13: P&R speed higher than synthesis
147632: 10/05/10: Re: FPGA Compilation Time Windows vs Linux
adrian:
36997: 01/11/28: Re: Creating a jitter free clock
36998: 01/11/28: Re: Creating a jitter free clock
38551: 02/01/17: Too many errors
78754: 05/02/07: xilinx parallel cable IV
78958: 05/02/10: XMD/GBD problems
78969: 05/02/10: Re: XMD/GBD problems
78980: 05/02/10: Re: XMD/GBD problems
79936: 05/02/26: lwip on spartan3
80100: 05/03/01: pin assignment on an expansion module
80465: 05/03/06: Re: pin assignment on an expansion module
80471: 05/03/06: using NET1 external module with a Spartan-3 board
80656: 05/03/09: ethernet core on a xc3s200
80719: 05/03/10: Re: ethernet core on a xc3s200
84657: 05/05/24: using a SDRAM FIFO
89304: 05/09/12: Xilkernel problem
Adrian Aichner:
6783: 97/06/27: Re: Verilog Simulation and Synthesis for FPGA Devices
Adrian Bica:
45557: 02/07/26: Re: ALU in VHDL and a bunch of questions
Adrian Byszuk:
161109: 19/02/03: Re: Open Source Synthesis Tools
161590: 19/12/06: Re: Enabler for New FPGA Companies
Adrian Donegan:
16848: 99/06/14: Seen any good Boundary Scan companies?
16896: 99/06/16: Re: Seen any good Boundary Scan companies?
Adrian Dunn:
16211: 99/05/10: Re: One Sheep Farmer's Impressions of SNUG'99
20198: 00/01/31: Actel proAsic availability, experiences?
26283: 00/10/10: Re: Testing embedded RAMs
26603: 00/10/22: Re: Very Lucrative FPGA Jobs
Adrian Godwin:
1514: 95/07/06: Re: JEDEC File format
Adrian Hey:
30869: 01/05/02: Re: Comparison of FPGA and DSP
Adrian Jansen:
127666: 08/01/05: Re: Where are the LCD or OLED bitmapped displays?
Adrian Knoth:
88412: 05/08/17: Re: Xilinx ISE on remtoe Display
88456: 05/08/18: Re: Two microblaze in EDK
88479: 05/08/19: Re: Two microblaze in EDK
88818: 05/08/29: Re: Two microblaze in EDK
89322: 05/09/12: Re: ISE 7.1i & Linux / reg code question
89323: 05/09/12: Re: Microblaze & Memory DMA operation
89576: 05/09/19: Re: Reprogramming FPGA over PCI???
89598: 05/09/20: Re: ISE 7.1i & Linux / reg code question
89700: 05/09/22: Re: picoblaze IDE for Linux
89727: 05/09/23: Re: Linux USB XUP board
89947: 05/09/30: Re: Preloading SDRAM?
90274: 05/10/07: Re: ise (lin64) and debian
91913: 05/11/16: Re: ISE SP4 installer on Linux
91996: 05/11/18: Re: ISE SP4 installer on Linux
92106: 05/11/22: Xst optimizes almost everything away
92166: 05/11/23: Re: Xst optimizes almost everything away
92167: 05/11/23: Re: Xst optimizes almost everything away
92248: 05/11/24: Re: Xst optimizes almost everything away
92250: 05/11/24: Re: Xst optimizes almost everything away
93269: 05/12/17: Re: rs232 and picoblaze :)
93834: 06/01/01: Re: basic DSP with FPGA
94999: 06/01/20: Re: ISE8.1 on Linux, first impressions
96015: 06/01/28: Re: ISE8.1 on Linux, first impressions
Adrian Mora:
78481: 05/02/01: reading from CF card
Adrian Spilca:
88036: 05/08/07: Re: System Engineering in the R/D World
Adrian Thompson:
6248: 97/05/02: Re: FPGA chip on Khepera robot
11556: 98/08/24: New Evolutionary Electronics Book
11608: 98/08/26: FACTS: Evolutionary Electronics Book
Adriano:
110713: 06/10/20: JTAG pins of the xc2s200E for user I/O
110716: 06/10/20: Re: JTAG pins of the xc2s200E for user I/O
110726: 06/10/20: Re: JTAG pins of the xc2s200E for user I/O
110733: 06/10/20: Re: JTAG pins of the xc2s200E for user I/O
Adrianus:
34157: 01/08/15: fpga with the smallest i/o setup and hold requirement
Adric Frost:
59591: 03/08/22: Re: Win2k service packs for running Xilinx tools
<adubinsky457@gmail.com>:
131434: 08/04/21: Turning off the DLL to run DDR2 at very low frequency
131490: 08/04/22: Re: Turning off the DLL to run DDR2 at very low frequency
<adventleaf@gmail.com>:
99040: 06/03/19: PCI Configuration access and Target State Machine...
99041: 06/03/19: Re: PCI Configuration access and Target State Machine...
adventurer:
135944: 08/10/23: Soft core processor + CAD choose.Again
135972: 08/10/24: Re: Soft core processor + CAD choose.Again
<adwordsmcc@r720.co.uk>:
133494: 08/07/01: Nintendo DS Screenshots / Video Capture
133529: 08/07/02: Re: Nintendo DS Screenshots / Video Capture
133548: 08/07/03: Re: Nintendo DS Screenshots / Video Capture
<adyer@m5.dyer.dhs.org>:
41303: 02/03/25: Re: High speed clock routing
ae:
43354: 02/05/20: Re: Xilinx 4000XLA-8: is 4 stages of logic ok?
43515: 02/05/22: Re: Xilinx 4000XLA-8: is 4 stages of logic ok?
43641: 02/05/28: Timing Analyzer lockups
43649: 02/05/28: Daisy Chain synchronization option
44642: 02/06/25: Re: too hot fpga device
44643: 02/06/25: Re: Xilinx tools under WinXP
44644: 02/06/25: Virtex w/PowerPC cores
46143: 02/08/20: Re: INOUT port
46247: 02/08/22: Re: Want a most simple develop board's design example for Xilinx FPGA(SP-II)?
48806: 02/10/24: Equivalent clock logic?
48871: 02/10/25: Re: What speed grade do I have?
49691: 02/11/19: Re: What combinational logic will produce a falling edge only.
AE:
50543: 02/12/12: READBACK black box...
50830: 02/12/20: XC400XL, Xchecker, and Hardware Debugger
Aedan Coffey:
267: 94/10/10: Re: Any documentation for Xilinx XNF file format?
714: 95/02/15: Re: Synopsys FPGA Compiler
1735: 95/08/21: Re: Simulation not matching lab results
9831: 98/04/08: Re: Xilinx Foundation Express
aeeaee.com.br:
21842: 00/04/03: Re: Virtex bitstreams wanted for compression study
<aejf@bmvr.com>:
aesolutions:
24570: 00/08/14: Re: Help with Xilinx
24571: 00/08/14: this is a test
24573: 00/08/14: Re: this is a test
24574: 00/08/14: Re: this is a reply test
24576: 00/08/14: Re: Help with Xilinx
<afarrahi@my-deja.com>:
20150: 00/01/28: GLSVLSI-2000 Advance Registeration
<aflkjasdl@alfjasdfjs.com>:
7274: 97/08/20: Pamela & Tommy Lee's Secret Sex Tape
<african@hol.gr>:
10748: 98/06/16: Wallace trees
AG:
98397: 06/03/09: Altera PowerPlay Analyser
116000: 07/02/27: Altera PowerPlay Power estimation
agb:
75511: 04/11/08: ISE problems with Linux
148954: 10/09/15: Preventing timing warnings
148974: 10/09/17: Re: Preventing timing warnings
Aggie:
118983: 07/05/08: ML405 LCD
agi:
97020: 06/02/14: Re: Problem of Initial Value in VHDL code
AGIJohnU:
2697: 96/01/25: VHDL Microcontroller Model
agou:
94941: 06/01/19: DDR Memory Access Interfact by Virtex-4 FX12
94946: 06/01/19: Re: DDR Memory Access Interfact by Virtex-4 FX12
94960: 06/01/19: Re: DDR Memory Access Interfact by Virtex-4 FX12
95056: 06/01/20: Matching the UCF files from MIG and ML403 turtoial demo
95864: 06/01/26: Are the Xilinx pcores files not searchable?
95894: 06/01/26: Re: Are the Xilinx pcores files not searchable?
96372: 06/02/02: Source address in IPIC
96376: 06/02/02: IP2IP_Addr in IPIF
96448: 06/02/03: Re: IP2IP_Addr in IPIF
98006: 06/03/02: Device ID of GPIO
104319: 06/06/23: Optimization of Multiplication in FPGA
106670: 06/08/16: Problems about the synthesis(XST)
ah:
55306: 03/05/03: use of DRAM as massive FIFO
57355: 03/06/28: RS422 to I2C Converter
AH:
35736: 01/10/16: open-drain bidirs in xilinx or altera
37276: 01/12/06: IEEE 1149.1 boundary scan and HIGHZ opcode
37277: 01/12/06: Re: IEEE 1149.1 boundary scan and HIGHZ opcode
37278: 01/12/06: ISP via JTAG
37318: 01/12/07: anyone in comp.arch.fpga in irc?
38613: 02/01/19: Re: I2C multiplexer
ahakan:
100195: 06/04/04: done pin didn't go high
100209: 06/04/05: Re: done pin didn't go high
Ahem A Rivet's Shot:
145870: 10/02/26: Re: using an FPGA to emulate a vintage computer
145945: 10/03/01: Re: using an FPGA to emulate a vintage computer
145997: 10/03/02: Re: using an FPGA to emulate a vintage computer
146077: 10/03/05: Re: using an FPGA to emulate a vintage computer
146104: 10/03/05: Re: using an FPGA to emulate a vintage computer
146160: 10/03/07: Re: using an FPGA to emulate a vintage computer
146161: 10/03/07: Re: using an FPGA to emulate a vintage computer
146162: 10/03/07: Re: using an FPGA to emulate a vintage computer
146175: 10/03/07: Re: using an FPGA to emulate a vintage computer
146176: 10/03/07: Re: using an FPGA to emulate a vintage computer
146181: 10/03/07: Re: using an FPGA to emulate a vintage computer
146185: 10/03/07: Re: using an FPGA to emulate a vintage computer
146192: 10/03/08: Re: using an FPGA to emulate a vintage computer
146194: 10/03/08: Re: using an FPGA to emulate a vintage computer
<ahf@watson.ibm.com>:
20676: 00/02/17: GLSVLSI-2000
ahk:
49908: 02/11/25: ModelSim XE v5.6a : missing libswiftpli.dll
Ahmad:
78316: 05/01/28: Quartus II megafunction
Ahmad A.:
18672: 99/11/06: Re: Why DSP in a FPGA?
19061: 99/11/26: HDL editor?
Ahmad Alsolaim:
5078: 97/01/21: FPGA Lab.
15736: 99/04/11: Re: Does any one want to talk about Dynamic Configuration?
15924: 99/04/21: Re: Virtex based PCI cards
16054: 99/04/30: pricess for Xilinx Virtex XV300 and XV800
<ahmad2smile@gmail.com>:
156393: 14/03/27: Re: MapLib:93 - Illegal LOC on symbol "clk.PAD" (pad signal=clk) or
Ahmed:
30972: 01/05/06: Re: Wanted: ISA bus implementation for Xilinx
120350: 07/06/05: Difference between DCM and PMCD
Ahmed Abdelfattah:
152719: 11/10/08: Is it possible to use a remote desktop viewer on NIOS Linux
Ahmed Ablak:
157139: 14/10/17: Handel-C to VHDL
Ahmed Abou El Farag:
7411: 97/09/07: some help
Ahmed H. Hussien:
8199: 97/11/27: need help on FPGA
8200: 97/11/27: Re: I need Help
Ahmed Shihab:
43: 94/08/03: Xact 5.0 users
35106: 01/09/21: Re: Altera 20KE Bus Switching
35543: 01/10/10: Re: Video processing
Ahmed Talaat:
65726: 04/02/05: FPGA architecture
<ahmedablak0@gmail.com>:
158152: 15/08/21: Re: Handel-C to VHDL
<aholtzma@gmail.com>:
88691: 05/08/25: Re: XST Help - Device Utilization Woes
89185: 05/09/07: Re: ISE 64bit question
89863: 05/09/28: Re: Dolby Digital AC-3 Decode on an FPGA - Possible ? Big ?
90160: 05/10/05: evaluation edk in Spartan-3 starter kit
90203: 05/10/06: Re: evaluation edk in Spartan-3 starter kit
90813: 05/10/21: Re: evaluation edk in Spartan-3 starter kit
90883: 05/10/24: Re: evaluation edk in Spartan-3 starter kit
90886: 05/10/24: Re: evaluation edk in Spartan-3 starter kit
91058: 05/10/27: Re: evaluation edk in Spartan-3 starter kit
91878: 05/11/15: ISE SP4 installer on Linux
93935: 06/01/03: Re: S3e starter kits available
94935: 06/01/19: Re: Disabling cross domain checking for Xilinx ISE
108247: 06/09/06: Re: fastest FPGA
109035: 06/09/20: Re: maximum life of FPGA based products ????
116152: 07/03/02: Re: Potential problem in batch files for Xilinx
116156: 07/03/02: Re: Xilinx ISE webpack in Ubuntu?
116762: 07/03/16: Re: Virtex5 LXT and synthesis..
ahosyney:
80693: 05/03/10: New in C to RTL
80769: 05/03/11: Re: New in C to RTL
80881: 05/03/13: I need systemc.h
83618: 05/05/04: Re: Multiply Accumulate FPGA/DSP
130333: 08/03/20: Power Estimation of Microblaze (Power PC) based architectures
130334: 08/03/20: Re: Power Estimation of Microblaze (Power PC) based architectures
130851: 08/04/03: Re: Power Estimation of Microblaze (Power PC) based architectures
Ahren Hartman:
18436: 99/10/24: FPGA Timing Problem
<ahuramazda@my-deja.com>:
19464: 99/12/22: Re: Dumb question springing from a discussion about chess on a chip...
19475: 99/12/23: Re: Dumb question springing from a discussion about chess on a chip...
19479: 99/12/24: Re: Dumb question springing from a discussion about chess on a chip...
19485: 99/12/25: Re: Dumb question springing from a discussion about chess on a chip...
19486: 99/12/25: Re: regular expression matching and parsing in FPGAs (was chess...)
aibk01:
152003: 11/06/21: Verilog Custom Core To Read and Write From RAM
152102: 11/07/07: Re: Verilog Custom Core To Read and Write From RAM
152105: 11/07/07: Re: Verilog Custom Core To Read and Write From RAM
152106: 11/07/07: Re: Verilog Custom Core To Read and Write From RAM
152139: 11/07/13: FSL Problem:Data Return and Use
152150: 11/07/13: Re: FSL Problem:Data Return and Use
152217: 11/07/22: Re: FSL Problem:Data Return and Use
Aida:
122832: 07/08/08: Regional Clock Resources
<aiiadict@gmail.com>:
92771: 05/12/06: Job available... 2 projects
92789: 05/12/06: fpga tutorial?
96860: 06/02/12: schematic capture
96873: 06/02/12: Re: spartan3 starter kit.
96874: 06/02/12: digital logic library by 74xxxx part number?
96877: 06/02/12: Re: digital logic library by 74xxxx part number?
97666: 06/02/25: fpga to 5v ttl logic
97897: 06/03/01: Re: fpga to 5v ttl logic
97903: 06/03/01: Re: fpga to 5v ttl logic
98603: 06/03/13: Re: Soldering SMT/BGA
100319: 06/04/06: gameboy camera to FPGA
103697: 06/06/08: stable, tested 6502 core
103703: 06/06/08: Re: stable, tested 6502 core
106508: 06/08/14: Spartan3 dev board... will USB keyboard work?
112865: 06/11/30: wanted: FPGA programmer
115973: 07/02/26: spartan 3E USB port... use for i/o instead of programming
<aijazbaig1@gmail.com>:
105746: 06/07/31: Problems compiling with ISE Webpack 8.2.01i
105755: 06/07/31: Re: Problems compiling with ISE Webpack 8.2.01i
105803: 06/08/01: Re: Problems compiling with ISE Webpack 8.2.01i
105886: 06/08/02: Re: Problems compiling with ISE Webpack 8.2.01i
106304: 06/08/11: Compiler can't detect std_logic_1164 package
106316: 06/08/11: Re: Compiler can't detect std_logic_1164 package
106347: 06/08/12: Re: Compiler can't detect std_logic_1164 package
106366: 06/08/12: Re: Compiler can't detect std_logic_1164 package
110740: 06/10/20: Inferring block ram in Spartan II with non standard bus sizes
Aiken:
126958: 07/12/06: Re: student requiring assistance :)
126959: 07/12/06: Re: How can I get data from Altera Triple Speed Ethernet (TSE) MAC
131824: 08/05/02: Re: Forking in One-Hot FSMs
131825: 08/05/02: Re: Style for Highly-Pipelined State Machines
132254: 08/05/19: HELP: a Funny asynchronous input design
132277: 08/05/20: Re: HELP: a Funny asynchronous input design
132286: 08/05/20: Re: HELP: a Funny asynchronous input design
132614: 08/06/03: Re: VHDL to Verilog Converter
132615: 08/06/03: Re: using hard tri-mode ethernet MAC and MPMC on virtex 5
132788: 08/06/06: Re: HDL tricks for better timing closure in FPGAs
133050: 08/06/16: Re: FPGA to solve the two most annoying problems on usenet -
136775: 08/12/04: Modelsim warning message
140593: 09/05/19: Re: Sigasi Public Beta: future of VHDL design
<aimsir@hotmail.com>:
15832: 99/04/16: Zero power gals won't wake up on slow input transitions?
15917: 99/04/21: Re: Zero power gals won't wake up on slow input transitions?
Aio:
143078: 09/09/18: Re: FPGA for acoustic adaptive beamforming
143081: 09/09/18: Re: FPGA for acoustic adaptive beamforming
<air_bits@yahoo.com>:
91253: 05/11/02: FPGA C Compiler on sourceforge.net (TMCC derivative)
91271: 05/11/02: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91275: 05/11/02: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91283: 05/11/02: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91285: 05/11/02: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91288: 05/11/02: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91293: 05/11/02: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91294: 05/11/02: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91330: 05/11/03: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91340: 05/11/03: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91341: 05/11/03: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91353: 05/11/03: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91368: 05/11/04: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91371: 05/11/04: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91378: 05/11/04: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91382: 05/11/04: The HLL GUI multi-fpga DIME design environment
91388: 05/11/04: Re: icarus verilog -- look here ...
91406: 05/11/05: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91409: 05/11/05: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91413: 05/11/05: Re: The HLL GUI multi-fpga DIME design environment
91438: 05/11/06: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91553: 05/11/08: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91671: 05/11/10: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
91673: 05/11/10: Re: fpga speed logic/density MIPS/FLOPS as compared to general purpose microprocessors
91674: 05/11/10: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91675: 05/11/10: Re: Is this even true???
91677: 05/11/10: Re: Is this even true???
91680: 05/11/10: Re: Is this even true???
91684: 05/11/10: Re: fpga speed logic/density MIPS/FLOPS as compared to general purpose microprocessors
91685: 05/11/10: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
91686: 05/11/10: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
91691: 05/11/10: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
91692: 05/11/10: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
91693: 05/11/10: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
91696: 05/11/10: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
91700: 05/11/10: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
91701: 05/11/10: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
91706: 05/11/10: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
91707: 05/11/10: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
91711: 05/11/10: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
91712: 05/11/10: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
91742: 05/11/11: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91744: 05/11/11: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
91745: 05/11/11: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91747: 05/11/11: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
airol:
144832: 10/01/07: Add custom Ip to EDK - No result from sw registers
<airtom@gmail.com>:
102522: 06/05/17: disappointing 550Mhz performance of V5 DSP slices
102527: 06/05/17: Re: "disappointing" 550Mhz performance of V5 DSP slices
aisitei:
152136: 11/07/12: FPGA input pin connection to receive MIPI CSI-2
aitan ameti:
19316: 99/12/13: Re: power on reset with FLEX 10K
<aitezaz.abd@gmail.com>:
140406: 09/05/12: 100 Mbps on 1000/100/10 Mbps PHY
140412: 09/05/13: Re: 100 Mbps on 1000/100/10 Mbps PHY
140413: 09/05/13: 100 Mbps on NETFPGA http://netfpga.org
140456: 09/05/13: Re: 100 Mbps on 1000/100/10 Mbps PHY
140657: 09/05/21: 90 degree phase shifted clock for RGMII
AJ:
64935: 04/01/16: Avnet Virtex-II Pro Development Kit Help
64937: 04/01/16: Re: Avnet Virtex II Pro Dvpt board : linux drivers ??
65401: 04/01/27: Re: Avnet Virtex-II Pro Development Kit Help
aj:
91466: 05/11/07: how to map kernel element of FFT to VIRTEX Pro Board
91571: 05/11/08: how to implement Fast Fourier Transform on virtex pro
91961: 05/11/17: Parallel Cable IV not detecting
91980: 05/11/18: Re: Parallel Cable IV not detecting
92144: 05/11/22: Question on 2048 point FFT( Basic)
Aj:
87007: 05/07/12: Observations on passing clock constraints through DCM in Synplify 8.1
87009: 05/07/12: Observations on passing clock constraints through DCM in Synplify 8.1
89636: 05/09/21: Re: XST equivelent for Synplify "synthesis syn_preserve = 1"
Ajack:
30733: 01/04/27: Anyone use Altera PCI developement Kit ?
Ajay:
91600: 05/11/09: Best Case Timing Parameters
91791: 05/11/13: Re: Best Case Timing Parameters
104804: 06/07/06: XPS-Microblaze-Xilkernel
Ajay Roopchansingh:
84030: 05/05/11: Re: Virtex4 running at 360Mhz DDR
<ajbhavana89@gmail.com>:
155915: 13/10/16: Re: draw lines, circles, squares on FPGA by mouse and display on VGA
ajcrm125:
93476: 05/12/22: RTL for Z8000 series CPU?
93527: 05/12/23: Re: RTL for Z8000 series CPU?
93531: 05/12/23: Re: RTL for Z8000 series CPU?
93534: 05/12/23: Re: RTL for Z8000 series CPU?
93542: 05/12/23: Re: RTL for Z8000 series CPU?
93543: 05/12/23: Re: RTL for Z8000 series CPU?
93545: 05/12/23: Re: RTL for Z8000 series CPU?
93566: 05/12/24: Re: RTL for Z8000 series CPU?
93872: 06/01/02: Re: RTL for Z8000 series CPU?
148020: 10/06/14: Killer FPGA Multimedia SoC system found in trash!
ajd:
26875: 00/11/02: cryptography/Block ciphers
26914: 00/11/03: Re: cryptography/Block ciphers
29081: 01/02/05: Re: FPGA board with lots of SRAM?
29082: 01/02/05: Re: Rijndael
29413: 01/02/20: RSA on FPGA
29540: 01/02/26: RE: Rijndael
30311: 01/04/02: Re: Anadigms FPAA
32259: 01/06/21: Re: Searching any 144 pin SO-DIMM module
ajeetha:
106376: 06/08/12: Re: Invoking Cadence NC Sim within Xilinx ISE
Ajeetha:
48347: 02/10/16: Re: PCI simulation model, available as open source
89657: 05/09/21: Re: Modelsim XE, what's the latest version?
95310: 06/01/22: Re: How in Design Compiler disable writing out "Assign" statement into the netlist?
99495: 06/03/25: Re: Verilog Task pass value problem?
99516: 06/03/25: Re: Verilog Task pass value problem?
110538: 06/10/17: Re: Synopsys's VMM and Mentor's AVM
110562: 06/10/17: Re: Synopsys's VMM and Mentor's AVM
Ajeetha Kumari:
57878: 03/07/08: Re: Books
58100: 03/07/14: Re: free downloadable VLSI softwares
68981: 04/04/23: Re: reading files in vhdl
72959: 04/09/09: Re: Initializing memory from a testbench
<ajeetha@gmail.com>:
91149: 05/10/31: Re: hex rep. in VHDL
92050: 05/11/21: Re: Modelsim Verification : Retain FSM state names
92072: 05/11/21: Re: Modelsim Verification : Retain FSM state names
Ajey Patil:
68629: 04/04/10: Help need writing Single Port Block Ram in verilog
68633: 04/04/11: Re: Help need writing Single Port Block Ram in verilog
<ajholme@hotmail.com>:
82420: 05/04/12: Re: State of MAX7000S I/O pins before programming
<ajin1983@gmail.com>:
131231: 08/04/16: Help Need about reconfiguring the PLL with prescale counter n and
Ajit Kurian George:
903: 95/03/27: Need 100 MHz, relatively low power FPGAs
Ajit Mathew:
156310: 14/02/14: Online Hardware Design Competition: Kode Da Circuit
Ajit Oke:
42535: 02/04/26: Spartan II configuration
<ajit_madhekar@my-deja.com>:
20818: 00/02/23: PCI problem
Ajith:
79083: 05/02/13: Re: SATA and RocketIO
ajith.thamara@gmail.com:
123382: 07/08/26: Partial reconfiguration using ICAP
123602: 07/08/30: Re: Partial reconfiguration using ICAP
125952: 07/11/10: System ACE generation
125953: 07/11/10: SystemACE generation
132882: 08/06/09: aurora channel initialization fails
ajithroy:
82383: 05/04/11: Virtex4 rocketio
ajjc:
110982: 06/10/26: Re: Stream cipher
118166: 07/04/18: Re: 80000 Bit Shift Register
121138: 07/06/26: Re: How to choose FPGA for a huge computation?
129816: 08/03/05: Re: verifying UNIFORM using matlab
133435: 08/06/28: Re: Standard forms for Karnaugh maps?
144109: 09/11/11: Re: free software/open source projects and FPGA?
147898: 10/05/31: =?windows-1252?Q?Re=3A_Verifying=2Fcomparing_the_FFT_output_between_Xilin?=
147963: 10/06/04: =?windows-1252?Q?Re=3A_Verifying=2Fcomparing_the_FFT_output_between_Xilin?=
ajpanicker:
110159: 06/10/11: Re: TIG Being Ignored?
147003: 10/04/09: Can Spartan-6 Support M-LVDS ?
<ajpkane@gmail.com>:
156539: 14/04/18: Re: New Lattice FPGAs on 40nm ?
156987: 14/08/13: Re: Professional VHDL Examples?
157205: 14/11/04: Re: USB PHY recommendations
ajv:
146177: 10/03/07: Re: Virtex-4 driving a 5V CMOS
ajwitz:
134641: 08/08/22: Virtex 5 evaluation boards
134822: 08/09/02: Re: Is it possible to do incremental synthesis and placement?
134873: 08/09/04: Re: Is it possible to do incremental synthesis and placement?
AK:
16988: 99/06/22: ProASIC
aka:
128201: 08/01/17: Quartus-II 7.2sp1 and Systemverilog Assertion SVA?
128202: 08/01/17: When will Xilinx Webpack and EDK support Vista/64?
128203: 08/01/17: Re: Basic FPGA question about Reset
akandel:
43528: 02/05/22: Free emulator
Akash Rai:
42183: 02/04/17: Re: FPGA Partioning
akcooper8@gmail.com:
93597: 05/12/25: Re: FPGA : Decimation Filter Implementation
109532: 06/09/27: ISE DDR Memory Controller to write between RAM and FPGA
109561: 06/09/28: Re: ISE DDR Memory Controller to write between RAM and FPGA
109610: 06/09/30: PLB/OPB Bus Access from ISE
109732: 06/10/04: PLB/OPB Bus Access from ISE
<akhailtash@gmail.com>:
94106: 06/01/05: Re: Synplify Pro batch mode
akhar:
42039: 02/04/13: Re: new to fpga's need insight
Akhil:
92656: 05/12/03: Hardware Modeling Verification
122407: 07/07/27: X values in ASIC
122408: 07/07/27: MS 6.2 code coverage report
Akhundov Jafar:
140235: 09/05/05: ISE 11.1 won't work on Fedora 10 32bit
Aki M Suihkonen:
24095: 00/07/26: Re: Variable shifting
30758: 01/04/27: Comparison of FPGA and DSP
30987: 01/05/08: Re: Shannon Capacity
31011: 01/05/09: Re: Shannon Capacity
33316: 01/07/23: Re: a newbie question -- The cost between 3-to-1 MUX and 4-to-1 MUX
38174: 02/01/08: Re: 128 bit compare delay kill me!
Aki Niimura:
40959: 02/03/18: A petition for Synplify's new fature (FPGA synthesis tool)
41511: 02/03/31: Update: A petition for Synplify's new fature (FPGA synthesis tool)
47362: 02/09/24: Installing ISE5.1i (Alliance) on Solaris 7.
50985: 02/12/24: Xilinx Makefile for ISE 5.1i
51155: 03/01/03: Re: Xilinx Makefile for ISE 5.1i
54497: 03/04/11: Too early to throw away Parallel Cable III...
54526: 03/04/12: Re: Too early to throw away Parallel Cable III...
Aki Suihkonen:
42756: 02/05/02: machine constraints for NIOS in gcc?
48482: 02/10/18: Complete control of carry chains on Altera's Mercury/Stratix
akineko:
135119: 08/09/16: Free H/W Co-sim solution (Call for Wiki participation)
135691: 08/10/12: CPU Model for Co-simulation
<akineko@gmail.com>:
80694: 05/03/10: Virtex 4 USER1 ~ USER4 JTAG commands
80725: 05/03/10: Re: Virtex 4 USER1 ~ USER4 JTAG commands
80742: 05/03/10: Re: Virtex 4 USER1 ~ USER4 JTAG commands
Akinori Sugiura:
651: 95/01/28: Question on 22v10 fitting in Warp2
917: 95/03/30: Re: Any suggestions for chips to implement uCode machines?
<akiriwas@gmail.com>:
83115: 05/04/23: Relative number of CLBs
83129: 05/04/24: Re: Relative number of CLBs
83174: 05/04/25: Re: Relative number of CLBs
Akito:
27353: 00/11/19: Xilinx FPGA: SRAM based, but is it dependant upon SEEPROM?
27470: 00/11/23: Xilinx XC4000** Speed Grades
27532: 00/11/28: Re: Xess - XS40-005XL question
27577: 00/11/29: Gates in a typical small MPU
28054: 00/12/20: Methods to speed up timings by hdl?
akohan:
143331: 09/10/02: Virtx 4 and FPGA programming
143332: 09/10/02: Re: Virtx 4 and FPGA programming
143781: 09/10/25: looking for documents.
144070: 09/11/10: order
akshat:
127827: 08/01/08: V5 System Monitor
128205: 08/01/18: CPLD Pad File
129595: 08/02/28: Re: CPLD Pad File
132266: 08/05/19: V4 - VTRX & AVCCAUXRX
133977: 08/07/21: DVI to BT.656
Akshay:
35210: 01/09/25: Handle C
52626: 03/02/17: Generating a sin wave with vhdl
52688: 03/02/19: Re: Generating a sin wave with vhdl
52750: 03/02/20: Re: Generating a sin wave with vhdl
akshay:
137543: 09/01/21: testing a processor
138122: 09/02/06: Re: testing a processor
138401: 09/02/19: generic parameterised coding:passing of parameters
Akshay Athalye:
66911: 04/02/29: RPM of block RAMs
Akshay Eldho Jose:
156556: 14/04/29: Ethernet interfacing
akshay jain:
77351: 05/01/04: Help needed getting started with virtex II pro
akshayvreddy:
144989: 10/01/18: compiler output to fpga.
145062: 10/01/23: Post route simulation warning
akshye:
79677: 05/02/23: Debugging error in VHDL
<akuchlous@gmail.com>:
79616: 05/02/21: Re: BACK to FPGA
79618: 05/02/21: Re: BACK to FPGA
akun:
93725: 05/12/29: FSM goes into invalid state after reset...
akur061:
154070: 12/07/26: MapLib:978 - LUT6 symbol error during Mapping Stage
al:
41819: 02/04/08: bad experience with Xilinx ISE 4.1i and Xilinx hotline suppot
41823: 02/04/08: Re: bad experience with Xilinx ISE 4.1i and Xilinx hotline suppot
46089: 02/08/18: Re: Xilinx iMPACT/Parallel Port programming in Win XP soloution?
46843: 02/09/10: 555 schematic or vhdl for xilinx or other clock circuit ?
46854: 02/09/10: Re: 555 schematic or vhdl for xilinx or other clock circuit ?
AL:
79292: 05/02/16: DNL and INL calculation
79359: 05/02/17: Re: DNL and INL calculation
79360: 05/02/17: Make program stop
79397: 05/02/18: Re: Make program stop
79413: 05/02/18: Re: DNL and INL calculation
79414: 05/02/18: Re: Help on a FPGA design
79425: 05/02/18: Re: DNL and INL calculation
79490: 05/02/19: Re: DNL and INL calculation
79491: 05/02/19: Re: Make program stop
79563: 05/02/20: Re: DNL and INL calculation
79565: 05/02/20: Re: Make program stop
79650: 05/02/22: Re: Make program stop
79660: 05/02/22: Re: Make program stop
79661: 05/02/22: Re: Make program stop
79662: 05/02/22: Re: Make program stop
79663: 05/02/22: Re: Make program stop
79915: 05/02/25: SVF file
80088: 05/03/01: Memory or registers and JTAG
80090: 05/03/01: Re: SVF file
80125: 05/03/01: Re: Memory or registers and JTAG
80921: 05/03/14: XSVF file
80972: 05/03/15: Re: XSVF file
82820: 05/04/18: Problem installing ISE 7.1
82836: 05/04/18: Can't find folder
83102: 05/04/23: playxsvf file501b
83103: 05/04/23: Re: playxsvf file501b
83278: 05/04/26: Re: Instantiate RAM in Spartan3
83541: 05/05/02: Re: Force sequential assigment
83542: 05/05/02: Re: Force sequential assigment
83594: 05/05/03: Re: Force sequential assigment
83595: 05/05/03: Re: Force sequential assigment
Al:
109552: 06/09/28: Re: ISE DDR Memory Controller to write between RAM and FPGA
110420: 06/10/15: Re: Libero 7.2
110427: 06/10/15: Re: SPAM - Re: Platform USB Cable schematic
110508: 06/10/17: Re: more than 90% occupancy in an Actel FPGA
110509: 06/10/17: Re: Libero 7.2
110541: 06/10/17: Re: Newbie : Please give me an idea about programming an FPGA
110544: 06/10/17: Re: Newbie : Please give me an idea about programming an FPGA
110575: 06/10/18: Re: how to implement integrator?
110581: 06/10/18: Re: mapping memory to fpga
110641: 06/10/19: Re: Cheapest FPGA board to study VHDL on
110654: 06/10/19: Re: Meeting Timing Constraint
110655: 06/10/19: Re: An implementation of a clean reset signal
110758: 06/10/21: cross-post: newsgroup servers
111763: 06/11/09: bidirectional bus
111789: 06/11/10: Re: bidirectional bus => mux
112177: 06/11/17: pulse jitter due to clock
112354: 06/11/21: Re: pulse jitter due to clock
112356: 06/11/21: Re: pulse jitter due to clock
112357: 06/11/21: Re: pulse jitter due to clock
112360: 06/11/21: Re: pulse jitter due to clock
112364: 06/11/21: Re: pulse jitter due to clock
112367: 06/11/21: Re: pulse jitter due to clock
112368: 06/11/21: Re: pulse jitter due to clock
112374: 06/11/21: Re: pulse jitter due to clock
112375: 06/11/21: Re: pulse jitter due to clock
112383: 06/11/21: Re: pulse jitter due to clock
112389: 06/11/21: Re: pulse jitter due to clock
112551: 06/11/24: run a counter without a clock
112582: 06/11/25: Re: run a counter without a clock
112583: 06/11/25: Re: run a counter without a clock
112662: 06/11/27: Re: run a counter without a clock
112724: 06/11/28: Re: run a counter without a clock
112726: 06/11/28: Re: run a counter without a clock
112736: 06/11/28: Re: run a counter without a clock
113601: 06/12/18: solder mask for fpga dissipation
113603: 06/12/18: Re: solder mask for fpga dissipation
113605: 06/12/18: Re: solder mask for fpga dissipation
113655: 06/12/19: Re: solder mask for fpga dissipation
114474: 07/01/17: Modelsim: Warning: (vsim-WLF-5000) Log file vsim.wlf currently in
114475: 07/01/17: Re: Modelsim: Warning: (vsim-WLF-5000) Log file vsim.wlf currently
114476: 07/01/17: Re: Modelsim: Warning: (vsim-WLF-5000) Log file vsim.wlf currently
114479: 07/01/17: Re: Modelsim: Warning: (vsim-WLF-5000) Log file vsim.wlf currently
120798: 07/06/17: fitting problem on A54SX72A
120817: 07/06/18: Re: fitting problem on A54SX72A
120820: 07/06/18: Re: fitting problem on A54SX72A
120857: 07/06/19: Re: fitting problem on A54SX72A
Al Arduengo:
25593: 00/09/14: Re: hardware compatibility and patent infringement
Al Clark:
63305: 03/11/19: Small PLD choices
63586: 03/11/26: Re: Quote from Xilinx re: XPLA3
75645: 04/11/11: Re: digital analog conversion
76623: 04/12/07: Verilog Book Recommendation
76630: 04/12/07: Re: Verilog Book Recommendation
76830: 04/12/13: Re: Cyclone device misteriously overheats
76859: 04/12/15: Re: Cyclone device misteriously overheats
76886: 04/12/15: Quartus II Graphic Editor Anomaly?
76902: 04/12/15: Re: Quartus II Graphic Editor Anomaly?
76910: 04/12/15: Re: Quartus II Graphic Editor Anomaly?
77621: 05/01/12: Re: Looking for low-cost protoboards.
77711: 05/01/15: Re: I2C --> SPI or Parallel Port Concentrator
77930: 05/01/20: Quartus Signal Tap problem
78882: 05/02/09: Re: ASIC vs DSP vs FPGA
80219: 05/03/02: [Promo] Danville releases SHARC kit for $199
80854: 05/03/12: Re: [Promo] Danville releases SHARC kit for $199
81905: 05/04/04: Re: [info] Sine generation
86025: 05/06/20: 5 Volt tolerance - Altera
86034: 05/06/20: Re: 5 Volt tolerance - Altera
86075: 05/06/21: Re: 5 Volt tolerance - Altera
87312: 05/07/21: Re: IP-cores for digital audio
87363: 05/07/22: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87584: 05/07/26: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87602: 05/07/27: Re: Best Practices to Manage Complexity in Hardward/Software Design?
89161: 05/09/07: Re: Cyclone conf flash - 25p10 !
89247: 05/09/09: Re: Cyclone conf flash - 25p10 !
89249: 05/09/09: Re: Cyclone conf flash - 25p10 !
89260: 05/09/09: Re: Cyclone conf flash - 25p10 !
89622: 05/09/21: Re: JTAG USB Circuit
94517: 06/01/13: Re: OT: RoHS and Lead?
94609: 06/01/14: Re: OT: RoHS and Lead?
94572: 06/01/13: Re: Don't even get me started on lead,
94608: 06/01/14: Re: Don't even get me started on lead,
96925: 06/02/13: Altera RoHS Irony
96992: 06/02/14: Re: Altera RoHS Irony
97008: 06/02/14: Re: Altera RoHS Irony
97016: 06/02/15: Re: Altera RoHS Irony
97028: 06/02/15: Re: Altera RoHS Irony
99155: 06/03/21: Re: Fixed vs Float ?
99209: 06/03/21: Re: Fixed vs Float ?
136914: 08/12/12: Re: dsp boards with multiple AD channels question
140327: 09/05/08: Re: Can the complex DSP archetecture based on FPGA+DSP be replaced by FPGA
141200: 09/06/11: Re: IF board for fpga?
141542: 09/06/27: Re: IF board for fpga?
143554: 09/10/16: Re: Softcore for ADSP-2181/2191
146453: 10/03/18: Re: FPGA Board and a adc working between 20MHz and 100MHz
152898: 11/10/31: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
152909: 11/10/31: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
152910: 11/10/31: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
152917: 11/11/01: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
152918: 11/11/01: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
156546: 14/04/21: JTAG issues Cyclone V SoC
156551: 14/04/22: Re: JTAG issues Cyclone V SoC
Al Dev:
26598: 00/10/21: CPU Design HOWTO v2.0 - To design, test and manufacture CPUs
Al Gosselin:
76798: 04/12/12: Re: Virtex-II PRO, DDR2 SDRAM, RocketIO
77268: 05/01/02: Re: Altera NIOS II/Stratix II vs Xilinx Products
77269: 05/01/02: Re: Verilog /DIP Switch Question....
77271: 05/01/02: Re: Verilog /DIP Switch Question....
Al Grant:
29283: 01/02/12: Re: double precision floating point arithmetic
29297: 01/02/13: Re: double precision floating point arithmetic
Al Guyer:
1643: 95/08/09: Xilinx FPGAs ---> Xilinx EPLDs
Al Kossow:
145360: 10/02/06: Re: using an FPGA to emulate a vintage computer
145404: 10/02/08: Re: using an FPGA to emulate a vintage computer
145414: 10/02/08: Re: using an FPGA to emulate a vintage computer
Al McCormick:
22729: 00/05/20: Tech: looking for Allpro programming software
Al Momen:
145375: 10/02/07: Re: Databus crossing clock domains with data freeze
Al Sabay:
3482: 96/06/06: wtb Lattice isplsi1048c-70lq
Al Whelan:
4993: 97/01/09: Re: Linux & EDA at Usenix 97
7334: 97/08/28: Re: VHDL Synthesis for Linux?
Al Williams:
39922: 02/02/21: Beginner Altera Questions
39948: 02/02/22: Re: Beginner Altera Questions
39962: 02/02/22: Re: Beginner Altera Questions
40066: 02/02/26: Re: Beginner Altera Questions
40132: 02/02/28: Re: Beginner Altera Questions
40236: 02/03/02: Xilinx WebPack Simulation
40258: 02/03/03: Re: Xilinx WebPack Simulation
42356: 02/04/21: Re: FPGA books and tutorials ....
42822: 02/05/03: Re: Newbie--Where to start learning?
43492: 02/05/22: Re: i need help getting started with fpgas
44046: 02/06/10: Re: Information about FPGA
44125: 02/06/12: Re: virtual ground in Xilinx XC9572 CPLD?
44323: 02/06/17: Re: new to fpga.
44505: 02/06/21: Re: ISE Webpack Basics
45002: 02/07/09: Re: Getting started with FPGAs
45003: 02/07/09: Re: Xilinix or Altera - which dev-board?
45017: 02/07/09: Re: Getting started with FPGAs
45334: 02/07/19: Re: Getting started with WebPACK and Verilog
46171: 02/08/20: Re: Good documentation on CPLD
46482: 02/08/31: Re: Webpack 4.2 Schematic
46490: 02/09/01: Re: Webpack 4.2 Schematic
46491: 02/09/01: Re: Webpack 4.2 Schematic
46574: 02/09/03: Re: Webpack 4.2 Schematic
47292: 02/09/22: Re: Cheap development package for beginner?
47828: 02/10/04: Re: Need advice wiring up a CPLD
48500: 02/10/18: Re: HELP please! creating FPGA for first time
48887: 02/10/25: Re: Just some newbie ISE questions...
49077: 02/10/31: Re: Getting Started: Seeking intro FPGA material
49240: 02/11/05: PLD Project of the Month Experiment
50708: 02/12/17: PLD Project of the Month
52585: 03/02/14: Re: Newbie Starting Places + Books?
57545: 03/07/02: Re: projects for beginners
59128: 03/08/08: Re: I am new and I want to help
Al Zimmerman:
11330: 98/08/05: Re: PCI Core In FPGA
11367: 98/08/06: Re: PCI Core In FPGA
11376: 98/08/07: Re: PCI Core In FPGA
<al.basili@gmail.com>:
123692: 07/09/01: flip-flop enable
al82:
85267: 05/06/07: VirtexII:DCM:CLKFX phase delay
85351: 05/06/08: Re: VirtexII:DCM:CLKFX phase delay
85365: 05/06/08: Re: FPGA/CPLD trend
94664: 06/01/16: Re: Don't even get me started on lead,
94737: 06/01/17: Re: Don't even get me started on lead,
96399: 06/02/03: Re: BGA central ground matrix
107684: 06/08/31: Re: placing addiional caps across existing caps to reduce noise
al912912:
81456: 05/03/23: Re: Problem writing Pinouts on Webpack
81457: 05/03/23: Re: Problem writing Pinouts on Webpack
al99999:
92305: 05/11/26: Virtex 4 Tapped Delay Lines
92316: 05/11/27: Re: Virtex 4 Tapped Delay Lines
92340: 05/11/28: re:Virtex 4 Tapped Delay Lines
92465: 05/11/30: Re: Virtex 4 Tapped Delay Lines
93177: 05/12/15: Digilent SRAM Controller
93185: 05/12/15: Re: Digilent SRAM Controller
93191: 05/12/15: Re: Digilent SRAM Controller
96503: 06/02/05: NMEA Decoder/Display
96662: 06/02/08: Re: NMEA Decoder/Display
96673: 06/02/08: Re: NMEA Decoder/Display
97041: 06/02/15: DDR SDRAM on ML401
99088: 06/03/20: VHDL LUT
100783: 06/04/18: Virtex 4 Unbonded IOB
101084: 06/04/25: Xilinx ML401 Virtex 4 USB Peripheral
101576: 06/05/03: Virtex 4 LX25
101728: 06/05/05: Re: Virtex 4 LX25
101739: 06/05/05: Re: Virtex 4 LX25
101754: 06/05/05: Re: Virtex 4 LX25
105745: 06/07/31: Problem with assigning package pins using PACE
108959: 06/09/19: Avnet LX25 Evaluation Board - USB Problems
111579: 06/11/06: Cypress 68013 - Xilinx FPGA
111645: 06/11/07: Re: Cypress 68013 - Xilinx FPGA
112489: 06/11/23: Re: Cypress 68013 - Xilinx FPGA
<al_ko@web.de>:
119627: 07/05/24: SATA OOB detection with Virtex5
119634: 07/05/24: Re: SATA OOB detection with Virtex5
Ala:
149722: 10/11/20: Re: [O.T.] Audio DAC as AWG (test source)?
aladdinn:
27373: 00/11/20: Re: help
Alain:
12741: 98/10/27: Re: Schematic entry?
13576: 98/12/10: Re: Verilog/FPGA Express Synth Problem
13631: 98/12/15: Re: multi-dimensional arrays and viewlogic
51951: 03/01/27: FSM and XST
52028: 03/01/29: Re: FSM and XST
57509: 03/07/01: Celoxica feedback
58522: 03/07/25: Re: XST fails to recognize FSM with registered outputs
65146: 04/01/21: Re: ISE 6.1 and Win2000 sp4
99207: 06/03/21: Re: Virtex-4 RocketIO and G.709 OTU-2
99700: 06/03/28: Re: Specifying top level generics with XST 7.1
103727: 06/06/09: Re: Good free or paid merge software that edits two similar files?
105059: 06/07/12: Re: Binary Counter Core
115904: 07/02/24: Re: Interfacing to 10Gig ethernet with Xilinx FPGAs
115906: 07/02/24: Re: Interfacing to 10Gig ethernet with Xilinx FPGAs
125868: 07/11/07: Re: did i miss edk 9.2
127445: 07/12/26: TechXclusives from Xilinx
127463: 07/12/27: Re: TechXclusives from Xilinx
129269: 08/02/19: Re: Efficient division algorithm?
130691: 08/03/30: Re: ISE 10.1 - Initial experience
131216: 08/04/15: Re: DOS script file to synthesize a VHDL design
131845: 08/05/03: Re: Using SRL16
131977: 08/05/09: Re: SDIO CRC7 + VCD waves
133864: 08/07/17: Re: XAPP240 - Design Files
133871: 08/07/17: Re: example of counter for chipscope pro generator
133917: 08/07/19: Re: free video course fpga or asic
136649: 08/11/28: Re: Infer Dual Port Block ROM for Xilinx FPGA
alain arnaud:
2393: 95/11/28: Re: Xilinx XACT Windows Version
2404: 95/11/30: Re: Xilinx XACT Windows Version
2445: 95/12/06: Re: CRC-32 implementation
2556: 96/01/02: Verilog simulator for PC
2703: 96/01/25: Re: XILINX XACT 6.0.0 Tools flaky
2752: 96/02/02: Synplify from SYNPLICITY
3004: 96/03/12: Re: Xact6.o too slow
3368: 96/05/21: [ANNOUNCEMENT] Xilinx User's Mailing List
3490: 96/06/10: XUMA Digest #2
3491: 96/06/10: XUMA Digest #3
3555: 96/06/20: Re: XC1765 vs Atmel's AT17C65 Serial EEPROMs
3565: 96/06/25: Re: Atmel AT17C65/128/256 Serial EEPROM Memories.
3587: 96/07/02: XUMA Digest #9
3850: 96/08/09: Re: Xact 6.0.1: memgen
4053: 96/09/06: ViewSynthesis and Xilinx
4199: 96/09/25: XUMA #16
4220: 96/10/01: Re: Viewlogic 4.1 (DOS) mouse alternatives?
4235: 96/10/03: Re: Q on Xilinx/Viewsim macros
4410: 96/10/25: Re: Synplicity vs. FPGA Express
4443: 96/10/30: Re: Synplicity vs. FPGA Express
4605: 96/11/20: POSITION: VHDL ASIC Designer
4639: 96/11/25: Re: AAL5 SAR Design?
5069: 97/01/20: Re: Able to reverse a .JED back to logic?
5290: 97/02/04: Re: Xilinx keys break on fast machines
5691: 97/03/07: A viewlogic story
9140: 98/02/24: Survey - Proto Board for Xilinx FPGA
Alain Arnaud:
15071: 99/03/05: Dynachip
Alain BROISIN:
20751: 00/02/20: Spartan Config
Alain Cloet:
16357: 99/05/18: Onboard JTAG-programming Xilinx CPLD with Found.Series?
16412: 99/05/20: Re: Onboard JTAG-programming Xilinx CPLD with Found.Series?
16852: 99/06/14: Re: Seen any good Boundary Scan companies?
17691: 99/08/24: Re: JTAG 1149 Info
18456: 99/10/25: Basut-error in Foundation F1.5 / JTAG Programmer M.1.5.25
20896: 00/02/25: Re: Using JTAG on XC4k
21063: 00/03/05: Re: JTAG Programmer & Windows 2000
21970: 00/04/10: Re: JTAG programming
23873: 00/07/13: Re: Boundary-Scan Tests with JTAG Technologies Tools
23925: 00/07/15: Re: Boundary-Scan Tests with JTAG Technologies Tools
25331: 00/09/06: Re: 3.3/2.5 voltage regulators
25348: 00/09/07: Re: 3.3/2.5 voltage regulators
25798: 00/09/20: Re: Boundary scan
27976: 00/12/18: Re: JTAG protocol
28685: 01/01/21: Re: About JTAG
Alain RAYNAUD:
5029: 97/01/14: Re: DES Keysearch by FPGA: $10,000 prize
5676: 97/03/06: Re: Reverse Engineering FPGAs
9066: 98/02/18: Re: System Gates and Logic Cells...
<Alain.Chauche@esisar.inpg.fr>:
10863: 98/06/26: synthesis and simulation
<alaincloet@hotmail.com>:
21218: 00/03/10: Checksum CPLD with Foundation Series
Alan:
23872: 00/07/13: Re: Quartus
71160: 04/07/10: Xilinx Place and Route with changing LUT values
75842: 04/11/16: Re: Digital LP filter in multiplier free FPGA
78793: 05/02/08: System Generator: does it support high-level programming?
86091: 05/06/21: Re: FPGA Filter Design
93598: 05/12/25: Re: Xilinix Modular Flow
93959: 06/01/03: Re: Xilinix Modular Flow
93973: 06/01/04: A problem of the Dynamic Partial Reconfiguration
121240: 07/06/28: Re: Xilinx Modelsim XE-III 6.2g no more Systemverilog support?
135959: 08/10/24: Re: Entry Level FPGA Jobs and Outsourcing
136661: 08/11/28: Re: EPLD - FPGA - Is there a difference
148336: 10/07/08: Re: FPGA Video processing board (HDMI).. who makes one?
Alan Calac:
38771: 02/01/24: Re: Altera Nios v2
41547: 02/04/01: Re: powerpc in virtex2pro
42687: 02/04/30: Re: Altera Nios - ptf documentation
42692: 02/04/30: Re: Altera Nios - master/slave peripheral
43390: 02/05/20: Re: Nios 32bit - simulation problem
44507: 02/06/21: Re: Multiple Nios CPU's on Altera PLD?
52766: 03/02/20: Re: Should I choose Xilink or Altera for a small project
70804: 04/06/28: Download Nios II evaluation version today
Alan Chan:
15906: 99/04/20: Xilinx Virtex GCLKs
15929: 99/04/21: Re: Xilinx Virtex GCLKs
Alan Cooney:
2243: 95/11/09: BP Micro and CUPL -- a good start?
2357: 95/11/22: Re: Low Cost Tools
9128: 98/02/23: FS: Universal device programmer
Alan Cunningham:
5452: 97/02/17: Re: Lucent Orcas ...
Alan Donovan:
8034: 97/11/10: Re: FPGA basics please ?
Alan Fitch:
16335: 99/05/17: Re: Synopsys DC & Modelsim
16513: 99/05/26: Re: Synthesis problem
16629: 99/06/01: Re: Printing to picture files
18710: 99/11/09: Re: Problems in Viewlogic's Workview office
20472: 00/02/11: Re: Simulation problem
20473: 00/02/11: Re: Xilinx error message
20474: 00/02/11: Re: ROL VHDL operator.. need help!
22399: 00/05/08: Re: Code request
22489: 00/05/10: Re: Xilinx Student Edition 1.5 License.dat
22536: 00/05/11: Re: Shifting with STD_LOGIC_VECTOR???
23481: 00/06/27: Re: FPGA and ASIC
30750: 01/04/27: Re: XILINX Foundation UCF Problem
30754: 01/04/27: Re: Input Pins and Synthesis
30990: 01/05/08: Re: timing simulation on Modelsim
31177: 01/05/14: Re: Leonardo/Modelsim/Xilinx post synthesis simulation (VHDL)
31234: 01/05/16: Re: Fine phase shift in Virtex2
31235: 01/05/16: Re: Leonardo Spectrum Level 1 vs Level 3
32696: 01/07/05: Re: How to estimate the number of CLBs ?
34870: 01/09/12: Re: LeonardoSpectrum Timing reports
36405: 01/11/08: Re: Hex numbers in VHDL
36457: 01/11/09: Re: Hex numbers in VHDL
36549: 01/11/12: Re: Type of counter
36562: 01/11/12: Re: Type of counter
37514: 01/12/13: Re: How to use the CoreGen hdl code within my source?
37541: 01/12/14: Re: How to use the CoreGen hdl code within my source?
40323: 02/03/05: Re: Array case expression must have a static subtype (VHDL)
40374: 02/03/06: Re: exceeding 2GB limits in xilinx
41285: 02/03/25: Re: SystemC compiler
41985: 02/04/12: Re: regarding synthesis of signal and variable
42273: 02/04/19: Re: regarding synthesis of signal and variable
42703: 02/05/01: Re: synthesis error
42752: 02/05/02: Re: synthesis error
43881: 02/06/05: Re: synthesis issue
46036: 02/08/15: Re: Modelsim VHDL problem
46039: 02/08/15: Re: Modelsim VHDL problem
46154: 02/08/20: Re: Huge discrepanzcy between gate-array and standard cell synthesis
46183: 02/08/21: Re: "Tall Thin Engineer"
46231: 02/08/22: Re: X on bus
46930: 02/09/12: Re: Handel-C: Undeclared identifier: take2
46932: 02/09/12: Re: Handel-C: a bit of a funny 'for loop'
47515: 02/09/27: Re: Virtex2 Block Multiplier: Faster, Faster
48634: 02/10/22: Re: Nios and quartus linux version
48848: 02/10/25: Re: C to verilog
49124: 02/11/01: Re: FDRE inference in Synplify
49485: 02/11/13: Re: buffer ports on lower level VHDL modules
49975: 02/11/27: Re: Asynchronous FIFOs using Handel-C?
50537: 02/12/12: Re: MTBF Calculation
50582: 02/12/13: Re: Suggestions required for Handel-C code
50583: 02/12/13: Re: RPM Using ISE5.1i FloorPlanner
50682: 02/12/17: Re: Internal_Error of ISE 5.1.02i xst F.25.
50713: 02/12/18: Re: Internal_Error of ISE 5.1.02i xst F.25.
50772: 02/12/19: Re: Xilinx 4000 FPGA : ERROR XNFO-11
50821: 02/12/20: Re: How to asynchronously reset a flip-flop?
50822: 02/12/20: Re: 16-bit LFSR
51133: 03/01/03: Re: Latch inferring : Async OR Sync ?
51983: 03/01/28: Re: GNU C for custom processor
52294: 03/02/06: Re: Redhat versions
53619: 03/03/18: Re: Integrating an VHDL component in a project in Handel-C
53745: 03/03/21: Re: Integrating an VHDL component in a project in Handel-C
55270: 03/05/02: Re: [little OT] SystemC
55867: 03/05/22: Re: BC pipelined loop synthesis
57410: 03/06/30: Re: Interfaces in Handelc
57478: 03/07/01: Re: Celoxica DK1 to Xilinx Spartan II
57978: 03/07/11: Re: Quartus warning in NUMERIC_STD.vhd
58062: 03/07/14: Re: Quartus VHDL problem with aggregate and type cast
58109: 03/07/15: Re: Quartus VHDL problem with aggregate and type cast
58904: 03/08/04: Re: Showing my ignorance of VHDL again...
58953: 03/08/05: Re: More VHDL issues..
59003: 03/08/06: Re: More VHDL issues.. with ModelSim
59329: 03/08/15: Re: Problems with ModelSim (Atmel's System Designer)
60875: 03/09/24: Install problem RedHat 7.3 ISE 6.1i - no space available
63152: 03/11/17: Re: ISE5.2 on solaris, can't use promgen
63834: 03/12/05: Re: Different direction buses
64626: 04/01/09: Re: Newbie Question: No Vsim, Vlib etc in my ModelSim
65653: 04/02/04: Re: Passing user-defined types through the port (global variables??)
68516: 04/04/07: Re: Accesing a procedure
68517: 04/04/07: Re: VHDL: Use of literal '1' on an input port ?
68560: 04/04/08: Re: Problems with Quartus 2 v4 under Linux
69651: 04/05/17: Re: Error while simulation with XILINX DCM
70732: 04/06/25: Re: handel-c library file
71876: 04/08/03: Re: [VHDL] Personnal type as port
75281: 04/11/01: Re: Strange XST error in ISE 6.3.02i
75315: 04/11/02: Re: Strange XST error in ISE 6.3.02i
74244: 04/10/06: Re: I need help for Xilinx Demo Board (XC40xx-PC84
75388: 04/11/04: Re: XILINX Webpack VHDL synthesis question (unnecessary MUX infered)
75417: 04/11/05: Re: XILINX Webpack VHDL synthesis question (unnecessary MUX infered)
75855: 04/11/17: Re: ModelSim
77964: 05/01/21: Re: lasy question about VHDL: logic between a bit and a vector
81069: 05/03/17: Re: type states is std_logic_vector(4 downto 0);
118063: 07/04/17: Re: type/subtype definition in entity
134501: 08/08/14: Re: Real port types in VHDL
137348: 09/01/10: Re: spartan 3an usb connection issue
137746: 09/01/28: Re: new source wizard doesn't seem to work.
137801: 09/01/29: Re: new source wizard doesn't seem to work.
137819: 09/01/30: Re: new source wizard doesn't seem to work.
138156: 09/02/08: Re: offtnproblem during ise synthesis
138165: 09/02/08: Re: Is this phase accumulator trick well-known???
138196: 09/02/09: Re: REWARD $$$ Xilinx USB Platform Cable problems
138236: 09/02/10: Re: problem in place and route
138368: 09/02/18: Re: Problem with ModelSim and Xilinx PCIe endpoint block plus simulation
138576: 09/02/28: Re: Fm digital baseband demodulation
138615: 09/03/02: Re: timequest error
138654: 09/03/03: Re: Re-synthesizing with minor changes
138727: 09/03/06: Re: NGDBuild 604 Error while implementing the character generator
138793: 09/03/11: Re: Checking HDL syntax on command line with xilinx tools
139328: 09/03/26: Re: Sysace_fread syntax probleme
139693: 09/04/09: Re: Two stage synchroniser,how does it work?
141097: 09/06/05: Re: Help with Remote debugging ideas.
141923: 09/07/17: Re: Using OPEN in port map
142265: 09/07/31: Re: Using OPEN in port map
142381: 09/08/08: Re: Stale RTL schematic from VHDL in Xilinx ISE 11.1
142736: 09/08/29: Re: Mixed language simulation on the cheap
142959: 09/09/10: Re: ieee.math_real-support in Synplify for Lattice
143458: 09/10/12: Re: Getting started...
143497: 09/10/13: Re: Problem with Black Box in VHDL in ISE 11.2 :: ERROR:NgdBuild:604
145144: 10/01/29: Re: In system memory editor of Altera for Xilinx
145426: 10/02/09: Re: Progrmming a flash connected to a Stratix II GX
145718: 10/02/21: Re: Legal syntax for VHDL expression
145843: 10/02/25: Re: Xilinx XPS crash on Linux
146200: 10/03/08: Re: Some Active-HDL questions
146259: 10/03/10: Re: Some Active-HDL questions
146287: 10/03/10: Re: Translate Error: ngd build 604
146341: 10/03/13: Re: Translate Error: ngd build 604
146552: 10/03/22: Re: Why hardware designers should switch to Eclipse
146608: 10/03/23: Re: Xilinx ISE Tcl Script Error
146629: 10/03/24: Re: Xilinx ISE Tcl Script Error
146695: 10/03/26: Re: Newbie Coding Question
146782: 10/03/28: Re: XST optimization
146831: 10/03/30: Re: Free VHDL or Verilog Simulator
146845: 10/03/30: Re: XST optimization
147474: 10/04/28: Re: I'd rather switch than fight!
147679: 10/05/14: Re: Expecting sequential output, but RTL shows concurrent implementation.
148033: 10/06/15: Re: Simulation error
151925: 11/06/05: Re: verilog task and vhdl
152048: 11/06/28: Re: XST 13.1 explodes with generic of enum type with only one member
152065: 11/06/29: Re: XST 13.1 explodes with generic of enum type with only one member
153331: 12/02/01: Re: Difference between Xilinx isim and modelsim
153339: 12/02/03: Re: Difference between Xilinx isim and modelsim
153340: 12/02/03: Re: Difference between Xilinx isim and modelsim
153376: 12/02/11: Re: Difference between Xilinx isim and modelsim
153825: 12/06/01: Re: Variables, signals: behavioral and post-route simulation
153827: 12/06/01: Re: Variables, signals: behavioral and post-route simulation
153907: 12/06/29: Re: The definition of comnatorial prcess?
153934: 12/07/01: Re: The definition of comnatorial prcess?
153941: 12/07/01: Re: The definition of comnatorial prcess?
153950: 12/07/02: Re: The definition of comnatorial prcess?
154538: 12/11/25: Re: VHDL expert puzzle
154539: 12/11/25: Re: VHDL expert puzzle
154542: 12/11/25: Re: VHDL expert puzzle
155287: 13/06/22: Re: Modelsim ought to be cheaper
157099: 14/10/10: Re: looking for systemC/TLM 2.0 courses
157101: 14/10/12: Re: looking for systemC/TLM 2.0 courses
157140: 14/10/18: Re: looking for systemC/TLM 2.0 courses
157619: 15/01/06: Re: Parallel execution of Systemc code
157630: 15/01/09: Re: Parallel execution of Systemc code
157840: 15/04/12: Re: does anybody use systemc in FPGA flow?
158205: 15/09/13: Re: I am getting errors when i run a systemC Code in edaplayground
Alan Glynne Jones:
30992: 01/05/08: xplaopt.exe - Application error
31052: 01/05/10: 32 bit limit on integers
31286: 01/05/17: Xilinx Coolrunner 100% routable - but the tools aren't
31309: 01/05/18: Re: Xilinx Coolrunner 100% routable - but the tools aren't
31366: 01/05/21: Re: Xilinx Coolrunner 100% routable - but the tools aren't
Alan Gosselin:
45319: 02/07/18: Re: JTAG Analyzer with HP16510
Alan Hall:
16863: 99/06/15: Help with Foundation/Abel
16961: 99/06/20: More help with Foundation
29491: 01/02/23: Is anybody using Quicklogic PCI/FPGA devices?
29509: 01/02/24: Re: Is anybody using Quicklogic PCI/FPGA devices?
63282: 03/11/19: Re: PCI interface with attached PLD
Alan Horton:
25941: 00/09/27: ABEL truth table for 8-1 Mux
25963: 00/09/28: Re: ABEL truth table for 8-1 Mux
25971: 00/09/28: Re: ABEL truth table for 8-1 Mux (The solution)
29027: 01/02/02: Xilinx question
Alan Hu:
23630: 00/07/03: Re: Canadian University
Alan J. Coppola:
40011: 02/02/24: Announce: pdcodes-0.01 Beta Release: CRC code modeling
Alan Langman:
30062: 01/03/22: Re: Spartan-II Evaluation Board
Alan Lee:
30609: 01/04/19: Half-clock problem.
Alan Marshall:
6622: 97/06/06: Re: New Reconfigurable Computing newsgroup?
14098: 99/01/13: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10
14591: 99/02/05: Re: Help for the scientifically-challenged
Alan McKitterick:
40645: 02/03/12: Re: 32-taps FIR !
44782: 02/07/01: re..filter design for fpga
49011: 02/10/29: Re: filters on fpgas
Alan Myler:
96544: 06/02/06: Re: realize pci in fpga
97029: 06/02/15: Re: What is back_annotate?
97078: 06/02/16: Re: WebPACK license (and Quartus Web Edition too).
97443: 06/02/22: Re: state machine and i2c
98235: 06/03/07: Re: Questions about counter in VHDL
98322: 06/03/08: Re: can bus protocol on fpga
98383: 06/03/09: Re: for all those who believe in ASICs....
98449: 06/03/10: Re: can bus protocol on fpga
99595: 06/03/27: Re: Altera IP address?
100459: 06/04/10: Re: Why does Synplify add clock buffers?
103274: 06/05/30: Re: PCI Header types !!!
104631: 06/07/03: Re: Cyclone-II Configuration via a PCI bus
104699: 06/07/04: Re: ASCI to FPGA - require details
104701: 06/07/04: Re: ASCI to FPGA - require details
109138: 06/09/21: Re: Are you ready for Virtex-5? We are...
111022: 06/10/27: Re: Have you experience to program the APA series using FlashPro Lite?
111210: 06/10/31: Re: FPGA's for Ethernet?
111448: 06/11/03: Re: Xilinx ISE Webpack - Any usable simulator for the Linux platform ?
113099: 06/12/06: Re: Clock phase shift
113210: 06/12/08: Re: About Unstable Operation of ACTEL(A3P1000)....
113316: 06/12/11: Re: About Unstable Operation of ACTEL(A3P1000)....
119276: 07/05/16: Re: Global ressource problem
119699: 07/05/24: Re: Actel timing constraints
119726: 07/05/25: Re: Actel timing constraints
121795: 07/07/13: Re: Counter ?
122138: 07/07/20: Re: libero.actel. i need a clock in a non global pin.
Alan Myler (at home):
117873: 07/04/12: Re: how two sine signals are multiplied in VHDL language
Alan Nishioka:
30175: 01/03/27: Re: What's new in Synplify 6.20 than 6.13
30757: 01/04/27: Re: Virtex-E HDL -- Possible to clock register directly from ibuf?
30761: 01/04/27: Re: Setting Pins High
30983: 01/05/07: Xilinx compressed .bit file format
31029: 01/05/09: Re: Synplicity/Quicklogic choosing high drive input
31680: 01/06/02: Re: bitstream compression in Xilinx
31691: 01/06/02: Re: bitstream compression in Xilinx
32355: 01/06/24: Register balancing in FPGA Express
32378: 01/06/25: Re: Register balancing in FPGA Express
32380: 01/06/25: Re: IOB FF in Synplicity
32766: 01/07/08: Re: Shift and Add Multiplier With Signed Numbers
34560: 01/08/29: Re: download bitstream to FPGA
34579: 01/08/29: Re: download bitstream to FPGA
34851: 01/09/11: Re: Open collector outputs
35208: 01/09/25: Re: Xilinx 4.1 software
35673: 01/10/12: How do you program Xilinx XC18V00?
36122: 01/10/30: Re: Autostart Problem SPROM->FPGA
36196: 01/11/01: Re: Synplicity, Xilinx, & unwanted BUFGs
36830: 01/11/21: Re: jtag programming xilinx cpld
37808: 01/12/20: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
38487: 02/01/15: Re: Altera Compiling Error..WHY?????
38993: 02/01/29: Re: Flex10KA vs MAX7000S
39771: 02/02/19: Re: Coolrunner and ISP
39817: 02/02/20: Re: Coolrunner and ISP
39958: 02/02/22: Re: Coolrunner and ISP
41950: 02/04/11: Re: Price List ?
45078: 02/07/11: Re: Deterministic Output?
46167: 02/08/20: Re: need help with the JAM-Player from ALTERA
47019: 02/09/14: Re: Looking for programming algorithm for Xilinx 18v00 family
47382: 02/09/24: Re: Spartan II JTAG reconfiguration bug - workaround
48504: 02/10/18: Re: Size of configuration bitstream for xcv50 (xilinx)
48862: 02/10/25: Re: Xilinx FPGA troubles
57996: 03/07/11: Re: Quartus warning in NUMERIC_STD.vhd
58266: 03/07/18: Re: Altera ByteBlaster Standalone Programming Utility
58970: 03/08/05: Re: retiming with Synplify Pro
60282: 03/09/09: Xilinx clk to out variation
60573: 03/09/16: Re: 'RSVD' pin on V2/V2P
62729: 03/11/05: Re: Linux and FPGA compatibility
64642: 04/01/09: Re: FLASH memory programming with Altera NIOS and same question for Xilinx
65457: 04/01/29: Re: PowerPC and JTAG
65485: 04/01/30: Re: PowerPC and JTAG
65689: 04/02/04: Re: ByteBlaster fails on Windows 98
66504: 04/02/20: Re: Is this a bug in MAP?
75271: 04/10/31: Using Xilinx fpga pins on external connector
75322: 04/11/02: Re: Using Xilinx fpga pins on external connector
75973: 04/11/20: Re: Xilinx EDK - Unable to initialize BRAM in Simulation
91470: 05/11/07: Re: Malloc on PowerPC on VirtexII pro
91625: 05/11/09: Spartan 3e is slower than Virtex 2p
92839: 05/12/07: Re: PLX 9056 application
92957: 05/12/09: Re: First IP-core designed for and tested with Spartan-3E
92965: 05/12/09: Re: First IP-core designed for and tested with Spartan-3E
94463: 06/01/11: Re: Will ISE 8.1 work together with EDK 7.1?
94491: 06/01/12: Re: Will ISE 8.1 work together with EDK 7.1?
94518: 06/01/12: Re: Conflicts between ISE4.2 and win2000 SP4
96587: 06/02/07: Re: Verilog 2's Complement Shifter
98007: 06/03/02: Re: FPGA - software or hardware -2-
98195: 06/03/06: Microblaze multiplier Virtex2pro vs. Spartan3e
98196: 06/03/06: Re: Microblaze multiplier Virtex2pro vs. Spartan3e
98328: 06/03/08: Re: 5v Xilinx development board
99923: 06/03/30: Re: question about Virtex-II Pro program execution time
99978: 06/03/31: Re: hwicap can be used in the virtex4
99980: 06/03/31: Re: Configuration pins on Spartan-3
100106: 06/04/03: Re: PCB Bypass Caps
100510: 06/04/10: Re: Configuration Rate with multiple .bit files
100515: 06/04/10: Re: Configuration Rate with multiple .bit files
100577: 06/04/12: Re: Spartan3E readback, SPI programming
100578: 06/04/12: Re: Problem with Xilinx FTP
100580: 06/04/12: Re: Print FAT table in a compact flash ??????????
100582: 06/04/12: Re: Spartan3E readback, SPI programming
101643: 06/05/04: Re: xst segmentation fault
101664: 06/05/04: Re: CPU resource type
101770: 06/05/05: Anyone use Xilinx ppc405 profiling tools?
101782: 06/05/06: Re: Anyone use Xilinx ppc405 profiling tools?
101787: 06/05/06: Re: Xilinx document timing diagrams?
101852: 06/05/07: Re: Anyone use Xilinx ppc405 profiling tools?
102038: 06/05/09: Re: Anyone use Xilinx ppc405 profiling tools?
102146: 06/05/11: Re: XCFxxP Plaform Flash Device Questions
102171: 06/05/11: Re: XCFxxP Plaform Flash Device Questions
103501: 06/06/04: Re: Asynchronous BRAM input ?
103726: 06/06/09: Re: ppc instruction count
103758: 06/06/10: Re: initialization sequence and auto refresh for sdr-sdram
103760: 06/06/10: Re: initialization sequence and auto refresh for sdr-sdram
103791: 06/06/11: Re: initialization sequence and auto refresh for sdr-sdram
106625: 06/08/16: Re: Xilinx PowerPC run Program out of SDRAM
107092: 06/08/24: Re: Global signal conservation
107946: 06/09/02: Re: Impossible to download WebPACK?
107998: 06/09/03: Re: gpio help...
108714: 06/09/15: Re: microblaze lwip
108722: 06/09/15: Re: microblaze lwip
108740: 06/09/15: Re: microblaze lwip
109002: 06/09/19: Re: Old vs. New FPGAs
109906: 06/10/07: Re: VHDL count error when cascading
110430: 06/10/15: Re: SPAM - Re: Platform USB Cable schematic
110752: 06/10/21: Re: Code synthesizes to one FPGA but not to another?
110753: 06/10/21: Re: Reversing SPI shift out order on Microblaze design
110771: 06/10/21: Re: Where is the XORCY in the synthesised file?
110821: 06/10/23: Re: Data2Mem Error Help on dual PPC system
110875: 06/10/24: Re: Simple multiply in Xilinx?
110888: 06/10/25: Re: Simple multiply in Xilinx?
110923: 06/10/25: Re: tcp/ip
111596: 06/11/06: Re: Global Clocks in Xilinx Virtex-4
111807: 06/11/10: Re: Why 64-bit PLB?
111813: 06/11/10: Re: Why 64-bit PLB?
111840: 06/11/10: Xilinx Chipscope and EDK
112003: 06/11/14: Re: Xilinx platform cable USB
112303: 06/11/19: Re: Spartan-3E slice resources
112353: 06/11/20: Re: What's wrong with my tcl example in Quartus?
112887: 06/11/30: Anyone use Xilinx ppc405 profiling tools?
112976: 06/12/03: Re: EDk and DCM
113028: 06/12/05: Re: Question concerning XAPP224
113033: 06/12/05: Re: How to check high impedance of a RAM with Logic Analyzer
116333: 07/03/07: Re: Query regarding Project.Plz help very urgent
116367: 07/03/07: Re: using XIlinx impact in batch mode to generate EEPROM files
117280: 07/03/27: Re: (Xilinx) OPB watchdog timer fails to release RESET
117323: 07/03/28: Re: (Xilinx) OPB watchdog timer fails to release RESET
117474: 07/04/01: Re: broken mb-gcc -O2 ?
117653: 07/04/05: Re: what is the best practice to exchange data between microblaze softcore and customer hardware writen in VHDL
117801: 07/04/10: Re: Flip Flop problem (asynchronous or synchronous???? )
117879: 07/04/12: Re: how two sine signals are multiplied in VHDL language
117883: 07/04/12: Re: EDK + XMD
118401: 07/04/25: Re: Problem with PowerPC PIT interrupt
118434: 07/04/26: Re: Problem with PowerPC PIT interrupt
118676: 07/05/01: Re: Read 64-bit value over PLB
118857: 07/05/04: Re: ISE Simulator :Does nothing when double click
119244: 07/05/15: Re: Xilinx SD-RAM-Controller (Xilinx EDK 8.2)--problems with xil_printf reading from memory
119543: 07/05/22: Re: PLB behaviours strangely during burst transactions
119591: 07/05/23: Re: PLB behaviours strangely during burst transactions
119950: 07/05/29: Re: JTAG fundamentals question
119951: 07/05/29: Re: JTAG fundamentals question
120057: 07/05/31: Re: Xilinx Seminars in Wiesbaden, Berlin, Hannover
121390: 07/07/03: Spartan-3e JTAG no device id
121396: 07/07/03: Re: Spartan-3e JTAG no device id
121404: 07/07/03: Re: Spartan-3e JTAG no device id
121405: 07/07/03: Re: Spartan-3e JTAG no device id
121407: 07/07/03: Re: Spartan-3e JTAG no device id
121425: 07/07/03: Re: Spartan-3e JTAG no device id
121459: 07/07/04: Re: Spartan-3e JTAG no device id
121488: 07/07/05: SOLVED: Spartan-3e JTAG no device id
121920: 07/07/15: Re: spartan-3e idcode
121936: 07/07/15: Re: spartan-3e idcode
121960: 07/07/16: Re: spartan-3e idcode
121985: 07/07/16: Re: spartan-3e idcode
122764: 07/08/06: Re: xps error never seen before: google reveals nothing; help!
122866: 07/08/08: Re: Write of 64 from PowerPC to my IP conected to the PLB?
123055: 07/08/15: Re: Xilinx PACKER warning bout carry
123976: 07/09/09: Re: Help getting sdram running with EDK.
124174: 07/09/13: Re: Xilinx ISP JTAG progaramming (XCF32P using GPIO from V4FX12)
124181: 07/09/13: Re: Xilinx ISP JTAG progaramming (XCF32P using GPIO from V4FX12)
124415: 07/09/20: Re: Clock boundary crossing
124995: 07/10/15: Re: Newbie,the simplest way to program an FPGA at home?
125229: 07/10/18: Re: xilinx Edititons
126274: 07/11/18: Re: mb-g++ linker script problem 8.2i
127346: 07/12/18: Changes to use lwip 1.2.0 with Xilinx EDK 9.1 or earlier
127858: 08/01/09: Re: Bad micro blaze behaviour during power off
128082: 08/01/14: Re: DCR_INTC usage in EDK - where is SR18804?
128402: 08/01/24: Re: microblaze question
128780: 08/02/06: Re: OPB timer Microblaze
129110: 08/02/14: Re: Microblaze 7.0 on V2pro?
129973: 08/03/11: Re: Making changes to custom IP in EDK
130539: 08/03/26: Re: Places to visit in Amsterdam and Brussells
130602: 08/03/27: Re: Places to visit in Amsterdam and Brussells
130936: 08/04/05: Re: Protecting design from being downloaded on other (similar) FPGA
131141: 08/04/11: Re: high noise/signal in a simple serial to mono dac module
131482: 08/04/22: Xilinx is cancelling the Virtex-E XCV1000E-FG860
131511: 08/04/23: Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860
131522: 08/04/24: Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860
131547: 08/04/24: Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860
131624: 08/04/26: Re: CRC algorithm
131915: 08/05/07: Does anyone have sdio protocol experience?
132056: 08/05/12: sdio controller in fpga
132374: 08/05/23: Re: Software instabilities with EDK 10.01 and PPC405?!??!!!
132992: 08/06/12: Re: chipscope analyzer error
133005: 08/06/12: Re: chipscope analyzer error
134647: 08/08/23: Re: Scripting xsvf generation?
134800: 08/09/01: Re: ED 9.2 too new cygwin error
Alan P. Burke:
7875: 97/10/26: Re: Parallel-Serial Convertors for XC6200
Alan Peter Fitch:
83089: 05/04/23: Re: low budget SystemC to VHDL Compiler?
Alan R Sieving:
621: 95/01/20: Re: NeoCAD Experience
5608: 97/02/28: What to use instead? (was Re: Customizing Viewdraw...)
Alan R. Sieving:
12811: 98/10/30: Re: FPGA Decouple Capacitor values
Alan Randomdude:
77123: 04/12/23: VGA timing
77156: 04/12/26: USB JTAG programmers?
77588: 05/01/11: (d)ram interface
Alan Raphael:
45694: 02/08/01: Re: Xilinx ISE 4.2: UCF file name
45820: 02/08/06: Re: How to use distributed ram/luts ?
45983: 02/08/13: Re: Academics vs 'real' FPGA use
47216: 02/09/20: Functional VHDL Simulation Problem with Xilinx Coregen Async FIFOs
47652: 02/10/01: Re: Where can i buy xilinx fpga online?
48492: 02/10/18: Re: HELP please! creating FPGA for first time
50729: 02/12/18: Re: Power Estimation
51614: 03/01/17: Re: Modelsim crashes
51722: 03/01/20: Re: Virtex 2 FPGA Board ...
52213: 03/02/04: Re: component instantiation in Xilinx
53310: 03/03/10: Re: Using divided clock
Alan Reynolds:
155894: 13/10/13: Re: reset strategy FPGA Igloo
155906: 13/10/15: Re: reset strategy FPGA Igloo
158426: 15/11/19: Re: ERROR:HDLParsers:409 .... at left hand side. Please help
158504: 15/12/04: Re: Simulation vs Synthesis
158860: 16/05/12: Re: Problem with AXI4 Lite in Cyclone V
Alan Weir:
1226: 95/05/18: AT&T FPGA support ftp site
1640: 95/08/09: Clocking methods - which is prefered?
1883: 95/09/15: Is there a reprogramable XC17256D available?
3419: 96/05/28: Re: Xilinx and Viewlogic
3995: 96/08/30: Looking for s/w to generate test vectors
4111: 96/09/11: Re: ORCA and Viewlogic - any good?
4234: 96/10/03: Re: Q on Xilinx/Viewsim macros
4954: 97/01/03: Re: wir2xnf problem with NT 4.0 network
5765: 97/03/13: Re: Xil FPGA: Usage of Multi-purpose pins as I/O
<Alan.Calac@gmail.com>:
86863: 05/07/07: Re: NIOS2 subscription online?
alan@nishioka.com:
141781: 09/07/08: Re: About configuring FPGAs
141813: 09/07/10: Re: pullup
141817: 09/07/10: Re: pullup
141827: 09/07/10: Re: pullup
141828: 09/07/10: Re: pullup
141833: 09/07/11: Re: pullup
141852: 09/07/13: Re: Xilinx Spartan 3 DCM no output!
141878: 09/07/14: Re: pullup
142106: 09/07/24: Re: spartan-3 starter kit board JTAG-usb cable
142107: 09/07/24: Re: Xilinx ISE 11.x lossage
142323: 09/08/04: Re: AES encryption of bitstream - is my design secure?
<alan@nishioka.com>:
88995: 05/09/02: Re: I2C "SCL" line problem
89273: 05/09/09: Re: creating a custom opb bus master
90214: 05/10/06: Re: Xilinx PLB IPIF Master
90271: 05/10/07: Re: Xilinx PLB IPIF Master
90637: 05/10/18: Re: Program FPGA from PowerPC in V2P
90892: 05/10/24: Re: Doubt in using CD22M3494
91093: 05/10/28: Xilinx Microblaze prefill icache
alan_s:
82792: 05/04/18: Altera logic programmer card
<alancanniff@gmail.com>:
136323: 08/11/11: Virtex2pro Dimm slot memory
alangeering:
148308: 10/07/06: FPGA Video processing board (HDMI).. who makes one?
<alanmyler@yahoo.com>:
83898: 05/05/09: Altera Quartus Timing Models
83939: 05/05/10: Re: Altera Quartus Timing Models
84082: 05/05/12: Re: Looking for Rapid prototyping system, ?Quickturn ASIC-Emulator?
<alann@accom.com>:
76802: 04/12/12: Re: PLLs on biphase mark signals
<alanstv@ntlworld.com>:
Alasdair MacLean:
4769: 96/12/13: Re: ASICs Vs. FPGA in Safety Critical Apps.
4794: 96/12/16: Re: ASICs Vs. FPGA in Safety Critical Apps.
7164: 97/08/08: Re: Problems with SDF Backannotation XACTStep6000
7828: 97/10/20: Re: Q: Clocking for address decode/chip select.
8077: 97/11/15: Re: ? State Machine Design
8904: 98/02/06: Re: Can XACT6 run in a NT4 DOS box?
9515: 98/03/20: Re: Looking for space qualified FPGAs/ASICs
13573: 98/12/10: Re: The best PLD?
13724: 98/12/21: Re: Newbie's Xilinx core question
17210: 99/07/09: Re: Benchmark circuits - in VHDL for FPGA
21309: 00/03/16: Re: Difference between FPGA, PLD, CPLD ?
21337: 00/03/17: Re: Actel Design with A42MX36 Help
23674: 00/07/05: Re: BIST in FPGAs?
alasli:
151761: 11/05/15: spartan 3a ethernet
alastair:
72260: 04/08/12: Dual Microblaze System
72288: 04/08/13: Re: Dual Microblaze System
72347: 04/08/16: Re: Dual Microblaze System
72479: 04/08/20: Microblaze Cache
Alastair Allen:
6401: 97/05/21: PhD studentship (UK)
26151: 00/10/05: PhD studentship
alastairallen99:
23790: 00/07/08: PhD studentship: UK
23893: 00/07/14: PhD studentship: Aberdeen, UK
alb:
155592: 13/07/26: serial protocol specs and verification
155595: 13/07/28: Re: serial protocol specs and verification
155597: 13/07/29: Re: serial protocol specs and verification
155611: 13/07/30: Re: serial protocol specs and verification
155612: 13/07/30: Re: serial protocol specs and verification
155639: 13/07/31: Re: serial protocol specs and verification
155640: 13/07/31: Re: serial protocol specs and verification
155651: 13/07/31: Re: serial protocol specs and verification
155653: 13/08/01: Re: serial protocol specs and verification
155660: 13/08/01: Re: serial protocol specs and verification
155670: 13/08/02: Re: serial protocol specs and verification
155671: 13/08/02: Re: serial protocol specs and verification
155673: 13/08/02: Re: serial protocol specs and verification
155680: 13/08/02: Re: serial protocol specs and verification
155695: 13/08/08: [cross-post] vlib, vmap, vcom, how it all works...
155697: 13/08/08: Re: [cross-post] vlib, vmap, vcom, how it all works...
155700: 13/08/10: Re: [cross-post] vlib, vmap, vcom, how it all works...
155701: 13/08/10: Re: [cross-post] vlib, vmap, vcom, how it all works...
155750: 13/08/27: Actel Designer Warning: CMP201: Net drives no load
155756: 13/08/28: Re: Actel Designer Warning: CMP201: Net drives no load
155778: 13/08/30: Re: Actel Designer Warning: CMP201: Net drives no load
155820: 13/09/20: timing closure
155825: 13/09/24: Re: timing closure
155882: 13/10/11: reset strategy FPGA Igloo
155887: 13/10/11: Re: reset strategy FPGA Igloo
155888: 13/10/11: Re: reset strategy FPGA Igloo
155901: 13/10/14: Re: reset strategy FPGA Igloo
155916: 13/10/16: Re: reset strategy FPGA Igloo
155924: 13/10/16: Re: reset strategy FPGA Igloo
155939: 13/10/18: Re: reset strategy FPGA Igloo
155954: 13/10/22: Re: reset strategy FPGA Igloo
155955: 13/10/22: Re: reset strategy FPGA Igloo
155956: 13/10/22: Re: reset strategy FPGA Igloo
155965: 13/10/29: microsemi technical support
155976: 13/11/01: Re: reset strategy FPGA Igloo
156004: 13/11/06: Re: microsemi technical support
156005: 13/11/06: Re: reset strategy FPGA Igloo
156048: 13/11/13: Re: reset strategy FPGA Igloo
156054: 13/11/14: Re: reset strategy FPGA Igloo
156060: 13/11/18: Re: reset strategy FPGA Igloo
156110: 13/11/27: Re: FPGA Cryptosystem
156198: 14/01/17: embedded RAM vs. registers
156226: 14/01/18: Re: embedded RAM vs. registers
156234: 14/01/20: Re: embedded RAM vs. registers
156258: 14/01/25: Re: embedded RAM vs. registers
156326: 14/03/10: license server
156327: 14/03/10: cloud design flow
156329: 14/03/10: Re: license server
156333: 14/03/11: Re: license server
156348: 14/03/13: Re: cloud design flow
156349: 14/03/13: full functional coverage
156351: 14/03/13: Re: cloud design flow
156354: 14/03/17: CoreABC from Microsemi
156355: 14/03/17: [cross-post]path verification
156359: 14/03/18: Re: full functional coverage
156361: 14/03/18: Re: full functional coverage
156364: 14/03/19: license issue on synplify pro AE
156368: 14/03/19: Re: license issue on synplify pro AE
156369: 14/03/19: Re: license issue on synplify pro AE
156370: 14/03/19: Re: full functional coverage
156377: 14/03/20: Re: full functional coverage
156378: 14/03/20: Re: full functional coverage
156389: 14/03/27: [cross-post][long] svn workflow for fpga development
156395: 14/03/28: Re: [cross-post][long] svn workflow for fpga development
156407: 14/03/30: Re: [cross-post][long] svn workflow for fpga development
156408: 14/03/30: Re: [cross-post][long] svn workflow for fpga development
156427: 14/04/04: Re: Tristates in synthesis
156445: 14/04/07: static timing analysis
156452: 14/04/08: Re: [cross-post][long] svn workflow for fpga development
156476: 14/04/09: Re: Soft-Cores processors
156479: 14/04/09: [cross-post] group on systemC language
156482: 14/04/09: synplify_pro check constraints in batch mode
156483: 14/04/09: Re: [cross-post] group on systemC language
156488: 14/04/10: Re: [cross-post] group on systemC language
156499: 14/04/11: Re: static timing analysis
156500: 14/04/11: Re: cloud design flow
156501: 14/04/11: Actel Designer on multiple cores
156511: 14/04/14: Re: cloud design flow
156513: 14/04/14: Re: cloud design flow
156515: 14/04/14: Re: Actel Designer on multiple cores
156517: 14/04/14: more than 58'000 false paths...
156518: 14/04/14: Re: cloud design flow
156525: 14/04/15: Re: more than 58'000 false paths...
156526: 14/04/15: systemC and OSVVM (was: Re: [cross-post] group on systemC language)
156528: 14/04/15: Re: systemC and OSVVM
156529: 14/04/15: how to specify which feature for a license
156547: 14/04/22: Re: more than 58'000 false paths...
156548: 14/04/22: Re: more than 58'000 false paths...
156549: 14/04/22: Re: more than 58'000 false paths...
156554: 14/04/28: unclear tcl error
156584: 14/05/05: Re: unclear tcl error
156650: 14/05/23: Re: Microblaze and MBLite
156655: 14/05/27: Re: Microblaze and MBLite
156661: 14/05/27: Re: Microblaze and MBLite
156792: 14/06/28: [cross-post] dither generator on fpga
156794: 14/06/28: Re: [cross-post] dither generator on fpga
156796: 14/06/29: Re: [cross-post] dither generator on fpga
156798: 14/06/29: Re: [cross-post] dither generator on fpga
156800: 14/06/30: Re: [cross-post] dither generator on fpga
156828: 14/07/06: Re: What use of Python, Perl in FPGA development?
156829: 14/07/06: wishbone bus between two fpgas
156850: 14/07/09: Re: wishbone bus between two fpgas
156857: 14/07/10: Re: wishbone bus between two fpgas
156962: 14/08/08: multicycle path - synplify pro
156963: 14/08/08: Re: multicycle path - synplify pro
156965: 14/08/08: Re: multicycle path - synplify pro
156996: 14/08/14: Re: LVDS problem - Black magic anyone?
156998: 14/08/17: Re: LVDS problem - Black magic anyone?
157088: 14/10/09: looking for systemC/TLM 2.0 courses
157090: 14/10/09: Re: looking for systemC/TLM 2.0 courses
157092: 14/10/09: Re: looking for systemC/TLM 2.0 courses
157096: 14/10/10: Re: looking for systemC/TLM 2.0 courses
157100: 14/10/11: Re: looking for systemC/TLM 2.0 courses
157119: 14/10/14: Re: looking for systemC/TLM 2.0 courses
157159: 14/10/22: [cross-post] verification vs design
157164: 14/10/23: Re: [cross-post] verification vs design
157165: 14/10/23: Re: [cross-post] verification vs design
157166: 14/10/23: Re: [cross-post] verification vs design
157178: 14/10/28: looking for dev kit for ProAsic3
157184: 14/10/28: Re: looking for dev kit for ProAsic3
157195: 14/10/30: Re: looking for dev kit for ProAsic3
157207: 14/11/04: Re: practical experience with GPL IP core in commercial product
157218: 14/11/05: Re: practical experience with GPL IP core in commercial product
157221: 14/11/05: Re: practical experience with GPL IP core in commercial product
157223: 14/11/05: Re: practical experience with GPL IP core in commercial product
157230: 14/11/06: Re: practical experience with GPL IP core in commercial product
157231: 14/11/06: Re: practical experience with GPL IP core in commercial product
157232: 14/11/06: Re: practical experience with GPL IP core in commercial product
157234: 14/11/06: Re: practical experience with GPL IP core in commercial product
157244: 14/11/06: Re: practical experience with GPL IP core in commercial product
157263: 14/11/10: Re: practical experience with GPL IP core in commercial product
157278: 14/11/17: Re: disadvantages of inferring latches
157284: 14/11/17: Re: disadvantages of inferring latches
157318: 14/11/21: Re: Bypass Xilinx flexlm license check
157331: 14/11/24: Re: Bypass Xilinx flexlm license check
157333: 14/11/24: Re: Bypass Xilinx flexlm license check
157339: 14/11/25: Re: Bypass Xilinx flexlm license check
157341: 14/11/25: Re: Bypass Xilinx flexlm license check
157345: 14/11/26: Re: Bypass Xilinx flexlm license check
157346: 14/11/26: Re: Bypass Xilinx flexlm license check
157347: 14/11/26: Re: Bypass Xilinx flexlm license check
157637: 15/01/12: [cross-post] nand flash bad blocks management
157639: 15/01/12: Re: [cross-post] nand flash bad blocks management
157642: 15/01/13: Re: [cross-post] nand flash bad blocks management
157698: 15/02/07: data memory mapping microblaze
157706: 15/02/08: Re: data memory mapping microblaze
157707: 15/02/08: Re: data memory mapping microblaze
157708: 15/02/08: processor core validation
157713: 15/02/11: Re: processor core validation
157966: 15/06/06: hands on experience on SystemC
157971: 15/06/09: Re: hands on experience on SystemC
alba nohi:
53400: 03/03/12: line counter
53404: 03/03/12: Re: RESET --- Synchronous Vs Asynchronous
55149: 03/04/28: Virtex-II Pro misfire?
Albano, David (EXCHANGE:RTP:3H91):
17049: 99/06/28: Re: Virtex JTAG readback
Albert:
40125: 02/02/28: share two months salary with you if you have job information
40302: 02/03/04: Need Help
40361: 02/03/06: Re: share two months salary with you if you have job information
Albert A. Jeno:
6005: 97/04/04: Aptix/Win 95 Incompatible?
Albert Chang:
88383: 05/08/16: Re: Datasheet error in the Altera Cyclone 2C8F256 pindescription
90824: 05/10/21: Re: Altera Gate Delay Simulation
96800: 06/02/10: Re: quartus and VHDL/Verilog libraries
Albert Nguyen:
121197: 07/06/27: Xilinx FPGA to interface to special I/O
121210: 07/06/28: Re: Xilinx FPGA to interface to special I/O
121211: 07/06/28: Re: Xilinx FPGA to interface to special I/O
121212: 07/06/28: Re: Xilinx FPGA to interface to special I/O
121217: 07/06/28: Re: Xilinx FPGA to interface to special I/O
121225: 07/06/28: Re: Xilinx FPGA to interface to special I/O
121259: 07/06/29: Re: Xilinx FPGA to interface to special I/O
122929: 07/08/10: How to locate the internal state machine in timing simulation
122942: 07/08/11: Re: How to locate the internal state machine in timing
122945: 07/08/11: Re: How to locate the internal state machine in timing
122949: 07/08/11: Re: How to locate the internal state machine in timing
122958: 07/08/12: Re: How to locate the internal state machine in timing
Albert Ross:
48639: 02/10/22: Decoupling BF957 Virtex II package
Albert Tsai:
57007: 03/06/20: Reducing synthesize time for state machines
57040: 03/06/21: Re: Reducing synthesize time for state machines
Albert van der Horst:
66488: 04/02/20: Re: Dual-stack (Forth) processors
66500: 04/02/20: Re: Dual-stack (Forth) processors
69881: 04/05/23: Re: Transputer on FPGA
130516: 08/03/26: Re: A Challenge for serialized processor design and implementation
133225: 08/06/21: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
133226: 08/06/21: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
135978: 08/10/24: Re: XMOS XC-1 kits are shipping
138996: 09/03/18: Re: Zero operand CPUs
138997: 09/03/18: Re: Zero operand CPUs
139052: 09/03/19: Re: Zero operand CPUs
139078: 09/03/20: Re: Zero operand CPUs
152874: 11/10/29: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
155051: 13/04/04: Re: MISC - Stack Based vs. Register Based
155069: 13/04/05: Re: MISC - Stack Based vs. Register Based
155087: 13/04/08: Re: MISC - Stack Based vs. Register Based
Albert Wang:
39593: 02/02/14: Does anybody have the Xilinx Foundation Series 2.1i newest not locked license.dat file?
AlbertCo:
119041: 07/05/09: DVI over fiber
alberto:
7802: 97/10/16: Re: I looked up Altera in an Italian dictionary.....
Alberto Broggi:
2246: 95/11/09: Final CFP - Real-Time Imaging J. - Special Issue on Special Purpose Architectures
2842: 96/02/15: CFP: Hawaii Intl Conf: ENGINEERING COMPLEX COMPUTER SYSTEMS Track
Alberto C Moreira:
3118: 96/04/06: Help: logic design on a PC
3142: 96/04/12: Re: Help: logic design on a PC
3143: 96/04/12: Re: Help: logic design on a PC
Alberto Moreira:
39438: 02/02/09: Help with getting started
Albrecht Ditzinger:
5507: 97/02/21: Re: Mealy/Moore state machines
6262: 97/05/06: Re: New Lattice (is)pLSI Resynthesis Server now online
alco:
18793: 99/11/16: How to use GSR-net in Virtex?
18794: 99/11/16: What happens to power-on-reset when external signals control the GSR
37444: 01/12/11: ISP by JTAG using a microcontroller
Aldec-Brent Wood:
11711: 98/09/02: $99 VHDL Training
Alderaan:
98185: 06/03/07: Retiming a datapath
98356: 06/03/08: Shift Register synthesis??
119624: 07/05/24: Custom Memory Initialization
143756: 09/10/24: connecting Xilinx XUP expansion headers
Alderan:
49746: 02/11/20: Cpld beginner
49765: 02/11/20: Re: Cpld beginner
49771: 02/11/20: Re: Cpld beginner
49920: 02/11/25: Problem programming XC9536
49982: 02/11/27: Re: Problem programming XC9536
Aldo Mastrosimone:
29790: 01/03/09: Using LVDS I/O buffers on Virtex-II
Aldo Mozzi:
14903: 99/02/24: Re: Your view on this article?
Aldo Romani:
35271: 01/09/27: Using EABs in Leonardo Spectrum with Flex10K
35317: 01/09/28: Re: Using EABs in Leonardo Spectrum with Flex10K
35337: 01/09/29: Re: Using EABs in Leonardo Spectrum with Flex10K
aldorus:
150803: 11/02/14: Cyclone Based FPGA Dev Board With USB Cable Program Path
150807: 11/02/14: Re: Cyclone Based FPGA Dev Board With USB Cable Program Path
150932: 11/02/23: Programming FPGAs with Quartus under Linux
Aldorus:
141417: 09/06/23: EPM7064 Altera PLD oe1\oe2\gclr1
141498: 09/06/25: Re: EPM7064 Altera PLD oe1\oe2\gclr1
Alec Cawley:
17562: 99/08/10: Re: Emulating a transputer on FPGA
17566: 99/08/10: Re: Emulating a transputer on FPGA
Alec Cosic:
5862: 97/03/21: FPGA and PLL
6458: 97/05/26: Altera decimated filter design
Alec Stanculescu:
2960: 96/03/05: FinSim 4.2 - Enhanced Cycle Simulation Press Release
Aleco31:
70688: 04/06/23: Xilinx Sparta-3 configuration
74582: 04/10/14: Re: 1.2V
alekceywk:
152645: 11/09/21: Xilinx Spartan-3 Starter Kit and Webpack 13.2
aleksa:
133014: 08/06/13: CPLD beginner questions
133028: 08/06/14: Re: CPLD beginner questions
134216: 08/07/31: Simple 8253
134220: 08/07/31: Re: Simple 8253
134545: 08/08/17: How to see the contents of BRAM in simulator?
134550: 08/08/17: Re: How to see the contents of BRAM in simulator?
134876: 08/09/04: Spartan-3 -> Spartan-2 problem
135000: 08/09/10: Spartan-II, config pins 5V tolerant? (slave serial)
135029: 08/09/11: Re: Spartan-II, config pins 5V tolerant? (slave serial)
135040: 08/09/11: Re: Spartan-II, config pins 5V tolerant? (slave serial)
135811: 08/10/16: Using GCK pin as both clock and signal (Spartan 2)
135816: 08/10/16: Re: Using GCK pin as both clock and signal (Spartan 2)
135825: 08/10/16: Re: Using GCK pin as both clock and signal (Spartan 2)
135828: 08/10/16: Re: Using GCK pin as both clock and signal (Spartan 2)
135844: 08/10/17: Re: Using GCK pin as both clock and signal (Spartan 2)
135845: 08/10/17: Re: Using GCK pin as both clock and signal (Spartan 2)
135865: 08/10/18: Re: Using GCK pin as both clock and signal (Spartan 2)
137187: 08/12/31: One-channel >> multi-channel serial DAC
137382: 09/01/13: Counter: natural VS std_logic_vector
137387: 09/01/13: Re: Counter: natural VS std_logic_vector
137390: 09/01/13: Re: Counter: natural VS std_logic_vector
137412: 09/01/14: Re: Counter: natural VS std_logic_vector
137413: 09/01/14: Re: Counter: natural VS std_logic_vector
137427: 09/01/15: Re: Counter: natural VS std_logic_vector
137436: 09/01/16: Re: Counter: natural VS std_logic_vector
137445: 09/01/16: Re: Counter: natural VS std_logic_vector
137450: 09/01/17: Re: Counter: natural VS std_logic_vector
137879: 09/02/01: Dangling blockram output - how to remove warning?
138914: 09/03/14: Spartan 2: unused GCLK pins
139535: 09/04/02: Timing constraints problem
139556: 09/04/02: Re: Timing constraints problem
139720: 09/04/10: Strange order of BRAM data bus connections
139723: 09/04/10: Re: Strange order of BRAM data bus connections
139727: 09/04/10: Re: Strange order of BRAM data bus connections
139728: 09/04/10: Re: Strange order of BRAM data bus connections
140089: 09/04/28: Re: ISE 11.1 drops support for Virtex-2/Pro and Spartan-2/E
144370: 09/12/02: This works, this does not... why?
144375: 09/12/02: Re: This works, this does not... why?
144384: 09/12/03: Re: This works, this does not... why?
144415: 09/12/04: Re: This works, this does not... why?
144418: 09/12/05: Re: This works, this does not... why?
144427: 09/12/06: Re: This works, this does not... why?
147690: 10/05/16: Spartan 2 & 3, serial config and CS pin
147714: 10/05/18: Re: Spartan 2 & 3, serial config and CS pin
148310: 10/07/06: 6 kbytes BRAM and Xst:2260
150636: 11/01/30: Can't program Spartan3A with JTAG
150637: 11/01/30: Re: Can't program Spartan3A with JTAG
150638: 11/01/30: Re: Can't program Spartan3A with JTAG
150642: 11/01/31: Re: Can't program Spartan3A with JTAG
150643: 11/01/31: Re: Can't program Spartan3A with JTAG
150647: 11/01/31: Re: Can't program Spartan3A with JTAG
150652: 11/01/31: Re: Can't program Spartan3A with JTAG
150653: 11/01/31: Re: Can't program Spartan3A with JTAG
150654: 11/01/31: Re: Can't program Spartan3A with JTAG
150658: 11/02/01: Re: Can't program Spartan3A with JTAG
150659: 11/02/01: Re: Can't program Spartan3A with JTAG
150983: 11/02/26: Signal issues
150985: 11/02/26: DCM on S3A problem
150989: 11/02/27: Re: DCM on S3A problem
150990: 11/02/27: Re: DCM on S3A problem
151054: 11/03/02: Re: Signal issues
151081: 11/03/04: JTAG questions
151082: 11/03/04: Re: JTAG questions
153354: 12/02/06: Problem with post-route simulation
153357: 12/02/06: Re: Problem with post-route simulation
153358: 12/02/06: Re: Problem with post-route simulation
153359: 12/02/06: Re: Problem with post-route simulation
153369: 12/02/10: Dangling all pins, DIA0 through DIA31
153370: 12/02/10: Re: Dangling all pins, DIA0 through DIA31
153373: 12/02/10: Re: Dangling all pins, DIA0 through DIA31
153375: 12/02/10: Re: Dangling all pins, DIA0 through DIA31
153377: 12/02/11: Re: Dangling all pins, DIA0 through DIA31
Aleksandar Kuktin:
155857: 13/10/04: Lattice Diamond & tristate
155861: 13/10/04: Re: Lattice Diamond & tristate
155911: 13/10/16: Re: Lattice Diamond & tristate
156070: 13/11/22: Re: FPGA Cryptosystem
156128: 13/12/07: Implementing multiple interrupts
156139: 13/12/08: Re: Implementing multiple interrupts
156140: 13/12/08: Re: Implementing multiple interrupts
156896: 14/07/23: Re: Generating a desired synthesizable binary pulse train on FPGA
157012: 14/08/26: Re: Bidirectional Pin FPGA (Parallel ADC)
157720: 15/02/15: Re: Open Source GPGPU core
157722: 15/02/15: Re: Open Source GPGPU core
157748: 15/02/28: Re: Program Xilinx with Altera JTAG Programmer?
158085: 15/08/04: Re: Finally! A Completely Open Complete FPGA Toolchain
158086: 15/08/04: Re: Picking the best synthesis result before implementation
158103: 15/08/08: Re: Finally! A Completely Open Complete FPGA Toolchain
158104: 15/08/08: Re: Finally! A Completely Open Complete FPGA Toolchain
158201: 15/09/13: Re: Finally! A Completely Open Complete FPGA Toolchain
158266: 15/09/30: DDR* SDRAM modules for simulation
158269: 15/09/30: Re: DDR* SDRAM modules for simulation
158363: 15/10/24: Found: an FPGA with internal tri-states
158585: 16/01/08: Re: Opinions, on this newfangled thing, please
158592: 16/01/10: Re: Opinions, on this newfangled thing, please
158612: 16/01/25: Re: Fully preposterous gate arranger
158737: 16/04/06: Re: Using an FPGA to drive the 80386 CPU on a real motherboard
158738: 16/04/06: Re: Using an FPGA to drive the 80386 CPU on a real motherboard
158793: 16/04/09: Re: Using an FPGA to drive the 80386 CPU on a real motherboard
158794: 16/04/09: Re: Using an FPGA to drive the 80386 CPU on a real motherboard
158839: 16/05/01: Re: Using an FPGA to drive the 80386 CPU on a real motherboard
158890: 16/05/16: Re: Using an FPGA to drive the 80386 CPU on a real motherboard
159256: 16/09/10: iCE40: I/O toggle rate, hard numbers needed
160298: 17/11/05: Using LUTs to create a phase delayed clock - is it reproducible?
160676: 18/09/23: Need magic incantation to prevent synthesizer misoptimisation
160685: 18/10/09: Re: Need magic incantation to prevent synthesizer misoptimisation
<aleksazr@gmail.com>:
153523: 12/03/23: Why are my S3A pins getting destroyed?
153524: 12/03/23: Re: Why are my S3A pins getting destroyed?
153824: 12/06/01: Variables, signals: behavioral and post-route simulation
153826: 12/06/01: Re: Variables, signals: behavioral and post-route simulation
154961: 13/03/04: Farnell increased price on Spartan 6
Aleksei Chistyakov:
41934: 02/04/11: ASIC vs FPGA compare topic
Aleksey:
134099: 08/07/25: Connection XMD to the XMDstub
Aleksey Starikov:
16059: 99/04/30: Source code Ethernet, E1 Framer, HDLC Contr.
Ales Hvezda:
77748: 05/01/15: Re: Exportability of EDA industry from North America?
<ales.gorkic@gmail.com>:
130760: 08/04/01: Re: increase memory of microblaze
134812: 08/09/02: Re: Image input
134813: 08/09/02: Re: how to built a CCD camera + FPGA ???
135026: 08/09/11: Re: Load Application from External Memory without the use of XMD???
135045: 08/09/12: Re: Load Application from External Memory without the use of XMD???
136046: 08/10/29: PLBv4.6 with more than 16 slaves
136099: 08/10/31: Re: PLBv4.6 with more than 16 slaves
136502: 08/11/19: Re: vga interfacing for image display
136698: 08/12/02: Re: using memory of spartan 3sd1800a dsp fpga
136890: 08/12/11: Re: Adding 128Kx8 SRAM to Spartan 3E FPGA
136891: 08/12/11: Re: Adding 128Kx8 SRAM to Spartan 3E FPGA
136908: 08/12/12: Re: Xilinx ISE 10.1 SP3 MPMC NPI VHDL simple sample needed
136909: 08/12/12: Re: How to insert ChipScope
136965: 08/12/16: Re: BUFGMUX placement
137639: 09/01/25: dual MIG controller on spartan 3A DSP
137645: 09/01/26: Re: dual MIG controller on spartan 3A DSP
137665: 09/01/27: Re: dual MIG controller on spartan 3A DSP
137666: 09/01/27: Re: dual MIG controller on spartan 3A DSP
137667: 09/01/27: Re: dual MIG controller on spartan 3A DSP
138107: 09/02/06: Re: how to cope with read cycle latency in block ram on Xilinx device
139315: 09/03/26: Re: R/A FX2 connectors for S3A board - anyone have a couple spare?
139755: 09/04/11: Re: buy XSA-50
139777: 09/04/13: Re: Stupid question about COE files
139778: 09/04/13: Re: Stupid question about COE files
139790: 09/04/14: Mobile low power DDR SDRAM and MIG
139794: 09/04/14: Re: Mobile low power DDR SDRAM and MIG
139811: 09/04/14: Re: Mobile low power DDR SDRAM and MIG
140085: 09/04/27: Re: ISE 11.1 drops support for Virtex-2/Pro and Spartan-2/E
140086: 09/04/27: Re: FPGA/DSP/Video Board
140266: 09/05/07: Re: Xilinx XPS_INTC and XPS_UARTLITE interrupt issues
140660: 09/05/21: Re: please recommend a soft processor for small image processing
141098: 09/06/05: Re: Xilinx FIR Compiler gives zero only output in hardware
Alessandro:
134930: 08/09/07: Spartan 3E evaluation board manufacturers
134935: 08/09/07: Re: Spartan 3E evaluation board manufacturers
134938: 08/09/07: Re: Spartan 3E evaluation board manufacturers
134940: 08/09/07: Re: Spartan 3E evaluation board manufacturers
134967: 08/09/08: Re: Spartan 3E evaluation board manufacturers
134969: 08/09/09: Re: Spartan 3E evaluation board manufacturers
134970: 08/09/09: Re: Spartan 3E evaluation board manufacturers
134988: 08/09/09: Re: Spartan 3E evaluation board manufacturers
134989: 08/09/09: Re: Spartan 3E evaluation board manufacturers
134990: 08/09/09: Re: Spartan 3E evaluation board manufacturers
134991: 08/09/09: Re: Are Xilinx tools that bad, or am I missing something?
135020: 08/09/10: Re: Are Xilinx tools that bad, or am I missing something?
136107: 08/11/01: timing issue with ISE10 SP3
136110: 08/11/02: Re: timing issue with ISE10 SP3
136119: 08/11/02: Re: timing issue with ISE10 SP3
136120: 08/11/02: blockram init file in spartan 3E
136137: 08/11/03: Re: blockram init file in spartan 3E
136428: 08/11/16: Re: vga interfacing for image display
Alessandro Basili:
146468: 10/03/19: wishbone
146475: 10/03/19: Re: wishbone
146509: 10/03/21: Re: wishbone
146512: 10/03/21: Re: wishbone
146627: 10/03/24: Re: wishbone
149958: 10/12/03: FPGA development environment
149989: 10/12/06: Re: FPGA project structure definition
150037: 10/12/07: Re: Interconnection of multiple cores
150040: 10/12/07: Re: Linux on Microblaze
150056: 10/12/08: spacewire project on opencores.org
150065: 10/12/09: Re: spacewire project on opencores.org
150101: 10/12/13: Re: spacewire project on opencores.org
150147: 10/12/20: Re: spacewire project on opencores.org
150784: 11/02/10: Re: Simple clock question
150802: 11/02/13: Re: Simple clock question
150815: 11/02/14: why an FSM is not a counter?!
150827: 11/02/15: Re: why an FSM is not a counter?!
150834: 11/02/15: Re: why an FSM is not a counter?!
150868: 11/02/17: Re: why an FSM is not a counter?!
150984: 11/02/26: Re: Mathematical definition of an FPGA
150991: 11/02/27: Re: Mathematical definition of an FPGA
152045: 11/06/27: Re: boldport
152080: 11/07/01: Re: verilog task and vhdl
alessandro basili:
110278: 06/10/13: Re: An implementation of a clean reset signal
110311: 06/10/13: more than 90% occupancy in an Actel FPGA
110363: 06/10/14: Re: more than 90% occupancy in an Actel FPGA
110412: 06/10/15: Libero 7.2
Alessandro Capobianco:
49158: 02/11/03: R: DFT , Design For Test HELPPPPP
Alessandro Caserta:
15760: 99/04/13: 75% PAL video bars
alessandro de gloria:
811: 95/03/05: Re: Limits on on-chip FPGA virtual computing
Alessandro Patalani:
31597: 01/05/31: EPC2: no output signals
Alessandro Pinto:
18334: 99/10/16: VITERBI
18337: 99/10/16: Re: VITERBI
Alessandro Scaglione:
69616: 04/05/15: EDK6.1 MBlaze : problems with INTC IPIF and external interrupts
69646: 04/05/17: Re: EDK6.1 MBlaze : problems with INTC IPIF and external interrupts
Alessandro Strazzero:
71999: 04/08/05: NIOS Gnu Tools and Dynamic Memory
79392: 05/02/18: Is Altera Cyclone a good choice ?
81368: 05/03/22: NIOS II power-on reset
<alessandro.giulianelli@gmail.com>:
137642: 09/01/26: Re: fpga mac controller with tcp/ip/dhcp
alessandro.strazzero@gmail.com:
148430: 10/07/22: Using std_ulogic at synthesis level
148592: 10/08/04: A question from a VHDL beginner
149832: 10/11/25: Multiple clock domains
<alessandro.strazzero@gmail.com>:
88155: 05/08/10: Using an oscillator in a rugged environment
88322: 05/08/15: Clock generation
94675: 06/01/16: NIOS II fmax on a Cyclone
101488: 06/05/01: RESET pin on NIOS II processor
119287: 07/05/16: NIOS2 GNU tools under Windows Vista
133318: 08/06/24: External memory access
<alessandro.strazzero@virgilio.it>:
89506: 05/09/16: DEV_CLRn and CRC_ERROR on ALTERA Cyclone
alessio quagliariello:
71643: 04/07/26: Re: VHDL model of Xilinx's Rocket I/O MGT
Alex:
35104: 01/09/21: PCI design for Spartan-2
57748: 03/07/05: Xilinx:CAM
58364: 03/07/21: Leonardo spectrum synthesis result
58437: 03/07/23: Re: CRC questions
67286: 04/03/09: In-system configuration through JTAG on Spartan-3
70747: 04/06/26: RocketIO transmission error
72862: 04/09/06: Interfacing an 1GS ADC
78639: 05/02/04: Spartan-3 Starter Kit supplier in the UK?
78669: 05/02/05: Re: Spartan-3 Starter Kit supplier in the UK?
81598: 05/03/28: Xilinx / Linux Newbie Classes/Groups in Portland?
82104: 05/04/06: Xilinx ISE 7.1i / stuck down XCR3064 outputs
82113: 05/04/06: Re: Xilinx ISE 7.1i / stuck down XCR3064 outputs
82146: 05/04/07: Re: Xilinx ISE 7.1i / stuck down XCR3064 outputs
82233: 05/04/08: Re: ISE/Impact 7.1 Linux Driver problems
82846: 05/04/18: Re: XC95108 problem
84800: 05/05/27: Wrong type name (subtitution) in post-place & route simulation model.
86446: 05/06/28: proth siever in FPGA?
86457: 05/06/28: Re: proth siever in FPGA?
86497: 05/06/29: ADPLL for NRZ
86502: 05/06/29: Re: proth siever in FPGA? [LONG]
86515: 05/06/29: Re: ADPLL for NRZ
86517: 05/06/29: Re: ADPLL for NRZ
87686: 05/07/28: Re: proth siever in FPGA? [LONG]
87711: 05/07/28: Re: Remove Duplicate Registers / Logic
88282: 05/08/14: Re: Delay implementation and logic optimization.
88288: 05/08/14: Delay implementation and logic optimization.
88289: 05/08/14: Re: globally asyncronous vs locally syncronous?
88320: 05/08/15: Re: Delay implementation and logic optimization.
88323: 05/08/15: Re: Clock generation
88400: 05/08/17: Re: Easy USB2.0 hi-speed device solutions ?
88438: 05/08/18: Re: Synthesis : HowTo Preserve FSM encodings
88556: 05/08/23: Different Synthesis Results on Different Levels of Hierarchy (different amount of occupying slices)
88573: 05/08/23: Re: Different Synthesis Results on Different Levels of Hierarchy (different amount of occupying slices)
88578: 05/08/23: Re: Different Synthesis Results on Different Levels of Hierarchy (different amount of occupying slices)
88589: 05/08/23: Re: Different Synthesis Results on Different Levels of Hierarchy (different amount of occupying slices)
88650: 05/08/24: Re: Strange FPGA problem
88667: 05/08/25: Re: Different Synthesis Results on Different Levels of Hierarchy (different amount of occupying slices)
89551: 05/09/19: Re: Dll device for FPGA
91990: 05/11/18: Re: Bidirectional bus control
92020: 05/11/19: Assertion file update problem in ModeSim (via Tcl script)
92835: 05/12/07: PLX 9056 application
97697: 06/02/26: Re: VHDL to create LUT based delay
98144: 06/03/06: Re: How to interface ASIC on a PCB and and an FPGA
103905: 06/06/14: Re: Xilinx XST Error
104159: 06/06/20: Xilinx ISE 8.1i Trouble
104168: 06/06/20: Re: Xilinx ISE 8.1i Trouble
104172: 06/06/20: Re: Xilinx ISE 8.1i Trouble
104204: 06/06/21: Re: Xilinx ISE 8.1i Trouble
104206: 06/06/21: Re: Xilinx ISE 8.1i Trouble
104214: 06/06/21: Re: Xilinx ISE 8.1i Trouble
104240: 06/06/21: Re: Xilinx ISE 8.1i Trouble
104485: 06/06/28: Spartan 3E, Output File
104739: 06/07/05: "Large" memory array in VHDL
104745: 06/07/05: Re: "Large" memory array in VHDL
104765: 06/07/05: Re: "Large" memory array in VHDL
105281: 06/07/19: VHDL Data Buffer on Spartan-3E
108937: 06/09/19: VHDL oddity
108949: 06/09/19: Re: VHDL oddity
109054: 06/09/20: Unstable output pin?
110609: 06/10/18: Re: Scoreboard and Checker in Testbench?
110631: 06/10/18: Re: Scoreboard and Checker in Testbench?
110680: 06/10/19: Re: Scoreboard and Checker in Testbench?
110682: 06/10/19: Re: Scoreboard and Checker in Testbench?
110688: 06/10/19: Re: Scoreboard and Checker in Testbench?
112525: 06/11/23: Re: What's Nonpipelined bus mean?
112555: 06/11/24: Re: Verilog problem: default case to set signal xxxx
124974: 07/10/13: Re: Graphical VHDL Viewer ?
125880: 07/11/07: Re: Non-volatile FPGA in a small package
125899: 07/11/08: Re: Non-volatile FPGA in a small package
126365: 07/11/20: Re: Coolrunner in system programming - XAPP0058 - viable?
132218: 08/05/18: Re: ANNC: FPGA Design Software Webcast
132220: 08/05/18: Re: ANNC: FPGA Design Software Webcast
133436: 08/06/28: Re: NVRAM design in CPLD
135496: 08/10/05: A question about the use of FPGA
135508: 08/10/06: Re: A question about the use of FPGA
135542: 08/10/06: Re: A question about the use of FPGA
135966: 08/10/24: Small FPGA boards with USB/Ethernet
136007: 08/10/27: Re: Small FPGA boards with USB/Ethernet
136033: 08/10/28: Re: Register File distributed all over the FPGA
136038: 08/10/28: Re: Register File distributed all over the FPGA
136059: 08/10/29: Re: Register File distributed all over the FPGA
136073: 08/10/30: Re: Register File distributed all over the FPGA
141461: 09/06/24: Re: True dual-port RAM in VHDL: XST question
142059: 09/07/23: Re: How do you handle build variants in VHDL?
143703: 09/10/22: Time stability of clock on FPGA board
143707: 09/10/22: Re: Time stability of clock on FPGA board
143708: 09/10/22: Re: Time stability of clock on FPGA board
143712: 09/10/22: Re: Time stability of clock on FPGA board
143718: 09/10/22: Re: Time stability of clock on FPGA board
143728: 09/10/22: Re: Time stability of clock on FPGA board
143729: 09/10/22: Re: Time stability of clock on FPGA board
143731: 09/10/22: Re: Time stability of clock on FPGA board
143748: 09/10/23: Re: Time stability of clock on FPGA board
143749: 09/10/23: Re: Time stability of clock on FPGA board
143750: 09/10/23: Re: Time stability of clock on FPGA board
143753: 09/10/23: Re: Time stability of clock on FPGA board
143768: 09/10/24: Re: Time stability of clock on FPGA board
143776: 09/10/25: Re: Time stability of clock on FPGA board
143777: 09/10/25: Re: Time stability of clock on FPGA board
143814: 09/10/27: Re: Time stability of clock on FPGA board
143816: 09/10/27: Re: Time stability of clock on FPGA board
143817: 09/10/27: Re: Time stability of clock on FPGA board
143819: 09/10/27: Re: Time stability of clock on FPGA board
144584: 09/12/16: How to add cores in XPS 9.1i ?
145023: 10/01/20: A construction of FPGA based design by a beginner
145029: 10/01/20: Re: A construction of FPGA based design by a beginner
145063: 10/01/24: How to connect two BNC connectors to FPGA board?
145066: 10/01/24: Re: How to connect two BNC connectors to FPGA board?
145067: 10/01/24: Re: How to connect two BNC connectors to FPGA board?
145070: 10/01/24: Re: How to connect two BNC connectors to FPGA board?
145225: 10/02/01: What MAXIM chip is used on Spartan 3E 1600E Microblaze Board for
145227: 10/02/02: Re: What MAXIM chip is used on Spartan 3E 1600E Microblaze Board for
147447: 10/04/27: Question about PCB CAD for FPGA-based project
147481: 10/04/28: Re: Question about PCB CAD for FPGA-based project
149884: 10/11/30: Re: Hi-Z Output Bug in Lattice ispLever
149905: 10/12/01: Re: Hi-Z Output Bug in Lattice ispLever
149942: 10/12/02: Re: Hi-Z Output Bug in Lattice ispLever
150888: 11/02/19: Re: lattice machXO2 VCCP pin
150996: 11/02/28: Nanosecond pulse generator using Spartan-3E
151929: 11/06/07: Re: Best syntheses
156313: 14/02/18: Re: How to find power supply pins in Lattice Diamond projects
alex:
150377: 11/01/13: script for chipscope cores
Alex McHale:
103896: 06/06/14: Xilinx XST Error
Alex 00009:
4312: 96/10/13: 50 Mhz 24 CHANNEL LOGIC ANALYZER only $199
Alex Beynon:
11296: 98/08/03: Re: Symbols, design changes, pin changes
11628: 98/08/27: Re: CPLD/FPGA software
Alex Carreira:
23110: 00/06/14: Mutating Virtex FPGA
23336: 00/06/22: Re: FPGAs for Bioinformatics accelerators
23337: 00/06/22: Re: How to cut the power disipation down ?
23500: 00/06/27: Re: Porting C to FPGA
38410: 02/01/14: Re: Runtime reconfiguration internals
38654: 02/01/20: Re: JBits: Partial Reconfiguration
38762: 02/01/24: Re: Dynamic Reconfiguration of single Xilinx FPGA
38939: 02/01/28: Re: Dynamic Reconfiguration of single Xilinx FPGA
53108: 03/03/03: Re: Is anyone working with JBits there ?
53323: 03/03/10: Re: Are there any FPGA magazines/journals?
53330: 03/03/10: Re: Using divided clock
Alex CHOI:
8978: 98/02/11: Re: TPC1020AFN-068C DEVICES REQUIRED
Alex Clapperton:
43352: 02/05/20: Foundation 1.5
Alex Colvin:
94280: 06/01/09: Re: CRC error correction
114763: 07/01/24: Re: FPGA damage from bad bitstream
118196: 07/04/19: Re: Compiling a library
119949: 07/05/30: Re: Linux device driver for FPGA Xilinx Virtex-4
121139: 07/06/26: Re: Xilinx ISE 9.1 - Version Control - VSS
121140: 07/06/26: Re: Xilinx ISE 9.1 - Version Control - VSS
123409: 07/08/27: Re: Null statement in VHDL
124224: 07/09/14: Re: Physical Design Contribution to FPGA/CPLD success
125682: 07/10/31: Re: ERROR:Simulator:222 - Generated C++ compilation was unsuccessful
126127: 07/11/15: Re: FPGA for hobby use
128603: 08/01/31: Re: FPGA in Telecommunications
129656: 08/03/02: Re: HELP > Face/Edge detection on FPGA
130097: 08/03/14: Re: Problem with Spartan 3 StarterKit
135112: 08/09/16: Re: Xilinx build system
135154: 08/09/18: Re: Random Mask Generation on FPGAs
136333: 08/11/11: Re: Tilera multicore replaces FPGA?
137281: 09/01/07: Re: Which revision control do fpga designers use (2009)
137358: 09/01/11: Re: beginner synthesize question - my debounce process won't synthesize.
137570: 09/01/22: Re: testing a processor
ALEX CORNWELL:
Alex Cowie:
35064: 01/09/20: Postdoc and PhD Scholarships in Reconfigurable Computing
Alex Flitwick:
22035: 00/04/14: Re: Actel fpgas
22034: 00/04/14: PCMCIA Intellectual Property
22033: 00/04/14: Re: Virtex readback
Alex Freed:
79496: 05/02/20: Re: Is Altera Cyclone a good choice ?
79966: 05/02/27: Re: livedesign or ise
80049: 05/02/28: Re: FPGA interface to an asynchronous microcontroller memory bus
81952: 05/04/05: Re: Open PowerPC Core?
83120: 05/04/24: Re: Relative number of CLBs
84307: 05/05/17: Re: "Mine is bigger than yours..."
86329: 05/06/25: Re: Good FPGA introduction book ?
89528: 05/09/17: Re: Reading a PAL fusemap with a microscope
89574: 05/09/19: Re: Reading a PAL fusemap with a microscope
89631: 05/09/21: Re: digilent USB2 module
94578: 06/01/13: Re: how do I minimize the logic in this function?
103180: 06/05/27: Re: tft and uClinux
104041: 06/06/17: Re: Floppy to FPGA?
104058: 06/06/17: Re: Floppy to FPGA?
104130: 06/06/19: Re: Floppy to FPGA?
126873: 07/12/05: Spartan 3e and SDRAM
126908: 07/12/05: Re: Spartan 3e and SDRAM
126953: 07/12/06: SDRAM and S3E - is the example broken?
126997: 07/12/07: Which FPGA and memory to use? The eternal X vs. A question.
127020: 07/12/08: Re: Which FPGA and memory to use? The eternal X vs. A question.
127021: 07/12/08: Re: Which FPGA and memory to use? The eternal X vs. A question.
127022: 07/12/08: Re: Which FPGA and memory to use? The eternal X vs. A question.
127035: 07/12/09: Re: Which FPGA and memory to use? The eternal X vs. A question.
127104: 07/12/11: Re: Poor quality Xilinx boards ? Your experience ?
127308: 07/12/17: Re: Ethernet data rates using Spartan-3 FPGA
129068: 08/02/13: Re: microblaze firmware + UART handshaking blues
130055: 08/03/14: Re: Cyclone III FPGA Starter Kit: As USB device? Using JTAG terminal
130104: 08/03/14: Re: DDR3 speed, Altera vs Xilinx
130150: 08/03/17: Re: Designing CPU
130444: 08/03/24: Re: Spartan 3E intefacing for dummies
130449: 08/03/24: Re: Spartan 3E intefacing for dummies
132941: 08/06/10: Re: fpga reprogrammable?
132945: 08/06/10: Re: fpga reprogrammable?
134975: 08/09/08: Re: Spartan 3E evaluation board manufacturers
134993: 08/09/09: Re: Spartan 3E evaluation board manufacturers
135139: 08/09/17: Re: Random Mask Generation on FPGAs
135752: 08/10/14: Re: writing files to micro-SD with spartan 3e
137704: 09/01/27: Re: What software do you use for PCB with FPGA ?
137719: 09/01/28: Re: What software do you use for PCB with FPGA ?
138616: 09/03/02: Re: New person to CPLD programming
138719: 09/03/05: Re: New person to CPLD programming
139897: 09/04/18: source for Spartan 3E chips
139982: 09/04/22: Re: source for Spartan 3E chips
141975: 09/07/20: Re: How do you handle build variants in VHDL?
142612: 09/08/20: Re: Xilinx 3E design programs fine with 500E but fails with 250E
142928: 09/09/08: Re: IMPACT-Xilinx Platform Cable USB II
143286: 09/09/29: Re: How to program Spartan 3 Altium nanoboard with Xilinx tools ?
143822: 09/10/27: Re: ISe 10.1 nightmare bug
144496: 09/12/10: Re: Cheapest way to get a chipscope compatible cable?
145213: 10/02/01: Re: In system memory editor of Altera for Xilinx
145336: 10/02/05: Re: using an FPGA to emulate a vintage computer
145935: 10/02/28: Re: using an FPGA to emulate a vintage computer
147702: 10/05/17: Re: using ChipScope to debug external design
Alex Gaivoronsky:
29456: 01/02/22: Re: clock divider by 1.5
Alex Garachtchenko:
6290: 97/05/09: Re: Need Address/Phone/Fax List of Semiconductor Companies
Alex Gibson:
51367: 03/01/12: Re: Student development board
51410: 03/01/14: Re: need pointers to FPGA software & download hardware
52194: 03/02/04: Re: What's the difference: WebPack 5.1 vs. Xilinx Student Edition 4.2i ?
52405: 03/02/08: Re: USB2 or firewire or 100Mb ethernet link to FPGA design
52970: 03/02/28: Re: Xilinx Coolrunner-II Dev Kit
53043: 03/03/01: Re: Xilinx Coolrunner-II Dev Kit
53556: 03/03/16: Re: What is the diff between FPGA and CPLD?
53569: 03/03/17: Re: FPGA dev boards
53740: 03/03/21: Re: FPGA choice (UK)
54291: 03/04/08: Re: price of fpga chips
54324: 03/04/08: Re: Xilinx Impact and USB/LPT ports
55037: 03/04/25: Re: Webpack 5.2 Install problems?
55474: 03/05/09: Re: Info about development kit
55496: 03/05/10: Re: help on FPGA-programming tutorial for students
55942: 03/05/24: Re: problem with modelsim 5.7d on winXP system
55946: 03/05/24: Re: FPGA Board
55956: 03/05/25: Re: problem with modelsim 5.7d on winXP system
55965: 03/05/25: Re: Newbie CPLD question
55973: 03/05/25: Re: Newbie CPLD question
56195: 03/05/30: Re: 2 Questions about VHDL
56196: 03/05/30: Re: 2 Questions about VHDL
56198: 03/05/30: Re: Newbie CPLD question
56540: 03/06/09: Re: Protel DXP or other schematic entry?
58559: 03/07/26: Re: Should I use ABEL?
58560: 03/07/26: Re: Should I use ABEL?
58862: 03/08/03: Re: Pricing question....
60424: 03/09/13: Re: Embedded/Microcontroller FPGA and Software Defined Radio
61493: 03/10/06: Re: Good VHDL/Verilog editor?
62506: 03/10/31: Re: Logic Analyzer for FPGAs
62701: 03/11/05: Re: Picoblaze development tool
63133: 03/11/16: Re: getting started in FPGA
63336: 03/11/20: Re: Is this a good starter kit?
63684: 03/11/30: Re: Digilent Inc.
64301: 03/12/26: Re: Hyperthreading vs. Dual proc
65504: 04/01/31: Re: Which Environment for Xilinx Design?
65505: 04/02/01: Re: Image sensor?
65508: 04/02/01: Re: Image sensor?
66222: 04/02/15: Re: Sensible starter FPGA board
69365: 04/05/08: Re: Which board to buy? Status of open source tools?
69366: 04/05/08: Re: Which board to buy? Status of open source tools?
69604: 04/05/15: Re: best fpga development board?
71164: 04/07/10: Re: Xilinx Student Foundation Edition on Windows-XP ??
72077: 04/08/08: Re: LEGO mindstorms and FPGA
72078: 04/08/08: Re: Power Supply for Xilinx FPGA
72084: 04/08/08: Re: What is the price of the micro-blaze, ... ?
72308: 04/08/14: Re: let me have logic design for traffic light
72309: 04/08/14: Re: Altera winner?
72699: 04/08/30: Re: Impact vs. Linux RedHat Linux
73618: 04/09/26: Re: How to design a programming parallel cable
73630: 04/09/27: Re: Xilinx ISE 6.2i WebPack & project restoration
74992: 04/10/23: Re: configuring FPGA Spartan2
74292: 04/10/07: Re: Advice for a Beginner?
74381: 04/10/10: Re: Spartan 3 Kit
75723: 04/11/13: Re: Obsolete processors resurected in FPGAs
76085: 04/11/24: Re: FPGA development board
77500: 05/01/09: Re: EU patent debate, any effects on FPGA-design?
78361: 05/01/31: Re: i need xilinx edk
78362: 05/01/31: spartan3 starter kit now comes with eval version of edk
78374: 05/01/31: Re: spartan3 starter kit now comes with eval version of edk
80448: 05/03/06: Re: Newby Getting started with FPGA
80631: 05/03/10: Re: Newby Getting started with FPGA
80632: 05/03/10: Re: Newby Getting started with FPGA
81207: 05/03/19: Re: ISE 7.1 WebPack + EDK 6.3
81246: 05/03/20: Re: Is the Xilinx EDK free?
81552: 05/03/28: Re: Xilinx ISE 7.1 - Can this get any worse?
81867: 05/04/03: Re: WTB NIOS-II kit
82578: 05/04/15: Re: Reading old F2.1i schematics
83071: 05/04/23: Re: The DLP from Texas Instruments...
83177: 05/04/26: Re: New FPGA Development Board
83203: 05/04/26: Re: New FPGA Development Board
83212: 05/04/26: webpack for os x or freebsd ?
83213: 05/04/26: Re: New FPGA Development Board
83228: 05/04/26: Re: Another Altera FPGA Development Board
83308: 05/04/28: Re: Another Altera FPGA Development Board
83309: 05/04/28: Re: webpack for os x or freebsd ?
83810: 05/05/07: Re: embedded linux for v2pro PPC?
83848: 05/05/08: Re: embedded linux for v2pro PPC?
83926: 05/05/10: Re: DDR speed of the XUPV2P Board from Digilent
84257: 05/05/16: Re: FPGA design under Mac OS X ?
84317: 05/05/17: Re: FPGA design under Mac OS X ?
84336: 05/05/18: Re: "Mine is bigger than yours..."
84423: 05/05/19: Re: "Mine is bigger than yours..."
84680: 05/05/25: Re: How to download uClinux on Virtex4 Board.
84681: 05/05/25: Re: open support question to Xilinx. should be fairly simple to answer.
85115: 05/06/05: Re: re:XP for NIOS2
85241: 05/06/07: Re: XP for NIOS2
85470: 05/06/10: Re: ISE/EDK 6.3 vs 7.1...
85476: 05/06/10: Re: Question for Alex Gibson
85482: 05/06/10: Re: Question for Alex Gibson
85651: 05/06/13: Re: X-Fest devkit order leadtimes & software silliness....
85921: 05/06/18: Re: Update on availability of Spartan3
86105: 05/06/22: Low cost altera board
86113: 05/06/22: Re: choosing an fpga board
86118: 05/06/22: Re: choosing an fpga board
86210: 05/06/23: Re: choosing an fpga board
87015: 05/07/13: Re: Xilinx Conversion 3.1 --> 6.1
87193: 05/07/19: Re: setting XUP new board
88837: 05/08/30: Re: digilent spartan 3 kit example project
89038: 05/09/03: Re: XUP Virtex-II Pro "invalid target architecture"
89129: 05/09/06: Re: XUP Virtex-II Pro "invalid target architecture"
89183: 05/09/08: Re: Spartan-3E Starter Kit availability slips to December
89452: 05/09/15: Re: Xilinx V2Pro & SATA hard disk
90859: 05/10/24: Re: MAC Architectures
91420: 05/11/06: Re: Memec Insight Spartan-3 LC Development Kit USB drivers needed! Help!
91805: 05/11/14: Re: Viretx4 FX chip availability
93222: 05/12/16: Avnet hav2 s3e starter kit?
93275: 05/12/19: Re: Avnet hav2 s3e starter kit?
93497: 05/12/23: Re: Is there anybody that have ported the linux to the nios or microblaze?
93502: 05/12/23: Re: Is there anybody that have ported the linux to the nios or microblaze?
93507: 05/12/23: Re: Spartan3e and ChipScope
93556: 05/12/25: Re: Spartan3e and ChipScope
93657: 05/12/28: S3e starter kits available
94537: 06/01/13: Re: FPGA Journal Article
95282: 06/01/22: Re: FPGA Journal Article
95280: 06/01/22: Re: FPGA-Programmable power supply
95792: 06/01/26: Re: open source fpga programmer programs
95784: 06/01/26: Re: open source fpga programmer programs
97664: 06/02/26: Re: state-of-the-art schematic generation? [Was: SCHEMATICS ... ]
100688: 06/04/16: Re: Where is the xilinx online store gone?
100691: 06/04/16: Re: Where is the xilinx online store gone?
103487: 06/06/04: Re: Altium Livedesign eval boards - can you add a configuration prom?
104885: 06/07/08: Re: Fastest platform to run ISE?
113911: 06/12/29: Re: PicoBlaze C: compile to bitstream!
113913: 06/12/29: Re: FPGA workstation - should I wait for Window Vista?
116682: 07/03/15: Re: WTF? - Spartan-3E starter kit with no printed board manual?
116683: 07/03/15: Fpga sdr boards / kits
118669: 07/05/02: Re: DDR2 with Spartan-3A anybody having success??
120544: 07/06/09: Affordable pcie card ?
121308: 07/07/02: s3a kit - Use sma as signal output ?
121506: 07/07/06: Re: s3a kit - Use sma as signal output ?
Alex Iliev:
106179: 06/08/08: Avnet V2Pro dev board "Hello world"
106248: 06/08/09: Re: Avnet V2Pro dev board "Hello world"
106300: 06/08/10: Re: Avnet V2Pro dev board "Hello world"
Alex Ivchenko:
33770: 01/08/03: Looking for Verilog/FPGA engineer in Boston
Alex Jumper:
39264: 02/02/05: Re: F3.3 SP8
Alex K:
97089: 06/02/16: Re: WebPACK license (and Quartus Web Edition too).
Alex Koegel:
1365: 95/06/07: Fitter Quality
1527: 95/07/09: Re: Q: Need help with MAX+plus reading EDIF
1536: 95/07/11: Re: Abel and connectedt tri-state outputs
1854: 95/09/10: Re: pci board design guide
2077: 95/10/11: Altera Flex10K new family
2443: 95/12/06: Re: CRC-32 implementation
2891: 96/02/25: Re: Verilog vs. VHDL comparison
3123: 96/04/08: Re: Help: logic design on a PC
4026: 96/09/04: Synopsys Timing Analysis on Altera (flex10K) back-annotated design
8428: 97/12/14: Re: bus design in Altera 10K, how to increase speed
Alex Kouznetsov:
50444: 02/12/10: Re: Tiny Forth Processors
Alex Krynev:
3477: 96/06/06: FPGA Design flow
3487: 96/06/07: HEX - .LCA decompilation
Alex Krynew:
3775: 96/07/30: BIDIR Buses
Alex Lait:
7204: 97/08/14: Re: Low-cost programming FPGAs (was: Re: free FPGA software from actel)
Alex Leyn:
10788: 98/06/19: Re: Fpga Video interface
12719: 98/10/25: Re: clock divider chips
13242: 98/11/21: Re: Big-Endian vs Little-Endian
Alex Luccisano:
953: 95/04/02: Help selecting PLD design software/hardware
1015: 95/04/13: MINC's PLDesigner-XL Series
Alex M:
14466: 99/01/30: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
Alex Makris:
17420: 99/07/26: Re: Solaris vs. NT
17438: 99/07/28: Re: Problem with Max+PlusII / Flex10k
Alex Manninger:
18401: 99/10/22: Win NT
Alex Martin:
52495: 03/02/11: Re: Multicontext FPGA
Alex McDonald:
155062: 13/04/04: Re: MISC - Stack Based vs. Register Based
155064: 13/04/04: Re: MISC - Stack Based vs. Register Based
155068: 13/04/04: Re: MISC - Stack Based vs. Register Based
155071: 13/04/04: Re: MISC - Stack Based vs. Register Based
Alex P.Martin:
21948: 00/04/08: Re: EHW
22933: 00/06/04: Re: Where's OptiMagic?
Alex Protasiewicz:
13040: 98/11/12: Re: WorkView office Library files need
Alex Rast:
14740: 99/02/14: Re: Q:EEPROM for Xilinx XC4k
15185: 99/03/11: Virtex LUT equation syntax in Xilinx EPIC 1.5?
15286: 99/03/17: Allowed logic functions in Virtex LE
15319: 99/03/18: Re: Allowed logic functions in Virtex LE
15332: 99/03/19: Re: Allowed logic functions in Virtex LE
15540: 99/03/30: Re: HELP NEEDED: FPGA and Neural Networks
15559: 99/03/30: Re: FPGAs with ECL-compatible I/Os
28424: 01/01/12: JTAG configuration fails with XC95144XL
32325: 01/06/22: SmartMedia controller available as CPLD/FPGA core?
32327: 01/06/23: Re: SmartMedia controller available as CPLD/FPGA core?
32367: 01/06/25: Re: SmartMedia controller available as CPLD/FPGA core?
32719: 01/07/05: Best JTAG H/W, S/W for most meaningful debug info?
32830: 01/07/10: Problems with JTAG on XC95144 was:Best JTAG H/W,...
32914: 01/07/11: Re: Problems with JTAG on XC95144 was:Best JTAG H/W,...
32956: 01/07/12: How to fan out signals to bus lines in Xilinx Foundation Schematic Editor?
32982: 01/07/13: Re: Design entry
33034: 01/07/16: Re: How to fan out signals to bus lines in Xilinx Foundation Schematic Editor?
34417: 01/08/24: Xilinx FPGA Editor - how to route to an internal macro net?
34484: 01/08/27: Re: Xilinx FPGA Editor - how to route to an internal macro net?
34580: 01/08/29: Re: Xilinx FPGA Editor - how to route to an internal macro net?
36231: 01/11/02: 64-bit PCI core for Lattice CPLD?
36339: 01/11/07: Re: 64-bit PCI core for Lattice CPLD?
36576: 01/11/12: Xilinx F 2.1i files incompatible with 4.1i
36626: 01/11/13: Re: Reassemble a BGA560 device
36630: 01/11/13: Re: searchin for High density non bga packages something like PGA.
37355: 01/12/08: Xilinx FPGA Editor 4.1- problems with manually routing high-fanout nets
37358: 01/12/08: Re: Xilinx FPGA Editor 4.1- problems with manually routing high-fanout
37440: 01/12/11: Re: Xilinx FPGA Editor 4.1- problem...solved!
37756: 01/12/20: Virtex configuration problem: GTS being deasserted before DONE?
38247: 02/01/09: Error -10010 during Digital Buffer Control
42910: 02/05/06: Opinions on FPGA cores - best for a commercial project?
42991: 02/05/09: Re: Opinions on FPGA cores - best for a commercial project?
43052: 02/05/10: Re: Opinions on FPGA cores - best for a commercial project?
43085: 02/05/13: Re: Opinions on FPGA cores - best for a commercial project?
53864: 03/03/25: Anyone have difficulty downloading this core?
53966: 03/03/28: Re: Anyone have difficulty downloading this core?
53970: 03/03/28: Re: Anyone have difficulty downloading this core?
64565: 04/01/07: Xilinx ECS - connecting a single net to multiple bus lines?
64610: 04/01/08: Re: Large/Fast static RAM
64744: 04/01/13: Re: Xilinx ECS - connecting a single net to multiple bus lines?
64908: 04/01/16: Hardware to test (FPGA-based) prototype?
64963: 04/01/17: Re: Hardware to test (FPGA-based) prototype?
65067: 04/01/20: Re: Hardware to test (FPGA-based) prototype?
65122: 04/01/21: Re: Hardware to test (FPGA-based) prototype?
87233: 05/07/20: General-purpose STAPL Composer?
87303: 05/07/21: Re: General-purpose STAPL Composer?
87408: 05/07/22: Re: General-purpose STAPL Composer?
Alex Sherstuk:
16673: 99/06/02: Re: Printing to picture files
20071: 00/01/26: Re: Xilinx Foundation: VHDL to symbol
25137: 00/08/28: FPGA power pins decoupling <-> PCB autorouting
26790: 00/10/29: Re: Webpack Error?
27038: 00/11/08: Boundary Scan fundamentals
28906: 01/01/28: Q: VIRTEX experience, multipliers
31091: 01/05/11: Re: Spartan Annoyances
35613: 01/10/11: Re: contract assembler for BGA based board???
36728: 01/11/17: Q: XILINX binary .bit file header - ?
37163: 01/12/02: Phase noise (jitter) of XILINX logic elements - ?
37201: 01/12/03: Re: Phase noise (jitter) of XILINX logic elements - ?
37242: 01/12/04: Re: Phase noise (jitter) of XILINX logic elements - ?
38049: 02/01/03: Q: Cable for multiple LVDS signals - ?
39444: 02/02/10: Re: NT parallel port driver ...Any serial NT drivers?
41770: 02/04/07: Re: A learner of Modelsim
Alex Shot:
90580: 05/10/17: Re: Best Async FIFO Implementation
90631: 05/10/17: Re: Best Async FIFO Implementation
90742: 05/10/20: Re: Best Async FIFO Implementation
Alex Smith:
Alex Somesan:
76826: 04/12/13: Cyclone device misteriously overheats
76828: 04/12/13: Re: Cyclone device misteriously overheats
76842: 04/12/14: Re: Cyclone device misteriously overheats
76856: 04/12/14: Re: Cyclone device misteriously overheats
Alex Ungerer:
10043: 98/04/23: LCD Controller Macro
61425: 03/10/03: Simple I2C slave model (IO expander)
75510: 04/11/08: SDRAM sustained bursts
75831: 04/11/16: Re: SDRAM sustained bursts
Alex V. Sherstuk:
10789: 98/06/19: Re: XILINX Foundation - how to minimize project archive?
14823: 99/02/18: Re: edge-triggered registers on Xilinx 4000e.
15017: 99/03/03: Re: experience with Xilinx 4K series I/Os
Alex Weddell:
73287: 04/09/17: Verilog books
Alex.Louie:
133351: 08/06/25: Re: Xilinx tools in Windows or Linux - Suggestions
<alex65536@my-deja.com>:
20876: 00/02/25: Re: Xchecker schematic?
<alex_schreiber@my-dejanews.com>:
15011: 99/03/03: Re: Selt-Timed circuit
15053: 99/03/04: Re: Selt-Timed circuit
16379: 99/05/19: Re: Synopsys DC & Modelsim
16381: 99/05/19: Re: Synopsys DC & Modelsim
Alexander:
145448: 10/02/09: Stratix FPGA board up for grabs for cheap.
Alexander B. Taubin:
1498: 95/07/03: Async96 CALL FOR PAPERS
1937: 95/09/22: Reminder on Async96 Symposium
2590: 96/01/09: advanced program and registration for Async96
Alexander Belov:
52245: 03/02/05: Re: low pass FIR filter in FPGA
Alexander Firsov:
81140: 05/03/18: Anyone has a BSDL file for Qualcomm MSM (CDMA mobile station modem chips) ?
Alexander Gnusin:
52499: 03/02/11: Re: Synthesis Scripts
53385: 03/03/12: Re: DRC/ LVS
55725: 03/05/17: Re: Moore Vs Mealy machine ..
73035: 04/09/10: Re: why systemc?
73161: 04/09/14: Re: why systemc?
75469: 04/11/06: Re: how to force DC to use a specific cell ?
Alexander Jaud:
526: 94/12/20: wir2xnf License
529: 94/12/22: Re: wir2xnf License
Alexander Kane:
149122: 10/10/03: Starting a career with FPGAs
149142: 10/10/04: Re: Starting a career with FPGAs
151700: 11/05/06: Soft Processors and Licensing
151708: 11/05/08: Re: Soft Processors and Licensing
151772: 11/05/16: Re: Soft Processors and Licensing
153486: 12/03/08: Comparing relative power consumption
157219: 14/11/05: Re: USB PHY recommendations
157356: 14/11/27: Re: Low-end FPGA mezzanine standard
159697: 17/02/07: Re: Anyone use 1's compliment or signed magnitude?
Alexander Korff:
81827: 05/04/01: RAM Synthesized away
81871: 05/04/03: Re: RAM Synthesized away
83381: 05/04/28: crazy behaviour of fpga, timing ?
83444: 05/04/30: Re: crazy behaviour of fpga, timing ?
83515: 05/05/02: Re: crazy behaviour of fpga, timing ?
Alexander Krebs:
18482: 99/10/27: Xilinx F1.5 VHDL Sim. Libs for Synopsys
18535: 99/10/29: Re: Xilinx F1.5 VHDL Sim. Libs for Synopsys
Alexander Litvinov:
33621: 01/07/31: What way for Xilinx to ASIC migration ?
Alexander Marquardt:
64741: 04/01/12: Re: FPGA CAD researchers: documentation, APIs, file formats & tutorials for academics to interface to Quartus
Alexander Miks:
41461: 02/03/29: Homebuilt Altera-programmer totally dead...
41471: 02/03/29: Re: Homebuilt Altera-programmer totally dead...
41472: 02/03/29: Where to get MAX7000S
41727: 02/04/06: How sensitive is the EPM7064?
41754: 02/04/06: Re: How sensitive is the EPM7064?
41870: 02/04/09: Re: How sensitive is the EPM7064?
Alexander Paar:
24503: 00/08/11: Altera Byteblaster and Win2k
24517: 00/08/11: Re: Altera Byteblaster and Win2k
Alexander Perry:
8725: 98/01/22: Re: Xilinx Info.
Alexander Richter:
37614: 01/12/17: Re: SPI interface in VHDL
Alexander Sherstuk:
10499: 98/05/25: Problem with loading XC4000E configuration from 8051
10621: 98/06/06: Q: XILINX Foundation - how to minimize project archive?
10936: 98/07/05: Re: FPGA Bitstream Programming Compression
11908: 98/09/18: Re:programming via RS-232
11990: 98/09/23: Anyone received Xilinx Foundation 1.5 ?
12647: 98/10/22: RE: 100 Mhz FPGA
12839: 98/11/01: Q: 3.3 V regulators suitable for XILINX - ?
13389: 98/12/01: Re: Archiving Xilinx Foundation Projects
13391: 98/12/01: Editing XNF file
14118: 99/01/14: Unused port signals
14237: 99/01/21: Q: Counting GHz pulses - ?
14491: 99/02/01: NT sensitivity to PC hardware errors
14631: 99/02/07: RE: dual port RAM on XC4000
14710: 99/02/12: RE: Very Long Write Enable in Xilinx Dual Port RAMs
17594: 99/08/12: Foundation F1.5i Floorplanner document - ?
18648: 99/11/05: Analog FPGA ?!
18768: 99/11/13: Re: How many bits in an FPGA bitstream?
Alexander Sotnikov:
151346: 11/03/26: Re: Measuring the delay between two rising edges in modelsim simulation
Alexander Stoll:
13933: 99/01/03: Re: Can a cross coupled latch "oscillate"? was Re: ..........
Alexander Taubin:
6967: 97/07/17: CALL FOR PAPERS (CSD'98)
7488: 97/09/16: 2nd CALL FOR PAPERS-Application of Concurrency to System Design (CSD'98)
7859: 97/10/24: PAPER SUBMISSION DEADLINE EXTENSION FOR CSD'98
Alexander Teetaert:
9958: 98/04/17: Re: Survey of RTOS?
Alexander Weiss:
45209: 02/07/16: JTAG Analyzer with HP16510
Alexander Werger:
96042: 06/01/28: Serial flash configuration with "Xilinx platform cable USB"
103384: 06/06/01: Virtex4 FX12 - maximum frequency for Picoblaze
Alexander Wirtz:
70737: 04/06/25: Re: ise 6.2 + linuxdrivers.tar.gz + kernel 2.6
Alexander Wold:
153665: 12/04/11: Re: The Xilinx Definition Language
<alexander@eecs.wsu.edu>:
6555: 97/06/02: Re: New Reconfigurable Computing newsgroup?
6556: 97/06/02: Re: New Reconfigurable Computing newsgroup?
6558: 97/06/02: Re: New Reconfigurable Computing newsgroup?
Alexandr Solovkin:
3445: 96/05/31: The last Xilinx packages is needed
3824: 96/08/07: Re: Xilinx/FPGA Timing Problems
7086: 97/07/30: Where is Actel's www?
Alexandr V Shuvalov:
25143: 00/08/28: Guide revision in 2.1i
25310: 00/09/06: 3.3/2.5 voltage regulators
25337: 00/09/07: Re: 3.3/2.5 voltage regulators
Alexandr V. Arhipov:
687: 95/02/07: <none>
Alexandre:
144075: 09/11/10: Re: Analog power supplies to FPGAs
Alexandre Pechev:
8584: 98/01/11: PCI question
9108: 98/02/21: Re: download cable for lattice ISP -> schematics
9789: 98/04/05: Counter problem ?
12637: 98/10/21: Re: isp download cable ?
14181: 99/01/18: Re: AT40K popularity and available tools...
<alexandre.bezroutchko@gmail.com>:
138084: 09/02/05: Re: new source wizard doesn't seem to work.
alexandre.poltorak@gmail.com:
134825: 08/09/02: Re: how to built a CCD camera + FPGA ???
Alexandru Petrescu:
5001: 97/01/10: Re: What Does ASIC Stand For?
Alexandru Seibulescu:
3391: 96/05/23: Verilog Cycle Simulation & Code Coverage
3522: 96/06/14: Fintronic USA Inc. Announcement
6576: 97/06/03: Best value for Verilog Simulation!
9245: 98/03/04: Re: The case for Linux and EDA
33857: 01/08/06: Re: Can't Install Modelsim - Alternatives for Verilog Simulation???
<alexboyer@my-deja.com>:
26972: 00/11/06: FPGA programming through XC18V00 eeprom
26981: 00/11/06: Re: FPGA programming through XC18V00 eeprom
28121: 00/12/21: XC18V02 programming with xsvf file
Alexei A. Frounze:
80840: 05/03/12: Re: (Stupid/Newbie) Question on UART
80848: 05/03/12: Re: (Stupid/Newbie) Question on UART
80861: 05/03/13: Re: (Stupid/Newbie) Question on UART
80898: 05/03/14: Re: (Stupid/Newbie) Question on UART
80936: 05/03/15: Re: (Stupid/Newbie) Question on UART
Alexei Lomakin:
37744: 01/12/19: Re: Efficient new multiplier for Spartan2, Virtex &c.
Alexey:
52063: 03/01/30: Xilinx Foundation 3.1 problem
144029: 09/11/08: Interconnection of MicroBlaze processors
144055: 09/11/09: Re: Interconnection of MicroBlaze processors
144156: 09/11/14: Old EDK versions
144260: 09/11/23: Microblaze interconnection
Alexey Borisov:
36905: 01/11/24: Re: AHDL to VHDL
Alexey Kulentsov:
89739: 05/09/23: 802.11g solution usable for FPGA design
Alexey Lopich:
99712: 06/03/28: Re: WARNING:Xst:1778 - Inout <AddrBus>
Alexey Ovchinnikov:
18348: 99/10/17: Q
alexi:
47188: 02/09/20: Re: Modelsim XE question
77344: 05/01/05: Re: Using LM317S adjustable linear regulator for Spartan 3?
Alexis:
100014: 06/04/01: Re: USB Interface to Virtex-4
Alexis GABIN:
78032: 05/01/23: ModelSim & Constant
<alexkarpel@my-deja.com>:
27839: 00/12/12: Re: dual port ram for altera
AlexKrish:
158328: 15/10/22: Interfacing ADS7230 ADC to Altera FPGA
<alexlamba@my-deja.com>:
21078: 00/03/06: 300 Xilinx Xa7272a wanted, we'll pay up to 45$ each
AlexP:
34557: 01/08/29: Re: global VHDL signals and FPGA express
AlexS.:
37602: 01/12/17: Re: SPI interface in VHDL
AlexSeavision:
28209: 00/12/30: Money for College
28210: 00/12/30: Money for College
Alf Katz:
88296: 05/08/14: Re: Avnet spartan3E development board
Alf P. Steinbach:
67747: 04/03/18: Re: Synthesis algorithm - help needed
Alfmyk:
108903: 06/09/19: uBlaze : Reading Registers...
108905: 06/09/19: uBlaze : -m compile directives...
108915: 06/09/19: Re: uBlaze : -m compile directives...
109244: 06/09/22: uBlaze : Programming in C++... Is Possible ?
109347: 06/09/25: Re: uBlaze : Programming in C++... Is Possible ?
109354: 06/09/25: Re: uBlaze : Programming in C++... Is Possible ?
109966: 06/10/09: uBlaze : Compiling directive: possible Xilinx bug ?
111026: 06/10/27: EDK 8.2.01i:Spartan3E BSB Problem...
111030: 06/10/27: Re: EDK 8.2.01i:Spartan3E BSB Problem...
111035: 06/10/27: uBlaze Cache: update Cache Instruction...
111036: 06/10/27: uBlaze ISR : Steps to write/implement an ISR...
111103: 06/10/29: Re: EDK 8.2.01i:Spartan3E BSB Problem...
111104: 06/10/29: Re: uBlaze ISR : Steps to write/implement an ISR...
112485: 06/11/23: C++ on uBlaze : C++ Problems...Possible Xilinx bugs ?
112533: 06/11/24: Re: C++ on uBlaze : C++ Problems...Possible Xilinx bugs ?
113328: 06/12/11: ISR Routine:Copying application in RAM and jumping in it ISR(s) don't start !(?)
113374: 06/12/12: Re: ISR Routine:Copying application in RAM and jumping in it ISR(s) don't start !(?)
113414: 06/12/13: MicroBlaze : -mcpu=4.00.b option for mb-gcc compiler...
113479: 06/12/14: Re: MicroBlaze : -mcpu=4.00.b option for mb-gcc compiler...
Alfre:
107775: 06/09/01: MicroBlaze and RAM Application
108149: 06/09/06: XPS : Compiler advanced options...
Alfred:
808: 95/03/04: Re: area of RAM cells in FPGAs
alfred:
140473: 09/05/14: Re: arrays in VHDL
Alfred Bos:
1671: 95/08/14: Need information on MACH,FLEXlogix,ISPlsi
6991: 97/07/20: Larger designs with Lattice fitter ???
alfred fuchs:
16267: 99/05/12: Re: Virtex based PCI cards
18267: 99/10/11: Pull plug quickly!
29744: 01/03/07: Re: Bad Xilinx bitstream=big bang?
Alfred Fuchs:
3208: 96/04/24: Altera FLEX10k
3269: 96/05/07: Re: MAX+plusII LPMs, Synthesis Options & AHDL Design Style
3270: 96/05/07: Re: On FPGAs as PC coprocessors
3848: 96/08/08: Re: BIDIR/TRI-STATE busses in Altera AHDL
3883: 96/08/14: Re: 74HC123 MVR modify to TTL CIRCUIT
4084: 96/09/09: Re: FPGA design project
4401: 96/10/24: Re: Searching Demoboard for Altera Flex8000
4968: 97/01/06: Re: I2C Bus Interface in FPGAs
5478: 97/02/19: Re: What is the different between FPGA and CPLD?
5550: 97/02/24: Re: FPGA power dissipation
5551: 97/02/24: Re: Robust Applications with FPGAs
5553: 97/02/24: Re: Xilinx or Altera?
6039: 97/04/07: Re: PCI Bus Problems
7473: 97/09/15: 6809 in FPGA?
Alfred M.:
31485: 01/05/27: ORCAD Capture Symbols
Alfred Rodriguez:
20717: 00/02/18: Re: Logiblox and virtex
Alfredo:
42385: 02/04/22: Re: Xilinx Programmable World 2002 - Review
49505: 02/11/13: why systemc?
49826: 02/11/21: Re: why systemc?
53144: 03/03/04: Re: Mac Os X for FPGA design
56076: 03/05/28: why xflow?
59630: 03/08/25: Enhancing PAR with FPGA floorplanners
59646: 03/08/25: Re: Enhancing PAR with FPGA floorplanners
59700: 03/08/26: Re: Enhancing PAR with FPGA floorplanners
63676: 03/11/28: how to create timing report for all nets?
85905: 05/06/17: Lean Ethernet on Digilent board?
86005: 05/06/20: Re: Lean Ethernet on Digilent board?
86145: 05/06/22: Re: FPGAs: Where will they go?
97152: 06/02/17: Poll: what's would your requirments be for ESL (Electronic System Level) flows?
97160: 06/02/17: Re: what's would your requirments be for ESL (Electronic System Level) flows?
Alfredo Benso:
31722: 01/06/04: Xilinx Configuration Bitstream
Alfredo Rosado:
8454: 97/12/16: Problems with license server for Xilinx M1 and Workview
10442: 98/05/19: Building signal delays inside an FPGA
Alfreeeeed:
128874: 08/02/08: Looking for a development board
128879: 08/02/08: Re: Looking for a development board
128883: 08/02/08: Re: Looking for a development board
128910: 08/02/09: Re: Looking for a development board
128953: 08/02/11: Re: ModelSim versus Active-HDL....redux
129221: 08/02/19: FPGA Programming solution
129227: 08/02/19: Re: FPGA Programming solution
129234: 08/02/19: Re: FPGA Programming solution
129251: 08/02/19: Re: FPGA Programming solution
129285: 08/02/20: Re: FPGA Programming solution
133580: 08/07/04: Re: Serial Pheripheral Interface for XILINX FPGA
133710: 08/07/10: Help with Microblaze timer peripheral
135411: 08/10/01: Post-synthesis simulation
algous:
58247: 03/07/17: Re: Altera ByteBlaster Standalone Programming Utility
59915: 03/09/01: Re: Q:epax1 dma?
63689: 03/11/29: what's the problem?
63690: 03/11/29: MPEG2 decoder
63915: 03/12/08: Q:Altera's excalibur device
64054: 03/12/14: Re: Q:Altera's excalibur device
Ali:
33947: 01/08/09: Question on use of FPGA in a special Data Aquisition system
34094: 01/08/14: Development Boards for FPGA based Application
107923: 06/09/02: I do not know this !
108839: 06/09/18: Little help for Spartan 2 and 3 Programmer
109006: 06/09/19: What is the difference ?
135493: 08/10/05: OTU2 implementation with Virtex 4
135646: 08/10/10: Re: OTU2 implementation with Virtex 4
138316: 09/02/15: ERROR:NgdBuild:604
Ali Ahmadi Naaghed:
50035: 02/11/29: Re: Anybody know of vendors of PCI boards with FPGAs?
ali Benkhalil:
10856: 98/06/25: AHDL
11596: 98/08/25: Image processing Algorithms using Altera HDL
14666: 99/02/09: AHDL & VHDL
14772: 99/02/16: Re: AHDL & VHDL
Ali Dixon:
79621: 05/02/22: virtex II register file
Ali H Ersheid:
1078: 95/04/25: Re: BLIF to XNF translator
Ali Iqbal:
152097: 11/07/05: Re: Verilog Custom Core To Read and Write From RAM
Aliaksei Chapyzhenka:
152162: 11/07/14: Re: Any free timing diagram tools?
<AliBama@gmail.com>:
139104: 09/03/20: Re Zero operand CPUs
139309: 09/03/25: some nibz decoding ?
Alien Zord:
53668: 03/03/19: Re: FPGA specs
Alif Wahid:
101797: 06/05/07: Re: FPGA-based hardware accelerator for PC
101798: 06/05/07: Re: FPGA-based hardware accelerator for PC
101799: 06/05/07: Re: how to set a I/O as 3-state in xilinx =?UTF-8?B?RlBHQe+8nw==?=
101801: 06/05/07: Re: Reset
<aliphas@dspnet.dspnet.com>:
3050: 96/03/21: VirtuaLab on TechOnline to Introduce Remote Code Downloading - Testing
3094: 96/03/31: Eonics Joins TechOnline
alison:
50647: 02/12/15: Matrics Memory controller
50666: 02/12/16: Re: Matrics Memory controller
50671: 02/12/16: Re: Matrics Memory controller
51103: 03/01/01: Re: Matrics Memory controller
59358: 03/08/15: xilinx PAR removing Logic
59365: 03/08/16: Re: xilinx PAR removing Logic
Alissobn Brito:
88851: 05/08/30: Fine grain vs. Coarse Grain Architectures
88875: 05/08/30: Re: Fine grain vs. Coarse Grain Architectures
Alistair Lamb:
81470: 05/03/24: CLOCK__SIGNAL constraint! pls help
Alistair McEwan:
13192: 98/11/19: Content Addressable Memorys
Alistair Webb:
32148: 01/06/15: Virtex II multiplier question
32152: 01/06/15: Re: Virtex II multiplier question
32153: 01/06/15: Re: Virtex II multiplier question
aliumair926:
142617: 09/08/21: FM Broadcast receiver on Lyrtech SFF SDR Kit using vertex 4
Alkos Nikos:
39876: 02/02/21: IIR. convolution
<alkosd@yahoo.co.uk>:
147326: 10/04/22: confusion with ADC/DAC interface implementation
147355: 10/04/23: Re: confusion with ADC/DAC interface implementation
alla:
49094: 02/10/31: FPGA convert to ASIC
allahdadian:
149202: 10/10/07: pci express
149267: 10/10/13: pci didn't recognize pci express
Allan:
100957: 06/04/21: Re: Initializing array of BlockRAM instances in verilog
100973: 06/04/21: Re: Initializing array of BlockRAM instances in verilog
Allan Aasma:
35881: 01/10/22: Problems with writing into text file
Allan Cantle:
29928: 01/03/18: Re: Is there any Virtex-II Evaluation Board?
Allan Herriman:
8140: 97/11/20: Q: HDLC packet size in V5.2
8166: 97/11/24: Re: Q: HDLC packet size in V5.2
9302: 98/03/06: XC4000EX input hysteresis
10920: 98/07/01: Re: I squared C on an FPGA
10991: 98/07/09: Re: Spartan S30 DOUT/SGCK4 pin
11352: 98/08/06: Re: Delay Element for async design.
11298: 98/08/03: Re: How to write a VHDL counter for motion encoder
11475: 98/08/18: Xilinx 4000E Series Ram Problem
11618: 98/08/27: Re: SYNTHESIS TOOLS
11812: 98/09/11: Re: Xilinx Spartan vs. 4K series
11816: 98/09/11: Re: Xilinx Spartan vs. 4K series
11848: 98/09/14: Re: Xilinx Spartan vs. 4K series
11856: 98/09/15: Re: ASIC -> FPGA async issues
11947: 98/09/21: Re: Xilinx Spartan vs. 4K series
12294: 98/10/08: Re: Synthesis: Exemplar or Synopsys
13013: 98/11/11: Re: CCLK on Spartan
15918: 99/04/21: Re: Zero power gals won't wake up on slow input transitions?
16052: 99/04/30: Spartan Metastability parameters
16201: 99/05/10: Re: Spartan Metastability parameters
16208: 99/05/10: Re: Spartan Metastability parameters
16252: 99/05/12: Re: Spartan Metastability parameters
16166: 99/05/07: Re: How do I design this ?
16167: 99/05/07: Re: How do I design this ?
16768: 99/06/08: Q: Spartan XL pull-ups
16798: 99/06/09: Re: Q: Spartan XL pull-ups
16817: 99/06/11: Re: Q: Spartan XL pull-ups
17097: 99/06/30: Re: uLaw and ALaw conversion in an FPGA
17426: 99/07/27: Re: NRZ Deserializing in Virtex
17452: 99/07/29: Re: NRZ Deserializing in Virtex
17489: 99/07/31: Re: Semi-deterministic behaviour in FPGA's
18024: 99/09/24: Re: virtex clock questions
18202: 99/10/07: Re: Altera 10K50V in-rush/temp problem...
18264: 99/10/11: Re: Altera 10K50V in-rush/temp problem...
18393: 99/10/22: Re: Xilinx Orientation Question
18421: 99/10/23: Re: Xilinx Orientation Question
18462: 99/10/26: Re: Delta-Sigma DAC
18469: 99/10/26: Re: Delta-Sigma DAC
18484: 99/10/27: Re: Announcing Free VHDL Simulator for Windows
18571: 99/11/01: Re: Announcing Free VHDL Simulator for Windows
18705: 99/11/09: Re: Need a good Pullup for a VHDL Test Bench
18828: 99/11/18: Re: How to use GSR-net in Virtex?
18958: 99/11/23: Re: VHDL vs. schematic entry
18969: 99/11/23: Re: VHDL vs. schematic entry
19013: 99/11/24: Re: How to use multiple resets?
19690: 00/01/08: Re: Design security
19691: 00/01/08: Re: Xilinx Spartan2
19746: 00/01/11: Re: Virtex Temperature Sensing diode pins DXP, DXN
19857: 00/01/14: Re: Xilinx Spartan2
19932: 00/01/19: Re: Virtex Temperature Sensing diode pins DXP, DXN
19946: 00/01/20: Re: looping FIFO?
20129: 00/01/28: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
20176: 00/01/30: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
20188: 00/01/31: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
20265: 00/02/03: Re: Visualizing EDIF netlist for Xilinx
20291: 00/02/04: Re: Xilinx Virtex Decoupling Cap Guidelines
20427: 00/02/10: Re: Spartan and timing analyzer: clock nets using non-dedicated resources
21172: 00/03/09: Re: SpartanXL route and place
21215: 00/03/10: Spartan 2 Industrial temp range versions
21684: 00/03/29: Virtex bitstreams wanted for compression study
21822: 00/04/02: Re: Virtex bitstreams wanted for compression study
21845: 00/04/04: Re: Virtex bitstreams wanted for compression study
22124: 00/04/26: Re: Virtex bitstreams wanted for compression study
22007: 00/04/12: Re: Clock Dividers
22010: 00/04/12: Re: Clock Dividers
22025: 00/04/13: Re: Parallel to serial
26120: 00/10/05: DLL unlocking
26219: 00/10/09: Re: DLL unlocking
27478: 00/11/23: Re: Clock Skew : Does Xilinx know what they're doing?
28509: 01/01/16: Re: Virtex-II officially launched
28737: 01/01/23: Re: Virtex-II officially launched
28955: 01/01/31: Virtex Engineering Samples timing problem
28978: 01/02/01: Re: 64b/66b gearbox in an FPGA
30328: 01/04/03: Re: pseudo random numbers
30581: 01/04/18: PAR single pass vs multi-pass differences
30605: 01/04/19: Re: PAR single pass vs multi-pass differences
30614: 01/04/19: Re: PAR single pass vs multi-pass differences
30639: 01/04/20: Re: PAR single pass vs multi-pass differences
30778: 01/04/28: Re: BlockRAM outputs and the Placer
30805: 01/04/30: Re: C++ To Gates
30936: 01/05/04: Re: ccd imaging with fpga
31053: 01/05/10: Re: 32 bit limit on integers
31212: 01/05/15: Re: Quad Decoder
31231: 01/05/16: Re: SRAM fpga cell
31521: 01/05/29: Re: xilinx webpack warning !!
31567: 01/05/30: Re: Fun with DLLs.
31589: 01/05/31: Re: Fun with DLLs.
31640: 01/06/01: Re: Xilinx webpack and modelsim
31677: 01/06/02: Re: Xilinx webpack and modelsim
31701: 01/06/04: Re: Xilinx webpack and modelsim
31713: 01/06/04: Re: one state machine
31738: 01/06/05: Re: one state machine
31739: 01/06/05: Re: Virtex LUT4 problems in FPGA Express
31795: 01/06/06: Re: one state machine
31799: 01/06/06: Re: one state machine
31861: 01/06/07: Re: FPGA / starterkit / VHDL
32287: 01/06/22: Re: synplicity 6.2.4 'optimizing' instantiated designs
32303: 01/06/22: Re: synplicity 6.2.4 'optimizing' instantiated designs
32304: 01/06/22: Re: synplicity 6.2.4 'optimizing' instantiated designs
32668: 01/07/04: Re: 8031 microcontroller on FPGA development board :-(
32778: 01/07/09: Re: Simulation problems with BlockRAM's INIT values !
33271: 01/07/21: Re: Modulator Sizing Questions
33632: 01/08/01: Re: finite defect statistics
33913: 01/08/08: Re: Q: Revision and Database Control for FPGA Designs
33944: 01/08/09: Re: Map report question
34037: 01/08/12: Re: Q: Revision and Database Control for FPGA Designs
34056: 01/08/13: Re: Q: Revision and Database Control for FPGA Designs
34065: 01/08/13: Re: Q: Revision and Database Control for FPGA Designs
34091: 01/08/14: Re: Q: Revision and Database Control for FPGA Designs
34127: 01/08/15: Xilinx pin lists in text format
34132: 01/08/15: Re: Q: Revision and Database Control for FPGA Designs
34137: 01/08/15: Re: Xilinx pin lists in text format
34138: 01/08/15: Re: Xilinx pin lists in text format
34177: 01/08/16: Re: Major performance problem with Modelsim
34183: 01/08/16: Re: Replication of FFs in Xilinx XC4000
34190: 01/08/16: Re: Replication of FFs in Xilinx XC4000
34686: 01/09/04: Re: Multi-cycle constraints
34691: 01/09/04: Re: Multi-cycle constraints
35029: 01/09/18: Re: Synplify BUFG instantiation bug
35059: 01/09/20: Re: MCS overflow? promgen and xc2v6000
35170: 01/09/25: Re: comp.arch.fpga : Unusual clock divider ckt
35206: 01/09/26: Re: comp.arch.fpga : Unusual clock divider ckt
35264: 01/09/27: Xilinx UCF Syntax
35356: 01/10/01: Re: Xilinx 4.1 software
35419: 01/10/04: Re: comp.arch.fpga : Unusual clock divider ckt
35443: 01/10/05: Re: comp.arch.fpga : Unusual clock divider ckt
35596: 01/10/11: Re: High level synthesis will never work well :)
35750: 01/10/16: LUT Glitches
35762: 01/10/17: Re: LUT Glitches
35903: 01/10/23: Re: ModelSim SE vs. PE in terms of speed?
35954: 01/10/25: Re: S/PDIF interface for FPGA
36013: 01/10/26: Re: transferring data between related clocks
36015: 01/10/26: Re: S/PDIF interface for FPGA
36338: 01/11/07: Re: Virtex2 gate-level simulation: SDF and timing errors
36404: 01/11/08: Re: Virtex2 gate-level simulation: SDF and timing errors
36465: 01/11/09: Re: Log2(x) for vhdl?
36649: 01/11/14: Re: interleaver delay question
36980: 01/11/28: Re: Creating a jitter free clock
36985: 01/11/28: Re: Creating a jitter free clock
36993: 01/11/28: maximum output current on Spartan2
37039: 01/11/29: Re: maximum output current on Spartan2
37043: 01/11/29: Re: maximum output current on Spartan2
37097: 01/11/30: Re: FPGA startup current
37098: 01/11/30: Re: 128-bit scrambling and CRC computations
37142: 01/12/01: Re: What do you like/dislike about place and route tools?
37183: 01/12/03: Re: 128-bit scrambling and CRC computations
37213: 01/12/04: Re: 128-bit scrambling and CRC computations
37216: 01/12/04: Re: 128-bit scrambling and CRC computations
37951: 01/12/27: Re: vector reversed in netlist of XC9572XL
38208: 02/01/09: Re: Repost: Should clock skew be included for setup time analysis?
38220: 02/01/09: Re: bufg instantiation in ISE 4.1
38303: 02/01/11: Re: multiply (*) 11000000000
38514: 02/01/16: Re: Repost: Should clock skew be included for setup time analysis?
38542: 02/01/17: Re: Repost: Should clock skew be included for setup time analysis?
38693: 02/01/22: Re: Q: can ROM content affect logic syn result
38709: 02/01/22: Re: CRC-32 48bit(width)
38723: 02/01/23: Re: CRC-32 48bit(width)
39158: 02/02/02: Re: Linking IP
39342: 02/02/07: Re: Virtex-II and SDRAM Controller at 133MHz
39347: 02/02/07: Re: Announce: VHDL Simili 2.0 - Graphics, Windows, Linux, Affordable
40379: 02/03/06: Re: FPGA or DSP
40388: 02/03/06: Re: FPGA or DSP in a power supply?
40428: 02/03/07: Re: exceeding 2GB limits in xilinx
40430: 02/03/07: Re: Mutual Clock Synchronization
40497: 02/03/08: Re: exceeding 2GB limits in xilinx
40640: 02/03/12: Re: exceeding 2GB limits in xilinx
40650: 02/03/12: Re: Mystery two wire interface, or am I being dense?
40703: 02/03/13: Re: Mutual Clock Synchronization
40863: 02/03/17: Re: Spartan II IOB tristate control FF use
41051: 02/03/20: Re: VHDL OPEN association element error in QUARTUS compiler
41273: 02/03/24: Re: A petition for Synplify's new fature (FPGA synthesis tool)
41589: 02/04/03: Re: A petition for Synplify's new fature (FPGA synthesis tool)
41603: 02/04/03: Re: A petition for Synplify's new fature (FPGA synthesis tool)
41952: 02/04/11: Re: HDLC Controller Design
42836: 02/05/04: Re: EDIF parser (perl)
43240: 02/05/17: Re: Reading GSR signal of Spartan-II
43293: 02/05/18: Re: Reading GSR signal of Spartan-II
43349: 02/05/20: Re: Reading GSR signal of Spartan-II
43400: 02/05/21: Re: How to generate fractional-N clock ?
43402: 02/05/21: Re: How to generate fractional-N clock ?
43562: 02/05/24: Re: How to generate fractional-N clock ?
43662: 02/05/29: Re: Frequency synthesiser
43765: 02/06/01: Re: place and route simulation time
43774: 02/06/02: Re: place and route simulation time
43797: 02/06/03: Re: place and route simulation time
43873: 02/06/05: Re: place and route simulation time
43924: 02/06/06: Re: PowerPC Architecture
44120: 02/06/12: Re: Digital FM demodulator in FPGA-continue
44178: 02/06/13: Re: Xilinx primitives & ModelSim
44299: 02/06/17: Re: Power supply caps on PCB
44503: 02/06/21: Re: Logic Minimization in Max+Plus II compiler
44537: 02/06/22: Re: Bad Virtex2 devices - any similar experiences
44903: 02/07/05: Re: Macro/Function in VHDL testbench ?
45023: 02/07/10: Re: how to keep info. in RAM during reconfiguration?
45087: 02/07/12: Re: Deterministic Output?
45161: 02/07/14: Re: Deterministic Output?
45603: 02/07/29: Re: timing got worse?
45730: 02/08/02: GSR net skew
45835: 02/08/07: Re: Looking for behavioral Xilinx RAM model
45936: 02/08/12: Re: 485 core
46168: 02/08/20: Re: Xilinx FPGA start-up
46172: 02/08/21: Re: BRAM simulation model error?
46175: 02/08/21: Re: BRAM simulation model error?
46265: 02/08/23: Re: How to include Xilinx library for both ModelSim and Synplify?
46899: 02/09/11: Re: FPGA comes with a DAC?
47022: 02/09/14: Re: Clcok divison : Rational clock divider
47029: 02/09/15: Re: Clcok divison : Rational clock divider
47299: 02/09/23: Re: Xilinx RAM16x1D, Write fails in functional Simulation
47336: 02/09/24: Re: MAP problem: Trivial RPM fails
47338: 02/09/24: Re: writing across a column in an SDRAM
47510: 02/09/27: Re: Is it possible to build a Ring Oscillator in an FPGA chip?
47569: 02/09/29: Re: Why no ROC for Xilinx Verilog sim and synthesis?
47867: 02/10/06: Re: ANN: Embedded processor for Tcl language
48108: 02/10/11: Re: how do initialised signals really get set in Xilinx slices?
48208: 02/10/14: Re: Why can Xilinx sw be as good as Altera's sw?
48260: 02/10/15: Re: GCK as normal IO ?
48323: 02/10/16: Re: GCK as normal IO ?
48540: 02/10/19: Re: Floorplanner RPM. How to use it?
48561: 02/10/21: Re: Floorplanner RPM. How to use it?
48571: 02/10/21: Re: Floorplanner RPM. How to use it?
48628: 02/10/22: Re: Floorplanner RPM. How to use it?
48710: 02/10/23: Re: LCD driver implement with FPGA
48714: 02/10/23: Re: LCD driver implement with FPGA
48774: 02/10/24: Re: LCD driver implement with FPGA
48837: 02/10/25: Re: Please recommend a FPGA chip!
48956: 02/10/28: Re: High Performance FPGA's - Xilinx and ??????
48964: 02/10/28: Re: assigning TIG to a net in VHDL source (Xilinx)
48966: 02/10/28: Re: High Performance FPGA's - Xilinx and ??????
48974: 02/10/28: Re: assigning TIG to a net in VHDL source (Xilinx)
49065: 02/10/31: Re: Chip for fine delays
49110: 02/11/01: Re: How important is simulation?
49115: 02/11/01: Re: Metastability results are finally posted
49117: 02/11/01: FDRE inference in Synplify
49131: 02/11/01: Re: FDRE inference in Synplify
49413: 02/11/12: Re: Quicklogic PAsic problem
49936: 02/11/26: Re: Fast Digital Synthesis Generator
50324: 02/12/09: Re: LFSR question
50325: 02/12/09: Re: virtex 2 temperture sensing with max1617a on DXN and DXP
50724: 02/12/18: Re: A/D converter in FPGA
50763: 02/12/19: Re: Display "real" waves in simulation?
50778: 02/12/19: Re: 16-bit LFSR
50997: 02/12/25: syn_evaleffort attribute
51022: 02/12/26: Re: syn_evaleffort attribute
51076: 02/12/30: Re: what is bus keeper / bus gate.
51215: 03/01/07: Re: Co-simulation of Spice and Vhdl
51505: 03/01/15: Re: Simulate Virtex Primitive using ModelSim
51894: 03/01/25: Re: VHDL or Verilog?
52422: 03/02/09: Re: USB2 or firewire or 100Mb ethernet link to FPGA design
52423: 03/02/09: Re: Virtex-II Pro PowerPC cache memory as main program/data storage?
52424: 03/02/09: Re: LFSR: Galois and Fibonacci
52442: 03/02/10: Re: Virtex-II Pro PowerPC cache memory as main program/data storage?
52544: 03/02/13: Re: Causing Modelsim to break using VHDL code
52583: 03/02/15: Re: Xilinx BRAM enable or wrote
52644: 03/02/18: Re: LFSR: Galois and Fibonacci
53159: 03/03/05: Re: Using Xilinx DCMs out of specifications is not recommended!!!!
53259: 03/03/09: Re: Implementation of latch in FPGA
53489: 03/03/14: Re: RESET --- Synchronous Vs Asynchronous
53496: 03/03/14: Re: RESET --- Synchronous Vs Asynchronous
53924: 03/03/28: Re: Tristate pins + Inputs => External Pullup ?
54131: 03/04/03: Really long vectors in VHDL
54132: 03/04/03: Re: Really long vectors in VHDL
54172: 03/04/04: Re: Really long vectors in VHDL
54392: 03/04/10: Re: Really long vectors in VHDL
54419: 03/04/11: Re: Really long vectors in VHDL
54457: 03/04/11: Re: Really long vectors in VHDL
54459: 03/04/11: Re: Really long vectors in VHDL
54470: 03/04/11: Re: Really long vectors in VHDL
54531: 03/04/13: Re: Really long vectors in VHDL
54556: 03/04/14: Re: Tristate-Bus-Termination; fast pullup req'd
54632: 03/04/15: Re: Search for most relevant FPGA sites on the net
54844: 03/04/21: Re: Very low pin count FPGA
54989: 03/04/24: Re: Challenge: (n mod 3) in hardware???
54991: 03/04/24: Re: Challenge: (n mod 3) in hardware???
54999: 03/04/24: Re: Challenge: (n mod 3) in hardware???
55245: 03/05/02: Re: mcs files
55251: 03/05/02: Re: ModelSim 5.4d eats up memory as the simulation progresses
55330: 03/05/05: Re: PLL chips
55442: 03/05/08: Re: ModelSim 5.4d eats up memory as the simulation progresses
56023: 03/05/28: Re: Why is there a large gulf between CPLD and FPGA?
56046: 03/05/28: Re: Why is there a large gulf between CPLD and FPGA?
56077: 03/05/29: Re: why xflow?
56654: 03/06/11: Re: Pseudo random shift register - > DAC
56711: 03/06/12: Re: Pseudo random shift register - > DAC
56883: 03/06/18: Re: Automatic FPGA testing
57069: 03/06/23: Re: fpga4fun
57122: 03/06/24: Re: fpga4fun
57183: 03/06/25: Re: fpga4fun
57853: 03/07/09: Re: phase noise in NCO
57889: 03/07/09: Re: phase noise in NCO
57894: 03/07/09: Re: Rant mode ON
57896: 03/07/09: Re: How to change Read Only Constraint to Read-Write
57942: 03/07/10: Re: How to change Read Only Constraint to Read-Write
58412: 03/07/23: Re: asynchronous FIFO
58420: 03/07/23: Re: Using Quartus with VHDL
58458: 03/07/24: Re: asynchronous FIFO
58483: 03/07/25: Re: FPGA Editor
58530: 03/07/25: Re: VHDL predefined constants
59417: 03/08/19: Re: DDFS question
59462: 03/08/20: Re: DDFS question
59463: 03/08/20: Re: DDFS question
59625: 03/08/25: Re: TIG Constraint
59627: 03/08/25: Lithium cell on Virtex2 Pro
59671: 03/08/26: Re: Lithium cell on Virtex2 Pro
59680: 03/08/26: Re: Enhancing PAR with FPGA floorplanners
59695: 03/08/26: Re: FPGA minimum operating frequencies
59726: 03/08/27: Virtex2pro "Bufg Exclusivity"
59782: 03/08/28: Re: Lithium cell on Virtex2 Pro
59845: 03/08/29: keep_hierarchy in project manager
59855: 03/08/30: Re: keep_hierarchy in project manager
60091: 03/09/05: Re: New to FPGA, seeking advice, off topic again....
60115: 03/09/05: Re: ISE: use verilog-modules in an vhdl-design-flow
60248: 03/09/09: Re: Sending and receiving Ethernet traffic
60292: 03/09/10: Re: opinions are OK
60522: 03/09/16: 'RSVD' pin on V2/V2P
60587: 03/09/17: Re: 'RSVD' pin on V2/V2P
60599: 03/09/17: Re: spartan3 pin tables
60801: 03/09/23: Re: LUT and Registers in Xilinx Virtex 2
60914: 03/09/25: Re: Configuration Options:
60918: 03/09/25: Re: Configuration Options:
60925: 03/09/25: Re: Configuration Options:
60930: 03/09/25: Re: Configuration Options:
60983: 03/09/26: Re: Graphics rendering
60993: 03/09/26: Re: pullup on inputs
61000: 03/09/26: Re: Graphics rendering
61112: 03/09/29: Re: Xilinx S3 I/O robustness question
61200: 03/09/30: Xilinx XST 6.x and Verilog-2001?
61561: 03/10/07: Re: SDRAM types and availability
61582: 03/10/07: Re: More RPM / RLOC fun
61635: 03/10/08: Re: Visualizing VHDL
61648: 03/10/08: Re: More RPM / RLOC fun
61766: 03/10/10: Re: FPGA/PLD Reliability: High Speeds and Advanced Processes
62196: 03/10/22: Re: 74 logic to CPLD. how easy for a Newbie?
62214: 03/10/22: Re: 74 logic to CPLD. how easy for a Newbie?
62242: 03/10/23: Re: Lattice Mach CPLD - Leonardo Spectrum vs. Synplify
62246: 03/10/23: Re: I Need to Generate a NTSC Signal - Help!
62249: 03/10/23: Re: Strange Timing Problem
62355: 03/10/28: Re: Initializing inferred components with Xilinx ISE Foundation 6
62902: 03/11/11: Re: Reverse engineering an EDIF file?
62978: 03/11/12: Re: Reverse engineering an EDIF file?
63155: 03/11/17: Active-HDL 6.1 pricing
63156: 03/11/17: Re: Active-HDL 6.1 pricing
63194: 03/11/18: Re: Active-HDL 6.1 pricing
63206: 03/11/18: Re: Active-HDL 6.1 pricing
63262: 03/11/19: Re: Active-HDL 6.1 pricing
63263: 03/11/19: Re: Active-HDL 6.1 pricing
63266: 03/11/19: Re: Anyone use HDL as design tool for PCBs?
63471: 03/11/22: Re: Differential terminations in Virtex2 Pro.
63530: 03/11/25: Re: Differential terminations in Virtex2 Pro.
63584: 03/11/26: Re: Slightly unmatched UART frequencies
63642: 03/11/27: Re: DDFS technique problem in generating a few clocks
63673: 03/11/28: Timing Analyzer - delay to die pad or package pin?
63697: 03/12/01: Re: Timing Analyzer - delay to die pad or package pin?
63744: 03/12/03: Re: Exact Timing Constraints vs. Over-Constraining
63791: 03/12/04: Re: Command line in Windows?
63797: 03/12/04: Re: Ideal Development Machine Specifications
63819: 03/12/05: Re: Ideal Development Machine Specifications
63825: 03/12/05: Re: Slightly unmatched UART frequencies
64009: 03/12/12: Re: ISE5.2i strange behavior in PAR (command-line)
64134: 03/12/18: Re: VHDL comments in Vim?
64242: 03/12/22: Re: Hyperthreading vs. Dual proc
64347: 03/12/30: Re: LVPECL_33 to LVPECL_25 (virtex-II pro)
64348: 03/12/30: Re: A difference between VHDL sources working
64492: 04/01/06: Re: Hyperthreading vs. Dual proc
64704: 04/01/12: Re: Synthesis in VHDL vs. Verilog
64743: 04/01/13: Re: Synthesis in VHDL vs. Verilog
64759: 04/01/13: Re: Send Ethernet traffic from an FPGA
64785: 04/01/14: Re: Synthesis in VHDL vs. Verilog
64799: 04/01/15: Re: Synthesis in VHDL vs. Verilog
64802: 04/01/15: Re: Synthesis in VHDL vs. Verilog
64829: 04/01/15: Re: Synthesis in VHDL vs. Verilog
64832: 04/01/15: Re: Send Ethernet traffic from an FPGA
64896: 04/01/16: Re: Spartan-IIE as an ASYNC RAM?
64902: 04/01/16: Re: Spartan-IIE as an ASYNC RAM?
64930: 04/01/17: Re: Spartan-IIE as an ASYNC RAM?
65016: 04/01/19: Re: fpga4fun
65017: 04/01/19: Re: fpga4fun ethernet
65025: 04/01/19: Re: Send Ethernet traffic from an FPGA
65218: 04/01/23: Verilog 2001 indexed part select in XST 6.1.3?
65272: 04/01/23: Re: Random data generator...
65280: 04/01/23: Re: Send Ethernet traffic from an FPGA
65389: 04/01/27: Re: Verilog 2001 indexed part select in XST 6.1.3?
65639: 04/02/04: Re: Tools for developing high-speed interfaces
65658: 04/02/04: Re: Passing user-defined types through the port (global variables??)
65706: 04/02/05: Re: PS/2 Keyboard opencore (keyboard side) available ???
65858: 04/02/09: Re: Virtex-3 PRO
65862: 04/02/09: Re: mixing LVDS data
65910: 04/02/10: Re: VHDL:Dividing a real number by two??
65928: 04/02/10: Re: VHDL:Dividing a real number by two??
66244: 04/02/16: Re: Verilog and VHDL mix
66310: 04/02/17: Re: using fpga for sampling audio
66350: 04/02/18: Re: using fpga for sampling audio
66352: 04/02/18: Re: using fpga for sampling audio
66938: 04/03/02: XST ff merging - how do I "preserve" flip flops
66939: 04/03/02: Re: XST ff merging - how do I "preserve" flip flops
67023: 04/03/04: Re: XST ff merging - how do I "preserve" flip flops
67037: 04/03/04: Re: XST ff merging - how do I "preserve" flip flops
67042: 04/03/04: Re: XST ff merging - how do I "preserve" flip flops
67043: 04/03/04: Re: XST ff merging - how do I "preserve" flip flops
67077: 04/03/05: Re: XST ff merging - how do I "preserve" flip flops
67247: 04/03/09: Re: LVDS
67299: 04/03/10: Re: 66B mode of VirtexII-ProX Rocket I/O
67340: 04/03/11: Re: LVDS
67443: 04/03/12: Re: Answering Machine RAM
67664: 04/03/17: Re: newsgroup on channel coding?
67874: 04/03/22: Re: Why It Is not Recommended to Infer latches in VLSI Design...
68036: 04/03/25: Bug in PACE UCF parser?
68164: 04/03/29: Re: study verilog or vhdl?
68165: 04/03/29: Re: study verilog or vhdl?
68166: 04/03/29: Re: study verilog or vhdl?
68167: 04/03/29: Re: implementing LVDS deserialization using logic
68178: 04/03/29: Re: study verilog or vhdl?
68241: 04/03/31: Re: study verilog or vhdl?
68299: 04/04/01: Replace PPC in V2P with FPGA fabric!
68305: 04/04/01: Re: Replace PPC in V2P with FPGA fabric!
68443: 04/04/05: Re: FPGA pinout
68506: 04/04/07: Re: VHDL: Use of literal '1' on an input port ?
68712: 04/04/15: Re: DDS-Based PLL
68795: 04/04/19: Re: OT: Gigabit Ethernet MAC Throughput
68839: 04/04/20: Re: OT: Gigabit Ethernet MAC Throughput
68890: 04/04/21: Re: VCD file generation
69028: 04/04/26: Re: PLL and DLL
69086: 04/04/27: Re: transport applications
69215: 04/04/30: Re: Can assign same area group to multiple modules?
69381: 04/05/10: Re: VHDL Beginner: Reset a counter (instead of "000000000....000000") - better way ?
69383: 04/05/10: Equivalent Register Removal in XST
69490: 04/05/12: Re: VHDL-Verilog Co-Simulation
69791: 04/05/20: Re: Xilinx V2P: DCM and changing input clock
69878: 04/05/23: Re: Xilinx V2P: DCM and changing input clock
69907: 04/05/25: Re: Xilinx V2P: DCM and changing input clock
70050: 04/05/31: Re: Tool to help detecting race conditions with asych inputs?
70054: 04/05/31: Re: VHDL warning " Feedback mux " from synplify pro ...thx
70055: 04/05/31: Re: VHDL warning " Feedback mux " from synplify pro ...thx
70057: 04/06/01: Re: Serial I/O Standards
70085: 04/06/02: Re: Tool to help detecting race conditions with asych inputs?
70174: 04/06/08: Virtex-4 FX transceiver jitter
70179: 04/06/08: Re: Hardware implementation of the Xilinx configuration CRC generator
70246: 04/06/10: Virtex-4 suggestion: TSMCCCS change
70421: 04/06/16: Re: MGT pin details(Xilinx Virtex 2 PRO)
70458: 04/06/17: Re: Is there a verilog version of PicoBlaze?
70465: 04/06/18: Re: Is there a verilog version of PicoBlaze?
70467: 04/06/18: Re: Is there a verilog version of PicoBlaze?
70503: 04/06/18: Re: Is there a verilog version of PicoBlaze?
70505: 04/06/18: Re: compressing Xilinx bitstreams
70515: 04/06/18: Re: Is there a verilog version of PicoBlaze?
70561: 04/06/21: Re: Is there a verilog version of PicoBlaze?
70673: 04/06/23: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
70710: 04/06/24: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
70736: 04/06/25: Re: open source FPGA tools
70774: 04/06/28: Re: Simulation Tool with Video Display
70888: 04/07/01: Re: *RANT* Ridiculous EDA software "user license agreements"?
70898: 04/07/01: Re: How to prevent MAP from removing floating inputs?
70934: 04/07/02: Re: *RANT* Ridiculous EDA software "user license agreements"?
70943: 04/07/02: Re: Why this statement renders TWO multipliers in XST?
71195: 04/07/12: Re: FPGA to PCI Bus Interface
71201: 04/07/12: Re: Ethernet packet..
71374: 04/07/16: Re: Clock generation
71487: 04/07/20: Re: Using Verilog to embed the synthesis date and time
71598: 04/07/24: Re: XILINX RocketIO / MGT signal quality problems
71627: 04/07/26: Re: 1GHz FPGA counters
71635: 04/07/26: Re: 1GHz FPGA counters
71718: 04/07/29: Re: XILINX RocketIO / MGT signal quality problems
71740: 04/07/29: Re: XST vhdl adder with carry out : broken carry chain
71764: 04/07/30: Disable CDR in MGT
71765: 04/07/30: Re: XST vhdl adder with carry out : broken carry chain
71781: 04/07/30: Re: XST vhdl adder with carry out : broken carry chain
71870: 04/08/03: Re: Clock generator
71936: 04/08/04: Re: Guidelines for Timing Closure on FPGAs
71981: 04/08/05: Re: practical Virtex2 output buffer speeds
71988: 04/08/05: Re: Guidelines for Timing Closure on FPGAs
72339: 04/08/16: Re: Infiniband via RocketIOs (RocketIO, Rocket IO) on Virtex 2 (Virtex2, Virtex II, Virtex-II)
72474: 04/08/20: Re: Announcing JOLT - Yet Another Xilinx Programming Tool
72543: 04/08/24: Re: Ethernet
73769: 04/09/30: Re: Clock Edge notation
72863: 04/09/06: Re: Interfacing an 1GS ADC
72999: 04/09/10: Re: Picoblaze VHDL Code Block diagram
73005: 04/09/10: Re: EDIF generation from Verilog in ISE 6.2i
73100: 04/09/14: Re: clock divider
73264: 04/09/17: Re: Virtex 4 released Monday, and we are still learning about it......
73463: 04/09/22: Re: USER RESET in XILINX FPGA
75091: 04/10/26: Re: Clock Extraction from Bi-Phase Data
75310: 04/11/02: Re: FPGA & DDR-SDRAM
75312: 04/11/02: Re: FPGA & DDR-SDRAM
75317: 04/11/02: Re: Strange XST error in ISE 6.3.02i
75350: 04/11/03: Re: FPGA & DDR-SDRAM
74503: 04/10/13: Re: direct calculation of the modulus ?
74606: 04/10/15: Re: direct calculation of the modulus ?
74804: 04/10/20: Re: spartan 3 on 4 layers
75580: 04/11/10: Re: Research Project Re: Graphics Processor
75853: 04/11/17: Re: ISO Free cores repository
75997: 04/11/22: Re: DDR SDRAM with Xilinx Virtex 2 on self designed PCB
76291: 04/11/30: Re: Pin connection doubts
76295: 04/11/30: Re: Adder Tree Placement
76598: 04/12/07: Re: how to speed up my accumulator ??
76600: 04/12/07: Re: how to speed up my accumulator ??
76656: 04/12/08: Re: how to speed up my accumulator ??
76693: 04/12/09: Re: how to speed up my accumulator ??
76710: 04/12/10: Re: how to speed up my accumulator ??
76748: 04/12/10: Re: how to speed up my accumulator ??
76751: 04/12/10: Re: how to speed up my accumulator ??
76932: 04/12/16: Re: Digital clock synthesis
77090: 04/12/22: Re: Using low-core-voltage devices in industrial applications
77918: 05/01/21: Re: Xilinx constraint question- DC input
78057: 05/01/24: Re: Configuring FPGA using PROM/uP
78059: 05/01/24: Re: How to get 1.8432 MHz out of 24 MHz with Sparten-3?
78078: 05/01/25: Re: How to get 1.8432 MHz out of 24 MHz with Sparten-3?
78283: 05/01/28: Re: Rocket I/O + Optical Fiber
79167: 05/02/16: Re: ATM Cell Payload Scrambler / Descrambler Process Explaination Required
79176: 05/02/16: Re: ATM Cell Payload Scrambler / Descrambler Process Explaination Required
79188: 05/02/16: Re: ATM Cell Payload Scrambler / Descrambler Process Explaination Required
79383: 05/02/18: Re: CRC-4 algorithm using in G.704(&G.706)
79388: 05/02/18: Re: CRC-4 algorithm using in G.704(&G.706)
79486: 05/02/20: Re: hdl:lament
79776: 05/02/24: Re: Looking for some rules of thumb - migrating a discrete 74HCxxx design into an FPGA
95750: 06/01/26: Re: open source fpga programmer programs
96030: 06/01/28: Re: [OT]Re: encryption
96208: 06/02/01: Re: scrambling
96277: 06/02/02: Re: Back to max thermal and power for XC4VLX200's
96321: 06/02/02: Re: Back to max thermal and power for XC4VLX200's
96265: 06/02/02: Re: For our Study We need STM1, 4 , 16 Block diagram where to get it
96322: 06/02/02: Re: BPSK modulation on Xilinx FPGA
96323: 06/02/02: Re: Spartan3 pullups
96825: 06/02/11: Re: Async Processors
96837: 06/02/12: Re: LVDS
96841: 06/02/12: Re: Async Processors
96913: 06/02/14: Re: Async Processors
96915: 06/02/14: Re: PacoBlaze updated
96920: 06/02/14: Re: Async Processors
97197: 06/02/19: Re: equivalent time sampling
97323: 06/02/21: Re: Implementing a two-modulus PLL divider in Altera Stratix II
97324: 06/02/21: Re: Xilinx HardMacro "configurable" ?
97552: 06/02/24: Re: ARCnet interface gate count
97613: 06/02/25: Re: Need a SPI 4?
97614: 06/02/25: Re: System Packet Interface?
97924: 06/03/02: Re: FPGA communication, I2C and DAC
98186: 06/03/07: Re: Vccaux regulator
98187: 06/03/07: Re: what do the following constraints mean?
98207: 06/03/07: Re: Vccaux regulator
98274: 06/03/08: Re: what do the following constraints mean?
98283: 06/03/08: Re: DCM question
98372: 06/03/09: Re: what do the following constraints mean?
98433: 06/03/10: Re: FPGA imple. of aes
98498: 06/03/11: Re: FPGA imple. of aes
98499: 06/03/11: Re: Learning new stuff about FPGA
98500: 06/03/11: Re: Learning new stuff about FPGA
98582: 06/03/14: Re: Doubt on the xilinx Viretex E user guide
98708: 06/03/15: Re: FPGA imple. of aes
98709: 06/03/15: Re: Doubt on the xilinx Viretex E user guide
98716: 06/03/15: Re: FPGA imple. of aes
99068: 06/03/20: Re: Spartan 3 Power Supply Design
99102: 06/03/21: Re: DDS
99108: 06/03/21: Re: FPGA FIR advice
99109: 06/03/21: Re: DDS
99160: 06/03/21: Re: DDS
99170: 06/03/21: Re: DDS
99193: 06/03/22: Re: Ignoring hierachy while flagging false with with Xilinx flow.
99244: 06/03/22: Re: Virtex-4 RocketIO and G.709 OTU-2
99246: 06/03/22: Re: Tisdale?
99400: 06/03/24: Re: Virtex-4 RocketIO and G.709 OTU-2
99542: 06/03/26: Re: OpenSPARC released
99572: 06/03/27: Re: OpenSPARC released
99578: 06/03/27: Re: OpenSPARC released
99612: 06/03/28: Re: OpenSPARC released
99625: 06/03/28: Re: Variable Bus Input/Output Fifo
100194: 06/04/05: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan 3
100437: 06/04/10: Re: Virtex-4 RocketIO and G.709 OTU-2
101341: 06/04/29: Re: Async FPGA ~2GHz
101342: 06/04/29: Re: DRC has announced its newest FPGA that drops into AMD's Socket 940
119719: 07/05/25: Re: Use BRAM as ROM (Xilinx)
119783: 07/05/26: Re: Use BRAM as ROM (Xilinx)
124314: 07/09/19: Looking for fast AES cores with low latency
124355: 07/09/19: Re: Looking for fast AES cores with low latency
124389: 07/09/21: Re: Looking for fast AES cores with low latency
124451: 07/09/22: Re: Looking for fast AES cores with low latency
124514: 07/09/26: Re: Gated Clock Problems
125180: 07/10/17: Re: High level FPGA work flow: available tool?
125978: 07/11/11: Re: ROM (altsyncram) corruption
125980: 07/11/11: Re: ROM (altsyncram) corruption
126509: 07/11/26: Re: Hook open drain "power good" to nSTATUS or nCONFIG?
126511: 07/11/26: Re: Hook open drain "power good" to nSTATUS or nCONFIG?
126512: 07/11/27: Re: Hook open drain "power good" to nSTATUS or nCONFIG?
127025: 07/12/09: Re: DDS generator with interpolated samples for Spartan3E development board
127511: 07/12/31: Re: JTAG chain detects Xilinx FPGA XCV150 instead of XC2S150...
127548: 08/01/02: Re: Where are the LCD or OLED bitmapped displays?
127849: 08/01/09: Re: Real examples of metastability causing bugs
127851: 08/01/10: Re: Real examples of metastability causing bugs
127856: 08/01/10: Re: Real examples of metastability causing bugs
127859: 08/01/10: Re: Real examples of metastability causing bugs
127908: 08/01/11: Re: Real examples of metastability causing bugs
127914: 08/01/11: Re: Multiple UCF support in Xilinx ISE
128036: 08/01/15: Re: Virtex4 burn-in failure
128152: 08/01/17: Re: Basic FPGA question about Reset
128155: 08/01/17: Re: Basic FPGA question about Reset
128281: 08/01/20: Re: Source of accurate frequency
128321: 08/01/22: Re: Source of accurate frequency
128322: 08/01/22: Re: FPGA decoupling calculation
129084: 08/02/14: Re: i need fpga board with 10 Gig interface and pcie interface
129101: 08/02/15: Re: i need fpga board with 10 Gig interface and pcie interface
129778: 08/03/06: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
129782: 08/03/06: Re: Bit Error Rate Test
129783: 08/03/06: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
129791: 08/03/06: Re: Bit Error Rate Test
129792: 08/03/06: Re: Removal of a feature, moving SCD to production
129840: 08/03/07: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
129846: 08/03/07: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
130360: 08/03/21: Re: Synoplify ???
130911: 08/04/05: Re: Xilinx FPGA + SMPS
134682: 08/08/26: Re: need fast FPGA suggestions
135358: 08/09/28: Re: 50 Ohm Analog Output of FPGA
135516: 08/10/06: Re: OTU2 implementation with Virtex 4
135674: 08/10/12: Re: OTU2 implementation with Virtex 4
135930: 08/10/22: Re: Design security
136463: 08/11/18: Re: Aligned PLL clocks in RTL simulation
136589: 08/11/24: Re: hi need help in VHDL code For Input sequence Design
136668: 08/11/30: Re: How to evaluate program efficiency/functionality
136984: 08/12/17: Re: Gigabit Ethernet PHY without NDA?
137023: 08/12/19: Re: FPGA partial/catastrophic failure mode question
137504: 09/01/21: Intel "QuickAssist" FPGA architecture?
138353: 09/02/17: Re: Virtex 5 slave serial config
138375: 09/02/18: Re: Virtex 5 slave serial config
138391: 09/02/19: Re: Virtex 5 slave serial config
138418: 09/02/21: Re: Very fast counter in VirtexII
138467: 09/02/24: Configure FPGA via PCIe
138472: 09/02/24: Re: Configure FPGA via PCIe
138497: 09/02/25: Re: Configure FPGA via PCIe
138519: 09/02/25: Re: Configure FPGA via PCIe
138520: 09/02/25: Re: Configure FPGA via PCIe
138563: 09/02/27: Re: Configure FPGA via PCIe
138572: 09/02/28: Re: Configure FPGA via PCIe
138573: 09/02/28: Re: Configure FPGA via PCIe
139245: 09/03/24: Re: Xilinx XAPP052 LFSR and its understanding
139385: 09/03/28: Re: FIFO controlled loop, PLL, FLL or something else?
139424: 09/03/29: Re: added jitter on FPGAs
139444: 09/03/30: Re: added jitter on FPGAs
140310: 09/05/08: Re: FPGAs and Cryptography
140322: 09/05/08: Re: FPGAs and Cryptography
140367: 09/05/11: Re: difficulty during processing
141040: 09/06/03: Re: Has anyone tried to install a Xilinx floating license? The
141052: 09/06/04: Re: Has anyone tried to install a Xilinx floating license? The
141166: 09/06/10: Re: ISE 11.1
141167: 09/06/10: Re: Xilinx Block RAM Sim
141886: 09/07/15: Re: How to implementa an FSM in block ram
141904: 09/07/16: Re: How to implementa an FSM in block ram
141938: 09/07/18: Re: How to implementa an FSM in block ram
141939: 09/07/18: Re: How to implementa an FSM in block ram
142174: 09/07/28: Re: iCore7 vs Core2 simulation & FPGA tool performance?
142362: 09/08/06: Re: iCore7 vs Core2 simulation & FPGA tool performance?
142409: 09/08/10: Re: iCore7 vs Core2 simulation & FPGA tool performance?
148387: 10/07/17: Re: Drigmorn4 - Spartan-6 Board
149642: 10/11/13: Re: Spartan3 bidirectional 3.3V 5V level shifter
149721: 10/11/21: Re: Multiple Reset Inputs
149723: 10/11/21: Re: Debugging with a single LED
149728: 10/11/21: Re: Multiple Reset Inputs
149836: 10/11/26: idelayctrl vanishes in XST 12.2
150889: 11/02/19: Re: Power nets in Xilinx FPGAs
151309: 11/03/22: SRL as a synchroniser
151325: 11/03/23: Re: SRL as a synchroniser
151395: 11/04/02: Re: Ideal FPGA Development Kit
151399: 11/04/02: Re: Ideal FPGA Development Kit
151607: 11/04/26: Re: same RTL on two same boards giving different behaviour
151788: 11/05/18: Re: Modelsim
151830: 11/05/22: Re: Scoping a glitch
151831: 11/05/22: Re: Scoping a glitch
151838: 11/05/23: Re: Scoping a glitch
152260: 11/07/29: Re: Bitstream compression
152412: 11/08/20: Re: Testbench in verilog ps and human interactions don't mix
152431: 11/08/22: Re: Testbench in verilog ps and human interactions don't mix
153198: 12/01/06: Re: voltage drop on STRATIX FPGA supply planes
153199: 12/01/06: Re: voltage drop on STRATIX FPGA supply planes
153307: 12/01/30: Re: Relative paths in EDK user repository TCL script
153324: 12/02/01: Re: Relative paths in EDK user repository TCL script
153684: 12/04/22: Re: VHDL syntheses timestamp
153688: 12/04/22: Re: VHDL syntheses timestamp
153911: 12/06/29: Re: Modelsim MXE on wine?
154166: 12/08/24: Re: How do you do an incdir in Vivado
154377: 12/10/17: Re: .do files... why?
154491: 12/11/18: Re: Question about TCL command of modelsim
154504: 12/11/20: Re: Question about TCL command of modelsim
154570: 12/11/29: Re: VHDL expert puzzle
154598: 12/11/30: Re: V6 BUFR -> BUFG clocking structure (hold issue?)
154607: 12/12/01: Re: V6 BUFR -> BUFG clocking structure (hold issue?)
154608: 12/12/01: Re: V6 BUFR -> BUFG clocking structure (hold issue?)
154623: 12/12/03: Re: V6 BUFR -> BUFG clocking structure (hold issue?)
154631: 12/12/03: Re: V6 BUFR -> BUFG clocking structure (hold issue?)
154676: 12/12/16: Re: DC fifo behaviour at underflow/overflow
154858: 13/01/19: Re: full tcp offload solution with tcp session setup/teardown
155348: 13/06/24: Re: Pure HDL Xilinx Zynq Arm Instantiation
155482: 13/07/01: Re: USB Download Cable for Lattice Devices
155497: 13/07/02: Re: USB Download Cable for Lattice Devices
155739: 13/08/25: Re: Lattice Announces EOL for XP and EC/P Product Lines
156104: 13/11/23: Re: microZed adventures
156122: 13/12/01: Re: Use of hardware adders with long words to perform multiple
156585: 14/05/05: Re: The USB FPGA?
156592: 14/05/06: Re: The USB FPGA?
156942: 14/08/01: Re: Professional VHDL Examples?
156968: 14/08/08: Re: Basic question: sequence of execution within FPGAs
156988: 14/08/13: Re: Professional VHDL Examples?
157093: 14/10/09: Re: USB PHY recommendations
157443: 14/12/10: Re: VHDL Synchronization- two stage FF on all inputs?
157602: 14/12/27: Re: Prime number in verilog
157604: 14/12/28: Re: Prime number in verilog
157632: 15/01/10: Name this pipelining technique
157635: 15/01/11: Re: Name this pipelining technique
157835: 15/04/10: Re: Division by a constant
158290: 15/10/04: Re: Question about partial multiplication result in transposed FIR
158304: 15/10/07: Re: Question about partial multiplication result in transposed FIR
158351: 15/10/23: Re: DC Blocker
158832: 16/04/25: Re: Deep Embedded Processor Board
158834: 16/04/26: Re: Deep Embedded Processor Board
158835: 16/04/26: Re: Deep Embedded Processor Board
158983: 16/05/31: Re: Explicitly setting a variable to undefined
158991: 16/05/31: Re: Explicitly setting a variable to undefined
159062: 16/07/23: Re: Mod-24: The State of High-Level Synthesis in 2016
159070: 16/07/25: Re: Mod-24: The State of High-Level Synthesis in 2016
159229: 16/09/05: Re: eliminating a DDS
159232: 16/09/05: Re: eliminating a DDS
159328: 16/10/06: Re: xilinx aurora lane order
159332: 16/10/06: Re: xilinx aurora lane order
159358: 16/10/15: Re: CORDIC in a land of built-in multipliers
159388: 16/10/22: Re: Free timing diagram drawing software
159390: 16/10/23: Re: entity component binding issue with configurations
159655: 17/01/26: Re: Anyone use 1's compliment or signed magnitude?
159793: 17/03/04: Re: temperature sense diodes in Xilinx 7 series
159795: 17/03/05: Re: temperature sense diodes in Xilinx 7 series
159802: 17/03/09: Re: temperature sense diodes in Xilinx 7 series
159913: 17/04/25: Re: glitching AND gate
159977: 17/05/04: Re: RISC-V Support in FPGA
159989: 17/05/05: Re: RISC-V Support in FPGA
160028: 17/05/14: Re: increment or decrement one of 16, 16-bit registers
160139: 17/06/20: Re: Create FPGA to replace 1974 MOSTEK MK5017
160226: 17/08/10: Re: sram
160233: 17/08/11: Re: sram
160234: 17/08/11: Re: sram
160335: 17/12/14: Re: FPGA one-shot
160336: 17/12/14: Re: FPGA one-shot
160351: 17/12/15: Re: FPGA one-shot
160355: 17/12/16: Re: FPGA one-shot
160357: 17/12/16: Re: FPGA one-shot
160360: 17/12/18: Re: FPGA one-shot
160362: 17/12/19: Re: FPGA one-shot
161164: 19/02/08: Re: Is it possible to implement Ethernet on bare metal FPGA, Without
161368: 19/06/13: Re: bare-metal ZYNQ
161399: 19/07/04: Re: Unique uses for the DSP48
161415: 19/07/26: Re: New uses of FPGAs
161428: 19/08/11: Re: VHDL TIME support in Vivado
Allan Isfan:
1429: 95/06/21: usable gates quotes from Altera
1719: 95/08/18: Re: Simulation not matching lab results
Allan James Cantle:
16984: 99/06/22: Availability of Parts
17764: 99/09/01: Virtex dev boards
22719: 00/05/19: Traning for Nallatech??
22934: 00/06/04: VirtexE prototype board
ALLAN LIU:
5321: 97/02/06: Xilinx Xact Step Software
Allan Macneil:
2728: 96/01/31: Re: Programming Actels in circuit?
Allan Pedersen:
34760: 01/09/06: Spartan II configuration
Allan Redenbaugh:
7372: 97/09/03: Inferring RAM for Xilinx
9324: 98/03/06: Whats wrong with this method
23787: 00/07/08: Re: division in FPGA - help !
Allan Wang:
150257: 11/01/06: Cheap Altera dev board with LVDS-compatible connector?
150283: 11/01/07: Re: Cheap Altera dev board with LVDS-compatible connector?
150770: 11/02/09: Re: Good FPGA dev kit for a student who is not a complete newbie?
150773: 11/02/10: Re: Good FPGA dev kit for a student who is not a complete newbie?
Allan Willcox:
86691: 05/07/04: EDK 6.3, Xilinx ML40x ML402, XBD files
86892: 05/07/08: Re: EDK 6.3, Xilinx ML40x ML402, XBD files
<allan.herriman@gmail.com>:
138539: 09/02/26: Re: Configure FPGA via PCIe
<allanca@gmail.com>:
100917: 06/04/21: Initializing array of BlockRAM instances in verilog
<allanherriman@hotmail.com>:
86081: 05/06/21: Re: TDM over Aurora
86296: 05/06/24: Re: How do I convert a polynomial into a parallel scrambler formula?
86430: 05/06/27: Re: Good FPGA for an encryptor
86435: 05/06/28: Re: Good FPGA for an encryptor
86560: 05/06/29: Re: ADPLL for NRZ
87316: 05/07/21: Re: Optimizing out a divide on altera cyclone fpga
87375: 05/07/22: Re: Optimizing out a divide on altera cyclone fpga
88182: 05/08/11: Re: Delays in verilog
89011: 05/09/02: Re: Multidimensional port.
89345: 05/09/13: Re: several ucf files?
90352: 05/10/10: Re: iVerilog / VVP output to GTKwave.
90353: 05/10/10: Re: 64 bit processor for FPGA workstation?
91232: 05/11/01: Re: Virtex4 temperature-sensing feature... does it work?
91516: 05/11/07: Re: What does the IP in IPCORE stand for?
91783: 05/11/13: Re: Bitstream compression
91797: 05/11/13: Re: i2c slave does not acknowlege
91857: 05/11/15: Re: RoHS
92006: 05/11/19: Re: Oh no! Resets Again? Yes, but it could be important.
92013: 05/11/19: Re: Oh no! Resets Again? Yes, but it could be important.
92016: 05/11/19: Re: Oh no! Resets Again? Yes, but it could be important.
92108: 05/11/22: Re: Disabling Xilinx clock enable usage...
92109: 05/11/22: Re: Disabling Xilinx clock enable usage...
92130: 05/11/22: Re: Disabling Xilinx clock enable usage...
92163: 05/11/23: Re: Case expression?
92164: 05/11/23: Re: Case expression?
92170: 05/11/23: Re: Case expression?
92172: 05/11/23: Re: Case expression?
92282: 05/11/25: Re: XST :division and mod in vhdl
92473: 05/11/30: Re: ISE Simulator not present in Linux?
92478: 05/11/30: Re: ISE Simulator not present in Linux?
92612: 05/12/02: Re: Curious about FPGAs
93236: 05/12/16: Re: Simulating CRC32 according to IEEE Std. 802.3
93636: 05/12/27: Re: IEEE package VHDL reference manual
94187: 06/01/06: Re: CRC error correction
95665: 06/01/25: Re: encryption
95678: 06/01/25: Re: encryption
95711: 06/01/25: Re: encryption
95679: 06/01/25: Re: encryption
95686: 06/01/25: Re: encryption
95681: 06/01/25: Re: open source fpga programmer programs
Allard:
136138: 08/11/03: Testing ARM/FPGA with IAR EWARM and ModelSim (with Tcl Interface)
136140: 08/11/03: Re: Why does Nios cannot pass make?
allard jean-marc:
8536: 98/01/06: Re: SDRAM model
10110: 98/04/27: Re: Enforcing Clock Enable Connection in Synthesis
10126: 98/04/28: Re: Enforcing Clock Enable Connection in Synthesis
11845: 98/09/13: Re: A Linear Feedback Shiftregister
allen:
151385: 11/03/31: Ideal FPGA Development Kit
151660: 11/05/03: Win an Altera DE0-Nano (Cyclone IV Dev Kit)!
151701: 11/05/06: Re: Win an Altera DE0-Nano (Cyclone IV Dev Kit)!
Allen:
117118: 07/03/23: EDK and Custom Peripheral: error occur when generating bitstream
117162: 07/03/24: Re: EDK and Custom Peripheral: error occur when generating bitstream
117353: 07/03/28: Re: EDK and Custom Peripheral: error occur when generating bitstream
117825: 07/04/11: Re: EDK and Custom Peripheral: error occur when generating bitstream
118058: 07/04/17: Re: EDK and Custom Peripheral: error occur when generating bitstream
119142: 07/05/13: Re: EDK and Custom Peripheral: error occur when generating bitstream
121115: 07/06/25: Coding style of verilog for FPGA synthesis
121257: 07/06/29: Re: Coding style of verilog for FPGA synthesis
Allen - Celeritous:
47701: 02/10/02: Re: AMD9513 Timer Chip
Allen Litton:
22833: 00/05/25: Re: 8087 in FPGA?
Allen Middleton:
16997: 99/06/22: Re: combining multiple xilinx designs into one
Allen Norskog:
15031: 99/03/03: Bidirectional buffers with Orca?
<alleynb@gmail.com>:
123267: 07/08/22: ML401 (Virtex 4 development board) as a USB peripheral
123291: 07/08/22: Re: ML401 (Virtex 4 development board) as a USB peripheral
124215: 07/09/14: post translate and post PAR problems with XST and Modelsim
Allison:
12964: 98/11/08: Re: New free FPGA CPU
allsey87:
148118: 10/06/22: ASIC solution to UVC and FPGA interconnectivity
148119: 10/06/22: Re: ASIC solution to UVC and FPGA interconnectivity
150902: 11/02/20: Is fixed point (ieee_proposed.fixed_pkg_c) supported by XST for
150903: 11/02/20: Re: PLD suggestions for classroom use
<alm@mlnk.com>:
5272: 97/02/03: Re: Suggestions how wire wrap mount a Xilinx PG223
almerima:
30591: 01/04/18: Acces of JTAG port of the FPGA (XSV Board)
almost_a_gnome:
41899: 02/04/10: shift registers using virtex block RAM
41905: 02/04/10: Initializing the ram values on virtex.
42226: 02/04/18: Addressing Error Ram on Virtex E.
Alois HAHN:
15834: 99/04/16: How to write BIDIR IO in MAXPLUS2 VHDL ?
15838: 99/04/16: Re: How to write BIDIR IO in MAXPLUS2 VHDL ?
15891: 99/04/19: Re: How to write BIDIR IO in MAXPLUS2 VHDL ?
Alois Huber:
78544: 05/02/03: How to handle clock skew?
ALOK SAHOO:
26783: 00/10/29: Re: Fpga vs. ASIC
26784: 00/10/29: Re: Fpga vs. ASIC
Alon Hazay:
4804: 96/12/17: FPGA market overview
Alon Z:
51267: 03/01/09: In-Rush current in Stratix device
alonzo:
73750: 04/09/29: Read back FPGA configuration
73868: 04/09/30: Re: Read back FPGA configuration
74275: 04/10/06: JBits and Spartan
74277: 04/10/06: Re: Advice for a Beginner?
133469: 08/06/30: Re: on FRAME_ECC_VIRTEX4 functionality
133470: 08/06/30: Re: FIR filter with integer coefficients
139461: 09/03/30: initialize BRAM contents
139464: 09/03/30: Re: initialize BRAM contents
139956: 09/04/20: Re: initialize BRAM contents
Alonzo Vera:
72892: 04/09/07: Re: PDSPs vs FPGAs for DSP
alpha:
12960: 98/11/07: FPGA VGA interface
12969: 98/11/08: Re: FPGA VGA interface
13352: 98/11/29: Re: Will XILINX survive?
84805: 05/05/27: Hard Ethernet MAC for Virtex-4 FX12
86146: 05/06/22: ISE 7.1 - block memory init value issue during simulation
86309: 05/06/24: Re: ISE 7.1 - block memory init value issue during simulation
86475: 05/06/28: APEX 20K PLL
86639: 05/07/01: Re: APEX 20K PLL
88536: 05/08/22: ISE7.1i SP3, Dual port block ram, coregen issue
88562: 05/08/22: Re: ISE7.1i SP3, Dual port block ram, coregen issue
102631: 06/05/18: Re: Superscalar Out-of-Order Processor on an FPGA
102747: 06/05/19: Re: Superscalar Out-of-Order Processor on an FPGA
102900: 06/05/22: Re: Superscalar Out-of-Order Processor on an FPGA
102941: 06/05/23: Re: Superscalar Out-of-Order Processor on an FPGA
103164: 06/05/26: Re: Superscalar Out-of-Order Processor on an FPGA
148578: 10/08/03: Re: DMA operation to 64-bits PC platform (continued)
alphaboran:
68442: 04/04/05: FPGA pinout
Alphaboran:
52260: 03/02/05: Xilinx Foundation 5.1: reasons to upgrade
52354: 03/02/07: blockram initialization
52381: 03/02/07: Re: Xilinx Foundation 5.1: reasons to upgrade
52454: 03/02/10: Re: blockram initialization
55874: 03/05/22: Change the value of a register in an implemented design
<Alpharomeo2k@gmx.de>:
83252: 05/04/26: Re: A PC for make synthesis
83254: 05/04/26: Re: A PC for make synthesis
<already5chosen@yahoo.com>:
100229: 06/04/05: burstcount support in Quartus SOPC Component Editor
103242: 06/05/29: Fast Serial I/O on Virtex-5
111882: 06/11/12: SOPC builder/Nios2: booting from custom NV-RAM
111930: 06/11/13: Re: Pad to Setup, Clock to Pad
111934: 06/11/13: Re: Pad to Setup, Clock to Pad
111947: 06/11/13: Re: I look for a wideband SERDES chip
112252: 06/11/18: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112256: 06/11/18: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112358: 06/11/21: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112379: 06/11/21: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
117615: 07/04/04: Re: Implementing a communication protocol for data transfer over TCP on an FPGA
134772: 08/08/29: Re: Future architectures [was Re: Intel details future Larrabee ...]
155619: 13/07/30: Re: Lattice Announces EOL for XP and EC/P Product Lines
155742: 13/08/25: Re: Lattice Announces EOL for XP and EC/P Product Lines
155758: 13/08/28: Re: Lattice Announces EOL for XP and EC/P Product Lines
155767: 13/08/29: Re: Lattice Announces EOL for XP and EC/P Product Lines
156503: 14/04/11: Re: cloud design flow
156522: 14/04/14: Re: Actel Designer on multiple cores
156596: 14/05/07: Re: The USB FPGA?
156641: 14/05/19: Re: How to reduce "Core static thermal dissipation" from fpga design
156858: 14/07/11: Re: Using FPGA as dual ported ram
156866: 14/07/12: Re: Using FPGA as dual ported ram
156877: 14/07/15: Re: Using FPGA as dual ported ram
156881: 14/07/15: Re: Using FPGA as dual ported ram
156919: 14/07/28: Re: Primitive debuggable UART interface to a Nios within a multi-Nios system
156921: 14/07/28: Re: Primitive debuggable UART interface to a Nios within a multi-Nios system
156922: 14/07/28: Re: Primitive debuggable UART interface to a Nios within a multi-Nios system
156925: 14/07/29: Re: Primitive debuggable UART interface to a Nios within a multi-Nios system
156926: 14/07/29: Re: Primitive debuggable UART interface to a Nios within a multi-Nios system
156930: 14/07/29: Re: Primitive debuggable UART interface to a Nios within a multi-Nios system
156935: 14/07/30: Re: Primitive debuggable UART interface to a Nios within a multi-Nios system
157822: 15/04/02: Re: Intel in Talks to buy Altera
157824: 15/04/02: Re: Intel in Talks to buy Altera
157827: 15/04/05: Re: Intel in Talks to buy Altera
159100: 16/07/28: Re: Vivado parses wicked slow
159111: 16/08/02: Re: Vivado parses wicked slow
159113: 16/08/03: Re: Vivado parses wicked slow
159116: 16/08/04: Re: Vivado parses wicked slow
159120: 16/08/04: Re: Vivado parses wicked slow
159123: 16/08/06: Re: Vivado parses wicked slow
159124: 16/08/07: Re: Vivado parses wicked slow
159125: 16/08/07: Re: Vivado parses wicked slow
159171: 16/08/28: Re: Low End FPGAs
159245: 16/09/07: Re: eliminating a DDS
159274: 16/09/20: Re: requirement for PC for VHDL design
159275: 16/09/20: Re: requirement for PC for VHDL design
159276: 16/09/20: Re: requirement for PC for VHDL design
159281: 16/09/21: Re: requirement for PC for VHDL design
159286: 16/09/22: Re: requirement for PC for VHDL design
159292: 16/09/25: Re: requirement for PC for VHDL design
159347: 16/10/14: Re: CORDIC in a land of built-in multipliers
159348: 16/10/14: Re: CORDIC in a land of built-in multipliers
159741: 17/02/17: Re: Intel (Altera) announces Cyclone-10
159743: 17/02/17: Re: Intel (Altera) announces Cyclone-10
159748: 17/02/18: Re: Intel (Altera) announces Cyclone-10
160391: 18/01/10: Re: HDL simple survey - what do you actually use
160550: 18/03/24: Re: Microsemi now Microchip
160639: 18/07/04: Re: 8 bits vs. 9 bits in RAM Blocks
160764: 18/11/24: Re: New(ish) FPGA Company
160766: 18/11/25: Re: New(ish) FPGA Company
160768: 18/11/25: Re: New(ish) FPGA Company
160770: 18/11/26: Re: New(ish) FPGA Company
160776: 18/11/26: Re: New(ish) FPGA Company
161150: 19/02/06: Re: Altera Cyclone replacement
161151: 19/02/06: Re: Altera Cyclone replacement
161153: 19/02/07: Re: Is it possible to implement Ethernet on bare metal FPGA, Without
161154: 19/02/07: Re: Is it possible to implement Ethernet on bare metal FPGA, Without
161158: 19/02/07: Re: Altera Cyclone replacement
161159: 19/02/07: Re: Is it possible to implement Ethernet on bare metal FPGA, Without
161161: 19/02/07: Re: Altera Cyclone replacement
161167: 19/02/08: Re: Is it possible to implement Ethernet on bare metal FPGA, Without
161173: 19/02/14: Re: Altera Cyclone replacement
161175: 19/02/14: Re: Altera Cyclone replacement
161178: 19/02/14: Re: Altera Cyclone replacement
161184: 19/02/23: Re: Cyclone V decimation
161224: 19/03/19: Re: Tiny CPUs for Slow Logic
161230: 19/03/19: Re: Tiny CPUs for Slow Logic
161238: 19/03/19: Re: Tiny CPUs for Slow Logic
161245: 19/03/20: Re: Tiny CPUs for Slow Logic
161246: 19/03/20: Re: Tiny CPUs for Slow Logic
161248: 19/03/20: Re: Tiny CPUs for Slow Logic
161252: 19/03/20: Re: Tiny CPUs for Slow Logic
161255: 19/03/20: Re: Tiny CPUs for Slow Logic
161264: 19/03/20: Re: Tiny CPUs for Slow Logic
161268: 19/03/21: Re: Tiny CPUs for Slow Logic
Also-Antal Csaba:
16190: 99/05/08: Re: BGA Prototyping ?
16740: 99/06/05: Red-Solomon enc/decoder
18030: 99/09/24: test
18022: 99/09/24: only test
18318: 99/10/14: test
Alt Torsten:
69515: 04/05/12: APEX20KE PPA configuration error
Alta Technology:
185: 94/09/15: Looking for Altera's FTP site
Altec:
alten:
26336: 00/10/12: Category : Subject
Altera User:
119867: 07/05/28: Quartus-II 7.1 Systemverilog interface?
120078: 07/05/31: Re: Quartus-II 7.1 Systemverilog interface?
120290: 07/06/05: Re: Quartus-II 7.1 Systemverilog support define `` ?
Altera User #1:
472: 94/11/29: Does a digital comparator use 9 Mcells in Altera's 5000?
<altera_smells@hotmail.com>:
90012: 05/10/01: Re: altera new bee
91920: 05/11/16: Cyclone II and Stratix II dual ports are dead
92299: 05/11/26: RocketChips?
92302: 05/11/26: Re: Cyclone II and Stratix II dual ports are dead
92381: 05/11/28: Re: XC4VFX20 samples
alterauser:
106911: 06/08/22: Re: Video - DSP Eval board with Altera
106915: 06/08/22: Using multi-cycle contraint and simulate it correctly
106995: 06/08/23: Re: Video - DSP Eval board with Altera
106996: 06/08/23: Re: Using multi-cycle contraint and simulate it correctly
107711: 06/08/31: Re: fastest FPGA
107793: 06/09/01: Re: How to active a disappeared HDL source file in the project of ISE webpack
108103: 06/09/05: Exploring Quartus' Messages and Warnings
108159: 06/09/06: Re: Exploring Quartus' Messages and Warnings
108184: 06/09/06: Re: How to bound a Cores generated output in Modelsim
108192: 06/09/06: Re: How to bound a Cores generated output in Modelsim
108193: 06/09/06: Re: Exploring Quartus' Messages and Warnings
108205: 06/09/06: Re: How to bound a Cores generated output in Modelsim
108257: 06/09/07: Re: Exploring Quartus' Messages and Warnings
108286: 06/09/07: Re: Altera simulation model
108366: 06/09/09: FPGA Devices' stability and process parameters
108631: 06/09/14: Re: downloading bitstream on FPGA
108827: 06/09/17: Re: Spartan3: Multiplier Madness
109416: 06/09/26: Re: QuartusII: how to find out all the instances of a VHDL module in a design?
111658: 06/11/07: Re: Should I use an external synthesis tool?
111811: 06/11/10: Re: Non deterministic behaviour in quartus II ?
111900: 06/11/12: Re: SPI module in FPGA
113082: 06/12/06: Re: Altera starter kits
113276: 06/12/10: Re: JTAG programming of Altera Cyclone and CONF_DONE
113277: 06/12/10: linking two fpga boards
113377: 06/12/12: Re: linking two fpga boards
113564: 06/12/16: Re: Xilinx ISE 8.2.3 - Re-Creating Projects
Altogether_Andrews:
49319: 02/11/09: Has anyone tried Lattice's chips?
49321: 02/11/09: Re: functional test for Xilinx virtex II Pro
49322: 02/11/09: Re: glue logic device
49323: 02/11/09: Re: 250MHz Data Bus connected directly to Xilinx Virtex-II
<altras@yahoo.com>:
92363: 05/11/28: Re: Difficulty compiling on Quartus 2 version 5
<aludwin@altera.com>:
130396: 08/03/21: Re: ISE 10.0 finally with multi-threading and SV support ?
130451: 08/03/24: Re: ISE 10.0 finally with multi-threading and SV support ?
Alun:
22682: 00/05/17: Xilinx USB Multilinx download verrrrrrry slow
22683: 00/05/17: Re: Xilinx USB Multilinx download verrrrrrry slow
22905: 00/05/31: 1 minute to download a Virtex xcv1000!
23259: 00/06/19: Re: cpld
23566: 00/06/30: Re: Problem with uploading in XC95288 using ISP with HW-JTAG-PC
23659: 00/07/04: Re: Programming Virtex with the MultiLINX cable
23774: 00/07/07: Re: calculating modulo N
23775: 00/07/07: Re: Problem with XC95288 using JTAG with HW-JTAG-PC
23989: 00/07/19: Re: FPGAs in AC Magnetic Field
24151: 00/07/27: Re: Ya tengo mi correo @barcelona.com 4982
24219: 00/07/30: Virtex SelectMAP download from CPU problem
24802: 00/08/18: Re: multiplying DLL in Virtex
25551: 00/09/13: Re: Virtex 1800 series ISP proms
25721: 00/09/18: Re: Virtex clock fanout
25722: 00/09/18: system-gates and system-bytes
25980: 00/09/28: Re: hdl
26157: 00/10/05: Re: Category : virtex e I/O bank contention
26386: 00/10/13: Re: 5V compatible Virtex
28214: 00/12/31: Re: XC9500 and unused inputs
Alun Harford:
79399: 05/02/18: Re: Make program stop
79433: 05/02/18: Re: Make program stop
79817: 05/02/24: Re: Multiple additions
Alun Morris:
12305: 98/10/08: Re: Help Desperately Needed with Altera Microprocessor Design.
16118: 99/05/04: Re: Dynamic Reconfiguration
16117: 99/05/04: Re: Any Material on advances in FPGA Technology
ALuPin:
63091: 03/11/14: Re: Local nodes are not visible anymore after simulation (Altera Quartus II )
63730: 03/12/02: Design analyse methods
63839: 03/12/05: VHDL-Testbench-Simulation in QuartusII
63892: 03/12/07: Re: VHDL-Testbench-Simulation in QuartusII
64055: 03/12/14: Re: VHDL-Testbench-Simulation in QuartusII
64090: 03/12/15: Re: VHDL-Testbench-Simulation in QuartusII
64450: 04/01/05: Adding internal signals in MODELSIM
64459: 04/01/05: Something additional: Adding internal signals in MODELSIM
64496: 04/01/05: Re: Something additional: Adding internal signals in MODELSIM
64756: 04/01/13: Simulation model for UTMI available ?
64856: 04/01/15: Port mapping a Verilog component in a VHDL design
64909: 04/01/16: Simulating USB2.0Transceiver
65021: 04/01/18: Memory Initialization Files in Modelsim
65080: 04/01/19: Re: Memory Initialization Files in Modelsim
65081: 04/01/20: Re: Memory Initialization Files in Modelsim
65144: 04/01/21: Re: Memory Initialization Files in Modelsim
65927: 04/02/10: Synchronization of signals
66005: 04/02/11: Re: Synchronization of signals
66006: 04/02/11: .mif or .hex memory files?
66161: 04/02/13: Use of memory bits in QuartusII
66371: 04/02/18: Re: regarding synchronization
66414: 04/02/19: Simulation MODEL for SRAM
66568: 04/02/22: Barrel shifter synthesis in QuartusII
66629: 04/02/24: SRAM bidirectional bus
66933: 04/03/01: SRAM Controller Problems
67178: 04/03/07: Re: SRAM Controller Problems
67200: 04/03/08: SRAM timing simulation
67308: 04/03/10: Minimum VCO frequency correct?
67633: 04/03/16: Schematic Editor in QuartusII version4.0
67751: 04/03/18: Problems with Memory Initialization Files in Modelsim
67790: 04/03/19: Re: Problems with Memory Initialization Files in Modelsim
67891: 04/03/22: Synchronization of data
67987: 04/03/24: Timing Problem
68038: 04/03/24: Re: Synchronization of data
68039: 04/03/25: Switching clocks in FPAG internal clock trees
68091: 04/03/26: USB Traffic Generation for FPGA Test
68175: 04/03/28: Re: USB Traffic Generation for FPGA Test
68511: 04/04/07: Accesing a procedure
68802: 04/04/19: SRAM Controller
68925: 04/04/22: Re: SRAM Controller
69093: 04/04/27: FMF library
69099: 04/04/27: VHDL simulation models from Alliance Semiconductors
69390: 04/05/10: How to perform a timing simulation in Modelsim with QuartusII output file ?
69425: 04/05/10: Re: How to perform a timing simulation in Modelsim with QuartusII output file ?
69645: 04/05/17: Phase alignment
69686: 04/05/18: Quality of timing simulation
69731: 04/05/19: Inversion of signals on synthesis
69940: 04/05/25: Re: What can I do if my chip can't meet timing?
69980: 04/05/25: Re: Read/Write data from/to SRAM
70348: 04/06/14: Re: How to obtain original input/output signal name from SDF Timing Simulation within Modelsim?
70384: 04/06/15: Content of RAM
70388: 04/06/15: Library Mapping
70459: 04/06/17: Altera unable to respond
70614: 04/06/22: Unused signals in Modelsim
70616: 04/06/22: Synthesis of loops
70785: 04/06/28: Programming Altera Devices
70905: 04/07/01: Re: Programming Altera Devices
71025: 04/07/05: Re: crc32 vhdl implementation (4 bit data)
71057: 04/07/06: Re: crc32 vhdl implementation (4 bit data)
71204: 04/07/12: Programable Logic & Video stuff
71206: 04/07/12: Re: FIR filter running out of FPGA memory in stratix ep1s60
71460: 04/07/19: PLL phase after compensation
71492: 04/07/20: Re: PLL phase after compensation
71527: 04/07/21: Changing directory name in Quartus
71562: 04/07/21: Re: Changing directory name in Quartus
71634: 04/07/26: Cyclone Memory Development Board
71640: 04/07/26: Re: Gate Count vs Logic Element (LE)
71642: 04/07/26: Switching clocks in Xilinx / Altera devices
71673: 04/07/27: Re: Cyclone Memory Development Board
71703: 04/07/28: Choosing PLL
71751: 04/07/29: Problems with device
71753: 04/07/29: Re: connecting entities
71776: 04/07/30: Re: Problems with device
71845: 04/08/02: Re: Problems with device
72547: 04/08/24: DDR SDRAM
72570: 04/08/25: Re: DDR SDRAM
72635: 04/08/27: Re: DDR SDRAM
72815: 04/09/02: Re: reg: clock generatred by combinational logic
73755: 04/09/29: Content of RAM in Modelsim
73767: 04/09/29: Clock Edge notation
73849: 04/09/30: Enabling clock generation
72864: 04/09/06: VHDL modelling USB device
72877: 04/09/06: Re: VHDL modelling USB device
72917: 04/09/07: Re: VHDL code for 16-32 bit counter for quadrature encoder signals (A-B)
72925: 04/09/08: SignalTapII influencing timing of design?
73233: 04/09/16: Twister + Lancelot
73395: 04/09/21: Getting started with Altera IP Core
73396: 04/09/21: Tcl script window does not appear
73454: 04/09/22: Re: Tcl script window does not appear
75094: 04/10/26: Using Sync Reset as Async Reset
75102: 04/10/26: Re: unstable fpga design
75171: 04/10/27: Re: unstable fpga design
74160: 04/10/05: Archiving QuartusII project
74207: 04/10/05: Ripple counter ?
74218: 04/10/06: Changing clock domain
74232: 04/10/06: Re: Ripple counter ?
74233: 04/10/06: Re: Ripple counter ?
74279: 04/10/07: Re: Ripple counter ?
74284: 04/10/07: Unused pins
74296: 04/10/07: Re: Ripple counter ?
74330: 04/10/08: Re: Ripple counter ?
74413: 04/10/10: Routing PLL output
74464: 04/10/12: Re: Routing PLL output
74525: 04/10/13: Re: Routing PLL output
74561: 04/10/13: Re: Routing PLL output
74619: 04/10/14: Re: Routing PLL output
74739: 04/10/18: Internal Capture of clock in FPGA
74790: 04/10/19: Feeding PLL
74853: 04/10/20: Back-Annotate Assignments
75359: 04/11/03: Re: FPGA/CPLD Basics
75547: 04/11/09: Accessing rows in bank
75624: 04/11/11: Problem with PLL ?
75638: 04/11/11: Re: Problem with PLL ?
75690: 04/11/12: Demote assignments
75776: 04/11/15: Re: Demote assignments
75792: 04/11/15: LPM_MODOLUS warning
75820: 04/11/16: Re: LPM_MODOLUS warning
75821: 04/11/16: Re: Problem with PLL ?
75924: 04/11/19: Re: NIOSII problems?
76128: 04/11/25: Re: SDRAM Concurrent auto precharge
76387: 04/12/01: Controller Interface
76659: 04/12/08: Modelsim Directory
76757: 04/12/10: 30bit - adder performance improvement
77316: 05/01/04: Procedure exit on global signal
77607: 05/01/12: Lattice DDR Interface
77693: 05/01/14: Resetting FIFO
77827: 05/01/18: Timing Assignments in Cyclone/Stratix
77829: 05/01/18: Input clock of PLL
78223: 05/01/26: Input registers in ispLEVER
78442: 05/02/01: Synchronizing multibit bus
78462: 05/02/01: Synchronizing multibit bus - 2
78798: 05/02/08: Retaining not used nodes
78863: 05/02/09: Resetting FIFO
78883: 05/02/09: Global clock as input of a FF
78942: 05/02/10: Virtual Pins in QuartusII
80766: 05/03/11: Over-Sampling
81622: 05/03/28: Re: Initializing Altera MEGARAMs in simulation
81692: 05/03/29: Re: Initializing Altera MEGARAMs in simulation
81804: 05/04/01: Hierarchy in Schematic-VHDL Design
82642: 05/04/15: Functional vs, Timing
82791: 05/04/18: Odd Oversampling
82874: 05/04/19: Re: Odd Oversampling
82889: 05/04/19: Re: Odd Oversampling
82943: 05/04/20: Re: Odd Oversampling
82957: 05/04/20: Bug in DDR template in Lattice FPGAs ?
82985: 05/04/21: Re: Bug in DDR template in Lattice FPGAs ?
83046: 05/04/22: Re: Bug in DDR template in Lattice FPGAs ?
83047: 05/04/22: Re: CAM for FPGA ...
83049: 05/04/22: ispTRACY-Lattice vs. SignalTap-Altera
83150: 05/04/25: Re: Bug in DDR template in Lattice FPGAs ?
83162: 05/04/25: Re: "Correct design" and practical trouble and simulation trouble but why
83214: 05/04/26: Sync + FIFO
83287: 05/04/27: Re: Sync + FIFO
83355: 05/04/28: Re: Bug in DDR template in Lattice FPGAs ?
83360: 05/04/28: Signal use from pin
83522: 05/05/02: Re: crazy behaviour of fpga, timing ?
ALuPin@web.de:
91931: 05/11/17: Trying to define Opendrain Outputs
91935: 05/11/17: Re: Trying to define Opendrain Outputs
91966: 05/11/18: Re: Trying to define Opendrain Outputs
92861: 05/12/08: Re: Post PAR Simulation and Actual FPGA results differ
93128: 05/12/14: Simulating CRC32 according to IEEE Std. 802.3
93234: 05/12/16: Re: Simulating CRC32 according to IEEE Std. 802.3
93239: 05/12/16: Re: Simulating CRC32 according to IEEE Std. 802.3
93240: 05/12/16: Re: Simulating CRC32 according to IEEE Std. 802.3
93290: 05/12/19: Differential Pin Pairs in Lattice EC FPGAs
93325: 05/12/19: Re: Differential Pin Pairs in Lattice EC FPGAs
93331: 05/12/20: Re: Differential Pin Pairs in Lattice EC FPGAs
93856: 06/01/02: Re: FPGA DVI output with CH7301
93859: 06/01/02: Re: FPGA DVI output with CH7301
93893: 06/01/03: Re: FPGA DVI output with CH7301
93964: 06/01/03: Re: FPGA DVI output with CH7301
94146: 06/01/06: Re: Ethernet Encoding scheme
94684: 06/01/16: Re: problem with the SRAM
96524: 06/02/05: Re: DDR2 SDRAM controller
96591: 06/02/07: Re: Verilog 2's Complement Shifter
97148: 06/02/17: Re: DDR SDRAM Controller
97356: 06/02/21: Re: DDR SDRAM Controller
97436: 06/02/22: Re: DDR SDRAM Controller
97748: 06/02/27: Re: FPGA: Model-SIm XE problem
97829: 06/02/28: Re: conv_integer
97896: 06/03/01: Re: Pulse Shape in a functional simulation
98139: 06/03/06: Re: DDR SDRAM Controller
98140: 06/03/06: Re: DDR SDRAM Controller
98325: 06/03/08: Re: VHDL
98411: 06/03/09: Re: FIFO Simulation Oddities!
98649: 06/03/14: Re: DDR SDRAM Controller
98650: 06/03/14: Re: DDR SDRAM Controller
98655: 06/03/14: Re: DDR SDRAM Controller
98661: 06/03/14: Re: DDR SDRAM Controller
98853: 06/03/17: Re: SDRAM controller selection
100215: 06/04/05: Compressing DVI stream
100280: 06/04/06: Re: Compressing DVI stream
100283: 06/04/06: Re: Difference in output between testbench and chipscope
100348: 06/04/07: Re: Difference in output between testbench and chipscope
101006: 06/04/24: Re: regarding memories using megafunction wizard(altera)
101007: 06/04/24: Re: CAM, TCAM in Stratix
101637: 06/05/04: Re: Unreactive Output Pins on Xilinx Virtex-II
101976: 06/05/09: Crossing clock domains
101979: 06/05/09: Re: Crossing clock domains
101986: 06/05/09: Re: Crossing clock domains
105332: 06/07/20: Re: MIG DDR2 controller does not work (reset problems?)
105460: 06/07/24: Re: ROM implementation
105982: 06/08/04: Re: Cyclone I & II memory fmax
105983: 06/08/04: Re: Xilinx System Generator crashes repeatedly
106132: 06/08/08: Re: Newbie question
106306: 06/08/11: Re: Compiler can't detect std_logic_1164 package
108089: 06/09/05: FIFO with EBR
108152: 06/09/06: Re: FIFO with EBR
108155: 06/09/06: Re: FIFO with EBR
108626: 06/09/14: Re: FIFO with EBR
111460: 06/11/03: Re: reset
111557: 06/11/06: Re: reset
113027: 06/12/05: Question concerning XAPP224
113209: 06/12/08: Organization of character bit maps
113212: 06/12/08: Re: Organization of character bit maps
114660: 07/01/22: Scrambling for Lattice SC
114996: 07/01/29: Re: How to make an internal signal embedded deep in hierarchy to a gloal output signal
115332: 07/02/07: Parameter File in Mixed Mode Designs
115848: 07/02/22: Re: Cyclone II "altsyncram" timing constraints?
116515: 07/03/12: Dual edge detection
116574: 07/03/13: Re: Dual edge detection
116580: 07/03/13: Re: Dual edge detection
119238: 07/05/15: Re: How low DDR2 Clock Frequency can be? To make it work on FPGA.
124879: 07/10/09: 8B/10B Xilinx Paper
124895: 07/10/10: Re: 8B/10B Xilinx Paper
124935: 07/10/11: Re: 8B/10B Xilinx Paper
131413: 08/04/21: Re: not inferred RAM, on QII
131655: 08/04/28: Re: Timing closure problem --- how to make the QII fitter smarter
132608: 08/06/02: Re: VHDL to Verilog Converter
132891: 08/06/10: FSM running with unstable clock
132946: 08/06/11: Re: FSM running with unstable clock
133272: 08/06/23: DC-Fifo with write pointer confirm/clear
133303: 08/06/24: Re: DC-Fifo with write pointer confirm/clear
133846: 08/07/17: XAPP240 - Design Files
133875: 08/07/18: Re: XAPP240 - Design Files
135100: 08/09/16: Compiler Options
135102: 08/09/16: Re: Compiler Options
135121: 08/09/17: Re: Compiler Options
135772: 08/10/15: PLL in Altera PCI core ?
135773: 08/10/15: Re: PLL in Altera PCI core ?
135878: 08/10/20: WP335 - Examples
136758: 08/12/04: Timing analysis of related clocks
136764: 08/12/04: Re: Timing analysis of related clocks
<ALuPin@web.de>:
83619: 05/05/04: Re: Signal use from pin
83870: 05/05/09: Re: crazy behaviour of fpga, timing ?
83935: 05/05/10: CAM implementation on Lattice EC
84021: 05/05/11: Re: crazy behaviour of fpga, timing ?
84079: 05/05/12: Input Maximum Delay timing assignment in Altera
84085: 05/05/12: Auto-select clock for virtual pins
84139: 05/05/12: Re: Input Maximum Delay timing assignment in Altera
84153: 05/05/13: Tristate-Master-Slave testbench description
84295: 05/05/17: Re: Auto-select clock for virtual pins
84299: 05/05/17: Re: Tristate-Master-Slave testbench description
84309: 05/05/17: Re: Auto-select clock for virtual pins
84373: 05/05/18: Re: Tristate-Master-Slave testbench description
84377: 05/05/18: Re: Auto-select clock for virtual pins
84519: 05/05/20: Re: Auto-select clock for virtual pins
84621: 05/05/23: Re: CPLD Fitting problem
84672: 05/05/24: Programmer + Cable
85272: 05/06/07: Measuring DDR SDRAM
85354: 05/06/08: Re: Connecting two INOUT ports
85429: 05/06/09: Re: Lattice LFEC20 DDR SDRAM connection
85430: 05/06/09: Re: DDR desing with FPGA
85495: 05/06/10: Re: DDR desing with FPGA
86047: 05/06/21: Altera SCFIFO
86052: 05/06/21: Re: Altera SCFIFO
86513: 05/06/29: Hex files in simulation
86561: 05/06/30: Re: Hex files in simulation
86679: 05/07/03: Re: Hex files in simulation
86751: 05/07/06: Re: EDK/ISE 7.1 SmartModel Set-up Issue with ModelSim 6.0a
86769: 05/07/06: Re: VHDL Clock Domains
86817: 05/07/07: Problems with Timing Simulation
86828: 05/07/07: Re: Problems with Timing Simulation
86837: 05/07/07: Re: Problems with Timing Simulation
86886: 05/07/08: Re: Problems with Timing Simulation
86986: 05/07/12: Re: QII simulation annoyance
87070: 05/07/14: Re: Why cann't this block be synthesized in top level
87071: 05/07/14: Re: ise 7.1 Input clk is never used.
87237: 05/07/20: Using unregistered inputs in FSM
87240: 05/07/20: Re: Using unregistered inputs in FSM
87248: 05/07/20: Re: Using unregistered inputs in FSM
87249: 05/07/20: DDR SDRAM configuration
87250: 05/07/20: Re: Using unregistered inputs in FSM
87301: 05/07/21: Re: Using unregistered inputs in FSM
87366: 05/07/22: Re: Using unregistered inputs in FSM
87368: 05/07/22: Re: Using unregistered inputs in FSM
87488: 05/07/25: Re: Using unregistered inputs in FSM
87511: 05/07/25: Re: Using unregistered inputs in FSM
87512: 05/07/25: Re: How to look inside a RAM memory
87682: 05/07/28: Remove Duplicate Registers / Logic
87714: 05/07/29: Re: Remove Duplicate Registers / Logic
87715: 05/07/29: Re: Using unregistered inputs in FSM
87767: 05/08/01: Re: question about use SRAM on annapolis wildstarII board
87773: 05/08/01: Re: question about use SRAM on annapolis wildstarII board
87774: 05/08/01: Re: struggling with general digital design
87778: 05/08/01: Re: FPGA
87828: 05/08/02: Re: fpga- DDR or DDR2
87830: 05/08/02: Re: Conversion of Schematic to Verilog/VHDL
88002: 05/08/05: Holding in output registers
88003: 05/08/05: Holding in output registers
88051: 05/08/08: Re: Holding in output registers
88059: 05/08/08: Re: Holding in output registers
88086: 05/08/09: Re: Holding in output registers
88089: 05/08/09: Re: Holding in output registers
88125: 05/08/10: Re: Hiding data inside a FPGA
88179: 05/08/11: Re: rom
88221: 05/08/12: Re: high speed image capture
88304: 05/08/15: Re: VHDL Array indexing Issue in Modelsim
88391: 05/08/17: Re: Altera NIOSII IDE problem???
89078: 05/09/05: Re: Reading internal signals through a testbench.
89091: 05/09/05: Re: False values in Quartus In-System Memory Editor
89112: 05/09/05: Re: Quartus2 WEB: Simulating from test bench. Is that possible?
89113: 05/09/05: Re: False values in Quartus In-System Memory Editor
89117: 05/09/06: Re: Quartus2 WEB: Simulating from test bench. Is that possible?
89126: 05/09/06: Re: False values in Quartus In-System Memory Editor
89250: 05/09/09: Re: FSM extraction question
89633: 05/09/21: Output register instantiation in Quartus
89646: 05/09/21: Re: Output register instantiation in Quartus
89678: 05/09/22: Re: Output register instantiation in Quartus
89683: 05/09/22: Re: Output register instantiation in Quartus
89708: 05/09/23: Re: Output register instantiation in Quartus
89767: 05/09/26: Making timing assignment in Quartus
90235: 05/10/07: Re: FPGA behaviour when its used resource is >90% ?
90320: 05/10/10: Re: Clock routing
90321: 05/10/10: Re: VHDL : Use concatenation on port mapping
90911: 05/10/25: OSD implementation in FPGA
90916: 05/10/25: Re: OSD implementation in FPGA
91235: 05/11/01: Re: Simulating Cyclone II PLL
Alvaro:
79161: 05/02/15: Question about Virtex II Pro - Partial Reconfiguration
Alvaro Combo:
105741: 06/07/31: Re: Rocket IO as a high speed sampler
Alvin Andries:
56634: 03/06/10: Re: Which Init Technique for BlockRAMs and Modelsim?
56635: 03/06/10: Re: ucf file is not used in XILINX project navigator
57149: 03/06/24: Re: How to get 27MHz from 10 MHz in FPGA???
60050: 03/09/04: Re: More about metastability
60122: 03/09/05: Re: 200MHz ucf constraints for Xilinx DA Decimation by 2
62665: 03/11/04: Re: DCM recover after interruption of input clock
70519: 04/06/18: Re: Xilinx XST synthesis removes input pin even though it's LOCed
86693: 05/07/05: Re: Xilinx: XST synchronous FIFO using BRAMs
86694: 05/07/05: Re: Xilinx: XST synchronous FIFO using BRAMs
86699: 05/07/05: Re: Xilinx: XST synchronous FIFO using BRAMs
86701: 05/07/05: Re: Xilinx: XST synchronous FIFO using BRAMs
86739: 05/07/05: Re: Xilinx: XST synchronous FIFO using BRAMs
88645: 05/08/24: Re: Does LOCKED signal of Spartan3 DCM require clock to be de-asserted?
89453: 05/09/15: Re: SDRAM quality
89489: 05/09/16: Re: IP Protection of code block in Xilinx FPGA?
89772: 05/09/26: Re: Xilinx Spartan-3
90587: 05/10/17: Re: LSI RAPIDCHIP
90590: 05/10/17: Re: Distributed microcontroller computing
91159: 05/10/31: Re: Memory usage and ISE
116504: 07/03/11: Re: Heritage Data books!
118496: 07/04/28: Re: Problem cascading 2 DCMs
120838: 07/06/18: Re: fitting problem on A54SX72A
120897: 07/06/19: Re: fitting problem on A54SX72A
125779: 07/11/05: Re: How do I meet this memory IO with least resources on FPGA?
131034: 08/04/08: Re: 32 bit multiplier
131184: 08/04/14: Re: "Multi-source in Unit" Verilog synthesis woes
133432: 08/06/28: Re: Still a Beginner: Accumulator has no reset
133687: 08/07/09: Re: JTAG IR length detection
Alvin E. Toda:
4779: 96/12/13: Re: ASICs Vs. FPGA in Safety Critical Apps.
4801: 96/12/16: Re: ASICs Vs. FPGA in Safety Critical Apps.
4826: 96/12/17: Re: ASICs Vs. FPGA in Safety Critical Apps.
4914: 96/12/29: Re: ASICs Vs. FPGA in Safety Critical Apps.
4925: 96/12/30: Re: ASICs Vs. FPGA in Safety Critical Apps.
4942: 97/01/02: Re: ASICs Vs. FPGA in Safety Critical Apps.
5170: 97/01/28: Re: ASICs Vs. FPGA in Safety Critical Apps.
6160: 97/04/18: Low budget effort for JTAG EXTEST assembly test.
15580: 99/03/31: Re: IP cores and software industry
16330: 99/05/16: Re: Synchronizer design?
16605: 99/05/29: Re: FPGA express + VHDL: strange SR implementation?
16622: 99/05/31: Re: FPGA express + VHDL: strange SR implementation?
16742: 99/06/05: Re: [Q] low cost asic
17092: 99/06/29: Re: Virtex JTAG readback
17221: 99/07/09: IEEE P1532
17388: 99/07/23: Re: CAN WE HAVE SIGNALS WITH MULTIPLE SOURCES IN VHDL?
17781: 99/09/02: Re: What's meaning of "Partial Evaluation"
17807: 99/09/06: Re: What's meaning of "Partial Evaluation"
18147: 99/10/03: Re: Producing 60/40 clock in vhdl
alwin:
74834: 04/10/20: counter skrews up design
74862: 04/10/20: Re: counter skrews up design
alz:
11346: 98/08/05: Re: PCI Core In FPGA
11347: 98/08/05: Re: PCI Core In FPGA
11348: 98/08/05: Re: PCI Core In FPGA
11349: 98/08/05: Re: PCI Core In FPGA
11350: 98/08/05: Re: PCI Core In FPGA
11363: 98/08/06: Re: PCI Core In FPGA
11364: 98/08/06: Re: PCI Core In FPGA
Am:
113128: 06/12/06: How to reduce jitter of 30-bit accumulator
am85:
151896: 11/06/02: Microblaze and PowerPC
Amal:
100384: 06/04/07: Infer dual-clock block RAM for Xilinx
100391: 06/04/07: Re: Infer dual-clock block RAM for Xilinx
100422: 06/04/08: Re: Infer dual-clock block RAM for Xilinx
102172: 06/05/11: Re: Synplify - Not satisfactory results with re-timing option
117397: 07/03/29: Re: RFC: Enhancing VHDL for OO, Randomization, Functional Coverage
117545: 07/04/03: Re: RFC: VHDL testbench enhancements
117593: 07/04/04: Re: TI Tap Controller std8980
120320: 07/06/05: Portable TCP/IP socket library
120463: 07/06/07: Re: Portable TCP/IP socket library
121022: 07/06/22: Cadence TestBuilder
121024: 07/06/22: Re: Cadence TestBuilder
126072: 07/11/14: Xilinx Encrypted bit file
128156: 08/01/16: CynApps Cynlib
128181: 08/01/17: Re: CynApps Cynlib
128211: 08/01/18: Re: CynApps Cynlib
128444: 08/01/25: Re: CynApps Cynlib
134188: 08/07/29: Re: Creating new operators
136310: 08/11/10: Re: request: sample vcd files for TimingAnalyzer
136737: 08/12/03: VHDL Packages, Coding Styles for Arithmetic Operations and VHDL-200x
136799: 08/12/05: SystemVerilog OOP and OVM Summary
140702: 09/05/22: SPAM?
144716: 09/12/27: Re: Xilinx and Multi-port memories
145016: 10/01/19: Re: IEEE fixed_pkg not recognized in ISE 11.1
145017: 10/01/19: Re: IEEE fixed_pkg not recognized in ISE 11.1
146686: 10/03/25: Re: where is VHDL-POSIX ?
146757: 10/03/27: Re: where is VHDL-POSIX ?
147540: 10/04/30: Re: Synplify constraint problem
148345: 10/07/09: Re: HDL float to string (sprintf %.3E)?
149279: 10/10/13: Re: FPGAOptim0208r available
149301: 10/10/14: Re: FPGAOptim0208r available
Amal Khailtash:
19069: 99/11/26: Re: UTOPIA Interface on FPGA
21911: 00/04/06: Re: CoreGen incompatible with NT SP6 and Win2K?
117779: 07/04/10: JTAG Tap Master (was: TI Tap Controller std8980)
Aman Gayasen:
57871: 03/07/08: Benchmark designs for partial dynamic reconfiguration
57949: 03/07/10: Benchmarks for partial dynamic reconfiguration
58681: 03/07/30: AREA_GROUP constraint for Xilinx FPGAs
59555: 03/08/21: Some questions about Xilinx ISE
60705: 03/09/19: Questions about XPower
74399: 04/10/10: Problem in Constraining Routing in Xilinx PAR
74437: 04/10/11: Re: Problem in Constraining Routing in Xilinx PAR
Amanda:
52619: 03/02/16: XC9500 JTAG programming problems
Amar A. Kapadia:
1539: 95/07/11: [Q] Comments on Synario
Amar Agnihotri:
40906: 02/03/17: Hardware : How to set the RESET signal...
40907: 02/03/17: Re: How to deal with a high fan-out net in FPGA.
40909: 02/03/17: Re: How to deal with a high fan-out net in FPGA.
40910: 02/03/17: Re: How to deal with a high fan-out net in FPGA.
<amaraju@onramp.net>:
10427: 98/05/18: HOT NEW FPGA Position Available!
Amarpreet Singh Geadhoke:
4485: 96/11/04: Re: FPGA references for beginner?
Amaury Anciaux:
68094: 04/03/26: Bus macro in partial reconfiguration
68098: 04/03/26: Re: Bus macro in partial reconfiguration
68317: 04/04/01: Re: Bus macro in partial reconfiguration
68541: 04/04/07: Dual microblaze system, implemented with projnav.
68542: 04/04/07: Re: Bus macro in partial reconfiguration
Ambreen Ashfaq Afridi:
132598: 08/06/02: Checksums
132599: 08/06/02: Re: Checksums
132605: 08/06/02: VHDL to Verilog Converter
132606: 08/06/02: Re: Checksums
132892: 08/06/10: where is the IP address assigned to the fpga in Trimode Ethernet MAC
133369: 08/06/25: Hardware Demonstration Platform
133486: 08/07/01: Type Casting in verilog
133874: 08/07/17: verilog code
133925: 08/07/19: instantiation in verilog
AMDyer@gmail.com:
85953: 05/06/18: Re: Problem for xilinx!!!
149643: 10/11/12: Re: Spartan3 bidirectional 3.3V 5V level shifter
151613: 11/04/26: Re: advice needed for FPGA chip selection
151961: 11/06/15: Re: Area Optimization
153034: 11/11/18: Re: Production Programming of Flash for FPGAs and MCUs
154216: 12/09/10: Re: Looking for an extremely cheap FPGA board (in quantity, academic use)
155134: 13/04/25: Re: Low cost and/or small size CPU in an FPGA
AME:
35853: 01/10/20: Verilog vs. VHDL
35855: 01/10/20: Re: Verilog vs. VHDL
35865: 01/10/21: Re: Verilog vs. VHDL
35868: 01/10/21: Re: Verilog vs. VHDL
35872: 01/10/21: Re: Verilog vs. VHDL
35925: 01/10/23: Re: Verilog vs. VHDL
35926: 01/10/23: Re: Verilog vs. VHDL
35952: 01/10/24: Re: Verilog vs. VHDL
36049: 01/10/26: Re: Probing BGA Designs
36098: 01/10/29: Re: Verilog vs. VHDL
36344: 01/11/06: Re: Verilog vs. VHDL
Ameer Abdelhadi:
159550: 16/12/13: Re: Quad-Port BlockRAM in Virtex
159552: 16/12/16: Re: Quad-Port BlockRAM in Virtex
amerdsp:
123167: 07/08/17: Minimal power?
amey hegde:
31280: 01/05/17: Digital PLL (DPLL) design help
31307: 01/05/18: Re: Digital PLL (DPLL) design help
34754: 01/09/06: Selection of a suitable FPGA board
34900: 01/09/13: Using Synopsys Design Compiler to target Virtex-E FPGA
34939: 01/09/14: Re: Using Synopsys Design Compiler to target Virtex-E FPGA
AMID GUBTA:
38623: 02/01/19: Re: initial value
39160: 02/02/02: PAR prediction
<amie@mccarragher.com>:
159135: 16/08/17: IRC SERVER
159136: 16/08/17: IRC SERVER
amigabill:
19352: 99/12/15: Re: hobbyist friendly pld?
19353: 99/12/15: Re: hobbyist friendly pld?
20222: 00/02/01: Re: Which FPGA to learn with?
Amigo:
96084: 06/01/30: Remotely updating Altera FPGA configuration
96157: 06/01/30: Re: Remotely updating Altera FPGA configuration
<amigo65@gmail.com>:
134899: 08/09/05: Re: encryption
134900: 08/09/05: need sme help on data encryption based on fpga
<Amine.Miled@gmail.com>:
117797: 07/04/10: Flip Flop problem (asynchronous or synchronous???? )
117803: 07/04/10: Re: Flip Flop problem (asynchronous or synchronous???? )
117807: 07/04/10: Re: Flip Flop problem (asynchronous or synchronous???? )
117810: 07/04/10: Re: Flip Flop problem (asynchronous or synchronous???? )
117856: 07/04/11: Re: Flip Flop problem (asynchronous or synchronous???? )
118802: 07/05/03: Prunnning Register missunderstood!!
118804: 07/05/03: Re: Wait-for / until won't work ? Xilinx Spartan 3
118867: 07/05/04: Re: Prunnning Register missunderstood!!
119264: 07/05/15: Global ressource problem
119332: 07/05/16: Re: Global ressource problem
119338: 07/05/16: Re: Global ressource problem
119407: 07/05/17: Re: Unusual question about generic port use (optional ports??)
120610: 07/06/11: Power consumption problem
120638: 07/06/12: Re: Power consumption problem
120793: 07/06/16: Re: Power consumption problem
Amir:
123642: 07/08/31: Simple Project involving microblaze
124429: 07/09/21: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
141866: 09/07/14: Re: Adder size vs Register size
Amir Amin:
57526: 03/07/01: Need help in capturing serial data using FPGA and ethernet interface
Amir Farrahi:
18309: 99/10/13: Great Lakes Symposium on VLSI: Submission deadline has been extended till October 22, 1999
Amir Intisar:
82370: 05/04/11: Verilog examples???
82396: 05/04/12: Re: Verilog examples???
83056: 05/04/22: Writing to Ram
83123: 05/04/24: simple delays
Amir Manasterski:
8785: 98/01/27: Please help the damn rookie!
8975: 98/02/10: Questions on Synario (the rookie's back!)
11775: 98/09/08: free version of synario for atmel - where?
Amir Tabatabaei:
87829: 05/08/02: Xilinx 7.1, Kernel 2.6 and modules for install_driver_installscript
87842: 05/08/02: Re: Xilinx 7.1, Kernel 2.6 and modules for install_driver_installscript
Amir Torabi:
59716: 03/08/26: synthesizing registers :
<amir.intisar@gmail.com>:
84322: 05/05/17: delays
84384: 05/05/18: Re: delays
84453: 05/05/19: Spartan 3 CPI
84598: 05/05/22: Re: simple delays
88729: 05/08/26: Writing to Spartan 3 SRAM
89021: 05/09/02: Spartan 3 Ram Instantiation
89061: 05/09/04: Re: Spartan 3 Ram Instantiation
89176: 05/09/07: Re: Spartan 3 Ram Instantiation
<amirhossein.gholamipour@gmail.com>:
105069: 06/07/12: Micorblaze post place and route simulation...
Amirtham:
111539: 06/11/05: Integration of modules
111679: 06/11/07: problem in interfacing with SDRAM controller
111680: 06/11/07: Re: Integration of modules
112721: 06/11/27: Re: problems with verilog SDRAM models
113205: 06/12/08: Problem with connecting higher order address lines of SDRAM to FPGA
113308: 06/12/10: Re: Problem with connecting higher order address lines of SDRAM to FPGA
113373: 06/12/12: Re: Problem with connecting higher order address lines of SDRAM to FPGA
113404: 06/12/12: Re: Problem with connecting higher order address lines of SDRAM to FPGA
113417: 06/12/13: Re: Problem with connecting higher order address lines of SDRAM to FPGA
113462: 06/12/14: Re: Problem with connecting higher order address lines of SDRAM to FPGA
Amirul Khan:
34837: 01/09/10: Re: Give me some information!
Amish Rughoonundon:
109650: 06/10/02: Xilinx ISE 8.2 : Cannot find library
148221: 10/06/30: Automatic BUFG insertion on a non clock signal in ISE 12.1
148225: 10/06/30: Re: Automatic BUFG insertion on a non clock signal in ISE 12.1
148229: 10/06/30: Re: Automatic BUFG insertion on a non clock signal in ISE 12.1
148347: 10/07/12: manual Route before PAR starts in xilinx ISE 12
148349: 10/07/12: Re: manual Route before PAR starts in xilinx ISE 12
amit:
97595: 06/02/24: PPC405 - FPGA interface design
100364: 06/04/07: shared BRAM between PPC and FPGA fabric
Amit:
46673: 02/09/05: library
46705: 02/09/06: Re: library
51543: 03/01/16: Re: How to add pins in ISE 4.2
51559: 03/01/16: Re: Virtex II pro architecture question
51595: 03/01/16: Re: How to add pins in ISE 4.2
51597: 03/01/16: Re: Xilinx Constraint Problem
51608: 03/01/17: Re: Xilinx Constraint Problem
51615: 03/01/17: Re: Xilinx Constraint Problem
51789: 03/01/21: Re: Ram bits for Registers
52117: 03/02/01: Re: Static Timing Analysis
52193: 03/02/04: Re: Group Multiple tables
56890: 03/06/18: Re: FPGA to Custom ASIC ??
114306: 07/01/11: Re: EDIF generation from C
118547: 07/04/29: Re: debounce state diagram FSM
118549: 07/04/29: Re: debounce state diagram FSM
118550: 07/04/29: Re: debounce state diagram FSM
118554: 07/04/29: Re: debounce state diagram FSM
118555: 07/04/29: Re: debounce state diagram FSM
119212: 07/05/15: How low DDR2 Clock Frequency can be? To make it work on FPGA.
119268: 07/05/15: Re: How low DDR2 Clock Frequency can be? To make it work on FPGA.
125969: 07/11/10: newbie to 16v8
125971: 07/11/10: Re: newbie to 16v8
126124: 07/11/14: Re: newbie to 16v8
126449: 07/11/22: Re: newbie to 16v8
128569: 08/01/30: new to NIOS II
142740: 09/08/29: low power FPGA
142829: 09/09/02: Re: low power FPGA
Amit Deshpande:
41570: 02/04/02: how to synchronise asynchronous inputs?
41602: 02/04/03: how to synchronise asynchronous inputs?
Amit Kasat:
68194: 04/03/29: Re: ISE and EDK Incompatible?
68548: 04/04/07: Re: Dual microblaze system, implemented with projnav.
68549: 04/04/07: Re: EDK 6.1: User Logic
70696: 04/06/23: Re: Problems with a Virtex-II Engineering Sample
70697: 04/06/23: Re: EDK 6.2 ISE verilog toplevel possible ?
73440: 04/09/21: Re: Microblaze:ISE-EDK
75935: 04/11/19: Re: microblaze: execute program from external memory
76081: 04/11/23: Re: EDK 6.3i "Entry Point Not Found" error
76838: 04/12/13: Re: ISE/XPS ERRORS
78635: 05/02/04: Re: EDK6.2i - Error message during PlatGen after adding in HDL files
89157: 05/09/06: Re: Defining Environment variables inside EDK
107559: 06/08/29: Re: ISE/EDK "target pattern contains no `%'"
107561: 06/08/29: Re: no luck instantiating system.xmp (EDK project file) within ISE
116507: 07/03/11: Re: MPD Files
Amit Olkar:
71565: 04/07/22: Resources on FPGA wanted...
Amit Thakar:
38534: 02/01/16: Signal processing using FPGAs
38539: 02/01/16: Re: Signal processing using FPGAs
<amitpatel130@gmail.com>:
117134: 07/03/23: Amphion IP MPEG2 Video DecoderCores
<amk565@gmail.com>:
138015: 09/02/03: generating 320Mhz clk from 80Mhz source in Virtex4-vlx100 (-11)
amko:
85671: 05/06/13: Re: Adding Verilog processing core to Viretx2Pro at ML310
85825: 05/06/16: Re: uart / Nios2
86018: 05/06/20: Re: Design tools comparison between Xilinx, Altera and Lattice for FPGA designs
86391: 05/06/27: FPGA PC104 development board
86444: 05/06/28: Re: FPGA PC104 development board
86598: 05/06/30: FPGA development board - urgently
86634: 05/07/01: interpolation in FPGA
86798: 05/07/06: PC104 (ISA) bus in FPGA (Spatan 2E)
87001: 05/07/12: 16-bit Acesses on ISA bus
89119: 05/09/06: SPARATAN 2E - input clock
102917: 06/05/23: FPGA delay generator
102982: 06/05/24: Re: FPGA delay generator
102984: 06/05/24: Re: FPGA delay generator
102999: 06/05/24: Re: FPGA delay generator
103050: 06/05/25: Re: FPGA delay generator
Ammann Michael:
7881: 97/10/27: All Digital DLL or PLL with less than 20ps resolution
Ammar2k:
148618: 10/08/07: Re: A question from a VHDL beginner
<ammonton@cc.full.stop.helsinki.fi>:
100798: 06/04/18: Re: FPGA + FTDI
114795: 07/01/24: Re: Xilinx ISE 8.2
114885: 07/01/25: Re: Xilinx ISE 8.2
119205: 07/05/15: Re: Xilinx software quality - how low can it go ?!
<amolitor-at@visi-dot-com.com>:
28283: 01/01/05: Re: Nondeterministic FSMs in hardware?
43280: 02/05/17: Re: SDRAM pricing
43282: 02/05/18: Re: SDRAM pricing
43330: 02/05/19: Re: SDRAM pricing
AMONTEC:
111202: 06/10/31: Re: How to configuration 2 FPGAs mit one cable?
111208: 06/10/31: Re: How to configuration 2 FPGAs mit one cable?
111236: 06/10/31: Re: How to configuration 2 FPGAs mit one cable?
111937: 06/11/13: Re: FPGA Debug Tool
112156: 06/11/17: Re: use boundary scan in spartan-3
113510: 06/12/15: Re: gtkwave 3.0.18 for win32
113602: 06/12/18: Re: solder mask for fpga dissipation
113717: 06/12/20: Re: Slightly OT: Need a USB-to-LPT adapter for Xilinx Parallel IV
Amontec Team:
55140: 03/04/28: Re: Use of bidir ports on Flex 10k.
56087: 03/05/28: Re: Xilinx Spartan download with Parallel III cable
56096: 03/05/28: 5v TTL to 3.3v 2.5v 1.8v 1.2v LVTTL solution
56103: 03/05/28: Re: 5v TTL to 3.3v 2.5v 1.8v 1.2v LVTTL solution
56488: 03/06/06: Re: fifo or bram in spartan2e vs spartan3
57992: 03/07/11: XML for VHDL documention and structural description of Hardware SoC
57993: 03/07/11: Re: Xilinx Spartan-3 samples, how to get?
57994: 03/07/11: Re: Xilinx FPGA module
57995: 03/07/11: Re: Missing something...
57997: 03/07/11: Re: resynthesize ASIC netlist
58593: 03/07/28: Re: xilinx programing interface
58655: 03/07/30: Re: Parallel Port EPP in FPGA
58910: 03/08/04: LCD and step-up DC-DC converter.
59831: 03/08/29: Re: HDL Designer from Mentor
60488: 03/09/15: Spartan-3 : preconfiguration pull-up/float ?
60996: 03/09/26: Re: pullup on inputs
62792: 03/11/07: Re: Impact, SVF, assumed TCK frequency?
64147: 03/12/18: CRC-32 in spatan-3
64547: 04/01/07: IP or Core
65237: 04/01/22: Re: Random data generator...
66003: 04/02/11: SPARTAN2 BUFG mapping
70617: 04/06/22: Re: JTAG - XC2S200E-PQ208
70681: 04/06/23: Re: 5V board in a 3.3V PCI slot
70691: 04/06/23: Re: 5V board in a 3.3V PCI slot
71203: 04/07/12: Re: FPGA to PCI Bus Interface
71343: 04/07/15: programmable voltage control of a VCCIO Bank
73013: 04/09/10: delivering VHDL (RTL) IP core to my customer: how ?
73016: 04/09/10: Re: delivering VHDL (RTL) IP core to my customer: how ?
Amontec Team, Laurent Gauch:
56859: 03/06/17: Re: Spartan3 in WebPack
59055: 03/08/07: Re: Xilinx ISE WebPack 5.2 & VHDL : wait synthesis
60125: 03/09/05: Re: Disable Pull up
60226: 03/09/08: Re: Impact error
60281: 03/09/09: Re: Programming Xilinx CPLD under linux
60929: 03/09/25: Re: Portable computer for FPGA/CPLD tools
60963: 03/09/25: Re: IEEE 1284 Core for Xilinx | Reading Japanese FPGA pages
61273: 03/10/01: Automatic I/O voltage sensing (as XILINX ParallelCable IV)
61304: 03/10/01: Re: Any word on the V2Pro-X?
61353: 03/10/02: Re: Automatic I/O voltage sensing (as XILINX ParallelCable IV)
61585: 03/10/07: Re: beginner - exisit some free schematics programmer for fpga ?
61846: 03/10/14: Re: ByteBlasterII
62044: 03/10/17: Re: VFDs
62303: 03/10/25: Re: Picoblaze development tool
62373: 03/10/28: Re: Xilinx JTAG Parallel IV cable and INITIALIZING CHAIN
62374: 03/10/28: Re: Trenz-electronics (spartan2 development board) help?
62375: 03/10/28: Re: Xilinx JTAG Parallel IV cable and INITIALIZING CHAIN
62384: 03/10/28: Re: Picoblaze development tool
62385: 03/10/28: Re: Xilinx JTAG Parallel IV cable and INITIALIZING CHAIN
62614: 03/11/03: Re: Power-On-Reset from a xilinx
62621: 03/11/03: Re: Picoblaze development tool
63023: 03/11/12: Re: Will XPLA3 phase out?
63056: 03/11/13: Re: unknown devices in JTAG chain
63300: 03/11/19: Re: State Machines....
63496: 03/11/24: Re: Laptop without serial/parallel port
63726: 03/12/02: SPARTAN-II, busy signal
63779: 03/12/04: post-synth. with webpack
64119: 03/12/17: Xilinx .ucf
64455: 04/01/05: Re: how to set the ISP mode for programming CPLD?
64527: 04/01/06: Re: Where i can get the programming sequence of CoolRunner?
64587: 04/01/08: Re: Where i can get the programming sequence of CoolRunner?
64766: 04/01/13: simulating xilinx clkdll
64820: 04/01/14: Re: simulating xilinx clkdll
64821: 04/01/14: Re: translating .jed files to equations
64825: 04/01/15: Re: Can i get a sample XSVF file?
65197: 04/01/22: Re: Soft failures (?) 9536XL
65377: 04/01/27: Re: isp Cable for Lattice CPLD
65710: 04/02/05: Xilinx ILA -> supported FPGA ?
65747: 04/02/05: Re: European supplier of Xilinx chips
65749: 04/02/05: interfacing Chameleon POD
66080: 04/02/12: getting back Xilinx ISE commands
66084: 04/02/12: Re: getting back Xilinx ISE commands
66097: 04/02/12: Re: getting back Xilinx ISE commands
66103: 04/02/12: Re: getting back Xilinx ISE commands
66108: 04/02/12: Re: getting back Xilinx ISE commands
66118: 04/02/12: Re: Sine Wave Generation
66186: 04/02/13: Re: RFC: ARM+FPGA tiny board
66681: 04/02/25: Re: SmartMedia writer (implments using VHDL)....
67592: 04/03/15: low power Oscillator for Xilinx CoolrunnerII
67599: 04/03/15: Re: low power Oscillator for Xilinx CoolrunnerII
67600: 04/03/15: Re: low power Oscillator for Xilinx CoolrunnerII
67606: 04/03/15: Re: low power Oscillator for Xilinx CoolrunnerII
67714: 04/03/17: Re: Schematic Edition Tool : Suggestions
68283: 04/03/31: Re: Where to source CPLD XC2C256-7TQFP144I
69414: 04/05/10: unused IO on SPARTAN-IIE
69552: 04/05/13: Re: unused IO on SPARTAN-IIE
Amontec, Larry:
69657: 04/05/17: Re: How to replace Triscend - Xilinx plans for the future
71371: 04/07/15: SPARTAN-3 RDS resistor
71846: 04/08/02: Re: Spartan 3 prices
75838: 04/11/16: Re: Suggestion for Xilinx parallel port cable replacement.
76218: 04/11/29: Re: Programming flash connected to CPLD via JTAG
76398: 04/12/01: Re: Compact Flash Peripheral Design with FPGA
80201: 05/03/02: spartan3E price
80210: 05/03/02: Re: Lattice lowcost flash FPGAs announced
80498: 05/03/07: Re: Xilinx / Altera TCLK termination (Pull up or down)
82319: 05/04/11: Re: implement the JTAG MASTER --ACT8990 by using FPGA
83017: 05/04/21: Re: FIFO as a Logic Analyzer; Clock synthesizer
83585: 05/05/03: Re: JTAG communication Problems in Quartus using Signal Tap
96250: 06/02/01: Re: Parallel Cable IV does not work with parallel to usb cable
96785: 06/02/10: Re: ANTTI*HAPPY: building MicroBlaze uClinux on WinXP full sucess
99329: 06/03/23: Re: this JTAG thing is a joke
101267: 06/04/28: Re: Working Altera USB-Blaster compatible design published under
101270: 06/04/28: Re: Working Altera USB-Blaster compatible design published under
101433: 06/05/01: Re: Working Altera USB-Blaster compatible design published under
107192: 06/08/25: Re: Digilent USB support from Xilinx Impact (Programmer cable SDK
108703: 06/09/15: Re: Spartan3 driving mosfets
109838: 06/10/06: Re: Open protocol USB JTAG cable
110110: 06/10/11: Re: Xilinx MicroBlaze 4.00.a source codes released by Xilinx !?
110639: 06/10/19: Re: Meeting Timing Constraint
110791: 06/10/23: Re: Spartan 3 Configuration Questions
117484: 07/04/02: SVF Player
120676: 07/06/13: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
120968: 07/06/21: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
120973: 07/06/21: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
120977: 07/06/21: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
120981: 07/06/21: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
120987: 07/06/21: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
121053: 07/06/24: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
121055: 07/06/24: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
121245: 07/06/29: Re: USB JTAG Programming
121253: 07/06/29: Re: USB JTAG Programming
121431: 07/07/04: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
122367: 07/07/26: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
124270: 07/09/17: Altera / Lattice / Xilinx CPLDs ?
124304: 07/09/18: Re: Tristate bus on spartan FPGA
124729: 07/10/02: Re: Programming the ARM7 used to download our Xilinx FPGA
124851: 07/10/08: Re: JTAG interconnect testing, prototypes
125012: 07/10/15: Re: FPGA quiz: what can be wrong
125014: 07/10/15: Re: FPGA quiz: what can be wrong
125064: 07/10/16: Re: FPGA quiz: what can be wrong
125077: 07/10/16: Re: FPGA quiz: what can be wrong
125095: 07/10/16: Re: FPGA quiz: what can be wrong
125102: 07/10/16: Re: FPGA quiz: what can be wrong
125125: 07/10/16: Re: FPGA to FPGA Bus
127320: 07/12/18: VCCIO issue on Xilinx Spartan3E !
127321: 07/12/18: Re: VCCIO issue on Xilinx Spartan3E !
127361: 07/12/19: Re: VCCIO issue on Xilinx Spartan3E !
Amontec, Laurent Gauch:
70475: 04/06/17: SPARTAN-IIE -> LVCMOS18
70481: 04/06/17: Re: SPARTAN-IIE -> LVCMOS18
Amora:
82581: 05/04/14: Xilinx TMRTool price
83082: 05/04/22: Re: Virtex 4 Power consumption
86479: 05/06/28: Xilinx Virtex 4 device technology
Amos B. Moses:
63977: 03/12/10: Re: Soldering of FPGAs
63978: 03/12/10: Re: Manufacturing Tests
<amos@nsof.co.il-n0spam>:
10469: 98/05/20: Re: FPGA-based CPUs (was Re: Minimal ALU instruction set)
Amr Ahmadain:
86533: 05/06/29: Re: Xilinx Virtex 4 device technology
86553: 05/06/29: Re: Xilinx Virtex 4 device technology
86554: 05/06/29: Re: Xilinx Virtex 4 device technology
86557: 05/06/29: Re: Xilinx Virtex 4 device technology
87516: 05/07/25: Exact time-to-Failure data for FPGA devices
87547: 05/07/25: Re: Exact time-to-Failure data for FPGA devices
87558: 05/07/25: Re: Exact time-to-Failure data for FPGA devices
Amr G. Wassal:
6331: 97/05/15: Re: VHDL or Verilog?
Ams:
103715: 06/06/09: Linux 2.6 for PPC on Xilinx XUP-V2PRO board!
Amstel:
61864: 03/10/14: Electronic Dice ( 3 die ) In VHDL
62335: 03/10/27: Electronic Dice VHDL Program
62358: 03/10/27: Re: Electronic Dice VHDL Program
62582: 03/11/02: VHDL Xilinx Flow Engine ERROR
Amy:
70723: 04/06/24: Looking for Fax software
97738: 06/02/26: Re: VHDL to create LUT based delay
Amy Mitby:
49187: 02/11/04: tips for cutting down on slice usage in a VirtexII
49232: 02/11/05: Re: tips for cutting down on slice usage in a VirtexII
49311: 02/11/08: Pros and Cons of using Xilinx CoreGen components
49446: 02/11/12: Efficient implementation memory-mapped regisetrs
49447: 02/11/12: Registering inputs or outputs of modules
49448: 02/11/12: Re: FPGA Size?
49464: 02/11/12: Feedback from a 200 MHz Virtex2 design
53322: 03/03/10: Synplicity's Identify tool vs. Chipscope
55405: 03/05/06: Functional simulation model for SelectMAP and/or System ACE MPU port
Amy Vaughn:
28930: 01/01/30: FPGA DESIGN ENGINEER - NORTHERN CALIFORNIA
28953: 01/01/31: Help Please
Amy_jing:
152004: 11/06/21: How to open the interface GUI of ChipScope Pro Analyzer on linux
<amy_wakefield@my-dejanews.com>:
15127: 99/03/08: Design Engineers
amyler:
74913: 04/10/21: Nios & off-chip memory
<amyler@eircom.net>:
84659: 05/05/24: Re: using a SDRAM FIFO
84728: 05/05/25: Re: Single-endec clocks
84760: 05/05/26: Re: Single-endec clocks
84845: 05/05/30: Nios speed down
85856: 05/06/17: PCI in a PCI-X slot
87400: 05/07/22: Re: IP-cores for digital audio
89854: 05/09/28: 16-bit microprocessor dore for Actel
91597: 05/11/09: Re: How do i detect ethernet frames of layer 2 using ethereal?
91972: 05/11/18: Re: hi everyone, tell me something about Cyclone II.
92180: 05/11/23: Re: XST vs Synplify
92408: 05/11/29: Re: first time managing a project
92463: 05/11/30: Re: first time managing a project
92553: 05/12/01: Re: Download old Quartus versions (4.0, 4.1)
92623: 05/12/02: Re: first time managing a project
93032: 05/12/12: Re: FPGA in industrial environment
93064: 05/12/13: Re: xilinx constraint
93068: 05/12/13: Re: xilinx constraint
93072: 05/12/13: Re: xilinx constraint
94142: 06/01/06: Re: Ethernet Encoding scheme
94415: 06/01/11: Re: PLX PCI9656
95035: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95036: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95038: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95043: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95052: 06/01/20: Re: OT:Shooting Ourselves in the Foot
AmyS:
91825: 05/11/14: Xilinx flip-chip PCB processing
an:
28458: 01/01/13: Altera and LVDS
59136: 03/08/09: Re: Offshore engineering
An:
29084: 01/02/05: Xilinx Project Manager 3.1i: viewing signals
An Schwob in the USA:
147364: 10/04/23: Re: Need to run old 8051 firmware
<an222663@anon.penet.fi>:
1420: 95/06/20: Help with Viewlogic
1486: 95/06/28: Help with Viewlogic II
Anacrom:
124787: 07/10/04: Re: Count Leading Zero (CLZ) possible by MicroBlaze??
anal_aviator:
143094: 09/09/20: Re: Mac OS X support for Sigasi HDT
Analog_Guy:
109899: 06/10/07: Re: An implementation of a clean reset signal
123432: 07/08/28: Xilinx Virtex IOB Regiters and Noise???
123447: 07/08/28: Re: Xilinx Virtex IOB Regiters and Noise???
128695: 08/02/04: Re: Internal signal names in ModelSim
149710: 10/11/19: Multiple Reset Inputs
149738: 10/11/21: Re: Multiple Reset Inputs
AnamDar:
158327: 15/10/22: error Xst:899
aName:
104961: 06/07/11: Re: debouncing a switch (in hardware)
104962: 06/07/11: Implementing USB slow protocol into xilink XC95xxx..
104997: 06/07/11: Re: debouncing a switch (in hardware)
105000: 06/07/11: Re: Implementing USB slow protocol into xilink XC95xxx..
anand:
72566: 04/08/24: IP Coregen: FFT v2.1 IP core regd.
104075: 06/06/18: Newbie to FPGA
104076: 06/06/18: Re: Newbie to FPGA
104080: 06/06/18: Re: Newbie to FPGA
104087: 06/06/18: Re: Newbie to FPGA
104296: 06/06/22: stimulus for FPGA
104312: 06/06/23: Re: stimulus for FPGA
104343: 06/06/24: Re: newbie wants to do VHDL on an FPGA
114490: 07/01/17: Considerations for FPGA Based Acceleration in Bio medical simulations/computational biology
114529: 07/01/18: Re: Considerations for FPGA Based Acceleration in Bio medical simulations/computational biology
114577: 07/01/19: Re: Considerations for FPGA Based Acceleration in Bio medical simulations/computational biology
117599: 07/04/04: Gray code in asynchronous FIFO design
117609: 07/04/04: Re: Gray code in asynchronous FIFO design
117612: 07/04/04: Re: Gray code in asynchronous FIFO design
140347: 09/05/10: implementing arbitrary combinational functions using block rams
140355: 09/05/10: Re: implementing arbitrary combinational functions using block rams
140356: 09/05/10: Re: implementing arbitrary combinational functions using block rams
140357: 09/05/10: Re: Mapping FIFO into BRAM
Anand:
35213: 01/09/26: Virtex 2 : using IOB registers
49775: 02/11/20: programmable oscillator for Virtex-E (XCV2000E)
49954: 02/11/26: question about programmable oscillator ?
49964: 02/11/26: question about PCB traces for FPGA board... ?
50109: 02/12/02: question about series termination resistors and VIAS
50219: 02/12/05: series termination question
50258: 02/12/06: Re: series termination question
72539: 04/08/23: IP Coregen: FFT v2.1 IP core regd.
95818: 06/01/26: DDR2 SDRAM controller
96502: 06/02/05: Re: DDR2 SDRAM controller
96868: 06/02/12: Re: DDR2 SDRAM controller
Anand Kumar Rajaram:
52590: 03/02/14: Implementing BIG state machhine
Anand Kumar V:
37333: 01/12/07: Parameters deciding Max. Clock Frequency supported in a Sequential Ckt
anand kuriakose:
26334: 00/10/12: Category : Subject:Floorplanning
Anand P Paralkar:
57565: 03/07/02: Discrepancy in CLB Usage Report
68213: 04/03/30: FIFO Depth(Length) Calculation
68261: 04/03/31: Re: Metastablility
69033: 04/04/26: ASIC RTL and FPGA RTL
Anand Ramakrishna:
53267: 03/03/08: About Xilinx Spartan FPGA.
53881: 03/03/26: Re: How to avoid this Latch
<anandraj7k@gmail.com>:
121385: 07/07/03: MPC 8321E DDR2 interface
Ananth:
44214: 02/06/13: new to fpga.
ananth:
34553: 01/08/29: beginner
ANANTHARAJ.T.V.:
84838: 05/05/30: ISE 6.1 - Fatal Error
anas_waris:
129017: 08/02/12: Spartan 3A starter kit
<anas_waris@hotmail.com>:
128928: 08/02/10: Downloading codes to FPGA development Board
Anastasios D. Salis:
109677: 06/10/03: Virtex 4 Configuration Pins
Anastasios Salis:
109997: 06/10/09: Virtex 4 SX, Dedicated Configuration pins
Anatoli Ivanov:
5045: 97/01/16: Re: Market Share Stats for Synthesis Vendors?
Anatoli Sergienko:
68046: 04/03/25: Re: Bus width between registers in IIR
Anbarasu:
40556: 02/03/09: FPGA Synthesis ...new methodology
Ancient_Hacker:
95014: 06/01/20: Re: OT:Shooting Ourselves in the Foot
Ander Royo Orejas:
4327: 96/10/16: Re: FPGA for Reed-Solomon Codec
Anders:
69655: 04/05/17: How to replace Triscend - Xilinx plans for the future
Anders F:
76010: 04/11/22: Re: DDR SDRAM with Xilinx Virtex 2 on self designed PCB
Anders Hellerup Madsen:
63087: 03/11/14: Color STN LCD controller
63149: 03/11/17: Re: Color STN LCD controller
64619: 04/01/09: Re: Newbie Question: No Vsim, Vlib etc in my ModelSim
65560: 04/02/02: Re: Phase detector for DLL
66579: 04/02/23: Xilinx Microblaze and C++
70160: 04/06/07: Re: parameter feature of AHDL in Xilinx
Anders Kugler:
5628: 97/03/03: XILINX xchecker drivers on HP
Anders Ramdahl:
31522: 01/05/29: Re: Fun with DLLs.
Anders Sandgren:
7351: 97/08/29: Microchip 24LC164
<Anders.Montonen@kapsi.spam.stop.fi.invalid>:
149997: 10/12/06: Re: : The Danger of When Programmable Logic Meets the Consumer Market -- The Informercial
152494: 11/08/29: Re: Very cheap Spartan3 board that can be configured by simple USB
152638: 11/09/19: Re: Virtex 6 dev. board suppliers?
152698: 11/10/03: ISE 13.2 CPLD Schematic projects
153037: 11/11/19: Re: Production Programming of Flash for FPGAs and MCUs
157058: 14/09/18: Re: NetCPU or DotNetCPU DB200 anyone?
157063: 14/09/19: Re: NetCPU or DotNetCPU DB200 anyone?
157349: 14/11/26: Re: Bypass Xilinx flexlm license check
<anders.rustad@broadpark.no>:
110531: 06/10/17: Xilinx DCT reference design
Anders=?iso-8859-1?q?_Bostr=F6m?=:
26142: 00/10/05: Re: Xilinx par tool version 3.2i triggers wine bug
andersod2:
134213: 08/07/30: Is there a totally command-line driven way to use Xilinx Webpack?
134239: 08/07/31: Re: Is there a totally command-line driven way to use Xilinx Webpack?
134256: 08/08/01: What's the deal with PSoC programmers?
134259: 08/08/01: Re: Is there a totally command-line driven way to use Xilinx Webpack?
134266: 08/08/02: Re: Is there a totally command-line driven way to use Xilinx Webpack?
134371: 08/08/07: Re: ISE 8.1i sp3: map is not recognized as an internal or external
134372: 08/08/07: Re: What's the deal with PSoC programmers?
134380: 08/08/08: Re: ISE 8.1i sp3: map is not recognized as an internal or external
134400: 08/08/08: Re: ISE 8.1i sp3: map is not recognized as an internal or external
134438: 08/08/10: Re: ISE 8.1i sp3: map is not recognized as an internal or external
134526: 08/08/16: why does inferred RAM cause synthesis times to explode?
134527: 08/08/16: Re: Verilog modules and stimulus in same file
134541: 08/08/17: Re: why does inferred RAM cause synthesis times to explode?
134562: 08/08/18: Re: why does inferred RAM cause synthesis times to explode?
134568: 08/08/19: Re: why does inferred RAM cause synthesis times to explode?
134679: 08/08/25: Re: ISE 8.1i sp3: map is not recognized as an internal or external
andfn:
148504: 10/07/28: problem in loading from flash to spartan-3 xc3s200
Andi:
75818: 04/11/15: Re: OpenCore USB 2.0
75827: 04/11/16: Xilinx EDK 6.3 : DDR Burst Mode
76039: 04/11/23: Re: EDK 6.3i "Entry Point Not Found" error
77021: 04/12/20: Re: Virtex II Pro Memory Questions
77059: 04/12/21: Re: Help with importing a comp. as a netlist, edk6.2i
77062: 04/12/21: Re: DSOCM BRAM I/F Controller
77137: 04/12/25: Re: timer-interrupt not recognized
86758: 05/07/06: Re: Program from external memory
86820: 05/07/07: Re: PowerPC interrupt
103249: 06/05/29: Re: How to add a peripheral IP generated by Coregen to EDK?
104469: 06/06/28: Re: Achieving timing in Xilinx EDK designs
104521: 06/06/29: Re: Achieving timing in Xilinx EDK designs
105123: 06/07/14: Re: EDK adding custom vhdl with multiple arch/entity
105124: 06/07/14: Re: EDK - Debugging software applications located in ISOCM
141778: 09/07/08: Breakdown of utilisation
141790: 09/07/09: Re: Breakdown of utilisation
andi:
142772: 09/08/31: Re: Where is Altera On-Demand Webinars show on radar signal
00andi:
86562: 05/06/30: Re: read & write on SDRAM speed with PPC 300 MHz
<andi_carmon@my-deja.com>:
16649: 99/06/01: Re: Verilog PLI website
16753: 99/06/07: Re: Verilog PLI website
andip1982:
140336: 09/05/09: Re: ISE 10.1 installation troubles on windows Vista 32bit
140337: 09/05/09: Which alternative prog to use for hdl handling ?
00andiweb.de:
86773: 05/07/06: Re: PowerPC interrupt
86774: 05/07/06: Re: Program from external memory
86775: 05/07/06: Re: EDK/ISE 7.1 SmartModel Set-up Issue with ModelSim 6.0a
andpaoli:
81697: 05/03/30: exp(-x) function
Andras Tantos:
52282: 03/02/05: Re: Xilinx Foundation 5.1: reasons to upgrade
52708: 03/02/19: Re: PCB Design for a Xilinx Spartan-II FPGA
52721: 03/02/20: Re: PCB Design for a Xilinx Spartan-II FPGA
52904: 03/02/25: Re: VHDL & FPGA Design tools
55349: 03/05/05: Re: PLL chips
56541: 03/06/08: Controlling FPGA speed with VCCINT
56543: 03/06/08: Re: Controlling FPGA speed with VCCINT
56584: 03/06/09: Re: Controlling FPGA speed with VCCINT
56585: 03/06/09: Re: Controlling FPGA speed with VCCINT
56657: 03/06/10: Re: Controlling FPGA speed with VCCINT
56984: 03/06/20: Re: Controlling FPGA speed with VCCINT
57066: 03/06/22: Re: vga controller
58663: 03/07/30: Re: Parallel Port EPP in FPGA
58664: 03/07/30: Re: using block rams in FPGAs
58677: 03/07/30: Re: Parallel Port EPP in FPGA
59449: 03/08/19: Re: Parallel interface to an FPGA
60558: 03/09/16: Re: fpga +cpu + wireless
60576: 03/09/16: Re: fpga +cpu + wireless
60785: 03/09/22: Re: FPGA implementation in (V)HDL
61228: 03/09/30: Re: Sparten-IIE Configuration (Slave Parallel Mode)
61284: 03/10/01: Re: DP RAM infering
61362: 03/10/02: Re: ISE WebPack 6.1 Impact problem
62520: 03/10/31: Re: Wishbone interface, FPGA newbie and advice
62523: 03/10/31: Re: Are there more I/O pins than I/O blocks?
62558: 03/11/01: Re: Wishbone interface, FPGA newbie and advice
62719: 03/11/05: Re: Announcement
63447: 03/11/21: Re: graphic card accelarator vs. FPGA: which is better for the following task?
63583: 03/11/25: Re: graphic card accelarator vs. FPGA: which is better for the following task?
63769: 03/12/03: Re: Command line in Windows?
63776: 03/12/03: Re: Command line in Windows?
69598: 04/05/14: Re: 5V signals at Spartan-IIE inputs
78841: 05/02/08: Re: SimmStick FPGA module
Andre:
56763: 03/06/13: Re: RISC CPU plus FPGA in small package
64872: 04/01/15: after the synthesis total logic elements are equal zero
66001: 04/02/11: Re: JAM and Xilinx/Altera CPLDs
66064: 04/02/11: Re: JAM and Xilinx/Altera CPLDs
66066: 04/02/12: How many PCB layers ?
66475: 04/02/19: Amontec problems...
126495: 07/11/25: Re: Unable to scan device chain
Andre Bonin:
73217: 04/09/16: Synthesis problems with while and non-constant terminal point.
73295: 04/09/18: Verilog vs VHDL for Loops
73322: 04/09/19: Where are the Cyclones2
73323: 04/09/19: Re: Verilog vs VHDL for Loops
73326: 04/09/19: Re: Where are the Cyclones2
73339: 04/09/20: Re: Where are the Cyclones2
73376: 04/09/21: Re: Verilog vs VHDL for Loops
73613: 04/09/25: PCI FPGA Dev kits/SOPC boards
73631: 04/09/27: Re: embedded linux on FPGA?
Andre G.:
89108: 05/09/05: Quartus2 WEB: Simulating from test bench. Is that possible?
Andre Hergenhan:
4655: 96/11/26: Re: FPGA TEST BOARDS
Andre Klindworth:
1112: 95/05/01: AT&T ORCA data book
1116: 95/05/01: Any experiences with Altera MAX9000 ?
1230: 95/05/19: FPGA market shares
1375: 95/06/09: Need access to Actel ALS tool
1633: 95/08/09: Looking for info on ACM FPGA'96 workshop
1733: 95/08/21: Altera EPM9560 device availability
1830: 95/09/07: Altera MAX+plusII with Windows '95
3035: 96/03/18: Problems with Altera Bitblaster
3038: 96/03/19: Troubles with Altera Bitblaster
3069: 96/03/26: Altera BitBlaster Download tool
3153: 96/04/15: MAX+plusII LPMs, Synthesis Options & AHDL Design Style
3328: 96/05/14: Fitting problems with Altera MAX9560
3606: 96/07/03: FSM encoding in VHDL with MAX+plusII
3590: 96/07/02: Using MAX+plusII under UNIX
Andre Powell:
7008: 97/07/22: Re: Clock generator
15737: 99/04/11: Re: Application Consulting Engineer (ACE)
52462: 03/02/10: Re: Static Timing Analysis
52463: 03/02/10: Re: Synthesis Scripts
52489: 03/02/11: Re: Synthesis Scripts
53294: 03/03/10: Re: Timing Simulation Glitches
53488: 03/03/14: Re: Timing Simulation Glitches
53787: 03/03/23: Re: FPGA specs
Andre Renee:
117521: 07/04/03: Implementing a communication protocol for data transfer over TCP on an FPGA
117529: 07/04/03: Re: Implementing a communication protocol for data transfer over TCP on an FPGA
Andre van der Avoird:
126966: 07/12/07: usb cable driver
126970: 07/12/07: Re: usb cable driver
126987: 07/12/07: Re: usb cable driver
Andre' DeHon:
804: 95/03/04: RE: Limits on on-chip FPGA virtual computing
2875: 96/02/21: Floating Point and Reconfigurable Architectures
2890: 96/02/24: Floating Point on FPGAs -- Numbers are great...
3218: 96/04/29: Proc+FPGA/reconfig-logic
3525: 96/06/14: Reconfigurable Computing -- Figures of Merit
3548: 96/06/19: CLB Size
4167: 96/09/21: BRASS and Re: query: C to FPGA
Andrea:
12690: 98/10/23: ORCAD Compile error
59061: 03/08/07: Excalibur - lpm_syncram
59159: 03/08/11: Re: Excalibur - lpm_syncram
59297: 03/08/14: LogicLock flow
59954: 03/09/02: altera latch synthesis
59961: 03/09/02: Re: altera latch synthesis
59987: 03/09/03: Re: altera latch synthesis
60167: 03/09/06: Re: altera latch synthesis
79720: 05/02/23: Re: XST: How to select the architecture for synthesis?
81485: 05/03/24: Re: ISE 7.1 on Fedora Core 3
"Andrea Marson":
25249: 00/09/01: Re: MP3 in FPGA ?
Andrea Miele:
147397: 10/04/26: Virtex 4 ICAP partial reconfiguration
Andrea Prati:
11279: 98/08/01: Examples of report on FPGA
Andrea Sabatini:
35450: 01/10/05: QuartusII compiler error message
35451: 01/10/05: Re: sensitivity list
37341: 01/12/07: Altera pin drivers
56603: 03/06/10: Acex1k100 & Quartus
56678: 03/06/11: Re: Acex1k100 & Quartus
56718: 03/06/12: Re: Acex1k100 & Quartus
70289: 04/06/11: Microblaze asm and C shared variables
70351: 04/06/14: Re: Microblaze asm and C shared variables
71588: 04/07/23: Xilinx registers resetr value
72192: 04/08/11: Xilinx PowerPC simulation problems
72526: 04/08/23: Xilinx Swift interface Licence (?) problem
74957: 04/10/22: Re: Verilog Simulation problem
74468: 04/10/12: Re: Reading RAM while
74571: 04/10/14: Re: ChipScope Pro : Data Samples and No of Trigger Occurences
75703: 04/11/12: Re: std_logic_vector(0 downto 0)
75861: 04/11/17: Re: Setup violation warning with constant signal in Modelsim/Webpack
76663: 04/12/08: Re: Modelsim Directory
78123: 05/01/25: Updating Xilinx Bitstream/HEX file
78198: 05/01/26: Re: Designing a simple PLB master using EDK 6.3i
78250: 05/01/27: Re: Updating Xilinx Bitstream/HEX file
78554: 05/02/03: Re: problem with Modelsim 5.8 Xilinx Edition
79310: 05/02/17: Re: binary constant divider theory
80167: 05/03/02: Re: Error on launch the Simulator
Andrea Sorio:
27067: 00/11/09: Xilinx PCI Core
27092: 00/11/10: Re: Xilinx PCI Core
27094: 00/11/10: Re: IOBUF's replaced by IBUF's
<andrea.cortis@gmail.com>:
135548: 08/10/07: Newbie question
135551: 08/10/07: Re: Newbie question
135599: 08/10/09: Re: Newbie question
<andrea.pellegrini@gmail.com>:
124646: 07/09/28: Re: FATAL ERROR ISE9.1i
125361: 07/10/23: XPS FIFO PLB device problems... (verilog)
Andrea05:
109678: 06/10/03: FPGA power-up and code relocation (basics)
109692: 06/10/03: Re: FPGA power-up and code relocation (basics)
109731: 06/10/04: Re: FPGA power-up and code relocation (basics)
109760: 06/10/05: Re: FPGA power-up and code relocation (basics)
115886: 07/02/23: Not power of two BRAM size problem
115895: 07/02/23: Re: Not power of two BRAM size problem
119766: 07/05/25: low speed communication
119770: 07/05/25: Re: low speed communication
119775: 07/05/25: Re: low speed communication
120051: 07/05/31: Re: low speed communication
120692: 07/06/13: custom peripheral registers
120837: 07/06/18: Re: custom peripheral registers
122252: 07/07/24: Xint64 ?
122318: 07/07/25: Re: Xint64 ?
124177: 07/09/13: Problem with Microblaze max clocking
124178: 07/09/13: Re: Peripheral Trouble!
Andreas:
47116: 02/09/17: Re: Has ISE 5.1i shipped?
74388: 04/10/10: Newbie, Altera vs Xilinx
92097: 05/11/22: Newbie: Problems with clocks
92139: 05/11/23: Re: Newbie: Problems with clocks
92154: 05/11/23: Re: Newbie: Problems with clocks
107410: 06/08/28: synchronisation on rising and falling edges
andreas:
42149: 02/04/17: Re: bad experience with Xilinx ISE 4.1i and Xilinx hotline suppot
Andreas Baenisch:
80247: 05/03/02: Design Compiler and Xilinx-Libs - Possible ?
Andreas Barthel:
18739: 99/11/11: looking for Xilinx/Actel Board
Andreas Bombe:
33433: 01/07/26: Re: FPGA Express or Spectrum?
Andreas C. Doering:
23556: 00/06/30: RE: Simulating Coregen AsyncFifo with Synopsys VSS
Andreas Doering:
2377: 95/11/25: looking for FPGA prototype platform
2882: 96/02/23: Re: Floating Point and Reconfigurable Architectures
3823: 96/08/07: Pin assignments synopsys->Maxplus2?
3963: 96/08/26: MAXPLUS2 6.2. setup problem (with synopsys)
4206: 96/09/26: hardware implementation of permutation multiplication
4280: 96/10/09: Re: Reversible LFSR?
4837: 96/12/19: Area spent for routing in FPGAs
5193: 97/01/30: Re: FPGA with SRAM
5652: 97/03/04: ALTERA MAX9000 BSCAN
7383: 97/09/05: user access to BSCAN
7636: 97/09/30: Implementation of partial orders
7928: 97/10/31: Slew Rate in ALTERA devices
8466: 97/12/18: Example Problem (was Metastability)
12206: 98/10/05: Power estimation of XILINX XV series
13002: 98/11/10: hard macros design flow for XILINX Foundation Express
13049: 98/11/13: Re: Affordable boundary scan (JTAG) interconnect testing software anybody?
15620: 99/04/03: XILINX CLB architecture
16256: 99/05/12: Re: Synchronizer design?
16296: 99/05/14: On-chip intercinnection system survey?
16348: 99/05/18: Re: Synchronizer design?
17003: 99/06/23: Re: combining multiple xilinx designs into one
18389: 99/10/21: XILINX: XDL - is this a secret?
18612: 99/11/03: Re: WEB reconfigurable FPGA, How?
19376: 99/12/17: Re: Speed grade
19785: 00/01/12: Re: Assignment of pins for thousand+ pin packages
19903: 00/01/17: Re: Random Number Generator
19958: 00/01/20: Indexing functions
20043: 00/01/25: Re: Indexing functions
21471: 00/03/23: Re: Giving fpga's unique id
21519: 00/03/24: Re: FPGA openness
21729: 00/03/30: Re: FPGA openness
21773: 00/03/31: Re: Adrian Thompson's and GA work on Xilinx
22217: 00/05/02: Re: How to Prevent theft of FPGA design
22284: 00/05/04: Re: Init/ line - CRC error ???
24076: 00/07/26: Re: Power PC with Xilinx - what do you think?
25018: 00/08/24: minor problem with 3.1i was (Re: run time doubled)
25067: 00/08/25: Re: make for design flow (was: Deterministic FPGA routing?)
27867: 00/12/13: Re: fpga :CLB locking prevents flops to be in IOB's
28208: 00/12/30: FFs in IOBs in XC4000
Andreas Ehliar:
41967: 02/04/11: Re: Low-cost FPGA + processor board?
88571: 05/08/23: Re: can use bram for VGA
94837: 06/01/18: ISE8.1 on Linux, first impressions
94911: 06/01/19: Re: ISE8.1 on Linux, first impressions
94989: 06/01/20: Re: ISE8.1 on Linux, first impressions
99259: 06/03/22: Re: Parallel Cable IV does not work with parallel to usb cable
99260: 06/03/22: Re: Xilinx programming cable; Linux notebook w/o parallel port; Am I doomed?
99432: 06/03/24: Re: Raggedstone specifications ...
99433: 06/03/24: Re: Raggedstone specifications ...
100126: 06/04/04: Cheap Spartan 3 PCI express starter kit
100141: 06/04/04: Re: MontaVista Linux and Virtex-II & 4
100785: 06/04/18: Re: Xilinx USB Platform Cable not working anymore (linux)
101064: 06/04/25: Re: Xilinx Virtex-4 OCM Usage Issues
101266: 06/04/28: Re: Xilinx Virtex-4 OCM Usage Issues
101864: 06/05/08: Re: FPGA-based hardware accelerator for PC
101865: 06/05/08: Re: FPGA-based hardware accelerator for PC
102299: 06/05/14: Floating point reality check
102626: 06/05/18: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
102965: 06/05/24: Re: FPGA : Constraint for BRAM placements
105873: 06/08/02: Re: Xilinx: Initializing BRAM content in the ngc
107055: 06/08/24: Re: Open source Xilinx JTAG Programmer released on sourceforge.net
107061: 06/08/24: Re: esoteric hardware?
107440: 06/08/28: Question on Virtex-4 CLB
107576: 06/08/30: Re: behavioral vs post-P&R simulation mismatch
107652: 06/08/30: Re: Questions
107796: 06/09/01: Sluggish FPGA Editor/floorplanner/etc in Linux
108160: 06/09/06: RLOC problems
108163: 06/09/06: Re: RLOC problems
108191: 06/09/06: Re: Open-source CableServer for Impact on sourceforge.net
108260: 06/09/07: Re: how can I decrease the time cost when synthesis and implement
108440: 06/09/11: Re: simplyrisc-s1 free core
108467: 06/09/11: Re: simplyrisc-s1 free core
108487: 06/09/12: Re: simplyrisc-s1 free core
108602: 06/09/13: Re: Xilinx Platform Cable USB on Linux: Impact always wants to update Firmware
108939: 06/09/19: Re: resets on synplicity inferred RAMs
109246: 06/09/22: Re: Lattice .bit file format
109857: 06/10/06: ISE 8.2 and partitions from command line
109868: 06/10/06: Re: ISE 8.2 and partitions from command line
109996: 06/10/09: Re: a clueless bloke tells Xilinx to get a move on
110196: 06/10/12: Re: ISE 8.2 and partitions from command line
110197: 06/10/12: Re: VGA timing
111252: 06/10/31: Re: A spectre is haunting this newsgroup, the spectre of metastability
111440: 06/11/03: Re: Help required regarding PCI Master core
111588: 06/11/06: Re: PCIe latency
111634: 06/11/07: Re: XUP USB
111745: 06/11/09: Re: ISE bugs or newbie error?
112052: 06/11/15: Re: VCD (value change dump) files
112146: 06/11/17: Re: Synthesis size of Circuits?
112308: 06/11/20: Re: Synthesis size of Circuits?
112491: 06/11/23: Re: Division of a (rather large) Gate level Combinational Design
112789: 06/11/29: Re: Bus structures question (Spartan 3)
112982: 06/12/04: Re: For those starting with Cypress Ez USB FX2LP and FPGA interfaces -- PART 1
113034: 06/12/05: RLOC weirdness
113134: 06/12/06: Re: How to find an FPGA board
113159: 06/12/07: Re: Xilinx PAR crashing with 'make'
113375: 06/12/12: Re: @(posedge clk)
113387: 06/12/12: Re: About Unstable Operation of ACTEL(A3P1000)....
113406: 06/12/13: Re: RLOC weirdness
113624: 06/12/18: Announce: XDLAnalyze v1.1 and colorized_signals (for ModelSim) v1.1
113668: 06/12/19: Re: Frequency divider ?
113720: 06/12/20: Re: Announce: XDLAnalyze v1.1 and colorized_signals (for ModelSim) v1.1
113740: 06/12/20: Re: Manually creating a LUT in VHDL
113992: 07/01/02: Re: help on Xilinx USB download cable
114561: 07/01/19: Re: "Gate" = ???
114843: 07/01/25: Re: Xilinx ISE 8.2
115046: 07/01/30: Re: Change ROM contents, .bit file
115048: 07/01/30: Re: USB 2.0 Streaming using FPGAs
115101: 07/01/31: Re: Graphics demo using FPGA?
115188: 07/02/02: XST broken for XC9536?
115247: 07/02/05: Re: XST broken for XC9536?
115261: 07/02/05: Re: or1k on spartan 3, 400K gate version
115263: 07/02/05: Re: or1k on spartan 3, 400K gate version
115471: 07/02/12: Re: Weird problem with WP 9.1sp1 and XC95144XL
115541: 07/02/13: Typical clock frequencies of FPGA designs
115664: 07/02/16: Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
115815: 07/02/21: Re: wintel CPU reads across the PCI Express bus
115890: 07/02/23: SystemVerilog?
115899: 07/02/24: Re: SystemVerilog?
115913: 07/02/25: Re: Xilinx Platform cable USB and impact on linux without windrvr
115925: 07/02/26: Re: XST broken for XC9536?
115933: 07/02/26: Re: Xilinx Platform cable USB and impact on linux without windrvr
115934: 07/02/26: Re: Xilinx platform cable USB API?
116027: 07/02/28: Re: Xilinx platform cable USB API?
116136: 07/03/02: Re: Xilinx ISE webpack in Ubuntu?
116401: 07/03/08: Re: Avnet Virtex-4 FX12 mini module
116415: 07/03/08: Re: Avnet Virtex-4 FX12 mini module
116448: 07/03/09: RLOC not working correctly in ISE 8.2 and 9.1?
116450: 07/03/09: Re: data2mem crash
116523: 07/03/12: Re: Power PC embeded in Virtex II Pro. Could I erase it with a new bitstream?
116569: 07/03/13: Re: Initialization of arrays in Verilog
116570: 07/03/13: Re: Power PC embeded in Virtex II Pro. Could I erase it with a new bitstream?
116636: 07/03/14: Re: Xilinx Netlist
116637: 07/03/14: Re: Xilinx Netlist
116658: 07/03/15: Re: Xilinx Netlist
116659: 07/03/15: Re: Xilinx Netlist
116666: 07/03/15: Re: Xilinx Netlist
116804: 07/03/19: Re: RLOC not working correctly in ISE 8.2 and 9.1?
116865: 07/03/20: Re: timing in xilinx fpga
117168: 07/03/25: Re: Tool to convert ISE project into makefile? (for Linux)
117300: 07/03/28: Re: Confuse on Spartan speed
117301: 07/03/28: Re: Help with Xilinx Parallel Cable IV.
117302: 07/03/28: Re: Lattice "Open IP" license is GPL-compatible?
117314: 07/03/28: Re: Help with Xilinx Parallel Cable IV.
117869: 07/04/12: Re: Timing violations though constraints have been met
118014: 07/04/16: Re: Xilinx ISE 9.1
118062: 07/04/17: Re: define variable in ISE9.1 Tcl scripts
118134: 07/04/18: Re: ModelSim Waveform naming question
118159: 07/04/18: ModelSim script for virtual type/function generation
118160: 07/04/18: Re: ModelSim Waveform naming question
118203: 07/04/19: Re: Summer with fpgas
118204: 07/04/19: Regarding drivers for FPGA based PCI cards
118286: 07/04/23: Re: Symbol names in the Design Hierarchy Window of the Xilinx Floorplanner
118352: 07/04/24: Re: VHDL editing with UltraEdit
118392: 07/04/25: Re: Modelsim simulation progress in batch/command line mode?
118405: 07/04/26: Re: VHDL editing with UltraEdit
118422: 07/04/26: Re: Modelsim simulation progress in batch/command line mode?
118670: 07/05/02: Re: Read 64-bit value over PLB
118689: 07/05/02: Re: Xilinx 9.x SW == Total Frustration (so far..)
118690: 07/05/02: Re: Xilinx 9.x SW == Total Frustration (so far..)
118758: 07/05/03: Re: Wait-for / until won't work ? Xilinx Spartan 3
118763: 07/05/03: Re: Wait-for / until won't work ? Xilinx Spartan 3
118815: 07/05/04: Re: Wait-for / until won't work ? Xilinx Spartan 3
119007: 07/05/09: Re: Xilinx software quality - how low can it go ?!
119035: 07/05/10: Re: Xilinx software quality - how low can it go ?!
119036: 07/05/10: Re: Xilinx software quality - how low can it go ?!
119042: 07/05/10: Re: Xilinx software quality - how low can it go ?!
119043: 07/05/10: Re: Darnaw1 - PGA Spartan-3E Module
119086: 07/05/11: Re: Xilinx software quality - how low can it go ?!
119274: 07/05/16: Re: Interfacing DDR RAMs to Virtex 2 Pro on Digilent boards
119346: 07/05/17: Re: An Open-Source suggestion for Xilinx
119741: 07/05/25: Re: Xilinx 8.2 : Multippass P&R
119956: 07/05/30: Re: Xilinx 8.2 : Multippass P&R
119985: 07/05/30: Re: XS40 Download Cable
120102: 07/06/01: Re: Can anyone explain the details of the FPGA design flow in ISE
120128: 07/06/01: Re: ISE/EDK Kubuntu linux installation issues
122409: 07/07/27: Re: Xilinx XC9536 current draw ?
122413: 07/07/27: Re: Anyone know any good vhdl ethernet tutorials?
122685: 07/08/03: Re: Best CPU platform(s) for FPGA synthesis
123272: 07/08/22: Re: Power Reduction Strategy
123713: 07/09/02: Re: FPGA CPU
123732: 07/09/03: Re: Low-level FPGA programming?
123734: 07/09/03: Re: FPGA CPU
123736: 07/09/03: Re: FPGA CPU
124613: 07/09/28: Re: Low-level FPGA programming?
125812: 07/11/06: Re: Digilent V2P Board
125821: 07/11/06: Re: Linux capable free/GPL SOFT CPU for XC3S500E?
126136: 07/11/15: Re: Xilinx Virtex-II Newbie
126172: 07/11/16: Re: Structured way of changing eg time constants for real world build / simulation?
126464: 07/11/23: Re: Xilinx Virtex-II Newbie
127206: 07/12/14: Re: Xilinx Dual processor design
127619: 08/01/04: Re: WebPack on GNU/Linux
127781: 08/01/08: Re: Processor in CPLD
127817: 08/01/08: Re: Low Power CPU Implementation
128121: 08/01/16: Re: speed... CORDIC vs. pure arithmetic expression
128478: 08/01/28: Re: microblaze question
128931: 08/02/11: Re: Marking Flase paths for Timing Ignore + Virtex 2 Pro support
129189: 08/02/18: Re: Linux and the Digilent Basys ?
129286: 08/02/20: Re: Ballpark PLB frequency
129375: 08/02/22: Re: Reconfiguration (on the fly) using SPARTAN 3A
129488: 08/02/26: Typical jitter of high frequency oscillators?
129524: 08/02/27: Re: Typical jitter of high frequency oscillators?
129812: 08/03/06: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
129938: 08/03/11: Contradicting messages from Xilinx' place and route/timing analyzer
130016: 08/03/13: Re: Could I develop a new gui using java based on the script language of ChipScope?
130513: 08/03/26: Re: ISE 10.0 finally with multi-threading and SV support ?
130993: 08/04/08: Re: Protecting design from being downloaded on other (similar) FPGA devices
131055: 08/04/09: Re: Modify POF with new ESB (ROM) content?
131283: 08/04/17: Chip photos of old FPGAs
131293: 08/04/18: Re: Chip photos of old FPGAs
131496: 08/04/23: Re: Verilog state machines, latches, syntax and a bet!
131858: 08/05/05: Re: FPGA Processor for Signal Processing ?
131887: 08/05/06: Re: Getting started with VHDL and Verilog
132263: 08/05/20: Re: synthesis...
132275: 08/05/20: Re: synthesis...
132311: 08/05/21: Re: synthesis...
132329: 08/05/22: Re: synthesis...
132459: 08/05/28: Re: Ph.D Student
132596: 08/06/03: Re: Checksums
132666: 08/06/05: Re: Using ethernet on a Xilnx board (Help appreciated)
133044: 08/06/16: Re: FPGA to solve the two most annoying problems on usenet - Suggestions Welcome
133265: 08/06/23: Re: FPGA JTAG commands
133366: 08/06/26: Re: FPGA area use by module?
134816: 08/09/02: Open source licenses for hardware
134831: 08/09/03: Re: Open source licenses for hardware
135079: 08/09/15: Some random impressions from FPL 2008
135281: 08/09/24: Re: duty cycle significance
135304: 08/09/25: Re: Peter says Good Bye
135315: 08/09/26: Re: Please recommend good textbook or technical report about FPGA coprocessor
135443: 08/10/02: Re: floating point round off errors
135618: 08/10/10: Re: Mismatch between XST and trce delay estimation
135623: 08/10/10: Re: Mismatch between XST and trce delay estimation
135759: 08/10/15: Re: Unexpected output in Post-translate Simulation: PLZ HELP
135790: 08/10/16: A couple of CPLD design challenges for the group
135791: 08/10/16: Re: A couple of CPLD design challenges for the group
135792: 08/10/16: Re: A couple of CPLD design challenges for the group
135799: 08/10/16: Re: A couple of CPLD design challenges for the group
135800: 08/10/16: Re: A couple of CPLD design challenges for the group
135834: 08/10/17: Re: Literature on 100Base-TX request
135843: 08/10/17: Re: A couple of CPLD design challenges for the group
135926: 08/10/22: Re: Design security
135960: 08/10/24: Re: A couple of CPLD design challenges for the group
136021: 08/10/28: Re: Register File distributed all over the FPGA
136023: 08/10/28: Re: Register File distributed all over the FPGA
136049: 08/10/29: Re: Register File distributed all over the FPGA
136270: 08/11/08: Re: Data transfer between CPU and FPGA over PCI bus
136283: 08/11/10: Re: How to handle the problem "timing constraint not met"?
136341: 08/11/12: Re: Linux on Microblaze
136396: 08/11/14: Re: purpose of MULTAND
136440: 08/11/17: Re: purpose of MULTAND
136441: 08/11/17: Re: Synplicity/Synplify and Systemverilog support?
136442: 08/11/17: Re: rank beginner here, need to know where to start to get RS232 comm's working, and ...
136536: 08/11/21: Re: Student FPGAs
136627: 08/11/27: Re: Problem with post-route simulation / timing simulation
136632: 08/11/27: Re: Caches & FPGAs
136785: 08/12/05: Re: Equivalent ASIC Gate Estimate
136826: 08/12/08: Re: Equivalent ASIC Gate Estimate
136889: 08/12/11: Re: mapping to custom architecture
136892: 08/12/11: Doubt about the maximum speed of FPGA clock nets
136925: 08/12/14: Re: Doubt about the maximum speed of FPGA clock nets
137074: 08/12/22: Re: Synthesis Problem
137196: 09/01/01: Classifying different kinds of FPGA optimizations
137198: 09/01/01: Re: Classifying different kinds of FPGA optimizations
137252: 09/01/06: Re: Classifying different kinds of FPGA optimizations
137253: 09/01/06: Re: beginner synthesize question - my debounce process won't synthesize.
137260: 09/01/06: Re: beginner synthesize question - my debounce process won't synthesize.
137274: 09/01/07: Re: Which revision control do fpga designers use (2009)
137417: 09/01/15: Death of the RLOC?
137496: 09/01/21: Re: FPGA granularity (was Re: Actel IGLOO FPGA)
137514: 09/01/21: Re: rank beginner here, need to know where to start to get RS232 comm's working, and ...
137534: 09/01/21: Re: testing a processor
137674: 09/01/27: Re: Got UART Working!!! need syntax help with using ascii/buffer scheduling.
137758: 09/01/29: Re: UART RS232 "hello world" program trial and terror.
137763: 09/01/29: Re: UART RS232 "hello world" program trial and terror.
137766: 09/01/29: Re: UART RS232 "hello world" program trial and terror.
137859: 09/02/01: Re: Heavily pipelined design
137883: 09/02/02: Re: MPEG-1 Layer 3 (Mp3) Encoder and Decoder
137913: 09/02/02: Re: MPEG-1 Layer 3 (Mp3) Encoder and Decoder
138201: 09/02/09: Re: MPEG-1 Layer 3 (Mp3) Encoder and Decoder
138491: 09/02/25: Re: XST hangs on HDL Analysis
138492: 09/02/25: Re: mb-gcc producing incorrect code ???
138652: 09/03/03: Re: Re-synthesizing with minor changes
138675: 09/03/04: Re: writing current date to a register
139082: 09/03/20: Re: What happens at opencores.org?
140265: 09/05/07: Re: board with 2 gigabit ethernet connectors?
140454: 09/05/14: Re: XML for LUT+FF netlist representation in (academic) tools
140508: 09/05/15: Re: Survey: What's a good FPGA-related conference?
140786: 09/05/26: Re: Online tool that generates parallel CRC and Scrambler
140787: 09/05/26: Re: Doubt about a Microblaze Based Multiprocessor SoC
141000: 09/06/02: Re: Has anyone tried to install a Xilinx floating license? The documentation (UG631 (v 11.1.0) April 27, 2009) says that the required
141358: 09/06/20: Re: FDRSE Spartan 3A - Active high/low set/reset
148486: 10/07/27: Re: Announcing AjarDSP - an open source VLIW DSP
152154: 11/07/14: Re: P&R based on the post-map simulation model?
152169: 11/07/15: Modelsim script to print simulation progress and a TCL question
152180: 11/07/15: Re: ASM vs. RAM
152181: 11/07/15: Re: Looking for a FPGA board
152682: 11/09/29: Re: PCI core with expansion ROM support
Andreas Ernst:
86123: 05/06/22: FPGAs in Cray XD1
Andreas F.:
113658: 06/12/19: C2H problems
113718: 06/12/19: Re: C2H problems
Andreas Gauckler:
109391: 06/09/26: Re: ISE Simulator Error 222: SuSE 10.1 Linux
115347: 07/02/08: ISE 9.1 Installation crash SuSE 10.2
122784: 07/08/07: Digilent USB module linux
Andreas Georgiou:
54346: 03/04/08: Dead cpld?
54370: 03/04/09: Re: Dead cpld?
Andreas Gieriet:
19963: 00/01/20: Re: Indexing functions
53426: 03/03/13: Re: Bus Functional Model
Andreas Heiner:
20097: 00/01/27: Re: What has happened to freecore.com ?
20292: 00/02/04: Re: Xilinx Virtex Decoupling Cap Guidelines
20311: 00/02/04: Re: Xilinx Virtex Decoupling Cap Guidelines
20349: 00/02/07: Re: Xilinx Virtex Decoupling Cap Guidelines
20468: 00/02/11: Re: Xilinx Virtex Decoupling Cap Guidelines
20815: 00/02/23: Re: ALTERA BitBlaster
20824: 00/02/23: Re: ALTERA BitBlaster
20885: 00/02/25: Re: Design security
20886: 00/02/25: Re: Xilinx PCI pinout ?
Andreas Hofmann:
2838: 96/02/15: Re: re-routing with locked pinout
3604: 96/07/03: Re: Using MAX+plusII under UNIX
3661: 96/07/10: Re: Using MAX+plusII under UNIX
32576: 01/06/30: Re: free 8 bit cpu core and spartan2
108493: 06/09/12: Xilkernel: Problem with mutex
108497: 06/09/12: Re: Xilkernel: Problem with mutex
108502: 06/09/12: Re: Xilkernel: Problem with mutex
108585: 06/09/13: Xilkernel pthread_mutex_lock() broken Was: Xilkernel: Problem with
108853: 06/09/18: Re: Xilkernel pthread_mutex_lock() broken Was: Xilkernel: Problem
109043: 06/09/20: APU disabled after context switch in Xilkernel
109050: 06/09/20: Re: lwip xilinx
109135: 06/09/21: Re: APU disabled after context switch in Xilkernel
109480: 06/09/27: Re: edk 8.2 user needed
109486: 06/09/27: Re: APU disabled after context switch in Xilkernel
110473: 06/10/16: Re: 75Mhz Spartan3e microblaze
110527: 06/10/17: Re: xilinx power pc & microblaze
116032: 07/02/28: Re: Spartan MicroBlaze
117238: 07/03/27: Re: RISC implementation questions
118410: 07/04/26: Re: Increase Memory Resource in SDRAM.
118465: 07/04/27: Re: Increase Memory Resource in SDRAM.
120736: 07/06/15: Re: How to make a small (<4Kbyte) program for V4 PPC
121455: 07/07/04: ICAP in V4 FX20 only working after Reset
121467: 07/07/05: Re: ICAP in V4 FX20 only working after Reset
121919: 07/07/15: Re: Microblaze and software interrupts?
121950: 07/07/16: Microblaze V4 / FSL2.0 - putfsl_interruptable() not working reliably
121968: 07/07/16: Re: Microblaze V4 / FSL2.0 - putfsl_interruptable() not working reliably
122220: 07/07/24: Re: Interfacing the EDK based video decoder
122223: 07/07/24: Re: Connecting Bram LMB Controller to Microblaze
122488: 07/07/28: Re: Best CPU platform(s) for FPGA synthesis
126046: 07/11/13: Re: EDK 9.2 install problem
126068: 07/11/14: Re: Synthesis-place&route performance test.
126278: 07/11/19: Re: how to KEEP_HIERARCHY [EDK]
126347: 07/11/20: Re: Update to Xilinx ISE 9.2
126355: 07/11/20: Re: New Laptop for work
126533: 07/11/27: Re: scanf and printf in EDK's BSP
126534: 07/11/27: Re: Xilinx Dual processor design
129736: 08/03/04: Re: PARAMETER C_SPLIT error
130026: 08/03/13: Re: microblaze to blockram - Byte-Writes
Andreas Holz:
62205: 03/10/22: Beginners advice for selecting an environment for FPGA design
Andreas Jungmaier:
13287: 98/11/24: Actel FPGA libraries for Synopsys
Andreas Kemper:
10843: 98/06/25: Simple XC95xx isp - howto?
Andreas Kirchgraber:
26558: 00/10/20: DSP-Core C31
Andreas Kirschbaum:
2364: 95/11/23: Call for Papers: FPL '96
Andreas Koch:
216: 94/09/26: Exemplar CORE experiences?
1655: 95/08/11: Re: external connections for efficient internal routing
2911: 96/02/28: Viewlogic WIR or XNF from/to SLIF or BLIF?
5146: 97/01/27: Re: Designing Xilinx with cadence
7751: 97/10/11: Thesis on web: Regular Datapaths on FPGAs
17153: 99/07/05: Virtex: Excessive PAR run-times without user-feedback?
26915: 00/11/03: Re: Alliance 3.2i
32296: 01/06/22: Re: synplicity 6.2.4 'optimizing' instantiated designs
117510: 07/04/03: ISE 9.1i SP3 simulator problems on Linux
117523: 07/04/03: Re: ISE 9.1i SP3 simulator problems on Linux
117896: 07/04/12: Re: ISE 9.1i SP3 simulator problems on Linux
Andreas Koschak:
41849: 02/04/09: Modelsim XE can't handle Clock Dividers with CLKDLL
Andreas Kröpfl:
18491: 99/10/27: FPGA
Andreas Kuehlmann:
9119: 98/02/21: ICCD Call for Papers
Andreas Kugel:
191: 94/09/16: Address of VIRTUAL COMPUTERS Inc ???
384: 94/11/03: Re: about downloading FPGAs
642: 95/01/26: XC4000 boundary scan configuring. How??
781: 95/03/01: FCCM95 conference: Info on US visit requested
801: 95/03/03: Re: FPGA Custom Computing Machine
820: 95/03/07: Re: FPGA Custom Computing Machine
858: 95/03/15: Re: <--> Proposed Newsgroup for Programmable Log
1077: 95/04/25: Re: Lattice low-cost start kit
1355: 95/06/06: LowCost CPLD/FPGA tools ???
1451: 95/06/23: Re: Low cost ISA board
1549: 95/07/13: Synopsys timing simulation of two XC3000 chips
1558: 95/07/14: Re: Q: New XILINX XC6200-FPGA
1756: 95/08/28: Re: AMD MACH eval package ?
1774: 95/08/30: Re: AMD MACH eval package ?
2028: 95/10/04: Re: cheap (free) fpga design software (VHDL
2350: 95/11/22: Re: Low Cost Tools
4970: 97/01/07: Motorola FPGA anyone ?
4974: 97/01/07: Re: Motorola FPGA anyone ?
4975: 97/01/07: Re: Motorola FPGA anyone ?
5364: 97/02/11: Re: Software for FPGA software
5626: 97/03/03: JTAG config on ALTERA FLEX10K10: How?
5646: 97/03/04: Re: JTAG config on ALTERA FLEX10K10: How?
5644: 97/03/04: Re: JTAG config on ALTERA FLEX10K10: How?
5642: 97/03/04: Re: JTAG config on ALTERA FLEX10K10: How?
5650: 97/03/04: Re: JTAG config on ALTERA FLEX10K10: How?
5643: 97/03/04: Re: JTAG config on ALTERA FLEX10K10: How?
5641: 97/03/04: Re: JTAG config on ALTERA FLEX10K10: How?
5693: 97/03/07: Re: JTAG config on ALTERA FLEX10K10: How? SUMMARY
5757: 97/03/12: Re: VHDL & ABEL synthesis tools on 95/NT
5867: 97/03/21: Re: BIT SERIAL MULTIPLY
5640: 97/03/04: Re: JTAG config on ALTERA FLEX10K10: How?
6006: 97/04/04: Re: PCI Bus Problems
6004: 97/04/04: Motorola FPGAs (again)
7239: 97/08/18: Re: Low-cost programming FPGAs (was: Re: free FPGA software from actel)
7448: 97/09/11: Re: daisy-chained bitstreams
7660: 97/10/01: Please comment on new uC+FPGA board
8245: 97/12/03: Re: FPGAs for hobbyist, HELP
34738: 01/09/05: Re: DLL locks with no clock present
34739: 01/09/05: Virtex-2 engineering samples
34761: 01/09/06: Re: Spartan II configuration
34762: 01/09/06: Re: Selection of a suitable FPGA board
36099: 01/10/29: Re: Virtex 2 or E Evaluation Board
36152: 01/10/31: Re: pci-card with Virtex2?
36364: 01/11/07: Re: Virtex II introduction schedule
38462: 02/01/15: Virtex-2 Frequency Synhtesis
46260: 02/08/23: Virtex-2Pro CPU to memory performance
48213: 02/10/14: Xilinx MicroBlaze ZBT ionterface
49174: 02/11/04: Excessive heating on Xilinx XC9500XL
53161: 03/03/05: Problems with Xilinx EDK and Spartan2e devices
53198: 03/03/06: DCM usage in Virtex-2Pro for Rocket I/O and PPC
53542: 03/03/15: Re: Development boards with optics
Andreas Loew:
47120: 02/09/17: Re: Multiple divide by 10
84381: 05/05/18: Xilinx IP: PCI Express
Andreas Merkle:
49381: 02/11/11: problem with rocbuf
Andreas Nett:
91968: 05/11/18: FPGA Reconfiguration : Virtex-4 Frames
Andreas Purde:
32177: 01/06/18: Timing results Xilinx Core Multiplier in FPGA Compiler 2
32200: 01/06/19: Re: Timing results Xilinx Core Multiplier in FPGA Compiler 2
32226: 01/06/20: Re: Timing results Xilinx Core Multiplier in FPGA Compiler 2
32305: 01/06/22: Broken links to DW in Synopsys Sim 2000.12
32373: 01/06/25: Re: Broken links to DW in Synopsys Sim 2000.12
32503: 01/06/28: Instanced Xilinx Core causes FPGA-LINK-7 warning
32600: 01/07/02: Re: VHDL using Xilinx foundation
53202: 03/03/06: implementing unfinished designs
53425: 03/03/13: Xilinx ISE sometimes seems to use old edf-file
Andreas Roland:
38791: 02/01/25: Re: Synthsis Tools for Xilinx
Andreas Sch.:
64551: 04/01/07: Re: Xilinx Question
71268: 04/07/13: Xilinx Virtex 4
Andreas Schallenberg:
76302: 04/11/30: Xilinx Virtex 4 question
76372: 04/12/01: Re: Xilinx Virtex 4 question
76374: 04/12/01: Re: Xilinx Virtex 4 question
112387: 06/11/21: Re: FFT in VHDL (or Verilog) Tutorial
Andreas Schmidt:
8932: 98/02/07: Re: Asic to FPGA
16183: 99/05/07: Re: Xilinx netlister - Workaround needed
21951: 00/04/08: Digital Design/Systems/CAD Engineer looking for position in California
31940: 01/06/08: Re: Flash programming via FPGA's JTAG ????
32546: 01/06/29: Re: Asynchronous design in Virtex FPGA => sleepless nights
32550: 01/06/29: Re: Date/Time at synthesis -> std_logic_vector => just use a ROM
35241: 01/09/26: Digital design/ASIC/FPGA/CAD engineer (MSEE) looking for a new position
35242: 01/09/26: Digital design/ASIC/FPGA/CAD/Hardware engineer (MSEE) looking for a new
Andreas Schwarz:
71989: 04/08/05: Re: nco and phase detector
122864: 07/08/08: Synthesizing fixed_pkg in ISE 9.2
122901: 07/08/09: Re: secure interfacing between an fpga and a connected device
123072: 07/08/15: Re: Synthesizing fixed_pkg in ISE 9.2
123374: 07/08/25: Re: Synthesizing fixed_pkg in ISE 9.2
123452: 07/08/28: Re: Synthesizing fixed_pkg in ISE 9.2
124803: 07/10/04: Re: Optimized bitcounting on FPGA
Andreas Schweizer:
38048: 02/01/03: Re: A Fast counter in VHDL?
49375: 02/11/11: Xilinx Virtex SelectMAP question
49424: 02/11/12: Re: Xilinx Virtex SelectMAP question
49797: 02/11/21: Virtex timing problem
50168: 02/12/04: Re: Virtex timing problem
50186: 02/12/04: Re: Full-Page in SDRAM
51090: 02/12/31: Unused FPGA I/O Pins?
51110: 03/01/02: Re: Unused FPGA I/O Pins?
51118: 03/01/02: Re: interface DRAM to FPGA
52375: 03/02/07: Xilinx Virtex-II Readback
52479: 03/02/11: Re: Xilinx Virtex-II Readback
Andreas Spanias:
3818: 96/08/06: Image Processing and Voice Recognition
Andreas Steinhauer:
143628: 09/10/19: Re: FSM-states after reconf.
Andreas Tillmann:
9529: 98/03/21: My Semiconductor Linkpage
9932: 98/04/14: MY SEMICONDUCTOR LINKPAGE
Andreas Wassatsch:
6076: 97/04/10: Download Xilinx Fpga
6078: 97/04/10: Cadence dfII Layout Plotter: which type are the best solution ?
6642: 97/06/09: readback on xc40xx ?
6657: 97/06/10: Re: readback on xc40xx ?
38057: 02/01/03: Re: Automatically pipeline combinatorial EDIF
43605: 02/05/27: Re: XC4000 series pin compatability
44229: 02/06/14: ISE 4.2i and Synopsys Design Compiler
44230: 02/06/14: Re: ISE 4.2i and Synopsys Design Compiler
126345: 07/11/20: EDK 9.2 and virtex 2 devices
126349: 07/11/20: Re: EDK 9.2 and virtex 2 devices
126353: 07/11/20: Re: EDK 9.2 and virtex 2 devices
126354: 07/11/20: Re: EDK 9.2 and virtex 2 devices
126361: 07/11/20: Re: EDK 9.2 and virtex 2 devices
Andreas Weder:
71139: 04/07/09: Virtex II Pro - Frame Addressing
73296: 04/09/18: AREA_GROUP and Modular Design Flow
Andreas Wehr:
4374: 96/10/22: Re: VHDL for Xilinx designs?
4391: 96/10/23: Re: VHDL for Xilinx designs?
4582: 96/11/18: Re: VHDL adder: how do I get at the carry b
4839: 96/12/19: Cascaded serial PROMS
5689: 97/03/07: Xilinx config pins M0..M2
7809: 97/10/17: PROM for FLEX10K
7810: 97/10/17: [Reposted due to Enlow UCE cancel]: PROM for FLEX10K
8262: 97/12/04: Re: Xilinx pullup / pulldown resistors
Andreas Wolf:
29568: 01/02/27: Re: Spartan II/Virtex DLL with Exemplar - help
29986: 01/03/20: virtex block ram
Andreas Wortmann:
54013: 03/03/31: connecting 2 FPGAs
55375: 03/05/06: Xilinx VirtexII Pro Rocket-IO
Andreas Wuestefeld:
24463: 00/08/09: Timing Constraints
Andreas Wstefeld:
23558: 00/06/30: There is no output on pins
Andreas Wüstefeld:
23953: 00/07/18: download to a xilinx fpga
AndreasWallner:
141863: 09/07/14: Re: How to initialize a Rom with a list of coefficients
141872: 09/07/14: Problem with System ACE, can't get it to work with partitioned Card
141932: 09/07/17: Re: Do you prefer paper or plastic... er, I mean paper or e-books?
141937: 09/07/17: Re: Problem with System ACE, can't get it to work with partitioned
142009: 09/07/21: Re: Problem with System ACE, can't get it to work with partitioned
andreiseb:
149925: 10/12/02: SPI master controller with no embedded microprocessor
150664: 11/02/01: Re: PCI Express Transfer
151215: 11/03/15: Re: Regfile access
Andrej:
32935: 01/07/12: ModelSim v5.5
82875: 05/04/19: Celoxica RC1000: problems accessing fpga control registers
Andrej Jancura:
29821: 01/03/12: Re: Again Spartan II power
38662: 02/01/21: Atmel FPGA configuration memory?!
38689: 02/01/22: Re: Atmel FPGA configuration memory?!
38726: 02/01/23: Re: Atmel FPGA configuration memory?!
38756: 02/01/24: Re: Atmel FPGA configuration memory?!
<andreprado88@gmail.com>:
154897: 13/02/01: Re: MicroBlaze MCS Error.
Andres:
65281: 04/01/23: time set up
Andres Calderon:
75104: 04/10/26: OPB in Verilog
Andres David Garcia Garcia:
14836: 99/02/19: Power estimation on FLEX10K applications
14837: 99/02/19: Re: P&R times for Altera10K200E and Virtex
15178: 99/03/11: FOUNDATION EPIC EDITOR
15252: 99/03/16: Re: Power Estimiation
15253: 99/03/16: Problems with foundation
15280: 99/03/17: Re: Power Estimiation
15341: 99/03/19: Re: Power Estimiation
15342: 99/03/19: Biterby or treillis application
15417: 99/03/23: viterbi coder/decoder
Andres Garcia:
14242: 99/01/21: Power Consumption in FPGAs
14255: 99/01/22: Re: FPGA express warning
Andres Vasquez:
10295: 98/05/10: $$$ This Really Work !!!
Andrew:
34197: 01/08/16: Re: star-wars ascii-animation:)
34299: 01/08/20: Re: star-wars ascii-animation:)
45886: 02/08/09: Re: AES (rijndael) Ip core
71052: 04/07/06: Understanding Xilinx Spartan 3 datasheet IOB timing information
91800: 05/11/13: Re: Add files to Xilinx ISE Project w/script
91997: 05/11/18: Chipscope Pro License Problem
102887: 06/05/22: ModelSim Designer
120316: 07/06/05: System Generator vs Synplify DSP vs Simulink HDL Coder
120334: 07/06/05: Re: System Generator vs Synplify DSP vs Simulink HDL Coder
Andrew Bailey:
11858: 98/09/15: Job: Researcher, Oxford Univ.
Andrew Barnes:
32785: 01/07/09: Re: SpartanII: non clock pad drives clock net ?
32832: 01/07/10: Re: SpartanII: non clock pad drives clock net ?
Andrew Barnish:
35454: 01/10/05: ROM based FSMs
35473: 01/10/06: Re: ROM based FSMs
36880: 01/11/22: Re: Synplicity and BlockRAM?
Andrew batchelor:
21314: 00/03/16: Actel Design with A42MX36 Help
21420: 00/03/22: Re: Actel Design with A42MX36 Help
Andrew Bridger:
32246: 01/06/21: Date/Time at synthesis -> std_logic_vector
32401: 01/06/26: Xilinx logic usage
32604: 01/07/02: Xilinx Foundation vs Foundation ISE?
33507: 01/07/29: Jitter Added by FPGA counter
41856: 02/04/09: Re: Low-cost FPGA + processor board?
41913: 02/04/10: ChipScope ILA, cable requirements
42063: 02/04/14: Using SRL16E Xilinx primitive.
42101: 02/04/15: Re: Using SRL16E Xilinx primitive.
42146: 02/04/16: Re: Using SRL16E Xilinx primitive.
44649: 02/06/25: Foundation ISE 4.2i SP3 release notes
44662: 02/06/26: Applying voltage to FPGA I/O while FPGA is not powered
47296: 02/09/22: Re: Spartan II JTAG reconfiguration bug - workaround
Andrew Brown:
14391: 99/01/28: Re: Ratings for Synplicity Synplify
14814: 99/02/18: Re: Synplify resource usage report for Virtex devices
17935: 99/09/17: Re: speeding up place and route
21540: 00/03/24: Re: Clock disabling
21544: 00/03/24: Re: FPGA openness
21697: 00/03/29: Re: FPGA openness
21698: 00/03/29: Re: FPGA openness
35079: 01/09/20: Re: Clockin on rising AND falling edge
35513: 01/10/09: Re: FPGA reset
35581: 01/10/11: Re: High level synthesis will never work well :)
35590: 01/10/11: Re: High level synthesis will never work well :)
35595: 01/10/11: Re: High level synthesis will never work well :)
35626: 01/10/12: Re: High level synthesis will never work well :)
35632: 01/10/12: Re: High level synthesis will never work well :)
35644: 01/10/12: Re: High level synthesis will never work well :)
35713: 01/10/15: Re: future Xilinx products wish list ...
35904: 01/10/23: Re: Verilog vs. VHDL
35927: 01/10/24: Re: Verilog vs. VHDL
36278: 01/11/05: Re: High level synthesis will never work well :)
andrew browning:
108732: 06/09/15: shift register with clock divder and debounce.....HELP
112092: 06/11/15: ise 7.1
Andrew Buckin:
19188: 99/12/04: Simple programmator for EP910
23666: 00/07/05: Help I/O pin
23794: 00/07/09: I/O Help
23888: 00/07/14: IDE VHDL
Andrew Bunsick:
14201: 99/01/19: ASIC/FPGA Designers Available
14902: 99/02/24: FPGA/ASIC Design Teams Available
17647: 99/08/18: FPGA/ASIC Design Engineers Available
18160: 99/10/04: Contract Design Services
Andrew Burnside:
122988: 07/08/13: Re: DDR/DDR2 controller - core
123053: 07/08/15: Re: Xilinx DDR2 SDRAM controller performance
123054: 07/08/15: Re: DDR/DDR2 controller - core
123943: 07/09/07: Re: PCB Impedance Control
124684: 07/09/30: Re: Own soft-processor
124699: 07/10/01: Re: Own soft-processor
125282: 07/10/19: Re: FPGA pin swapping utility
126226: 07/11/17: Re: FPGA for hobby use
127212: 07/12/14: Re: FPGA Board design basics
130119: 08/03/15: Re: DDR3 speed, Altera vs Xilinx
Andrew Cannon:
3508: 96/06/12: Xilinx 4013E and PCI
12102: 98/09/29: Re: I2C controller references needed!
12103: 98/09/29: Re: Metastability
13174: 98/11/18: Re: Atmel AT17C010?
19296: 99/12/11: Re: JTAG use after FPGA configuration on board
24222: 00/07/30: OT: was Re: Which one is good coding style?
24232: 00/07/31: Re: OT: was Re: Which one is good coding style?
Andrew Crosland:
13552: 98/12/09: Re: ALTERA isp cable
13553: 98/12/09: Re: ALTERA isp cable
Andrew Dauman:
16664: 99/06/01: Synplicity Users Group Announcement
18018: 99/09/23: Re: Synplfy 5.21 and 5.08a
28663: 01/01/19: Re: Synplicity newsgroup?
28670: 01/01/19: Re: Synplicity newsgroup?
58298: 03/07/19: Re: Synplify syn_direct_enable doesn't work for me.
61685: 03/10/09: Re: synplify vqm not able to fit in Quartus
Andrew DeWeerd:
6799: 97/06/28: Re: Smart Card Design and Interface. How?
30689: 01/04/24: Re: PCMCIA implemented with Xilinx. Spec info needed.
32102: 01/06/14: Re: Video Compression on an FPGA
Andrew Doucette:
81729: 05/03/30: Out of Memory Error comes suddenly.
Andrew Dow:
20409: 00/02/09: Lattice isp programming problems
Andrew Dupont:
117253: 07/03/27: Re: EDK : Import Custom Peripheral
Andrew Dyer:
2369: 95/11/24: Re: Xilinx Viewlogic simulation
6019: 97/04/05: Re: PCI Bus Problems
9250: 98/03/04: Re: The case for Linux and EDA
11139: 98/07/21: problems in SDF files from foundation 1.4?
11152: 98/07/21: Re: problems in SDF files from foundation 1.4?
34866: 01/09/12: Re: ISE 4.1
34961: 01/09/17: Re: ISE 4.1
35168: 01/09/25: way to test foundation express version in fe_shell?
70442: 04/06/17: Re: MGT pin details(Xilinx Virtex 2 PRO)
70664: 04/06/23: Re: Nios II and eCos
71180: 04/07/11: Re: Spartan 3 termination question (DCI)
71561: 04/07/22: Re: programmable voltage control of a VCCIO Bank
71932: 04/08/04: Re: VGA Signals
72190: 04/08/11: Re: Power Supply for Xilinx FPGA
72475: 04/08/20: Re: Spooling from FPGA to the PC
72860: 04/09/06: Re: vga to ethernet converter
80140: 05/03/01: Re: Learning resources for Xilinx memory controllers
88949: 05/08/31: Re: Spartan-3 LVDS driving TFT LCD panel..?
88988: 05/09/02: Re: Spartan-3 LVDS driving TFT LCD panel..?
Andrew Feldhaus:
148467: 10/07/26: Connecting "signed" to "std_logic_vector" ports.
148605: 10/08/05: Re: Connecting "signed" to "std_logic_vector" ports.
148684: 10/08/17: Re: Getting started with FPGA
148738: 10/08/19: Re: Getting started with FPGA
Andrew FPGA:
84836: 05/05/29: Xilinx Spartan 3 SSO Guidelines for 3.3V LVCMOS when using "series DCI"
84849: 05/05/30: Re: Xilinx Spartan 3 SSO Guidelines for 3.3V LVCMOS when using "series DCI"
86364: 05/06/26: Xilinx Spartan 3 CLB Slice Options - more detail than in datasheet available?
86371: 05/06/26: Re: Xilinx Spartan 3 CLB Slice Options - more detail than in datasheet available?
86426: 05/06/27: Re: Xilinx Spartan 3 CLB Slice Options - more detail than in datasheet available?
86485: 05/06/28: Re: proth siever in FPGA?
86551: 05/06/29: Re: proth siever in FPGA? [LONG]
86808: 05/07/06: Re: Spartan-3e order of availability?
87554: 05/07/25: Distributed Arithmetic Architecture - LUT Contents
87857: 05/08/02: Re: Asynchronous Priority comparator
87931: 05/08/03: Re: Modulation Clock to set FPGA timing
88348: 05/08/15: Re: Spartan-3 configuration -- peculiar problem
88548: 05/08/22: Re: XST Help - Device Utilization Woes
88617: 05/08/23: Re: DCM does not do anything?
88669: 05/08/24: Re: XST Help - Device Utilization Woes
89103: 05/09/05: Re: Reading internal signals through a testbench.
89620: 05/09/20: Xilinx ISE Passing IO pad attributes using UCF file.
89625: 05/09/20: Re: Xilinx ISE Passing IO pad attributes using UCF file.
90051: 05/10/03: Re: re:FPGA : Decimation Filter
90332: 05/10/10: Re: Power on reset generation in FPGA
97336: 06/02/20: Xilinx Spartan 3 SSO guidelines for CP132 package?
97338: 06/02/20: Re: Xilinx Spartan 3 SSO guidelines for CP132 package?
99322: 06/03/22: Installing ISE 8.1i - don't use a space in the install path
99564: 06/03/26: Clock multiplication without using the Xilinx DCM's
99669: 06/03/27: Re: Clock multiplication without using the Xilinx DCM's
99750: 06/03/28: Re: Xilinx Coregen
99753: 06/03/28: Re: Clock multiplication without using the Xilinx DCM's
99763: 06/03/28: Re: Clock multiplication without using the Xilinx DCM's
99764: 06/03/28: Re: how to immitate clock behavior----Please guide
99895: 06/03/30: Re: USB Interface to Virtex-4
100769: 06/04/17: Xilinx DCI resistor placement guidelines
100995: 06/04/23: Re: Xilinx DCI resistor placement guidelines
101847: 06/05/07: Can an FPGA be operated reliably in a car wheel?
101856: 06/05/07: Re: Can an FPGA be operated reliably in a car wheel?
102417: 06/05/15: Re: Actel Fusion FPGAs
103438: 06/06/01: Re: XIlinx 7.1i ISE problem with Spartan 3e design
105905: 06/08/02: Re: generating sine-like waveforms
106199: 06/08/08: Re: WHAT SITUATION I NEED A BUFFER
109668: 06/10/02: Re: Looking for HDL code for sin( a ) and x ** y Functions
109826: 06/10/05: Re: An implementation of a clean reset signal
109942: 06/10/08: Re: An implementation of a clean reset signal
111186: 06/10/30: Re: FFT help
111725: 06/11/08: Re: can you please help me VHDL coding on CSMA and DCF based project of wireless LAN
111727: 06/11/08: Re: Static Power vs. Temperature
113011: 06/12/04: Re: XEM3010
114461: 07/01/16: Re: Clock Frequency
115833: 07/02/21: Re: Can someone give me some pointers on using ibis models?
124239: 07/09/16: Re: Beginner Advice (Languages, tools etc.)
124256: 07/09/16: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
124892: 07/10/09: Xcell Article on 1.2Gsamples/sec FFT
124997: 07/10/15: Re: Newbie,the simplest way to program an FPGA at home?
125548: 07/10/28: Re: FPGA vs ASIC
125596: 07/10/29: Re: FPGA vs ASIC
125637: 07/10/30: Re: FFT for an arbitrary number of points (not power of 2)
125871: 07/11/07: Re: Custom processor developement issues
126126: 07/11/14: Xilinx Chipscope Pro in EDK system - ILA:how specify separate signals
126164: 07/11/15: Re: Xilinx Chipscope Pro in EDK system - ILA:how specify separate
126626: 07/11/28: Re: Global Reset using Global Buffer
133135: 08/06/18: Re: Fixed point number hardware implementation
133195: 08/06/20: Re: Fixed point number hardware implementation
133762: 08/07/13: How to prevent mapper stripping when synthesizing without IO buffers?
133793: 08/07/15: Re: How to prevent mapper stripping when synthesizing without IO
133796: 08/07/15: Xilinx timing parameter definitions? e.g. Tbxcy, Tcinck, etc? Where
134045: 08/07/22: Re: Xilinx timing parameter definitions? e.g. Tbxcy, Tcinck, etc?
134062: 08/07/23: Xilinx mapper errors out when placing an RLOCed distributed ram in
134698: 08/08/26: Re: need fast FPGA suggestions
136330: 08/11/11: Re: How to constrain time-multiplexed pathes
136361: 08/11/12: Re: Using the FF @ Port pin
136385: 08/11/13: Re: How to constrain time-multiplexed pathes
146834: 10/03/29: Spartan 6 PLL - Why such a strict input jitter requirement?
147153: 10/04/15: Re: I'd rather switch than fight!
Andrew Gabriel:
127738: 08/01/07: Re: Ethernet on recent FPGAs
Andrew Ganger:
126079: 07/11/14: Xilinx Virtex-II Newbie
126080: 07/11/14: Re: Xilinx Virtex-II Newbie
126083: 07/11/14: Re: Xilinx Virtex-II Newbie
126108: 07/11/14: Re: Xilinx Virtex-II Newbie
126109: 07/11/14: Re: Xilinx Virtex-II Newbie
126119: 07/11/15: Re: Xilinx Virtex-II Newbie
126120: 07/11/15: Re: Xilinx Virtex-II Newbie
126139: 07/11/15: Re: Xilinx Virtex-II Newbie
126140: 07/11/15: Re: Xilinx Virtex-II Newbie
126141: 07/11/15: Re: Xilinx Virtex-II Newbie
126145: 07/11/15: Re: Xilinx Virtex-II Newbie
126200: 07/11/16: Re: simulating xilinx block ram with modelsim
126831: 07/12/03: Xilinx Platform USB Cable
Andrew Gray:
33195: 01/07/19: FPGA based SmartMedia controller
33283: 01/07/22: Where can I download A|RT Builder & A|RT Designer
33284: 01/07/22: Maxplus II download sites
34189: 01/08/16: Help with ACEX1K100 device
34196: 01/08/16: Re: Help with ACEX1K100 device
34240: 01/08/17: Re: Help with ACEX1K100 device
34392: 01/08/23: SmartMedia
34688: 01/09/04: Interfacing Verilog and VHDL
34734: 01/09/05: Re: Interfacing Verilog and VHDL
34778: 01/09/07: FPU core
34875: 01/09/12: Fixed or Floating point for MP3 algorithim?
34898: 01/09/13: Re: Fixed or Floating point for MP3 algorithim?
35256: 01/09/27: Maxplus waveform simulations
35521: 01/10/09: Help reading from SmartMedia cards
35538: 01/10/10: Linking components in VHDL
35578: 01/10/11: Re: Linking components in VHDL
35588: 01/10/11: I found the error
36400: 01/11/08: Hex numbers in VHDL
36401: 01/11/08: VHDL testbench question
36409: 01/11/08: Maxplus error
36762: 01/11/19: Modelsim
36775: 01/11/20: Re: Modelsim
Andrew Greensted:
65388: 04/01/27: Xilinx JTAG download under Linux (urgent)
65392: 04/01/27: Re: Xilinx JTAG download under Linux (urgent)
65548: 04/02/02: Re: Xilinx JTAG download under Linux (urgent)
65549: 04/02/02: JTAG pin states
65550: 04/02/02: Re: asynchronous counter an Xilinx FPGA for a newbie
65597: 04/02/03: Re: asynchronous counter an Xilinx FPGA for a newbie
65619: 04/02/03: Re: JTAG pin states
66070: 04/02/12: Re: Sine Wave Generation
66173: 04/02/13: Re: ISE 6.1.03i Linux...
66175: 04/02/13: Re: How many PCB layers ?
70244: 04/06/10: Stupid Xilinx Rubbish
70247: 04/06/10: Help For Linux ISE users (DLC5, impact)
70248: 04/06/10: Re: Not so Stupid Xilinx Rubbish
79782: 05/02/24: Adjustment for FPGA-FAQ 0044
88233: 05/08/12: Xilinx ISE 6.3i on Gentoo Linux
88241: 05/08/12: Re: Xilinx ISE 6.3i on Gentoo Linux
88306: 05/08/15: Re: Xilinx ISE 6.3i on Gentoo Linux
88398: 05/08/17: Xilinx ISE on remtoe Display
88399: 05/08/17: Re: Xilinx ISE on remtoe Display
88409: 05/08/17: Re: Xilinx ISE on remtoe Display
88410: 05/08/17: Re: Evolutionary VHDL code example
88437: 05/08/18: Re: Xilinx ISE on remtoe Display
88644: 05/08/24: Re: Xilinx ISE on remtoe Display
89136: 05/09/06: Any GOSPL Docs?
89885: 05/09/29: Synchronous & Asymchrnous Flip Flop Implementation
89940: 05/09/30: Re: Synchronous & Asymchrnous Flip Flop Implementation
91872: 05/11/15: Celoxica RC1000 Linux driver
94085: 06/01/05: Modelsim FLI: Accessing values from large arrays (RAM)
94138: 06/01/06: Re: Modelsim FLI: Accessing values from large arrays (RAM)
94157: 06/01/06: Re: Modelsim FLI: Accessing values from large arrays (RAM)
94087: 06/01/05: Re: Virtex2 I/O state in configure phase
101087: 06/04/25: XST Internal error: VHDL constant record support
101125: 06/04/26: Re: XST Internal error: VHDL constant record support
116519: 07/03/12: EDK & custom board definitions
116535: 07/03/12: Re: EDK & custom board definitions
118684: 07/05/02: Unused Pin setting on per-pin basis
118692: 07/05/02: Re: Unused Pin setting on per-pin basis
119208: 07/05/15: Re: downto usage in EDK
119209: 07/05/15: Xilinx EDK: Slow OPB write speeds
119215: 07/05/15: Re: Xilinx EDK: Slow OPB write speeds
119219: 07/05/15: Re: Xilinx EDK: Slow OPB write speeds
119237: 07/05/15: Re: Xilinx EDK: Slow OPB write speeds
124198: 07/09/14: Spartan-3E Slave Serial Configuration
124204: 07/09/14: Re: Spartan-3E Slave Serial Configuration
126009: 07/11/12: Spartan3E Slave Serial Daisy chain
126014: 07/11/12: Re: Spartan3E Slave Serial Daisy chain
126036: 07/11/13: Re: Spartan3E Slave Serial Daisy chain
126052: 07/11/13: Re: Spartan3E Slave Serial Daisy chain
126296: 07/11/19: TPS75003 Spartan-3(E) Regulator Design
126298: 07/11/19: Re: TPS75003 Spartan-3(E) Regulator Design
126299: 07/11/19: Re: TPS75003 Spartan-3(E) Regulator Design
126344: 07/11/20: Re: problem with adding custom logic to an IP core (xilinx edk)
126434: 07/11/22: Re: FPGA Editor (9.2.03i) under Linux x86_64
129485: 08/02/26: Re: Picoblaze enhencement and assembler
130735: 08/03/31: JTAG: First of 4 Spartan-3E always UNKNOWN
130737: 08/03/31: Re: JTAG: First of 4 Spartan-3E always UNKNOWN
130765: 08/04/01: Re: JTAG: First of 4 Spartan-3E always UNKNOWN
130773: 08/04/01: Re: JTAG: First of 4 Spartan-3E always UNKNOWN
130838: 08/04/03: Re: JTAG: First of 4 Spartan-3E always UNKNOWN
Andrew Ha:
38529: 02/01/16: I2C multiplexer
Andrew Haley:
13143: 98/11/17: Re: DES in VHDL?
108088: 06/09/05: Re: Forth-CPU design
138999: 09/03/18: Re: Zero operand CPUs
155311: 13/06/23: Re: New soft processor core paper publisher?
155315: 13/06/23: Re: New soft processor core paper publisher?
155420: 13/06/26: Re: New soft processor core paper publisher?
Andrew Hana:
3155: 96/04/15: Re: VHDL conversion function from int to time ...?
3418: 96/05/28: Re: impossible for Synthesizer to optimize FSM??!
3437: 96/05/30: Re: VHDL synthesis & style questions
5768: 97/03/13: Re: Rising_Edge/Falling_Edge Functions
6007: 97/04/04: Re: clock edge specification for Synopsys synthesis
Andrew Holme:
71612: 04/07/24: Image export from Quartus?
72871: 04/09/06: Quartus II and MAX7000S unused pins
72896: 04/09/07: Re: Quartus II and MAX7000S unused pins
73006: 04/09/10: Re: Quartus II and MAX7000S unused pins
73066: 04/09/13: Re: Adding a Delay
73274: 04/09/17: EPM7160SLC84 ex-stock in UK?
73364: 04/09/20: MAX7000 power-up state
74305: 04/10/07: Re: Unused pins
75462: 04/11/06: Re: Data Swtich from LPT to LCD Module!
75501: 04/11/08: Re: Data Swtich from LPT to LCD Module!
77752: 05/01/16: Re: What is the difference between ASIC and FPGA?.
81558: 05/03/27: User I/O via Altera MAX7000S JTAG?
81581: 05/03/28: Re: User I/O via Altera MAX7000S JTAG?
82347: 05/04/11: State of MAX7000S I/O pins before programming
82428: 05/04/12: Re: State of MAX7000S I/O pins before programming
82438: 05/04/12: Quartus POWER_UP_LEVEL bug?
82460: 05/04/13: Re: Quartus POWER_UP_LEVEL bug?
82467: 05/04/13: Re: State of MAX7000S I/O pins before programming
82468: 05/04/13: Re: State of MAX7000S I/O pins before programming
82469: 05/04/13: Re: State of MAX7000S I/O pins before programming
82758: 05/04/17: MAX7000S CPLD tri-state OE delay
82786: 05/04/18: Re: Multi-page schematics (.bdf) in Quartus II?
84739: 05/05/25: lpm_counter bug?
84743: 05/05/25: Re: lpm_counter bug?
84744: 05/05/25: Re: lpm_counter bug?
88780: 05/08/28: CPLD Jitter
88806: 05/08/29: Re: CPLD Jitter
88807: 05/08/29: Re: CPLD Jitter
88808: 05/08/29: Re: CPLD Jitter
88824: 05/08/29: Re: CPLD Jitter
88830: 05/08/30: Re: CPLD Jitter
88877: 05/08/30: Re: CPLD Jitter
91632: 05/11/10: Re: How do i detect ethernet frames of layer 2 using ethereal?
99487: 06/03/25: Re: How to write compact DFF chain?
107647: 06/08/30: Re: Performance Appraisals
112277: 06/11/19: Re: How could the 'Serial write time out' happen
112298: 06/11/19: Re: How could the 'Serial write time out' happen
112495: 06/11/23: DCM Jitter
112496: 06/11/23: Voltage prorating for Spartan 3
112497: 06/11/23: Constraining timing analyser when using two DCMs
112509: 06/11/23: Re: Constraining timing analyser when using two DCMs
112513: 06/11/23: Re: Constraining timing analyser when using two DCMs
112518: 06/11/23: Re: DCM Jitter
112538: 06/11/24: Re: DCM Jitter
112540: 06/11/24: Re: DCM Jitter
112552: 06/11/24: Re: DCM Jitter
112559: 06/11/24: Re: Altera MAX3000A OE and GCLR-Pins
112898: 06/11/30: DCM jitter (again)
112977: 06/12/03: Re: EDk and DCM
114201: 07/01/07: Re: Basic questions about digital phase locked loop
114322: 07/01/11: Re: Xilinx Synchronous FIFOs
114492: 07/01/17: Re: microcode in verilog?
114605: 07/01/20: Re: How can I make xst to infer BlockRAM instead of Distributed RAM
114608: 07/01/20: Re: How can I make xst to infer BlockRAM instead of Distributed RAM
114980: 07/01/28: Re: How to make an internal signal embedded deep in hierarchy to a gloal output signal
119833: 07/05/27: Re: Best way of moving paralell bits of data from over clock domains?
120791: 07/06/16: Re: Xilinx FPGA Pinout spreadsheets
121882: 07/07/14: Re: DCM CLK driving load problem
123133: 07/08/16: Re: Routing JTAG pins thru FPGA
123916: 07/09/07: Re: VCCAUX too high on a Spartan 3 design
124843: 07/10/07: Re: Daisy chaining FPGA with CPLDs
127061: 07/12/10: Re: GAL16V8
138911: 09/03/14: Re: Virtex 5 LVDS
139152: 09/03/22: Spartan 3 LVDS
139161: 09/03/22: Re: Spartan 3 LVDS
139335: 09/03/26: Re: added jitter on FPGAs
139369: 09/03/27: Re: PLL in Actel Igloo part
139884: 09/04/18: Re: Dual-frequency quartz oscillator with a FPGA ?
140599: 09/05/20: DCM Jitter
140605: 09/05/20: Re: DCM Jitter
140686: 09/05/21: Re: DCM Jitter
140751: 09/05/25: Re: Adders with multiple inputs?
141071: 09/06/04: Re: how to write data to a register in the FPGA
141233: 09/06/11: Fast carry chain
141406: 09/06/23: Re: i2c Start and stop detection
141446: 09/06/24: Re: EPM7064 Altera PLD oe1\oe2\gclr1
141533: 09/06/26: Re: EPM7064 Altera PLD oe1\oe2\gclr1
141783: 09/07/08: bufif0 wired-or in Altera FLEX10K
141796: 09/07/09: Re: Generating a negated clock
141807: 09/07/10: Re: Generating a negated clock
142538: 09/08/16: BCD in FPGA
142539: 09/08/16: BCD in FPGA
142559: 09/08/17: Re: BCD in FPGA
142589: 09/08/19: Re: BCD in FPGA
142980: 09/09/11: Re: Behavior of crystal oscillator?
142982: 09/09/11: Re: Behavior of crystal oscillator?
144451: 09/12/08: Re: Cheapest way to get a chipscope compatible cable?
146170: 10/03/07: Spartan 3 minimum clock pulse width
146410: 10/03/16: Spartan 3 LVDS - current mode outputs?
150632: 11/01/30: Discrete time PID control
150634: 11/01/30: Re: Discrete time PID control
150640: 11/01/31: Re: Discrete time PID control
150813: 11/02/14: Re: Xilinx USB programming cable.
151743: 11/05/14: Re: Counter clocks on both edges sometimes, but not when different IO pin is used
151750: 11/05/14: Re: Counter clocks on both edges sometimes, but not when different IO pin is used
151810: 11/05/19: Re: Scoping a glitch
151822: 11/05/21: Re: Can a glitch-free mux be designed in an FPGA?
152053: 11/06/28: Re: Delta-Sigma in an FPGA
152324: 11/08/09: ISE bug?
152326: 11/08/09: LUT glitches (was Re: ISE bug?)
152328: 11/08/09: Re: LUT glitches (was Re: ISE bug?)
152338: 11/08/10: ISE bug found
152432: 11/08/22: MAXDELAY constraint
154192: 12/09/02: Re: General Build Question
154373: 12/10/16: Phase 15.18 placement optimization
154732: 12/12/31: Re: Which to learn: Verilog vs. VHDL?
155211: 13/06/08: Re: A Question about FPGA IO Standard
Andrew Hosmer:
30389: 01/04/05: Altera 20k programming
30403: 01/04/06: Re: Altera 20k programming
30408: 01/04/06: Re: Altera 20k programming
30418: 01/04/07: Re: Altera 20k programming
Andrew Ince:
20765: 00/02/21: Re: multiplier
20771: 00/02/21: Re: BEHAVIOURAL VHDL
23023: 00/06/09: Re: XILINX RAM Useless
23137: 00/06/15: Re: XILINX RAM Useless
23366: 00/06/23: Re: 500 million transistor FPGA's
24432: 00/08/08: Re: tbuf
24512: 00/08/11: Re: tbuf
24508: 00/08/11: Re: Deterministic FPGA routing?
28067: 00/12/20: Re: Question about Xilinx pins at high-frequency
28078: 00/12/20: Re: Is it necessary to synchronize the reset signal in an FPGA ?
32387: 01/06/25: Re: RAM_blocks inference in Leonardo Spectrum!
Andrew Jackson:
132752: 08/06/06: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
146692: 10/03/26: Re: USB 3.0 implementation on FPGA
146793: 10/03/29: Re: USB 3.0 implementation on FPGA
Andrew Kirby:
68138: 04/03/27: Xilinx ChipScope - JTAG Blues
Andrew Klien:
Andrew Krenz:
32281: 01/06/21: Xilinx: Download times with Parallel/Multilinx cable
Andrew Leo:
68845: 04/04/20: What does a "background check" mean? ...
Andrew Lohbihler:
84593: 05/05/22: Looking for core that does a vector product
86336: 05/06/25: Updating FPGA SPROM firmware over the IP network?
87742: 05/07/29: Farrow filter VHDL implementation?
91392: 05/11/04: Anybody understand this ISE 7.1 error, and what to do about it???
91399: 05/11/05: Re: Anybody understand this ISE 7.1 error, and what to do about it???
91425: 05/11/06: Re: Anybody understand this ISE 7.1 error, and what to do about it???
91434: 05/11/06: Re: Anybody understand this ISE 7.1 error, and what to do about it???
91442: 05/11/07: Re: Anybody understand this ISE 7.1 error, and what to do about it???
91578: 05/11/09: Re: Anybody understand this ISE 7.1 error, and what to do about it???
91946: 05/11/17: Re: xst synthesis
91947: 05/11/17: Re: ISE 6.2i strange behavior
91963: 05/11/18: Setting the environment variable in ISE 7.1?
91985: 05/11/18: Re: Setting the environment variable in ISE 7.1?
92079: 05/11/22: Uart core for a virtex-4
92220: 05/11/24: Re: Uart core for a virtex-4
101750: 06/05/05: Re: done pin didn't go high
101751: 06/05/05: Re: ERROR:iMPACT:1210 - '1':Boundary-scan chain test failed at bit position '1'
103942: 06/06/15: Re: Anyone get a Pictiva OLED to work?
109711: 06/10/04: TTL signal to an FPGA I/O pin?
134396: 08/08/08: Re: RS232 Interface
Andrew M. Dyer:
18887: 99/11/20: FPGA Compiler II Altera Edition vs. FPGA Express Xilinx
20123: 00/01/27: Re: XC9500 0,5u Mask: Errors?
21794: 00/03/31: Re: What's so good about antifuse???
Andrew MacCormack:
22980: 00/06/07: Re: Free tools "OpenTech cdrom"
24141: 00/07/27: Re: Which one is good coding style?
31655: 01/06/01: Re: Help requested in choosing a career
35961: 01/10/25: Re: How to make an implementable big counter?
36679: 01/11/15: Re: interleaver delay question
47205: 02/09/20: Re: Multiple divide by 10
49209: 02/11/05: Re: C\C++ to HDL Converter, why not HDL -> C instead
Andrew MacLennan:
109886: 06/10/06: Re: Spartan-3E USB for I/O?
Andrew McCartney:
20776: 00/02/21: JTAG Programmer & Windows 2000
Andrew McMeikan:
51016: 02/12/26: Re: Interested in FPGA design
Andrew Metcalfe:
3183: 96/04/21: Re: Low-power FPGA or EPLD
3184: 96/04/21: Re: What bus is a Xilinx XC1736DP SPROM?
3550: 96/06/20: Re: Xilinx CLB allocation question
4002: 96/09/01: Xilinx Foundation w/64Mb RAM
5542: 97/02/24: Re: Reverse Engineering FPGAs
5930: 97/03/27: Re: Sole source
5991: 97/04/03: QAM in FPGA
Andrew Montreuil:
17634: 99/08/16: We have everything from websites to hardware to software. All to save you money.
Andrew Morley:
2603: 96/01/10: Re: [q][Reverse Engineering Protection]
3684: 96/07/13: Re: What about the XC6200 ?
4651: 96/11/26: Re: Which Mentor Graphics synthesis tool?
4871: 96/12/22: Re: New CAD tools for new Xilinx XC6200 FPGA
5846: 97/03/20: Re: Sole source
7574: 97/09/23: Re: HELP: FIFO's on an FPGA
Andrew Owen:
36517: 01/11/10: Re: ZX81 production run, is there any interest?
36536: 01/11/11: Re: ZX81 production run, is there any interest?
Andrew Papageorgiou:
4827: 96/12/18: Re: How to use Xilinx ?
5787: 97/03/14: Re: Xilinx FPGA & SIMMs
5900: 97/03/24: Re: 8-bit divider in FPGA
Andrew Papageorgiou, SWI, C:
11761: 98/09/08: Re: 22V10 programming
Andrew Paule:
58207: 03/07/16: Re: Combinational logic and gate delays - Help
58349: 03/07/21: Re: synplify pro
58350: 03/07/21: Re: virtex2 map error?
58365: 03/07/21: Re: asynchronous FIFO
58386: 03/07/22: Re: How to choose FPGA device?
58415: 03/07/23: Re: asynchronous FIFO
58455: 03/07/23: Re: workstation for virtex2 - 8000
58484: 03/07/24: Re: Pricing question....
58489: 03/07/24: Re: Should I use ABEL?
58512: 03/07/24: Re: temux
58514: 03/07/25: Re: Reseting the whole thing
58519: 03/07/25: Re: Reseting the whole thing
58611: 03/07/28: Re: Replacing Spartan 300E by 600E
58693: 03/07/30: Re: PLL / DPLL phase question
58696: 03/07/30: Re: DDS question. How to generate a square from a sine wave?
58705: 03/07/31: Re: PLL / DPLL phase question
58800: 03/08/01: Re: How to update LPM_ROM in ALTERA device quickly?
58819: 03/08/01: Re: PLL / DPLL phase question
58820: 03/08/01: Re: PLL / DPLL phase question
58850: 03/08/02: Re: Ground planes on 4-layer PCB
58855: 03/08/02: Re: Size does matter
58859: 03/08/03: Re: Unused Pins on big Virtex-II
58863: 03/08/03: Re: Size does matter
58885: 03/08/03: Re: Gates Counting?
58958: 03/08/05: Re: JTAG programmers
59013: 03/08/06: Re: Gates Counting?
59019: 03/08/06: Re: Gates Counting?
59110: 03/08/08: Re: Virtex-E power trace
59127: 03/08/08: Re: Virtex-II RocketIO: Serial ATA?
59137: 03/08/09: Re: Virtex-II RocketIO: Serial ATA?
59142: 03/08/10: Re: Virtex-II RocketIO: Serial ATA?
59312: 03/08/14: Re: Virtex II Output Impedance
59361: 03/08/16: Re: Virtex II Output Impedance
59399: 03/08/18: Re: Altera JTAG verification
59410: 03/08/18: Re: Altera JTAG verification
59469: 03/08/20: Re: 22V10, ABEL & Current Design Tools?
59522: 03/08/20: Re: 22V10, ABEL & Current Design Tools?
59530: 03/08/21: Re: 22V10, ABEL & Current Design Tools?
59534: 03/08/21: Re: 22V10, ABEL & Current Design Tools?
59571: 03/08/21: Re: 22V10, ABEL & Current Design Tools?
59711: 03/08/26: Re: What is the context switching time
59712: 03/08/26: Re: Free FPGA samples anywhere?
59723: 03/08/26: Re: What is the context switching time
59751: 03/08/27: Re: Convert Jedec to logical equations
59803: 03/08/28: Re: Selecting between two clock signals
59805: 03/08/28: Re: Thinking out loud about metastability
59822: 03/08/28: Re: Thinking out loud about metastability
59826: 03/08/29: Re: Convert Jedec to logical equations
59827: 03/08/29: Re: Convert Jedec to logical equations
59902: 03/08/31: Re: Thinking out loud about metastability
60161: 03/09/05: Re: ISE: use verilog-modules in an vhdl-design-flow
60165: 03/09/05: Re: Original (5V) Xilinx Spartan ?
60344: 03/09/10: Re: CMOS camera w/ USB2 -- crazy?
60345: 03/09/10: Re: Newbee question? Schematic entry
60367: 03/09/11: Re: CMOS camera w/ USB2 -- crazy?
60387: 03/09/11: Re: CMOS camera w/ USB2 -- crazy?
60438: 03/09/12: Re: frequency constraint changes routability
60468: 03/09/13: Re: logic from jed file
60476: 03/09/14: Re: logic from jed file
60621: 03/09/17: Re: Actel Desktop Schematic Viewer
60728: 03/09/19: Re: LVDS in Xilinx (Spartan-3)
60738: 03/09/20: Re: show-ahead FIFOs
60745: 03/09/21: Re: show-ahead FIFOs
60749: 03/09/21: Re: show-ahead FIFOs
60796: 03/09/22: Re: show-ahead FIFOs
60797: 03/09/22: Re: Synchronous counter enable pulse length
61333: 03/10/01: Re: Good VHDL/Verilog editor?
Andrew Phillips:
382: 94/11/03: Re: High Bus Drive (24mA) FPGAs/CPLDs?
525: 94/12/20: Re: Any Way to Download a XNF to FPGA
4091: 96/09/10: Re: FPGA design project
4092: 96/09/10: Which FPGA design tools do you use ??
9266: 98/03/05: ++ TMS320C6x DSP info website ++
9922: 98/04/14: ++ TMS320C6x DSP info website ++
10338: 98/05/13: ++ TMS320C6x DSP info website ++
10671: 98/06/10: ++ TMS320C6x DSP info website ++
11061: 98/07/16: ++ TMS320C6x DSP info website ++
11995: 98/09/23: easier testing for PCI cards??
Andrew Pichler:
147545: 10/05/01: Cheap FPGAs for tutorial
Andrew Plumb:
4394: 96/10/23: Suggestions for inexpensive FPGA EVM (new and used)?
13642: 98/12/15: Samples of Xilinx Virtex XVC300+?
13645: 98/12/16: XCV300 Samples? (not Re: Samples of Xilinx Virtex XVC300+?)
13664: 98/12/16: Re: Samples of Xilinx Virtex XVC300+?
Andrew Reddig:
19258: 99/12/09: JTAG programming problem with multiple Altera MAX7000A devices
19297: 99/12/10: Re: JTAG programming problem with multiple Altera MAX7000A devices
Andrew Reilly:
66453: 04/02/20: Re: Dual-stack (Forth) processors
66723: 04/02/25: Re: difference btw H/W & S/W implementations !!
146843: 10/03/30: Re: Which is the most beautiful and memorable hardware structure in a
152616: 11/09/18: Re: The Manifest Destiny of Computer Architectures
152622: 11/09/19: Re: The Manifest Destiny of Computer Architectures
152632: 11/09/19: Re: The Manifest Destiny of Computer Architectures
Andrew Rogers:
34808: 01/09/08: Xilinx dev. kit for Linux?
34814: 01/09/09: Alliance: xlmap, XC3020
51370: 03/01/12: Open FPGA please!
51374: 03/01/12: Re: Open FPGA please!
51380: 03/01/12: Re: Open FPGA please!
51387: 03/01/12: Re: Open FPGA please!
51389: 03/01/12: Re: CONCEPT OF BALL GRID ARRAY
51431: 03/01/13: Re: Open FPGA please!
51449: 03/01/13: Re: Open FPGA please!
51452: 03/01/14: Re: Open FPGA please!
51531: 03/01/15: Problem with XST libraries.
51534: 03/01/16: Re: Problem with XST libraries.
51824: 03/01/23: Re: Problem with XST libraries.
51989: 03/01/28: XC3020 .nph
52003: 03/01/28: Re: XC3020 .nph
71420: 04/07/18: Re: Xilinx 6.2i ISE WebPACK running under wine?
71426: 04/07/18: Re: Xilinx 6.2i ISE WebPACK running under wine?
71513: 04/07/20: Re: Xilinx 6.2i ISE WebPACK running under wine?
71536: 04/07/21: Re: Xilinx 6.2i ISE WebPACK running under wine?
72107: 04/08/09: Impact running on wine?
72307: 04/08/14: Free Spartan3 download program for GNU/Linux
72312: 04/08/14: Re: Free Spartan3 download program for GNU/Linux
72313: 04/08/14: Re: Free Spartan3 download program for GNU/Linux
72329: 04/08/15: Re: Free Spartan3 download program for GNU/Linux
72332: 04/08/15: Re: Free Spartan3 download program for GNU/Linux
72434: 04/08/18: Free Flash PROM programming tool for GNU/Liunx
72440: 04/08/19: Re: Free Flash PROM programming tool for GNU/Liunx
72679: 04/08/28: Counter counting on both clock edges.
72701: 04/08/29: Re: Counter counting on both clock edges.
72720: 04/08/30: Re: Counter counting on both clock edges.
72797: 04/09/02: Re: Xilinx in Linux
73101: 04/09/14: Re: clock divider
114349: 07/01/12: xc3sprog
114350: 07/01/12: Re: xc3sprog
114372: 07/01/13: Re: xc3sprog
Andrew Sanger:
Andrew Shelley:
172: 94/09/08: I Cube FPIDs
603: 95/01/17: ACTEL and EXEMPLAR
1037: 95/04/19: Exemplar to Powerview
1562: 95/07/17: ROM synthesis
Andrew Siska:
4275: 96/10/08: Atmel Serial Configuration EEPROM - AT17C128
4287: 96/10/09: Re: Atmel Serial Configuration EEPROM - AT17C128
4321: 96/10/14: Update on Atmel AT17C128 Problem
Andrew Smallshaw:
80919: 05/03/14: Re: (Stupid/Newbie) Question on UART
81174: 05/03/18: Re: (Stupid/Newbie) Question on UART
132731: 08/06/05: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
132733: 08/06/05: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
Andrew Steer:
62510: 03/10/31: Minimalist RS232 on Cyclone
Andrew Tubbiolo:
55138: 03/04/28: Use of bidir ports on Flex 10k.
Andrew V. Nesterov:
9657: 98/03/28: Re: New radix-4 CORDIC for computing sine and cosine
Andrew Valentine:
4269: 96/10/08: Require micrograph picture of an antifuse
Andrew Veliath:
10190: 98/05/03: Xilinx Foundation and Linux
10204: 98/05/03: Re: Xilinx Foundation and Linux
10484: 98/05/22: Re: Minimal ALU instruction set.
Andrew W. Hill:
137097: 08/12/22: EDK map error 1492 - incompatible programming error
137114: 08/12/23: Re: EDK map error 1492 - incompatible programming error
137227: 09/01/04: EDK terminates in unusual way (map phase 6.2)
138743: 09/03/06: Making static C libraries in Xilinx EDK
Andrew W. Reynolds:
42280: 02/04/19: Re: Simulating Unisim
Andrew Ward:
93374: 05/12/20: Interactive Logic
96155: 06/01/31: Interactive Logic software now available for download
96935: 06/02/14: Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?
96939: 06/02/14: Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?
Andrew Webb:
31248: 01/05/16: Ideas for Faster XILINX compilations ?
31283: 01/05/17: Re: Ideas for Faster XILINX compilations ?
Andrew Wheeler:
1480: 95/06/27: Re: Help with Viewlogic
1966: 95/09/25: Re: Why does MAX5000 is getting hot?
Andrew Whyte:
80547: 05/03/08: File I/O with Synplify
80644: 05/03/09: Re: File I/O with Synplify
Andrew Wolfe:
339: 94/10/24: Re: I/O pin currents on Xilinx FPGAs?
Andrew Xiang:
42158: 02/04/17: does multilinx driver work on winxp?
<andrew.hood@gmail.com>:
101273: 06/04/28: Xilinix SPI programming with USB Platform Cable
102397: 06/05/15: Microblaze dcm_module problems
102473: 06/05/16: Re: Microblaze dcm_module problems
<andrew.nelson@cdott.com>:
11235: 98/07/29: low power FPGAs
<andrew.nesterov@softhome.net>:
131495: 08/04/23: 10.1 EDK - How can I create a user library in SDK?
134011: 08/07/21: Xilinx SDK 9.2 memory monitor problem
<andrew.newsgroup@gmail.com>:
140464: 09/05/14: EMACS VHDL mode: how to rescan project so that makefile generates
140637: 09/05/20: Can we expect ISE Gui and makefile to produce identical bit files?
140745: 09/05/24: Re: EMACS VHDL mode: how to rescan project so that makefile generates
<andrew29@littlepinkcloud.invalid>:
69880: 04/05/23: Re: Transputer on FPGA
andrew<AT>rogerstech<DOT>co<DOT>uk:
70577: 04/06/21: Linux.
71413: 04/07/18: Xilinx 6.2i ISE WebPACK running under wine?
<andrew_f66@my-deja.com>:
26394: 00/10/14: Sinusoidal PWM on a Xilinx FPGA
26395: 00/10/14: Sinusoidal PWM on Xilinx FPGA
Andrew_from_Synplicity:
83016: 05/04/21: Re: Do Synplify DSP and Accelchip support multiple clock domains?
83128: 05/04/24: Re: Do Synplify DSP and Accelchip support multiple clock domains?
<andrewfelch@gmail.com>:
100652: 06/04/14: Counting bits
100664: 06/04/14: Re: Counting bits
100666: 06/04/15: Re: Counting bits
100675: 06/04/15: Re: Counting bits
100716: 06/04/16: Re: Counting bits
100827: 06/04/18: Re: Counting bits
101039: 06/04/24: Max and Argmax across 1,000 unsigned 10-bit numbers
101081: 06/04/25: Re: Max and Argmax across 1,000 unsigned 10-bit numbers
101100: 06/04/25: Re: Max and Argmax across 1,000 unsigned 10-bit numbers
<andrewgschmidt@gmail.com>:
104466: 06/06/27: PLB IPIF Master Read Failure
Andrey Likholit:
59962: 03/09/02: Re: Input comparator
60132: 03/09/05: Re: Disable Pull up
Andrey Ushenin:
18570: 99/11/01: Re: Xilinx TPSYNC constraint
Andries Kruithof:
528: 94/12/21: Re: Analog FPGA ???
Andris:
151616: 11/04/26: Re: EDK - program behavior
Andromodon:
81844: 05/04/01: Re: Out of Memory Error comes suddenly.
Andrzej Ekiert:
36186: 01/11/01: Re: LeonardoSpectrum-Altera stability
45726: 02/08/02: Spartan II BlockRAM - inverting control signals
45734: 02/08/02: Re: Spartan II BlockRAM - inverting control signals
45749: 02/08/04: Re: Spartan II BlockRAM - inverting control signals
Andy:
58561: 03/07/26: Virtex II boards with PCI 66MHz support.
68387: 04/04/02: vertex II vs Stratix
70663: 04/06/22: Division in Xilinx
84927: 05/06/01: Anybody know cost/supplier for Virtex-4 LX40?
94003: 06/01/04: Re: Timing problem in ModelSim, Post-Route Simulation.
94028: 06/01/04: Re: Timing problem in ModelSim, Post-Route Simulation.
94000: 06/01/04: Re: Start up condition of flip flops in FPGA?
93998: 06/01/04: Re: Using posedge and negedge causing me grief
94308: 06/01/09: Re: Question on Alias in VHDL
97310: 06/02/20: Re: multiphase data extraction question
97374: 06/02/21: Re: DIFF_OUT buffer example
98361: 06/03/08: Re: 5v Xilinx development board
99788: 06/03/29: Re: Keystroke saving w/ IEEE.Numeric_Std
99943: 06/03/31: Re: PCB Bypass Caps
100079: 06/04/03: Re: Inferring RAM with FOR loop
100081: 06/04/03: Re: PCB Bypass Caps
100083: 06/04/03: Re: PCB Bypass Caps
101013: 06/04/24: Re: Xilinx DCI resistor placement guidelines
101222: 06/04/27: Re: Synplify is not translating xilinx template for block ram
101318: 06/04/28: Re: initializing array of registers in XST
101534: 06/05/02: Re: Reset
102883: 06/05/22: Re: Building a board with Spartan 3 FPGA.
103399: 06/06/01: Re: combining state machines.
103404: 06/06/01: Re: Quartus and source control
103596: 06/06/06: Re: Efficient implementation of Address Decoding logic
103602: 06/06/06: Re: Efficient implementation of Address Decoding logic
103610: 06/06/06: Re: Efficient implementation of Address Decoding logic
103638: 06/06/07: Re: Efficient implementation of Address Decoding logic
103639: 06/06/07: Re: FlipChip BGA Conformal Coating
103695: 06/06/08: Re: Rumor Control:: Will Quartus phase out supporting AHDL?
103721: 06/06/09: Re: Efficient implementation of Address Decoding logic
103806: 06/06/12: Re: Rumor Control:: Will Quartus phase out supporting AHDL?
103821: 06/06/12: Re: How to get lowest price for a ModelSim license?
103849: 06/06/13: Re: Rumor Control:: Will Quartus phase out supporting AHDL?
104155: 06/06/20: Re: FSM State Minimization on FPGAs
104209: 06/06/21: Re: FSM State Minimization on FPGAs
104313: 06/06/23: Re: xst can, but vcomp can't
104531: 06/06/29: Re: Generic synthesis target in Synplify Pro
104799: 06/07/06: Re: Inferring multiple-DSP48 pipelined multiplier in VHDL
104800: 06/07/06: Re: stable reset in fpga
104801: 06/07/06: Re: Can I use all 18bits of a BlockRAM?
104980: 06/07/11: Re: High-speed DAC/ADC with FPGA
104989: 06/07/11: Re: High-speed DAC/ADC with FPGA
105184: 06/07/17: Re: Need for reset in FPGAs
105185: 06/07/17: Re: design partition across multiple FPGAs
105368: 06/07/20: Re: Hardware book like "Code Complete"?
105478: 06/07/24: Re: Hardware book like "Code Complete"?
105484: 06/07/24: Re: ROM implementation
105536: 06/07/25: Re: Hardware book like "Code Complete"?
105540: 06/07/25: Re: Hardware book like "Code Complete"?
105584: 06/07/26: Re: Hardware book like "Code Complete"?
105629: 06/07/27: Re: Rocket IO as a high speed sampler
105891: 06/08/02: Re: Hardware book like "Code Complete"?
106084: 06/08/07: Re: How do I treat "default" case which is useless?
106088: 06/08/07: Re: Counter status flags don't stay asserted not sure why?
106091: 06/08/07: Re: verilog versus vhdl
106097: 06/08/07: Re: How do I treat "default" case which is useless?
106104: 06/08/07: Re: verilog versus vhdl
106112: 06/08/07: Re: How do I treat "default" case which is useless?
106499: 06/08/14: Re: synthesis intelligence of quartus regarding range of values
106578: 06/08/15: Re: IIR filter example ?
107011: 06/08/23: Re: Timing
107104: 06/08/24: Re: Style of coding complex logic (particularly state machines)
107431: 06/08/28: Re: synchronisation on rising and falling edges
107450: 06/08/28: Re: Style of coding complex logic (particularly state machines)
107452: 06/08/28: Re: Style of coding complex logic (particularly state machines)
107468: 06/08/28: Re: Style of coding complex logic (particularly state machines)
107626: 06/08/30: Re: Style of coding complex logic (particularly state machines)
107904: 06/09/02: EDK 7.1
108452: 06/09/11: Re: RESET Signals
108454: 06/09/11: Re: RESET Signals
108503: 06/09/12: Re: xilinx bram instantation template in vhdl?
109041: 06/09/20: Re: VHDL oddity
110015: 06/10/09: Re: An implementation of a clean reset signal
110160: 06/10/11: Re: nicer code => slower code??
110484: 06/10/16: Re: Scoreboard and Checker in Testbench?
110604: 06/10/18: Re: Cheapest FPGA board to study VHDL on
111161: 06/10/30: Re: clock multiplexor device
111162: 06/10/30: Re: Survey: simulator usage
111166: 06/10/30: Re: Taking forever to synthesise (XILINX ISE 8.1i)
111227: 06/10/31: Re: A spectre is haunting this newsgroup, the spectre of metastability
111312: 06/11/01: Re: Dual Port RAM
111315: 06/11/01: Re: Spectre of Metastability Update
111325: 06/11/01: Re: De-serializer using Xilinx DCM
111753: 06/11/09: Re: abel to vhdl converter
111833: 06/11/10: Re: bidirectional bus => mux
112042: 06/11/15: Re: Influence of temperature and manufacturing to propagation delay
112078: 06/11/15: Re: Influence of temperature and manufacturing to propagation delay
112101: 06/11/16: Re: Influence of temperature and manufacturing to propagation delay
112792: 06/11/29: Re: Hardware in the loop simulation for Altera design
112802: 06/11/29: Re: So who has used Lattice FPGAs recently?
112803: 06/11/29: Re: Bus structures question (Spartan 3)
113193: 06/12/07: Re: Recursive component instantiation
113441: 06/12/13: Re: electrical interface problem LVPECL - LVDS multi-inputs
113488: 06/12/14: Re: How does FPGA tools infer FIFO
113491: 06/12/14: Re: electrical interface problem LVPECL - LVDS multi-inputs
113778: 06/12/21: Embedded Development Tools
113818: 06/12/22: Embedded Development Tools
114580: 07/01/19: Re: Beginner VHDL questions
115273: 07/02/05: Re: help with Design Compiler -> Quartus
117066: 07/03/22: Re: FF's are inffered instead of distributed RAM
117245: 07/03/27: Re: A suggestion for a new input interface for functions in VHDL: XOR(a0, a1, ...)
117316: 07/03/28: Re: A suggestion for a new input interface for functions in VHDL: XOR(a0, a1, ...)
117537: 07/04/03: Re: RFC: VHDL testbench enhancements
117761: 07/04/09: File open, read and write in Xilinx EDK 7.1
118019: 07/04/16: Re: Order of the synchronous operations
118086: 07/04/17: Re: type/subtype definition in entity
118102: 07/04/17: Re: 80000 Bit Shift Register
118185: 07/04/19: Re: Back annotating to RTL
118190: 07/04/19: Re: VHDL source code for polyphase filter
118440: 07/04/26: Re: VHDL editing with UltraEdit
118623: 07/05/01: Re: synthesis tools
118650: 07/05/01: Re: synthesis tools
118765: 07/05/03: Re: Wait-for / until won't work ? Xilinx Spartan 3
118803: 07/05/03: Re: Wait-for / until won't work ? Xilinx Spartan 3
118915: 07/05/07: Re: V5 LVPECL Inputs
118930: 07/05/07: Re: V5 LVPECL Inputs
119088: 07/05/11: Re: 'EVENT (or rising_edge) static prefix requirement....
119505: 07/05/21: Re: VHDL newbie: building sequential circuits with basic gates
119506: 07/05/21: Re: Timing not met but working on board
119537: 07/05/22: Re: VHDL newbie: building sequential circuits with basic gates
119774: 07/05/25: Re: How to code a bidirectional databus?
120407: 07/06/06: Re: What should be taken care of when two FPGA broad connected together?
120582: 07/06/11: Re: synthesis - design compiler or synplify pro?
120607: 07/06/11: Re: synthesis - design compiler or synplify pro?
121177: 07/06/27: Re: Bidirectional LVDS
121617: 07/07/09: Re: Synplify Problem
122062: 07/07/18: Re: 1ms delay in V5 FPGA
122106: 07/07/19: Re: Latches
122562: 07/07/31: Re: Xilinx/ModelSim bug ? Clocking headache ...
122627: 07/08/01: Re: Xilinx/ModelSim bug ? Clocking headache ...
123066: 07/08/15: Re: Xilinx PACKER warning bout carry
123270: 07/08/22: Re: Power Reduction Strategy
123271: 07/08/22: Re: Need to force all signals in a design to a known value at start of simulation
123293: 07/08/22: Re: Power Reduction Strategy
123295: 07/08/22: Re: Need to force all signals in a design to a known value at start of simulation
123315: 07/08/23: Re: Need to force all signals in a design to a known value at start of simulation
123319: 07/08/23: Re: Xilinx / ISE multi-cycle path constraint pitfall
123411: 07/08/27: Re: Null statement in VHDL
123413: 07/08/27: Re: Null statement in VHDL
123414: 07/08/27: Re: tricking bitgen into creating rom-like behavior
123476: 07/08/28: Re: New keyword 'orif' and its implications
123481: 07/08/28: Re: Null statement in VHDL
123484: 07/08/28: Re: New keyword 'orif' and its implications
123539: 07/08/29: Re: New keyword 'orif' and its implications
123597: 07/08/30: Re: New keyword 'orif' and its implications
123606: 07/08/30: Re: New keyword 'orif' and its implications
123630: 07/08/31: Re: New keyword 'orif' and its implications
123634: 07/08/31: Re: New keyword 'orif' and its implications
123656: 07/08/31: Re: New keyword 'orif' and its implications
123762: 07/09/04: Re: New keyword 'orif' and its implications
123763: 07/09/04: Re: New keyword 'orif' and its implications
123767: 07/09/04: Re: New keyword 'orif' and its implications
123772: 07/09/04: Re: New keyword 'orif' and its implications
123816: 07/09/05: Re: Null statement in VHDL
123820: 07/09/05: Re: Null statement in VHDL
123824: 07/09/05: Re: New keyword 'orif' and its implications
123830: 07/09/05: Re: New keyword 'orif' and its implications
123831: 07/09/05: Re: New keyword 'orif' and its implications
123878: 07/09/06: Re: New keyword 'orif' and its implications
123891: 07/09/06: Re: New keyword 'orif' and its implications
124001: 07/09/10: Re: VHDL Synthesis Error
124002: 07/09/10: Re: Is it possible to perform gate level simulation on a design without a reset?
124060: 07/09/11: Re: Uses of Gray code in digital design
124137: 07/09/12: Re: Address sensitive process, Xilinx virtex2pro
124138: 07/09/12: Re: Good VHDL reference?
124146: 07/09/12: Re: Address sensitive process, Xilinx virtex2pro
124209: 07/09/14: Re: Is post-place and route simulation useful?
124220: 07/09/14: Re: Physical Design Contribution to FPGA/CPLD success
124244: 07/09/16: Re: Spartan-3E Slave Serial Configuration
124595: 07/09/27: Re: Bug in Synplify?
124623: 07/09/28: Re: Bug in Synplify?
124639: 07/09/28: Re: Bug in Synplify?
124794: 07/10/04: Re: Bug in Synplify?
125192: 07/10/17: Re: High level FPGA work flow: available tool?
125264: 07/10/18: Re: FPGA pin swapping utility
125335: 07/10/22: Re: microprocessor on fpga problems
125432: 07/10/25: Re: Changing refresh rate for DRAM while in operation?
125496: 07/10/26: Re: Changing refresh rate for DRAM while in operation?
125500: 07/10/26: Re: Signetics N82F101F
125566: 07/10/29: Re: Changing refresh rate for DRAM while in operation?
125595: 07/10/29: Re: FPGA Configuration
125623: 07/10/30: Re: FPGA vs ASIC
125657: 07/10/31: Re: Is it possible to debug a vhdl design over jtag?
125791: 07/11/05: Re: Global Variables
125833: 07/11/06: Re: not totally repulsive
125842: 07/11/06: Re: not totally repulsive
125908: 07/11/08: Re: not totally repulsive
125941: 07/11/09: Re: not totally repulsive
126048: 07/11/13: Re: Structured way of changing eg time constants for real world build / simulation?
126049: 07/11/13: Re: bidirectional in fpga
126057: 07/11/13: Re: Structured way of changing eg time constants for real world build / simulation?
126162: 07/11/15: Re: FPGA for hobby use
126669: 07/11/29: Re: What tools do you use ? Why ?
126880: 07/12/05: Re: What's the difference for VHDL code between simulation and
126881: 07/12/05: Re: What's the difference for VHDL code between simulation and
126954: 07/12/06: Re: What's the difference for VHDL code between simulation and
126974: 07/12/07: Re: converting verilog to vhdl
127052: 07/12/10: Re: What's the difference for VHDL code between simulation and
127360: 07/12/19: Re: sampling error between 2 clocks
127592: 08/01/03: Re: round,fix and floor algortihms
127596: 08/01/03: Re: round,fix and floor algortihms
127604: 08/01/03: Re: round,fix and floor algortihms
127607: 08/01/03: Re: TechXclusives from Xilinx
127654: 08/01/04: Re: simulation problems
127761: 08/01/07: Re: question on AND
127821: 08/01/08: Re: Real examples of metastability causing bugs
127823: 08/01/08: Re: Real examples of metastability causing bugs
128055: 08/01/14: Re: Is it possible to define an Integer so it could be incremented
128344: 08/01/22: Re: Is it possible to define an Integer so it could be incremented
128374: 08/01/23: Re: Is it possible to define an Integer so it could be incremented
130318: 08/03/20: Re: Optimizing an inferred counter
130718: 08/03/31: Re: Writing to DDR RAM on Virtex II Pro Board on PLB Bus
130952: 08/04/06: Re: Use of floating point numbers in xilinx EDK .........
131133: 08/04/11: Re: case statements- verilog to vhdl
131247: 08/04/16: Re: Snythesis error
131262: 08/04/17: Re: how do I test signals in a testbench that are 1 or 2 levels down
131275: 08/04/17: Re: Survey: FPGA PCB layout
131603: 08/04/25: Re: ANNOUNCE: Maia 0.8.2: module-level HDL verification tool
131613: 08/04/25: Re: PLB Master Example
131659: 08/04/28: Re: Very simple VHDL problem
131740: 08/04/30: Re: how to optimize this comparator for better synthesis result?
132869: 08/06/09: Re: Compare and update in same clock cycle synthesis problem
133153: 08/06/19: Re: VHDL refactoring tools
133288: 08/06/23: Re: FPGA based database searching
133325: 08/06/24: Re: Cycle-based or Event-based simulation?
133457: 08/06/30: Re: Standard forms for Karnaugh maps?
133460: 08/06/30: Re: arithmetic problem
133496: 08/07/01: Re: VHDL libraries
134163: 08/07/28: Re: Creating new operators
134211: 08/07/30: Re: Creating new operators
134492: 08/08/13: Re: eliminating individual array registers?
134821: 08/09/02: Re: why does inferred RAM cause synthesis times to explode?
134885: 08/09/04: Re: XST bug on illigal states of a FSM ?
134962: 08/09/08: Re: XST bug on illigal states of a FSM ?
134968: 08/09/08: Re: XST bug on illigal states of a FSM ?
135051: 08/09/12: Re: Ultra low power FPGAs
135254: 08/09/23: Re: Use of divided clocks inside modules
135273: 08/09/23: Re: Xilinx Mode Select Pins
135276: 08/09/23: Re: Use of divided clocks inside modules
135277: 08/09/23: Re: Use of divided clocks inside modules
135285: 08/09/24: Re: Xilinx Mode Select Pins
135326: 08/09/26: Re: Use of divided clocks inside modules
135403: 08/09/30: Re: reasonable timing analysis without mapping design to IO
135569: 08/10/08: Re: MUX Inference
135571: 08/10/08: Re: Do two clock system blocks with one clock running half of other's
136464: 08/11/18: Re: Aligned PLL clocks in RTL simulation
136512: 08/11/19: Re: opinion about various code generators
137237: 09/01/05: Re: Classifying different kinds of FPGA optimizations
137288: 09/01/07: Re: beginner synthesize question - my debounce process won't
137315: 09/01/08: Re: beginner synthesize question - my debounce process won't
137649: 09/01/26: Re: How to make a ram shared?
138045: 09/02/04: Re: REWARD $$$ Xilinx USB Platform Cable problems
138841: 09/03/12: Re: Integer arithmetic in HDLs
139527: 09/04/02: Re: SSO
139718: 09/04/10: Re: Noise in Stratix3?
139740: 09/04/11: Re: Getting efficient logic synthesis
140008: 09/04/23: Re: problem with high speed data transfer
140491: 09/05/14: Re: sync vs async reset
140665: 09/05/21: Re: Are all these claims in VHDL correct?
140666: 09/05/21: Re: Port assignment question
140670: 09/05/21: Re: Muli-Cycle Path Constrains in RTL
140744: 09/05/24: Re: Are all these claims in VHDL correct?
140753: 09/05/25: Re: Muli-Cycle Path Constrains in RTL
140754: 09/05/25: Re: Adders with multiple inputs?
140769: 09/05/25: Re: When is it to generate transparent latch or usual combinational
140793: 09/05/26: Re: When is it to generate transparent latch or usual combinational
140818: 09/05/26: Re: When is it to generate transparent latch or usual combinational
140841: 09/05/27: Re: When is it to generate transparent latch or usual combinational
140842: 09/05/27: Re: Signal encoding for a user-defined type
140843: 09/05/27: Re: Signal encoding for a user-defined type
140912: 09/05/29: Re: When is it to generate transparent latch or usual combinational
141219: 09/06/11: Re: Safe margin in FPGA static timing analysis
141256: 09/06/12: Re: Verilog "for loop" - exit by setting i to exit value?
141297: 09/06/16: Re: what is non-aligned -- memory accesses ?
141316: 09/06/17: Re: Do you know how aggressive the patent fighting between Xilinx and
141441: 09/06/24: Re: True dual-port RAM in VHDL: XST question
141454: 09/06/24: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
141456: 09/06/24: Re: index in arrays doesn't work
141515: 09/06/26: Re: True dual-port RAM in VHDL: XST question
141929: 09/07/17: Re: Generating a negated clock
141972: 09/07/20: Re: How do you handle build variants in VHDL?
142000: 09/07/21: Re: How do you handle build variants in VHDL?
142001: 09/07/21: Re: Strange FPGA behavior
142096: 09/07/24: Re: How do you handle build variants in VHDL?
142153: 09/07/27: Re: How do you handle build variants in VHDL?
142187: 09/07/28: Re: Different behavior of FSM in same simulation
142270: 09/07/31: Re: Using OPEN in port map
142280: 09/08/01: Re: Using OPEN in port map
142468: 09/08/12: Re: Spartan-6 Boards - Your Wish List
142523: 09/08/14: Re: Is it possible to generate double data rate stream in the Virtex4
142547: 09/08/16: Re: Using carry chain of counters for term count detect
142567: 09/08/17: Re: Using carry chain of counters for term count detect
142568: 09/08/17: Re: Operating same logic at two frequencies
142618: 09/08/21: Re: Using carry chain of counters for term count detect
142678: 09/08/25: Re: Timing properties of FPGA devices at sub-clock frequencies
142809: 09/09/02: Re: Choice of Language for FPGA programming
142845: 09/09/03: Re: Choice of Language for FPGA programming
142850: 09/09/03: Re: Choice of Language for FPGA programming
142882: 09/09/05: Re: Choice of Language for FPGA programming
142890: 09/09/05: Re: Choice of Language for FPGA programming
143050: 09/09/17: Re: 82S153 Fuse Map / Disassembler
143053: 09/09/17: Re: Quartus top level entity name vs names of generated files
143129: 09/09/22: Re: VHDL question
143140: 09/09/23: Re: VHDL question
143165: 09/09/23: Re: VHDL question
143185: 09/09/24: Re: Shift left arithmetic?
143317: 09/10/01: Re: Up-counter with async load/clear and overflow detection (Verilog)
143861: 09/10/30: Re: Best way to model a large external ROM in a simulation? (XST
143865: 09/10/30: Re: Simple state machine output question
143868: 09/10/30: Re: Simple state machine output question
144357: 09/11/30: Re: How to evaluate design performance for FPGA
144372: 09/12/02: Re: This works, this does not... why?
144434: 09/12/07: Re: very wide counter (42-bit)
144494: 09/12/10: Re: Please Help me
144583: 09/12/16: Re: Please Help me
144879: 10/01/11: Re: Old School Hurts
145035: 10/01/21: Re: bit vs std_logic (was Re: Simulation of VHDL code for a vending
145078: 10/01/25: Re: State Machine Initialization in Synplify Pro
145160: 10/01/29: Re: synthesizing a completely empty design for an FPGA to measure
145646: 10/02/17: Re: How a state machine is constructed using latches?
145650: 10/02/17: Re: How a state machine is constructed using latches?
145755: 10/02/22: Re: System design in FPGA
145756: 10/02/22: Re: System design in FPGA
145839: 10/02/25: Re: How a state machine is constructed using latches?
146265: 10/03/10: Re: Why doesn't this situation generate a latch?
146266: 10/03/10: Re: Why doesn't this situation generate a latch?
146291: 10/03/10: Re: Why doesn't this situation generate a latch?
146310: 10/03/11: Re: Why doesn't this situation generate a latch?
146311: 10/03/11: Re: Why doesn't this situation generate a latch?
146315: 10/03/11: Re: Why doesn't this situation generate a latch?
146393: 10/03/15: Re: Awkward Arithmetic
146402: 10/03/16: Re: Awkward Arithmetic
146447: 10/03/18: Re: Why doesn't this situation generate a latch?
146650: 10/03/25: Re: EMC discussion
146660: 10/03/25: Re: EMC discussion
146672: 10/03/25: Re: EMC discussion
147008: 10/04/09: Re: I'd rather switch than fight!
147115: 10/04/14: Re: I'd rather switch than fight!
147142: 10/04/15: Re: I'd rather switch than fight!
147223: 10/04/19: Re: I'd rather switch than fight!
147233: 10/04/19: Re: I'd rather switch than fight!
147322: 10/04/22: Re: I'd rather switch than fight!
147343: 10/04/23: Re: I'd rather switch than fight!
147351: 10/04/23: Re: I'd rather switch than fight!
147421: 10/04/26: Re: I'd rather switch than fight!
147478: 10/04/28: Re: I'd rather switch than fight!
147535: 10/04/30: Re: I'd rather switch than fight!
147538: 10/04/30: Re: I'd rather switch than fight!
147633: 10/05/10: Re: I'd rather switch than fight!
147716: 10/05/18: Re: Xilinx Synthesis Tool generates clock signals from combinatorial
147725: 10/05/19: Re: Xilinx Synthesis Tool generates clock signals from combinatorial
148412: 10/07/19: Re: Dumb VHDL Question -- Type Conversion
148544: 10/07/31: Re: Connecting "signed" to "std_logic_vector" ports.
148579: 10/08/03: Re: Connecting "signed" to "std_logic_vector" ports.
148585: 10/08/03: Re: Xilinx ISE Webpack and Pipeline Optimization
148639: 10/08/10: Re: VHDL newbie- stuck just weeks before project submission
148884: 10/09/07: Re: Want to get into FPGA
148898: 10/09/09: Re: Want to get into FPGA
149023: 10/09/21: Re: Xilinx XST and a State Machine - A Mystery
149026: 10/09/21: Re: Xilinx XST and a State Machine - A Mystery
149059: 10/09/27: Re: Xilinx XST and a State Machine - A Mystery
149071: 10/09/28: Re: Xilinx XST and a State Machine - A Mystery
149216: 10/10/08: Re: help with bad synchronous description error
149293: 10/10/14: Re: FSM Problem with inout signal
149439: 10/10/25: Re: 0x80000000 Integer not supported??
149444: 10/10/25: Re: 0x80000000 Integer not supported??
149453: 10/10/26: Re: Ncvhdl Problem with simple logical operators
149466: 10/10/27: Re: Ncvhdl Problem with simple logical operators
149605: 10/11/10: Re: XST - configuration - VHDL
149614: 10/11/11: Re: XST - configuration - VHDL
149881: 10/11/30: Re: Brain Cramps...
149938: 10/12/02: Re: FSM single process...BIG question
149939: 10/12/02: Re: FSM single process...BIG question
149940: 10/12/02: Re: FSM single process...BIG question
149962: 10/12/03: Re: FSM single process...BIG question
150014: 10/12/06: Re: Concurrent Logic Timing
150024: 10/12/06: Re: FSM single process...BIG question
150025: 10/12/06: Re: FSM single process...BIG question
150028: 10/12/06: Re: Concurrent Logic Timing
150041: 10/12/07: Re: FSM single process...BIG question
150240: 11/01/04: Re: Transfer data from one clock domain to another clock created by
150414: 11/01/18: Re: Verilog Book for VHDL Users
150861: 11/02/16: Re: why an FSM is not a counter?!
150863: 11/02/16: Re: PLD suggestions for classroom use
151008: 11/02/28: Re: Simulating mutiplication of 'X' with '0'
151027: 11/03/01: Re: Count bits in VHDL, with loop and unrolled loop produces
151036: 11/03/01: Re: Count bits in VHDL, with loop and unrolled loop produces
151051: 11/03/02: Re: Count bits in VHDL, with loop and unrolled loop produces
151061: 11/03/02: Re: Count bits in VHDL, with loop and unrolled loop produces
151368: 11/03/28: Re: fpga express 3.6
151482: 11/04/12: Re: Source of Dynamic Power Consumption in FPGAs
152581: 11/09/15: Re: Xilinx Tin Whiskers ?
153114: 11/12/05: Re: Is it possible to save the FPGA state periodically?
153116: 11/12/06: Re: Is it possible to save the FPGA state periodically?
153142: 11/12/12: Re: D-Type Flip flop with negated Q in Webise for a schematic capture
153162: 11/12/21: Re: Clock distribution for ADC and jitter
153176: 12/01/03: Re: Clock distribution for ADC and jitter
153185: 12/01/04: Re: Beginner question on FIFO in "FPGA prototyping by VHDL examples"
153187: 12/01/05: Re: Beginner question on FIFO in "FPGA prototyping by VHDL examples"
153218: 12/01/09: Re: Beginner question on FIFO in
153309: 12/01/30: Re: Design Notation VHDL or Verilog?
153311: 12/01/30: =?ISO-8859-1?Q?Re=3A_Post=2Dsynth=E8se_simulation?=
153319: 12/01/31: Re: Design Notation VHDL or Verilog?
153325: 12/02/01: Re: Design Notation VHDL or Verilog?
153334: 12/02/02: Re: Design Notation VHDL or Verilog?
153335: 12/02/02: Re: Difference between Xilinx isim and modelsim
153360: 12/02/07: Re: Difference between Xilinx isim and modelsim
153361: 12/02/07: Re: 'x' state on one bit of the input bus of an adder cause the
153362: 12/02/07: Re: Design Notation VHDL or Verilog?
153363: 12/02/07: Re: Design Notation VHDL or Verilog?
153367: 12/02/09: Re: Design Notation VHDL or Verilog?
153372: 12/02/10: Re: Design Notation VHDL or Verilog?
153643: 12/04/09: Re: Best FPGA for algorithmic acceleration
153735: 12/05/03: Re: Smallest GPL UART
153756: 12/05/15: Re: Best way to get an array of vectors into a vector?
153764: 12/05/16: Re: Synthesis Problem
153772: 12/05/16: Re: FDE vs latch?
153781: 12/05/17: Re: Xilinx ISE Multiple Drivers Error
153808: 12/05/24: Re: Logic Glitches in Spartan-3?
154820: 13/01/15: Re: Chisel as alternative HDL
154821: 13/01/15: Re: is this multicycle?
154828: 13/01/16: Re: Chisel as alternative HDL
154830: 13/01/16: Re: Chisel as alternative HDL
154842: 13/01/17: Re: Combination loops and false paths
Andy "Krazy" Glew:
146880: 10/03/30: Re: Which is the most beautiful and memorable hardware structure
146881: 10/03/30: Re: Which is the most beautiful and memorable hardware structure
146904: 10/04/01: Re: Which is the most beautiful and memorable hardware structure
146905: 10/04/01: Re: Which is the most beautiful and memorable hardware structure
146918: 10/04/01: Re: Which is the most beautiful and memorable hardware structure
146944: 10/04/03: Re: Which is the most beautiful and memorable hardware structure
146945: 10/04/03: Re: Which is the most beautiful and memorable hardware structure
149809: 10/11/24: Re: Atom 6000C perspective, anyone?
149833: 10/11/25: Re: Atom 6000C perspective, anyone?
150288: 11/01/07: Re: OT: Fast Circuits
Andy (Super) Glew:
156137: 13/12/08: Re: Implementing multiple interrupts
Andy Bartlett:
153461: 12/03/02: Re: configuring an Altera Cyclone 3
153632: 12/04/07: Re: Watchdog reset for fpga designs
153713: 12/04/29: Re: Smallest GPL UART
154127: 12/08/15: Re: "Decimals" word in binary space
154447: 12/11/04: Re: help
154449: 12/11/04: Re: help
154671: 12/12/15: Re: DC fifo behaviour at underflow/overflow
154673: 12/12/15: Re: DC fifo behaviour at underflow/overflow
154938: 13/02/24: Re: add-compare-select
155175: 13/05/22: Re: Die size of BRAM/DSP48 in CLBs
156558: 14/04/29: Re: Ethernet interfacing
156755: 14/06/18: Re: PLA? PAL? PLD? GAL?
156870: 14/07/14: Re: Help with Address load logic
157008: 14/08/25: Re: Bidirectional Pin FPGA (Parallel ADC)
Andy Bennet:
159044: 16/07/06: Re: need some help with altera quartus
159138: 16/08/19: Re: Multi-port memory
160260: 17/09/21: Re: duty cycle of clock divider
160262: 17/09/21: Re: duty cycle of clock divider
160267: 17/09/22: Re: duty cycle of clock divider
160327: 17/11/20: Re: additional fpga forums
160683: 18/09/28: Re: Schematic FPGA Design on twitch
160872: 18/12/13: Re: What is the name of the circuit structure that generates a state
161206: 19/03/14: Re: Implementation of Modbus Slave using only FPGA, without any
161309: 19/03/26: Re: TCS34725 Basys3 VHDL
161492: 19/11/08: Re: FPGA config sizes
161525: 19/11/26: Re: New coding method for a state machine in groups in HDL
161564: 19/11/30: Re: New coding method for a state machine in groups in HDL
Andy Bennett:
157608: 15/01/03: Re: Open source Verilog BCH encoder/decoder
158060: 15/07/30: Re: fifo or sdram bug?
Andy Botterill:
14094: 99/01/13: Re: programming language interface
33479: 01/07/27: Re: Xilinx/Altera "behavioral" verilog
33488: 01/07/28: Re: Xilinx/Altera "behavioral" verilog
33528: 01/07/29: Re: Xilinx/Altera "behavioral" verilog
33566: 01/07/30: Re: Xilinx/Altera "behavioral" verilog
52488: 03/02/11: Re: Synthesis Scripts
52492: 03/02/11: Re: Synthesis Scripts
122020: 07/07/17: Re: Xilinx XC9536 current draw ?
122069: 07/07/18: Re: Xilinx S3 Starterkit, how hot it is supposed to be?
122478: 07/07/28: dual port ram
122481: 07/07/28: Re: dual port ram
122486: 07/07/28: Re: dual port ram
122496: 07/07/29: Re: dual port ram
122502: 07/07/29: Re: dual port ram
122778: 07/08/06: Re: FPGA board connected to CMOS chip: ESD hazards?
125612: 07/10/30: Re: FFT for an arbitrary number of points (not power of 2)
127725: 08/01/06: Re: Cyclone II short-circuit failure mode
128560: 08/01/30: PC requirements for ISE webpack
128574: 08/01/31: Re: PC requirements for ISE webpack
128575: 08/01/31: Re: PC requirements for ISE webpack
128999: 08/02/12: Re: Virtex4FX over-voltage
130443: 08/03/24: Re: Spartan 3E intefacing for dummies
130554: 08/03/27: Re: Places to visit in Amsterdam and Brussells
130591: 08/03/27: Re: A Challenge for serialized processor design and implementation
131295: 08/04/18: Re: Survey: FPGA PCB layout
132813: 08/06/07: Re: Xilinx cuts 250 jobs.
132874: 08/06/09: how to track down an optimised away signal
132878: 08/06/09: Re: how to track down an optimised away signal
132926: 08/06/10: Re: how to track down an optimised away signal
135191: 08/09/19: Re: WebPack on CentOS 5 ?
135635: 08/10/10: Re: Can i ask some DFT questions
135647: 08/10/11: Re: Can i ask some DFT questions
135660: 08/10/11: Re: Can i ask some DFT questions
136384: 08/11/13: How to stop using a signed subtractor
136390: 08/11/14: Re: How to stop using a signed subtractor
136408: 08/11/14: Re: How to stop using a signed subtractor
140018: 09/04/23: how to create multiple gatelevel files from multiple rtl files during
140475: 09/05/14: Re: EMACS VHDL mode: how to rescan project so that makefile generates
140478: 09/05/14: Re: EMACS VHDL mode: how to rescan project so that makefile generates
141384: 09/06/22: Re: Subtleties of Booth's Algorithm Implementation
141399: 09/06/23: Re: Subtleties of Booth's Algorithm Implementation
141732: 09/07/05: Re: Subtleties of Booth's Algorithm Implementation
141735: 09/07/05: Re: Subtleties of Booth's Algorithm Implementation
141792: 09/07/09: how to get back multi hier netlist in xst
143341: 09/10/03: webpack 10.1.02 works for what versions of fedora?
143724: 09/10/22: Re: CPLD/FPGA with Linux
144250: 09/11/23: Re: EDK11 under 64-bit OS
144303: 09/11/25: webpack crashed how do I get these things back?
144318: 09/11/26: Re: webpack crashed how do I get these things back?
144376: 09/12/02: Re: webpack crashed how do I get these things back?
144653: 09/12/21: Re: Please help, Xilinx FIFO problem!
144895: 10/01/12: Re: Xilinx ISE 10.1.03
146245: 10/03/09: Re: using an FPGA to emulate a vintage computer
146357: 10/03/14: Re: usb device driver for ISP1362(in windows xp)
146454: 10/03/18: Re: usb device driver for ISP1362(in windows xp)
150214: 11/01/02: Re: I Give Up!
150217: 11/01/02: Re: I Give Up!
Andy Bryant:
16826: 99/06/11: PCI + I2O in a FPGA.... has anyone done it?
Andy Cooper:
57: 94/08/05: Re: Mouseproblems using Makebits (Xilinx 4.3)
886: 95/03/21: Re: Beyond Futurenet including PLD ?
Andy D. Pimentel:
Andy Dow:
41393: 02/03/27: XPower & Power Estimator Spreadsheet
41886: 02/04/10: Re: Excel Sheet for Virtex-II power estimation
Andy Evans:
14527: 99/02/03: Re: Hold Time Violation
Andy Fatkullin:
15665: 99/04/07: Help: FPGA for voltage working range 3...6 V
Andy Freeman:
32854: 01/07/10: Re: Handel-C
32886: 01/07/10: Re: Handel-C
32887: 01/07/10: Re: Handel-C
32907: 01/07/11: Re: Handel-C
73090: 04/09/13: Re: why systemc?
121232: 07/06/28: Re: Bit error counter - how to make it faster
Andy Glew:
105479: 06/07/24: Re: Hardware book like "Code Complete"?
Andy Glew, Public:
46580: 02/09/03: Re: Hardware Code Morphing?
Andy Green:
35068: 01/09/20: Re: Clockin on rising AND falling edge
Andy Greensted:
61014: 03/09/26: Xilinx: LOC'd IO internal to VHDL Module
Andy Gulliver:
2197: 95/10/30: Xilinx and Windows 95
2215: 95/11/02: Re: Xilinx XSI FPGA User Guide
2250: 95/11/09: Re: Can X30xx Reset itself?
2802: 96/02/09: Re: Looking for OPAL, PALASM, PLAN
2822: 96/02/12: Re: Xilinx is NOT specified MINIMUM delay -- is it right??
2933: 96/03/01: Re: JEDEC Specification?
3097: 96/04/01: Re: XACT5.2 bit file length count changes
3109: 96/04/03: Re: Does X-BLOX Work?
3160: 96/04/16: Re: What's the lowest-priced FPGA?
3299: 96/05/10: Re: Looking for free FPGA softw./Xilinx
3363: 96/05/21: Re: Xilinx and Viewlogic
3380: 96/05/23: Re: Xilinx and Viewlogic
3396: 96/05/24: Re: Xilinx and Viewlogic
3516: 96/06/13: Re: Double Port Ram - Xact Libs
3712: 96/07/19: Re: FPGA vs CPLD
3724: 96/07/22: Re: CPLD Failure
3786: 96/08/01: Re: assigning LOC in XACT
4044: 96/09/05: Re: speed up Xilinx P & R
4197: 96/09/25: Re: Xilinx X-blox Bidir_IO padnames?
4630: 96/11/22: Re: FPGA Gate Counts: No Truth in Advertising
6135: 97/04/15: Re: XC5204PQ160 Configuration
9853: 98/04/09: Re: Smoking Crater in a Xilinx 3k FPGA
Andy Hall:
37935: 01/12/25: Innoveda Speedwave vs. Modelsim?
37971: 01/12/27: Re: Innoveda Speedwave vs. Modelsim?
Andy Holt:
22442: 00/05/09: HELP - what to choose?
22443: 00/05/09: Re: HELP - what to choose?
22628: 00/05/15: Re: Future of FPGAs?
22631: 00/05/15: Re: Future of FPGAs?
22632: 00/05/15: Re: HELP - what to choose?
24017: 00/07/22: Re: 17 clocks in a Virtex
24754: 00/08/17: Re: state encoding in Synplify!!!
26197: 00/10/08: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
34769: 01/09/07: Re: Special counter for scheduling
37260: 01/12/05: Re: For Sale: Huge Xilinx FPGA lots
Andy Jones, x73313:
369: 94/10/31: Re: SRAM and antifuse for interconnects
Andy Kaos:
92096: 05/11/22: Re: How do I find the datasheet of this device "TIOPA 690 3BZL9"?
Andy Krumel:
20633: 00/02/16: Spartan-II Pricing - What gives?
21374: 00/03/20: Synthesis error
22422: 00/05/08: Xilinx Block Select Ram+ and LeonardoSpectrum
22737: 00/05/21: Dynamically configuring Vertex/Spartan II
23335: 00/06/22: Re: Distributed RAM and VHDL
24447: 00/08/08: Re: Xilinx Alliance Base
25042: 00/08/24: Re: Chipscope problem
27942: 00/12/15: Help configuring Spartan II using processor
27986: 00/12/18: Re: Help configuring Spartan II using processor
27987: 00/12/18: Re: Help configuring Spartan II using processor
Andy Luotto:
78255: 05/01/27: Synopsys Designware and FPGA mapping
97138: 06/02/17: sdram modeling
Andy Main:
39993: 02/02/23: Re: Need largest CPLD devices?
40076: 02/02/26: Re: Need largest CPLD devices?
40104: 02/02/27: Re: FPGA choices and questions
40481: 02/03/07: Re: How can I install Xilinx ISE 4.1i under Linux?
40568: 02/03/11: Re: Audio project with an FPGA?
40676: 02/03/12: Re: cyphers
80582: 05/03/08: Basic cheap fpga configuration
80597: 05/03/08: Re: Basic cheap fpga configuration
80628: 05/03/09: Re: Basic cheap fpga configuration
80907: 05/03/14: XCF01's in the UK
80913: 05/03/14: Re: XCF01's in the UK
80914: 05/03/14: Re: XCF01's in the UK
80933: 05/03/14: Re: XCF01's in the UK
Andy McClelland:
11310: 98/08/04: Re: Delay Element for async design.
159052: 16/07/11: Re: need some help with altera quartus
Andy McDaniel:
43395: 02/05/20: Any suggestions?
Andy Mitchell:
41565: 02/04/02: ISE Foundation - Making Macros
48973: 02/10/28: ERROR:Map:40 !!!
49950: 02/11/26: Custom FPGA synthesis
Andy NEGOI:
7855: 97/10/23: Re: [Reposted due to Enlow UCE cancel]: PROM for FLEX10K
Andy Papageorgiou:
12497: 98/10/14: Re: 2D- FFT of image in ALTERA FLEX 10k ?
Andy Peters:
10347: 98/05/13: Re: Help: 25Mhz XC4025E-2 FPGA having hold time errors during simulation
10380: 98/05/15: Re: Xilinx Foundation and Linux
10382: 98/05/15: "Inferred" I/O flip-flops in XC4000E
10394: 98/05/15: Re: Xilinx Foundation and Linux
10395: 98/05/15: Re: Motion Controller design for DC motor wanted
10396: 98/05/15: Re: "Inferred" I/O flip-flops in XC4000E
10429: 98/05/18: Re: XC5200s and Foundation 1.4
10599: 98/06/05: Non-periodic clock
10612: 98/06/05: Re: Non-periodic clock
10639: 98/06/08: Re: Non-periodic clock
10667: 98/06/09: Re: XC4000: post routing "customization"
11179: 98/07/22: Re: Schematic Symbol Generation
11231: 98/07/28: Re: [Q] motor control onto an FPGA
11243: 98/07/29: Re: How to connect my reset with GSR at Xilinx-FPGAs - response and Additional questions!
11253: 98/07/30: Re: How to connect my reset with GSR at Xilinx-FPGAs - response and Additional questions!
11254: 98/07/30: Re: How to connect my reset with GSR at Xilinx-FPGAs - response and Additional questions!
11320: 98/08/04: Re: [Q] motor control onto an FPGA
11306: 98/08/03: Re: How to connect my reset with GSR at Xilinx-FPGAs - response and Additional questions!
11401: 98/08/10: Re: PCI Core Thanks
11695: 98/09/01: Constraining Xilinx tools to NOT use certain pins?
11696: 98/09/01: Re: Constraining Xilinx tools to NOT use certain pins?
12022: 98/09/24: Re: easier testing for PCI cards??
12024: 98/09/24: Re: Xilinx ncd files
12030: 98/09/24: Re: Xilinx Spartan vs. 4K series
12113: 98/09/29: Re: Using Xilinx TBUF?
12162: 98/10/02: Re: Anyone received Xilinx Foundation 1.5 ?
12311: 98/10/08: Re: FIR Filter Design
12221: 98/10/05: Re: Synthesis: Exemplar or Synopsys
12239: 98/10/06: Re: USAGE of XILINX "FROM:TO" for VHDL and IMPLEMENTATION
12281: 98/10/07: Re: USAGE of XILINX "FROM:TO" for VHDL and IMPLEMENTATION
12282: 98/10/07: Re: Degradation of results from Xilinx F1.3 -> F1.4 -> F1.5
12289: 98/10/07: Re: Degradation of results from Xilinx F1.3 -> F1.4 -> F1.5
12310: 98/10/08: Re: Degradation of results from Xilinx F1.3 -> F1.4 -> F1.5
12316: 98/10/08: Xilinx F1.5/FPGA Express wackiness
12341: 98/10/09: Re: Xilinx F1.5/FPGA Express wackiness
12343: 98/10/09: Re: Synthesis: Exemplar or Synopsys
12448: 98/10/12: Re: Xilinx F1.5/FPGA Express wackiness
12447: 98/10/12: Re: Xilinx Foundation forgets the pin assignment. Bug?
12449: 98/10/12: Re: Xilinx may not support schematics for Virtex?????
12514: 98/10/14: Re: Schematic entry?
12520: 98/10/14: Re: Schematic entry?
12545: 98/10/15: Re: Xilinx Foundation forgets the pin assignment. Bug?
12570: 98/10/16: Re: Digital Sine Generator
12599: 98/10/19: Re: What's wrong at this Address decoder?
12818: 98/10/30: Re: $B$40FFb(J
13176: 98/11/18: Re: Atmel AT17C010?
13585: 98/12/10: Re: A short digression...
13536: 98/12/08: Re: Xilinx Dongles under NT
14103: 99/01/13: Re: Problems with processes
14219: 99/01/20: Re: Problems with processes
14220: 99/01/20: Re: Hard porting to FPGA Express
14247: 99/01/21: Re: Hard porting to FPGA Express
14248: 99/01/21: Re: FPGA express warning
14321: 99/01/25: Re: Worst service in India by Xilinx
14320: 99/01/25: Re: FPGA express warning
14371: 99/01/27: Re: Ratings for Synplicity Synplify
14404: 99/01/28: Re: Hysteresis on PLD Clock Inputs
14651: 99/02/08: Re: Off topic DRAM/SIMM question....
14817: 99/02/18: Re: "Altera FreeCore Library" back on the web
14843: 99/02/19: Inferring IOFFs with FPGA Express 3.x and Foundation 1.5i
14846: 99/02/19: Re: Inferring IOFFs with FPGA Express 3.x and Foundation 1.5i
14879: 99/02/22: Re: Inferring IOFFs with FPGA Express 3.x and Foundation 1.5i
14882: 99/02/22: Re: Inferring IOFFs with FPGA Express 3.x and Foundation 1.5i
14896: 99/02/23: Re: Problem with xilinx M1
14960: 99/02/27: Re: Problem with xilinx M1
14961: 99/02/27: Re: Where do I connect my reset pins to?
14962: 99/02/27: Re: Foundation V1.5 Crash
14983: 99/03/01: Re: Problem with xilinx M1
15265: 99/03/16: Re: Inferring IO's
15406: 99/03/22: Re: HDL-307 error
15407: 99/03/22: FPGA Express, STARTUPs and user clocks
15419: 99/03/23: Re: FPGA Express, STARTUPs and user clocks
15640: 99/04/05: Re: Problems with Foundation1.5
15759: 99/04/12: Re: fpga express stripping out Viewlogic busses
16046: 99/04/29: Re: z80 core
16047: 99/04/29: Re: Help with XACT 5.2 - 6
16114: 99/05/04: Re: Anyone use 27256 for config?
16133: 99/05/05: Re: Anyone use 27256 for config?
16311: 99/05/14: Re: Fancy Dram problem
16343: 99/05/17: Re: Fancy Dram problem
16344: 99/05/17: Re: Synchronizer design?
16365: 99/05/18: Re: Need crack
16392: 99/05/19: Re: Xilinx M1.5 Crash
16408: 99/05/20: Re: Xilinx M1.5 Crash
16431: 99/05/21: Re: How synthesize tools concern with size of the design?
16906: 99/06/16: Re: aobut analog
16905: 99/06/16: Re: vhdl and viewlogic problem
16946: 99/06/18: Re: Read/Writes to memories/register files for PIC core
17028: 99/06/25: fast counter in 4013XL?
17055: 99/06/28: Re: fast counter in 4013XL?
17057: 99/06/28: Re: Read/Writes to memories/register files for PIC core
17056: 99/06/28: Re: fast counter in 4013XL?
17068: 99/06/28: Re: pessimistic synth results (was: fast counter in 4013XL?)
17106: 99/06/30: Re: fast counter in 4013XL?
17246: 99/07/14: Re: MULTIPLE PIN ASSIGNMENTS QUESTION (ALTERA MAX+PLUS II)
17302: 99/07/19: Re: License sharing for synopsys/cadence/modeltech
17362: 99/07/22: Re: Solaris vs. NT
17467: 99/07/29: Re: Epld to Fpga design.
17486: 99/07/30: Re: nuneric_std package in Foundation 1.5
17510: 99/08/03: Re: nuneric_std package in Foundation 1.5
17548: 99/08/09: Re: help!
17648: 99/08/18: Re: VHDL'93 on Xilinx Foundation
17653: 99/08/18: Re: looking for info on programing XILINX 4000 series
17742: 99/08/28: Re: FPGA Express: Not enough storage...(etc.)
17820: 99/09/07: Re: synthesis comparion between Synplify and FPGA express
17826: 99/09/08: Re: synthesis comparion between Synplify and FPGA express
17849: 99/09/13: Re: Relative Location attribute
17885: 99/09/15: Re: xilinx v2.1i
17890: 99/09/15: Re: xilinx v2.1i
17911: 99/09/16: Re: xilinx v2.1i
17912: 99/09/16: Re: simple VHDL?
18034: 99/09/24: Re: Synopsys inside Foundation 2.1i does not infer fast-adder
18177: 99/10/05: Re: Multiplierless FIR filters in FPGAs
18209: 99/10/07: Re: External Cloking of Altera MAX 7000S
18271: 99/10/11: Re: External Cloking of Altera MAX 7000S
18528: 99/10/28: Re: Xilinx Orientation Question
18529: 99/10/28: Re: FPGA Timing Problem
18530: 99/10/28: Re: generating power on initialisation
18544: 99/10/29: Xilinx TPSYNC constraint
18572: 99/11/01: Re: Xilinx TPSYNC constraint
18574: 99/11/01: Re: Xilinx TPSYNC constraint
18575: 99/11/01: Re: Xilinx TPSYNC constraint
18635: 99/11/04: Re: Simulation of FPGA design. Please Help!
18636: 99/11/04: Re: which is the maximum freqency?
18647: 99/11/04: Xilinx M2.1i SP2?
18664: 99/11/05: Re: Xilinx M2.1i SP2?
18666: 99/11/05: Re: Xilinx M2.1i SP2?
18795: 99/11/16: Re: How to use GSR-net in Virtex?
18817: 99/11/17: Re: COM1-FPGA communication
18839: 99/11/18: Re: Actel FPGA prices
18841: 99/11/18: Re: How to use GSR-net in Virtex?
18848: 99/11/18: Re: Need advice on interfacing SDRAM modules
18873: 99/11/19: Re: How to use GSR-net in Virtex?
18876: 99/11/19: Re: Need advice on interfacing SDRAM modules
18875: 99/11/19: Re: How to use GSR-net in Virtex?
18938: 99/11/22: Re: Trouble with ATMEL's AT40K20
18984: 99/11/23: Re: Trouble with ATMEL's AT40K20
19021: 99/11/24: Re: Trouble with ATMEL's AT40K20
19152: 99/12/02: Re: Tristate bidirectional pads with Xilinx
19153: 99/12/02: Re: Command line for FPGA Express
19179: 99/12/03: Re: Tristate bidirectional pads with Xilinx
19273: 99/12/09: Re: Synopsys backannotation
19282: 99/12/09: Re: Synopsys backannotation
19383: 99/12/17: Re: JEDEC
19495: 99/12/27: Re: FIFO design
19510: 99/12/28: Re: xilinx help *desperately* needed
19531: 99/12/29: Re: USB2 core call for Volunteers
19541: 99/12/29: Re: USB2 core call for Volunteers
19685: 00/01/07: Re: Disable clockbuffer for only a single flip-flop
19733: 00/01/10: Re: 100 MHz counters
19734: 00/01/10: Re: XC4000 Configuration Bitstream structure
19770: 00/01/11: Re: 100 MHz counters
19832: 00/01/13: Re: Lattice
20251: 00/02/02: Re: XC9536 and Abel
20305: 00/02/04: Re: Visualizing EDIF netlist for Xilinx
20306: 00/02/04: Re: Xilinx Tools
20402: 00/02/08: Re: XC3000 series w/Foundation Student Edition?
20423: 00/02/09: Spartan and timing analyzer: clock nets using non-dedicated resources
20445: 00/02/10: Re: VHDL and Xilinx Books for beginners
20446: 00/02/10: Re: Spartan and timing analyzer: clock nets using non-dedicated resources
20447: 00/02/10: Re: Xilinx error message
20489: 00/02/11: Re: Spartan and timing analyzer: clock nets using non-dedicated resources
20488: 00/02/11: Re: Spartan and timing analyzer: clock nets using non-dedicated resources
20490: 00/02/11: Re: xilinx
20500: 00/02/11: Re: Spartan and timing analyzer: clock nets using non-dedicated resources
20501: 00/02/11: Re: xilinx
20502: 00/02/11: Re: A FPGA hickup
20507: 00/02/12: Re: Problem in Wildforce synthesis.
20550: 00/02/14: Re: Problem in Wildforce synthesis.
20555: 00/02/14: FPGA Express/XC4KXLA annoyance
20557: 00/02/14: Re: Post-synthesis simulation in Foundation Express
20561: 00/02/14: Re: Post-synthesis simulation in Foundation Express
20567: 00/02/14: Re: Advice please
20589: 00/02/15: Re: clock
20639: 00/02/16: Re: FPGA Express/XC4KXLA annoyance
20654: 00/02/16: Re: Runtime Conditionals?
20923: 00/02/28: Re: atmel fpga starter kit
20925: 00/02/28: Re: Spartan and timing analyzer: clock nets using non-dedicated resources
20971: 00/03/01: Re: Bit Serial Arithmetic De-mystified
20994: 00/03/02: Re: Bit Serial Arithmetic De-mystified : On-Line Arithmetic
20969: 00/03/01: Re: AMS board simple questions
21003: 00/03/02: Re: xilinx synthesis tool
21031: 00/03/03: Re: SpartanXL route and place
21032: 00/03/03: Re: xilinx synthesis tool
21033: 00/03/03: Re: ORCA 3T - input/output delay reduction?
21083: 00/03/06: Re: SpartanXL route and place
21123: 00/03/07: Re: Stupid Foundation question
21152: 00/03/08: Re: SpartanXL route and place
21164: 00/03/08: Re: ModelSim 2.1i ?
21191: 00/03/09: Re: SpartanXL route and place
21190: 00/03/09: Re: SpartanXL route and place
21273: 00/03/14: Today's Unexplained Phenomena, Xilinx Department
21274: 00/03/14: Re: Virtex IOB T register
21391: 00/03/21: Re: Open Drain and tristate buffer
21392: 00/03/21: Re: Clock nets using non-dedicated resources
21435: 00/03/22: Re: constant error in VHDL code
21438: 00/03/22: Re: How to implement STARTBUF / GSR with SpartanXL and VHDL on FNDTN 2.1i ?
21441: 00/03/22: Re: FPGA openness
21443: 00/03/22: Re: Clock nets using non-dedicated resources
21444: 00/03/22: Re: Clock nets using non-dedicated resources
21486: 00/03/23: Re: No- FPGA openness
21494: 00/03/23: Re: No- FPGA openness
21764: 00/03/30: Program non-Xilinx parts with Xilinx JTAG programmer and cable?
21791: 00/03/31: Re: Program non-Xilinx parts with Xilinx JTAG programmer and cable?
21793: 00/03/31: Re: Program non-Xilinx parts with Xilinx JTAG programmer and cable?
21863: 00/04/04: Re: Program non-Xilinx parts with Xilinx JTAG programmer and cable?
21862: 00/04/04: Re: No net is connected....... ( xilinx)
21872: 00/04/04: Re: Clocks and BUFGP
21913: 00/04/06: Re: Power up set
21977: 00/04/10: Re: setup and hold time violation
22017: 00/04/12: Re: Modeltech Error
22041: 00/04/14: Re: XCHECKER 3V adapter
22074: 00/04/18: Re: Handshaking in Xilinx Foundation Express ???
22138: 00/04/26: Re: PID on FPGA
22414: 00/05/08: Re: Programming FPGA
22456: 00/05/09: Re: pipeline shiftreg in virtex
22505: 00/05/10: Re: EETools Topmax
22506: 00/05/10: Re: pipeline shiftreg in virtex
22634: 00/05/15: Re: See if this code can work.
22680: 00/05/17: Re: Best choice between FPGA and CPLD
22751: 00/05/22: Re: Xilinx tools
22792: 00/05/24: Re: 8087 in FPGA?
22824: 00/05/25: Re: Help for Spartan XCS10
22825: 00/05/25: Re: 8087 in FPGA?
22972: 00/06/06: Re: 3.3V I/O TO 5V LOGIC?
23104: 00/06/14: Re: FS: FpgaGuru.com DOMAIN
23253: 00/06/19: Re: 3.1i
23276: 00/06/20: Re: How to cut the power disipation down ?
23295: 00/06/21: Re: How to cut the power disipation down ?
23334: 00/06/22: Re: Xilinx PAR & Tristate busses
23383: 00/06/23: Re: Atmel bidirectional pins problem
23385: 00/06/23: Re: dual processor PC for PPR - are they worth the extra cost?
23461: 00/06/26: Re: a lot of basic questions - where's the FAQ?
23493: 00/06/27: Re: configuration of RAM created with coregen
23568: 00/06/30: Re: Problem with uploading in XC95288 using ISP with HW-JTAG-PC
23688: 00/07/05: Re: Virtex Global Set Reset
23692: 00/07/05: Re: Viewlogic schematic from Synplify edif output?
23739: 00/07/06: Re: Clock Buffer
23740: 00/07/06: Re: VHDL code for LFSR
23771: 00/07/07: Re: Clock Buffer
23780: 00/07/07: Re: Clock Buffer
23984: 00/07/19: Re: Summary: Re: Silicon Valley Housing Nightmare?
24041: 00/07/24: Re: Silicon Valley Housing Nightmare?
24098: 00/07/26: Re: Pad trireg in XLA FPGA
24102: 00/07/26: Re: Pad trireg in XLA FPGA
24103: 00/07/26: Re: Xilinx "MUX_OP not inferred" error.
24139: 00/07/27: Re: Which one is good coding style?
24140: 00/07/27: Re: Pad trireg in XLA FPGA
24142: 00/07/27: Re: Pad trireg in XLA FPGA
24185: 00/07/28: Re: Which one is good coding style?
24353: 00/08/04: Re: Interview Questions
24419: 00/08/07: Re: models of digital ICs
24420: 00/08/07: Re: Xilinx Alliance Base
25003: 00/08/23: Re: Looks like Xilinx is at it again!
25002: 00/08/23: Re: Looks like Xilinx is at it again!
25147: 00/08/28: Re: Xilinx 3.1i ISE
25148: 00/08/28: Re: Large amout of Interconnect between FPGAs
25176: 00/08/29: Re: Spurious errors in full FPGA?
25179: 00/08/29: Re: run time doubled with Xilinx 3.1i upgrade
25178: 00/08/29: Re: run time doubled with Xilinx 3.1i upgrade
25204: 00/08/30: Re: Xilinx and CD databooks (rant)
25205: 00/08/30: Re: Large amout of Interconnect between FPGAs
25327: 00/09/06: Re: Mealy vs Moore FSM model
25326: 00/09/06: Re: 3.3/2.5 voltage regulators
25346: 00/09/07: Re: 3.3/2.5 voltage regulators
25373: 00/09/08: VirtexE availability?
25430: 00/09/11: Re: VirtexE availability?
25431: 00/09/11: Re: VirtexE availability?
25504: 00/09/12: Complaint: Xilinx functional simulation libraries
25540: 00/09/13: Re: Complaint: Xilinx functional simulation libraries
25541: 00/09/13: Re: Complaint: Xilinx functional simulation libraries
25542: 00/09/13: Re: Complaint: Xilinx functional simulation libraries
25555: 00/09/13: Re: Complaint: Xilinx functional simulation libraries
25556: 00/09/13: Re: Complaint: Xilinx functional simulation libraries
25583: 00/09/14: FPGA Express Strikes Again!
25622: 00/09/15: Re: MAX PLUS 2
25623: 00/09/15: Re: Physical Interpretation
25624: 00/09/15: Re: timing constraints
25626: 00/09/15: Re: FPGA Express Strikes Again!
25719: 00/09/18: Re: VirtexE availability?
25795: 00/09/20: Re: FPGA Express Strikes Again!
25796: 00/09/20: Re: Complaint: Xilinx functional simulation libraries
25931: 00/09/26: FPGA Express strikes again! Xilinx response
25953: 00/09/27: Re: FPGA Express strikes again! Xilinx response
25954: 00/09/27: Re: Synthesiser comparisons (was: FPGA Express strikes again)
26000: 00/09/29: Funny Message
25582: 00/09/14: Re: coregen or logiblox
26062: 00/10/02: Re: FPGA Express strikes again! Xilinx response
26061: 00/10/02: Synthesis failures
26063: 00/10/02: Re: Xilinx Student Edition 2.1i first impressions
26067: 00/10/02: Re: Synthesis failures
26086: 00/10/03: Re: Synthesis failures
26087: 00/10/03: Re: Synthesis failures
26118: 00/10/04: Re: Xilinx Licensing.
26149: 00/10/05: Final word on the inverted RAM write clock problem
26179: 00/10/06: Re: Project Leader, Architecture Modeling
26230: 00/10/09: Re: Analogue FPGAs ?
26231: 00/10/09: Re: Long Island Verilog and VHDL people wanted!!
26232: 00/10/09: Re: Project Leader, Architecture Modeling
26234: 00/10/09: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26235: 00/10/09: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26236: 00/10/09: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26279: 00/10/10: Re: Analogue FPGAs ?
26280: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26281: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26313: 00/10/11: Re: Analogue FPGAs ?
26314: 00/10/11: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26320: 00/10/11: Xilinx, Altera stocks take dumps!
26346: 00/10/12: Re: Analogue FPGAs ?
26347: 00/10/12: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26348: 00/10/12: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26378: 00/10/13: Re: palasm
26380: 00/10/13: Re: How to functionally simulate Xilinx Cores in my design ?
26381: 00/10/13: Re: Long filenames in Express schematic editor
26385: 00/10/13: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26445: 00/10/16: Re: palasm
26446: 00/10/16: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26537: 00/10/19: Re: Q: Xilinx unified libraries and synthesis
26538: 00/10/19: Re: VHDL vs Verilog
26573: 00/10/20: Re: UCF Question
26574: 00/10/20: Re: CoolRunner news :(
26580: 00/10/20: Re: UCF Question
26638: 00/10/23: Re: UCF Question
26639: 00/10/23: Re: RS422 interfacing to a FPGA ?
26697: 00/10/25: Re: UCF Question
26736: 00/10/26: Re: Using GSR Xilinx 4k
26766: 00/10/27: Re: Long Island Verilog and VHDL people wanted!!
26767: 00/10/27: Re: Excellent Opportunity ASIC Engineers CA International Relocation
26768: 00/10/27: Re: UCF Question
26831: 00/10/31: Re: High fan out CE signal.
26838: 00/10/31: Re: High fan out CE signal.
26839: 00/10/31: Re: High fan out CE signal.
26842: 00/10/31: Re: Alliance under Linux?
26843: 00/10/31: Re: Alliance 3.2i
26840: 00/10/31: Re: High fan out CE signal.
26841: 00/10/31: Re: High fan out CE signal.
26858: 00/11/01: Re: Alliance under Linux?
26882: 00/11/02: Re: OT: Xilinx T-Shirt
26901: 00/11/02: Re: OT: Xilinx T-Shirt
26902: 00/11/02: Re: OT: Xilinx T-Shirt
26938: 00/11/03: Re: OT: Xilinx T-Shirt
27049: 00/11/08: Re: Global buffers in xc40000xla
27066: 00/11/09: Re: Microprocessor Verilog/VHDL Models
27096: 00/11/10: Re: Pull-up
27097: 00/11/10: Re: Microprocessor Verilog/VHDL Models
27170: 00/11/13: Re: Pull-up
27171: 00/11/13: Re: Clear AND Preset Pins
27172: 00/11/13: Re: Anything wrong with Xilinx website?
27255: 00/11/16: Re: VHDL & Spartan: How to power-up a Register to '1' ?
27256: 00/11/16: Re: FPGA Pin Nunber
27257: 00/11/16: Re: Microprocessor Verilog/VHDL Models
27267: 00/11/16: Re: Can FPGA perform float point calculation?
27310: 00/11/17: Re: COREGEN ROM in VHDL... How do I use it?
27311: 00/11/17: Re: Spartan 3.3V Driving 5v input tristate + pull up problem...
27312: 00/11/17: Re: VHDL & Spartan: How to power-up a Register to '1' ?
27313: 00/11/17: Re: Microprocessor Verilog/VHDL Models
27387: 00/11/20: Re: Rambus Reveals Plans To Collect Royalties From Chipset Makers
27388: 00/11/20: Re: In the news
27456: 00/11/22: Re: Clock Skew : Does Xilinx know what they're doing?
27560: 00/11/28: Re: Fifo design problem
27596: 00/11/29: Re: Fifo design problem
27597: 00/11/29: Re: Fifo design problem
27598: 00/11/29: Re: question on initial states of FFs and GSR in Virtex
27710: 00/12/04: Re: which I/O pin belongs to each bank
27717: 00/12/04: Re: Issues with Spartan II
27886: 00/12/13: Re: ERROR: The net has more than one driver?
27887: 00/12/13: Re: Test Bench
27888: 00/12/13: Re: FPGA Express & VHDL files
27889: 00/12/13: Re: ADAPTIVE FILTER
27890: 00/12/13: Re: Issues with Spartan II
27941: 00/12/15: Re: Semiconductor process engineers needed
27973: 00/12/18: Re: Verilog or VHDL
28029: 00/12/19: Re: Question about Xilinx pins at high-frequency
28087: 00/12/20: Re: Samsung SDRAM behavioural models
28089: 00/12/20: Re: Question about Xilinx pins at high-frequency
28115: 00/12/21: Re: 3V -> 5V clock signal level conversion
28227: 01/01/02: Re: XC9500 and unused inputs
28365: 01/01/10: Re: Alliance for Linux
28411: 01/01/11: Re: Alliance for Linux
28420: 01/01/11: Re: address of ram using the clk net
28421: 01/01/11: Re: grey code counters
28449: 01/01/12: Re: Alliance for Linux
28584: 01/01/17: Re: Virtex-II officially launched
28585: 01/01/17: Re: Synplify Pro6.13
28586: 01/01/17: Re: Computer Wizard!
28587: 01/01/17: Re: I wanna Model Sim cracked
28588: 01/01/17: Re: grey code counters
28590: 01/01/17: Re: Alliance for Linux
28631: 01/01/18: Re: Virtex-II officially launched
28632: 01/01/18: Re: VHDL question
28753: 01/01/23: Re: Verilog model of Xilinx macro in VHDL Testbench fails
28793: 01/01/24: Re: Foundation - Source Constraints
28794: 01/01/24: Re: xilinx cpld
28795: 01/01/24: Re: Fixing pins on Spartan II
28796: 01/01/24: Re: APEX
28832: 01/01/25: Re: XC7272 vers XC9272.
28833: 01/01/25: Re: Encryption is supported in new Virtex II but.....
28834: 01/01/25: Re: Encryption is supported in new Virtex II but.....
28919: 01/01/29: Re: set/reset
28940: 01/01/30: Re: set/reset
29077: 01/02/05: Re: Help for a novice. Where to begin?
29105: 01/02/06: Re: Switching matrix, FPGA or CPLD? - smatrix.JPG (0/1)
29106: 01/02/06: Re: Help for a novice. Where to begin?
29202: 01/02/09: Re: Xilinx vs Altera
29307: 01/02/13: Re: any idea ?
29309: 01/02/13: Re: Virtex XCV2000E-6 BG560C - Orcad capture symbol
29311: 01/02/13: Re: Help for a novice. Where to begin?
29352: 01/02/15: Re: Rijndael
29402: 01/02/19: Re: ALtera CPLD
29466: 01/02/22: Re: Virtex USB solution
29467: 01/02/22: Re: UCF problem "- Could not find NET "
29606: 01/02/28: Re: cpul vs vhdl
29607: 01/02/28: Re: UNISIM
29608: 01/02/28: Re: ERROR on Xilinx fundation
29609: 01/02/28: Re: Virtex USB solution
29691: 01/03/05: Re: webpack ISE synthesis fails with exit code: 0002
29738: 01/03/06: Re: Virtex USB solution
30053: 01/03/21: Re: Senior I/O Designer - Canada
30155: 01/03/26: Re: Senior I/O Designer - Canada
30314: 01/04/02: Re: FPGA V CPLD
30489: 01/04/10: Re: VHDL falling edge in Xilinx Foundation...
34705: 01/09/04: Re: using non-standard eeprom to program xilinx fpga
34706: 01/09/04: Re: Prom : Question on Configuration
34707: 01/09/04: Re: ISA(PC/104) BUS DECODE ASYNC or SYNC?
35003: 01/09/17: Re: Specifing global clocks on a Spartan II (Newbee Quest)
35011: 01/09/17: Re: using BlockRAM
35012: 01/09/17: Re: Problems with Xilinx VirtexE (Newbie)
35013: 01/09/17: Re: Xilinx Foundation Base(DS-ISE-XB2). Exactly what do you get?
35015: 01/09/17: Re: Actel FPGA glitches
35119: 01/09/21: Re: problem with location constraints in Verilog
35279: 01/09/27: Re: how to dublicate logic?
35612: 01/10/11: Re: Linking components in VHDL
35671: 01/10/13: Re: High level synthesis will never work well :)
35672: 01/10/13: Re: Synplicity/Leonardo License Agreement Information
35754: 01/10/16: Re: Timing constraints for unrelated clocks?
35755: 01/10/16: Re: Synplicity/Leonardo License Agreement Information
35827: 01/10/18: Re: simple question
35829: 01/10/18: Re: Timing Constarint Error message
35887: 01/10/22: Re: Problems with writing into text file
35888: 01/10/22: Re: one-hot statemachine
35889: 01/10/22: Re: Verilog vs. VHDL
35890: 01/10/22: Re: Glitch Hunting, a true story ;-)
35920: 01/10/24: Re: Verilog vs. VHDL
35940: 01/10/24: Re: Bidirectional port is converted to input during synthesis
35941: 01/10/24: Re: Are there any Coolrunner P5Z22V10 (PLCC) devices left anywhere?
35942: 01/10/24: Re: S/PDIF interface for FPGA
35943: 01/10/24: Re: Verilog vs. VHDL
35944: 01/10/24: Re: Verilog vs. VHDL
35989: 01/10/25: Re: S/PDIF interface for FPGA
35991: 01/10/25: Re: LUT Glitches
36292: 01/11/05: Re: Help with Synplify Warning
36580: 01/11/12: Re: Incrementing counter from state-machine
36583: 01/11/12: Re: ideas
36585: 01/11/12: Re: Multiple levels of reset in CPLD
36586: 01/11/12: Re: Xilinx dedicated IO pins
36587: 01/11/12: Re: Question about pipelining a design
36765: 01/11/19: Re: Incrementing counter from state-machine
36767: 01/11/19: Re: Synopsys+Xilinx vs Synplicity
36768: 01/11/19: Re: 'Timing' simulation in ModelSIM
36769: 01/11/19: Re: Xilinx and Multirate clock ??
36772: 01/11/19: Re: Virtex2 gate-level simulation: SDF and timing errors
36808: 01/11/20: Re: Incrementing counter from state-machine
36838: 01/11/21: Re: Viewing generated VHDL
36839: 01/11/21: Re: Prototyping Board
36982: 01/11/28: Re: Device Support in Webpack
36983: 01/11/28: Re: Simple Logic State Analyser
37032: 01/11/28: Re: Creating a jitter free clock
37121: 01/11/30: Re: Modelsim
37195: 01/12/03: Re: What do you like/dislike about place and route tools?
37196: 01/12/03: Re: Is there a full open-source synthesis path for any FPGA?
37239: 01/12/04: Re: Installing ISE 4.1i
37240: 01/12/04: Re: What do you like/dislike about place and route tools?
37303: 01/12/06: Re: Has anyone successfully used opencores PCI?
37304: 01/12/06: Re: where is designed FPGA for apple II computer...?
37422: 01/12/10: Re: Timing Simulation Model
37620: 01/12/17: Re: newbie Xilinx Foundation ISE4.1 questions
37621: 01/12/17: Re: division 64
37645: 01/12/18: Re: is it OK?
37721: 01/12/19: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37723: 01/12/19: Re: Best-case timing?
37791: 01/12/20: Re: Best-case timing?
37958: 01/12/27: Re: Atmel FPSLIC - Problem with concurrent statements
37959: 01/12/27: Re: vector reversed in netlist of XC9572XL
37960: 01/12/27: Re: Lattice Filter Schematic?
37961: 01/12/27: Re: THE SIGNAL LIST IS NOT AVAILABLE TO SIMULATE
37980: 01/12/28: Re: Atmel FPSLIC - Problem with concurrent statements
38039: 02/01/02: Re: FPGA
38062: 02/01/03: Re: Atmel FPSLIC - Problem with concurrent statements
38063: 02/01/03: Re: Virtex-2 maximum clock speed
38157: 02/01/07: Re: WARNING
38233: 02/01/09: Re: bufg instantiation in ISE 4.1
38779: 02/01/25: Re: Audio time delay circuit
38780: 02/01/25: Re: Coregen Half-Band FIR filter implemenation does not work
47358: 02/09/24: OT: Ulticap/Ultiboard 2001 netlist import failure
47926: 02/10/07: Re: USB2 in FPGA?
50200: 02/12/04: Re: Interfacing DSP to PCI bridge using a FPGA
50201: 02/12/04: Re: Interfacing DSP to PCI bridge using a FPGA
51858: 03/01/23: Re: VHDL or Verilog?
51859: 03/01/23: Re: VHDL or Verilog?
51860: 03/01/23: Re: VHDL or Verilog?
52012: 03/01/28: Re: VHDL or Verilog?
52710: 03/02/19: Re: Generating a sin wave with vhdl
52845: 03/02/24: Re: Quick FPGA PCI I/O in Spartan-IIE for single peripheral
53946: 03/03/27: Re: Can ModelSim PE/SE and XE coexist?
54035: 03/03/31: Re: [Question] FPGA/PLX9054
54036: 03/03/31: Re: More xilinx webpack verilog questions: always @(clock) legal?
54061: 03/04/01: Re: [Question] FPGA/PLX9054
56471: 03/06/05: Re: defparam (Synthesizable or Not?)
56472: 03/06/05: Re: Post P&R Verilog/VHDL netlist
57772: 03/07/06: Re: QuartusII software licencing
58492: 03/07/24: Re: Active Probe
58732: 03/07/31: Re: Mentor Hyperlynx IBIS simulator (was Re: Spartan IIE max pin switching)
59219: 03/08/12: Re: Webpack sees 2 clocks when there is only one
59510: 03/08/20: Re: 22V10, ABEL & Current Design Tools?
59511: 03/08/20: Re: Anyone familiar with ispXPLD?
59900: 03/08/31: Re: How to listen to music through an FPGA pin?
59901: 03/08/31: Re: How to use Modelsim-Altera to do the timing simulation?
60144: 03/09/05: Re: Writing a Xilnx testbench
60959: 03/09/25: Re: Synchronous Binary counter question.
61036: 03/09/26: Re: FF with CE doesn't synthesize correctly by XST?
61037: 03/09/26: Re: Strange synthesis behavior from Quartus II 2.2
61038: 03/09/26: Re: Synchronous Binary counter question.
61039: 03/09/26: Re: virtex2p power consumption
61043: 03/09/26: Re: Xilinx S3 I/O robustness question
61044: 03/09/26: Re: How to change "X" to "0" or "1" (VHDL) ?
61171: 03/09/29: Re: Free WebPack 6.1i Download Available Now for Spartan-3
61238: 03/09/30: Re: Xilinx S3 I/O robustness question
61290: 03/10/01: Re: Frustrations with Marketing
61592: 03/10/07: Re: Problem with PCI cards
62229: 03/10/22: Re: Lattice Mach CPLD - Leonardo Spectrum vs. Synplify
62271: 03/10/23: Re: Lattice Mach CPLD - Leonardo Spectrum vs. Synplify
62273: 03/10/23: Re: The Luddite Needs Reference Books...
62280: 03/10/23: Re: Lattice Mach CPLD - Leonardo Spectrum vs. Synplify
62342: 03/10/27: Re: SDRAM Controller
63771: 03/12/03: Re: what's the problem?
63906: 03/12/08: Re: Quartus-II question
64064: 03/12/15: Re: VHDL-Testbench-Simulation in QuartusII
64306: 03/12/26: Re: Xilinx Johnson counter Verilog example bug?
64317: 03/12/27: Re: predictable timing for xilinx cpld?
64332: 03/12/28: Re: predictable timing for xilinx cpld?
64488: 04/01/05: Re: Something additional: Adding internal signals in MODELSIM
64782: 04/01/13: Re: Anybody know what the REAL story is?
64808: 04/01/14: Re: Synthesis in VHDL vs. Verilog
64881: 04/01/15: Re: Generating clock delays
64885: 04/01/15: Re: Gray encoding for FSM
64897: 04/01/15: Re: DMA w/ Xilinx PCIX core: speed results and question
65114: 04/01/20: Re: Tristate buffer
65365: 04/01/26: Re: Tristate buffer
65493: 04/01/30: Re: asynchronous counter an Xilinx FPGA for a newbie
65494: 04/01/30: Re: Phase detector for DLL
65563: 04/02/02: Re: asynchronous counter an Xilinx FPGA for a newbie
65797: 04/02/06: Re: need desperate help!
65798: 04/02/06: Re: Differences between Xilinx ISE and Altera Quartus software
65819: 04/02/06: Re: Pricing, 101
65954: 04/02/10: Re: Pricing, 101
65955: 04/02/10: Re: need desperate help!
65957: 04/02/10: Re: need desperate help!
66346: 04/02/17: Re: sdram controller problems
66428: 04/02/19: Re: Simulation MODEL for SRAM
66700: 04/02/25: Re: SRAM bidirectional bus
66961: 04/03/02: Re: Altera ACEX chip wide reset
67277: 04/03/09: Re: Can `protect-ed Verilog codes be synthesized with Xilinx XST?
67479: 04/03/12: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
67880: 04/03/21: Re: Why It Is not Recommended to Infer latches in VLSI Design...
67881: 04/03/21: Re: Why It Is not Recommended to Infer latches in VLSI Design...
67882: 04/03/21: Re: PCI Development Board
67971: 04/03/23: Re: PCI Development Board
68068: 04/03/25: Re: study verilog or vhdl?
68239: 04/03/30: Re: AHDL, VERILOG or VHDL??
68585: 04/04/08: Re: What is the use of MAX7128?
68704: 04/04/14: Re: what is a better approach to synthezise synchronous reset on FPGA?
68786: 04/04/18: Re: UART with FIFO -> CPLD / FPGA / ?
68856: 04/04/20: Re: State machines vs. Schematics
68858: 04/04/20: Re: Trouble with rising edge signals in functional simulation
68907: 04/04/21: Re: Trouble with rising edge signals in functional simulation
69195: 04/04/29: Re: Design development costs for FPGA on PCI board (sorry if slightly off-topic)
69263: 04/05/03: Re: Best way to handle multiple common data busses in Altera FPGA (and others)
69409: 04/05/10: Re: One issue about free hardware
69413: 04/05/10: Re: How to perform a timing simulation in Modelsim with QuartusII output file ?
69559: 04/05/13: Re: program flash memory through JTAG on FPGA
69560: 04/05/13: Re: Effects of moisture on CPLD
69814: 04/05/20: Re: program flash memory through JTAG on FPGA
69888: 04/05/23: Re: I2C Slave
69891: 04/05/23: Re: strange behaviour of the design
71239: 04/07/12: Re: FPGA to PCI Bus Interface
71278: 04/07/13: Re: new Lattice FPGAs vs Cyclone and SpartanIII
71361: 04/07/15: Re: new Lattice FPGAs vs Cyclone and SpartanIII
72277: 04/08/12: Re: Altera winner?
73716: 04/09/28: Re: Simple Counter in Verilog
73505: 04/09/22: Re: Verilog vs VHDL for Loops
74434: 04/10/11: Re: Daft modelsim question
82496: 05/04/13: Reading old F2.1i schematics
82835: 05/04/18: source control and Xilinx ISE 6 and 7
82847: 05/04/18: Re: source control and Xilinx ISE 6 and 7
82908: 05/04/19: Re: source control and Xilinx ISE 6 and 7
82918: 05/04/19: Re: Perl Preprocessor for HDL
83371: 05/04/28: Re: PCI plug n play and Graphics card implementation
84037: 05/05/11: Re: Analog to Digital Converted (ADC) & Spartan 3
84262: 05/05/16: Re: FPGA design under Mac OS X ?
84266: 05/05/16: Re: floorplanning
84351: 05/05/17: Re: FPGA design under Mac OS X ?
84399: 05/05/18: Re: FPGA design under Mac OS X ?
84481: 05/05/19: Re: For accessing my SDRAM,what should i do?
84551: 05/05/20: Re: For accessing my SDRAM,what should i do?
85197: 05/06/06: Re: Hope for OS X tools...
86320: 05/06/24: Re: using GUI and batch mode produces different results !
86405: 05/06/27: Re: vsync on dvi
86476: 05/06/28: Re: Two Verilog FSM style compare
86552: 05/06/29: XST: setting top-level generics
86596: 05/06/30: Re: Coverting .mcs file to .bit file
86597: 05/06/30: Re: XST: setting top-level generics
86605: 05/06/30: Re: Cannot find net in ucf, but it's there....
86640: 05/07/01: Re: Direct audio output from FPGA pins
86732: 05/07/05: Re: Xilinx: XST synchronous FIFO using BRAMs
86903: 05/07/08: Re: fastest FPGA speed grade?
86913: 05/07/08: Re: XST: setting top-level generics
86965: 05/07/11: Re: Verilog exponential operator issues in simulation (ISE 7.1 SP3 w/ ModelSim 6.0a)
87000: 05/07/12: Re: Testbenching and verification
87002: 05/07/12: Re: Xilinx MAP problem (>1 External Macro Output Pin on single net)
87003: 05/07/12: Re: output-value isn't stored
87004: 05/07/12: Re: Verilog exponential operator issues in simulation (ISE 7.1 SP3 w/ ModelSim 6.0a)
87046: 05/07/13: Re: ise 7.1 Input clk is never used.
87048: 05/07/13: Re: QII simulation annoyance
87049: 05/07/13: Re: QII simulation annoyance
87137: 05/07/16: Re: Doubts on Xilinx FPGA
87286: 05/07/20: Re: Design is too large for the device! xc3s400
87343: 05/07/21: Re: Design is too large for the device! xc3s400
87345: 05/07/21: Re: Generics of type time and XST synthesis
87396: 05/07/22: Re: What a nice day for XLNX
87397: 05/07/22: Re: verilog to blif(lut)
87587: 05/07/26: Re: Design is too large for the device! xc3s400
87590: 05/07/26: Re: July 20th Altera Net Seminar: Stratix II Logic Density
87704: 05/07/28: Re: XST and TCL support?
87728: 05/07/29: Re: VHDL 200x? when?
87791: 05/08/01: Re: struggling with general digital design
87792: 05/08/01: Re: struggling with general digital design
88010: 05/08/05: Re: Holding in output registers
88110: 05/08/09: Re: Can use SRAM instead of VRAM ......... how ???????????
88111: 05/08/09: Re: can use bram for VGA
88146: 05/08/10: Re: FPGA Programming using Block Design Files or Graphic Design Files
88147: 05/08/10: Re: How to setup Analyzer in ChipScope Pro
88149: 05/08/10: Re: Hiding data inside a FPGA
88162: 05/08/10: Re: FPGA Programming using Block Design Files or Graphic Design Files
88246: 05/08/12: Re: freeware/reasonable-ware c compiler for picoblaze
88309: 05/08/15: Re: VHDL Array indexing Issue in Modelsim
88310: 05/08/15: Re: Delay implementation and logic optimization.
88311: 05/08/15: Re: Modular design flow
88312: 05/08/15: Re: XST (ISE 6.1i): Error: It's interesting and surprising
88313: 05/08/15: Re: creating HARD MACROs broken in ISE 7.1 SP3 ?
88314: 05/08/15: Re: Creating EDIF from VHDL
88460: 05/08/18: Re: State Machine and BUFG
88461: 05/08/18: Re: Chipscope pro : timing constraint?
88549: 05/08/22: Re: How can I see the waveform of my verilog codes?
88872: 05/08/30: Re: Fine grain vs. Coarse Grain Architectures
88932: 05/08/31: Re: Hi-Z input
89508: 05/09/16: Re: Version Control Software
89656: 05/09/21: Re: Xilinx ModelSim VHDL Running Two Models
89730: 05/09/23: Re: Xilinx ModelSim VHDL Running Two Models
89862: 05/09/28: Re: chipscope pro
89865: 05/09/28: Re: Version Control Software
89961: 05/09/30: Re: Version Control Software
89963: 05/09/30: Re: Version Control Software
90030: 05/10/03: Re: Inferring design elements in ISE tool
90076: 05/10/04: Re: Xilinx IMPACT Problem... detects 101 unknown devices
90077: 05/10/04: Re: Prob in Synthesizing and Simulating large Mux
90079: 05/10/04: Re: vhdl question
90153: 05/10/05: Re: vhdl question
91211: 05/11/01: Re: Sigma-Delta A/D
91272: 05/11/02: Re: Newbie. Clocks.
91332: 05/11/03: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91479: 05/11/07: Re: icarus verilog
91679: 05/11/10: Re: Signal timing problem
91750: 05/11/11: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
91822: 05/11/14: Re: Power on problem--- signal behaving strangely
91823: 05/11/14: Re: PCI test bench
91962: 05/11/17: Re: Parallel Cable IV not detecting
91988: 05/11/18: Re: Parallel Cable IV not detecting
91991: 05/11/18: Re: Trying to define Opendrain Outputs
91993: 05/11/18: Re: Bidirectional bus control
92054: 05/11/21: Re: Verilog Editor.
92055: 05/11/21: Re: Oh no! Resets Again? Yes, but it could be important.
92101: 05/11/22: Re: Patient Monitors: Reading RS232 output w/ an FPGA
92103: 05/11/22: Re: Newbie: Problems with clocks
92112: 05/11/22: Re: Xst optimizes almost everything away
92190: 05/11/23: Re: Xst optimizes almost everything away
92416: 05/11/29: Re: Slow FIFO using external SRAM
92417: 05/11/29: Re: subtractor
92436: 05/11/29: Re: Slow FIFO using external SRAM
92559: 05/12/01: Re: Supplier of Xilinx XC2V1000 or 2V250?
92649: 05/12/02: Re: Synthesize: Error
92705: 05/12/05: Re: Tip: Spotlight (OS X) indexing of VHDL files
92781: 05/12/06: Re: VHDL SPI core
92782: 05/12/06: Re: ISE 8.1 release delayed?
93354: 05/12/20: Re: More beginner's verilog questions
93403: 05/12/21: Re: More beginner's verilog questions
93404: 05/12/21: Re: More beginner's verilog questions
93405: 05/12/21: Re: Can anyone have the evaluation board from xilinx and altera?
93483: 05/12/22: Re: More beginner's verilog questions
93484: 05/12/22: Re: More beginner's verilog questions
93485: 05/12/22: Re: More beginner's verilog questions
93486: 05/12/22: Re: Place and Route Algorithms: where's the fat?
93487: 05/12/22: Re: Place and Route Algorithms: where's the fat?
93520: 05/12/23: Re: Spartan3e and ChipScope
94019: 06/01/04: Re: Using posedge and negedge causing me grief
94379: 06/01/10: Re: Xilinx 7.1 ISE ModelSim input files
94613: 06/01/14: Re: FPGA Journal Article
94780: 06/01/17: Re: FPGA Journal Article
94855: 06/01/18: Re: FPGA Journal Article
95717: 06/01/25: Re: Xilinx padding LC numbers, how do you really feel about it?
95835: 06/01/26: Re: open source fpga programmer programs
95891: 06/01/26: Re: open source fpga programmer programs
95838: 06/01/26: Re: Xilinx padding LC numbers, how do you reeeeellly feel about it?
95839: 06/01/26: Re: Stop. Go. Yield.
96552: 06/02/06: Re: FPGA growth vs. ASIC growth
96634: 06/02/07: Re: why does speed grade effect VHDL program??
96732: 06/02/09: Re: cheap USB analyzer based on FPGA
96803: 06/02/10: Re: Async Processors
96883: 06/02/12: Re: Altera EPLD
96922: 06/02/13: Re: digital logic library by 74xxxx part number?
97061: 06/02/15: Re: digital logic library by 74xxxx part number?
97104: 06/02/16: Re: VHDL or verilog
97455: 06/02/22: Re: Is FPGA code called gateware?
97623: 06/02/24: Re: The 95108 cpld is getting heated when connected by CRO
98610: 06/03/13: Re: PROBLEMS WITH COOLRUNNER XPLA3
98611: 06/03/13: Re: Soldering SMT/BGA
98615: 06/03/13: Re: Why does Xilinx hate version control?
98733: 06/03/15: Re: Why does Xilinx hate version control?
98734: 06/03/15: Re: Why does Xilinx hate version control?
98735: 06/03/15: Re: Any PCAD users here by any chance?
98883: 06/03/17: Re: Instantiating addsub, comparators in Xilinx
98884: 06/03/17: Re: Where are FPGA heading?
99120: 06/03/20: Re: Instantiating addsub, comparators in Xilinx
99125: 06/03/20: Re: memories for virtex-4 and Spartan-3E
99299: 06/03/22: Re: Verilog's integer and reg?
99718: 06/03/28: Re: basic doubts about chipscope pro
99719: 06/03/28: Re: Specifying top level generics with XST 7.1
99884: 06/03/30: Re: USB Interface to Virtex-4
100258: 06/04/05: Re: USB Interface to Virtex-4
100327: 06/04/06: Re: USB Interface to Virtex-4
101221: 06/04/27: Re: UCF-mode for Emacs
101477: 06/05/01: Re: ISE 8.1 Comment Bug, Very hideous
101611: 06/05/03: Re: Interfacing Spartan 3 board to PC parallel port??
102203: 06/05/11: Re: can increase simulation run time while running modelsim?
102584: 06/05/17: Re: IEEE-1394 (aka FireWire) Core
104314: 06/06/23: Re: keys to the Kingdom
104542: 06/06/29: Re: help downloading picoblaze from xilinx (xapp627.zip)
104999: 06/07/11: Re: Implementing USB slow protocol into xilink XC95xxx..
105254: 06/07/18: Re: NAND flash hangs
105502: 06/07/24: Re: version control of ISE+EDK projects with CVS and/or SVN
106006: 06/08/04: Re: Chipscope
106235: 06/08/09: Re: logic analyzer for Spartan3 starterkit, GPL VHDL and java based sw
107137: 06/08/24: Re: QuickLogic
107837: 06/09/01: Re: Interface of 8051 microcontroller with FPGA Block RAM
109275: 06/09/22: Re: please tell me how to learn testbench?
109665: 06/10/02: Re: I2S serial to parallel conversion and generating C,V and Z bits
110731: 06/10/20: Re: Cheapest FPGA board to study VHDL on
111057: 06/10/27: Re: Survey: simulator usage
111153: 06/10/30: Re: Picoblaze simulation
111154: 06/10/30: Re: Survey: simulator usage
111317: 06/11/01: Re: Dual Port RAM
111319: 06/11/01: Re: Dual Port RAM
113353: 06/12/11: Re: approximation of an exponential ramp?
113354: 06/12/11: Re: Tarfessock1
114116: 07/01/04: Re: Surface mount ic's
114422: 07/01/15: Re: ISE 9.1i and partial reconfiguration
114879: 07/01/25: Re: Xilinx USB download cable
114880: 07/01/25: Re: Xilinx ISE 8.2
115089: 07/01/30: Re: Help with Xilinx i/o constracint for ps/2 port
115090: 07/01/30: Re: How to use the test bench wave form simulator?
115175: 07/02/01: Re: Webpack 9.1 problems with Impact on parallel cable
115276: 07/02/05: Re: ISE 9.1 SAY YOURS OPINION
116246: 07/03/05: Xilinx: it's about time!
116268: 07/03/05: Re: Multiple devices within one ISE project
116269: 07/03/06: Re: xilinx block ram synthesis
116419: 07/03/08: Re: Spartan3AN - Roadmap
116477: 07/03/09: XST 9.1 hates VHDL character types
116478: 07/03/09: Re: XST 9.1 hates VHDL character types
116553: 07/03/12: Re: odd warning in Xilinx ISE webpack
116554: 07/03/12: Re: Design report does not show BRAM usage
116895: 07/03/20: Re: FF's are inffered instead of distributed RAM
117136: 07/03/23: Re: Austin the Altera Mole
117137: 07/03/23: Re: Why is Xilinx's WebPACK so inferior?
117283: 07/03/27: Re: Where is Open Source for FPGA development?
117285: 07/03/27: Re: Where is Open Source for FPGA development?
117423: 07/03/30: Re: ModelSim VHDL Pragmas
118150: 07/04/18: Re: Printing problem with Ise 9.1.03i
118152: 07/04/18: Re: creating library in ISE 9
118153: 07/04/18: Re: ISE Smart Ident
118214: 07/04/19: Re: Printing problem with Ise 9.1.03i
119176: 07/05/14: Re: Camera Control
120410: 07/06/06: Re: Virtex4 CLKX2 DCM Jitter
120939: 07/06/20: Re: Suggestions for Xilinx based evaluation board for image processing
121003: 07/06/21: Re: Can anyone identify the manufacturer of this Chip ?
121004: 07/06/21: Re: Can anyone identify the manufacturer of this Chip ?
121005: 07/06/21: Re: Can anyone identify the manufacturer of this Chip ?
121335: 07/07/02: Re: Xilinx programmer, many unknown devices...
121984: 07/07/16: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
122126: 07/07/19: Re: Can multiple Ferrite Beads be used to connect ...?
122776: 07/08/06: Re: SDR SDRAM controller for Xilinx Spartan-3E
123603: 07/08/30: Re: Output signals not synchronized
124363: 07/09/19: Re: Camera Link i/f spec - signal requirements on FVAl/LVAL/DVAL
124527: 07/09/25: Re: Never buy Altera!!!!
124563: 07/09/26: Re: Never buy Altera!!!!
127991: 08/01/11: Spartan 3AN LVDS I/O
127992: 08/01/11: Re: Spartan 3AN LVDS I/O
128016: 08/01/12: Re: Spartan 3AN LVDS I/O
130795: 08/04/01: Re: ISE 10.1 - Initial experience
130796: 08/04/01: Re: ISE 10.0 finally with multi-threading and SV support ?
130817: 08/04/02: Re: ISE 10.1 - Initial experience
130853: 08/04/03: Re: EDK 10.1 first impressions
130891: 08/04/04: Re: One more question. WebPACK key with ISE
130982: 08/04/07: Re: system level language: why all this fuss about
131209: 08/04/15: Re: Snythesis error
131481: 08/04/22: Re: synchronous reset problems on FPGA
132083: 08/05/12: Re: How to input an analog signal to FPGA board for processing?
132592: 08/06/02: Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
134257: 08/08/01: Re: ISE new file wizard
134655: 08/08/24: Re: Xilinx extends Spartan 3A series
134656: 08/08/24: Re: More work, less posts
136838: 08/12/08: Re: ISE doesn't work after a crash
137318: 09/01/08: Re: Which revision control do fpga designers use (2009)
137320: 09/01/08: Re: Which revision control do fpga designers use (2009)
138086: 09/02/05: Re: Why the second flip-flop in Virtex-6?
138415: 09/02/20: Re: ERROR:Map:11 - serdes_4b_1to7_wrapper symbol "rx0" - more than
138633: 09/03/02: Re: xilinx-microblaze interrupt controller
138787: 09/03/10: Re: Integer arithmetic in HDLs
138788: 09/03/10: Re: Finding aligned clock transitions with state machine
138803: 09/03/11: Re: Finding aligned clock transitions with state machine
138814: 09/03/11: Re: asynchronous preloading a counter
139477: 09/03/31: Re: best soft core(s) that have C compiler support
140078: 09/04/27: Re: FPGA/DSP/Video Board
140095: 09/04/28: Re: ISE 11.1 drops support for Virtex-2/Pro and Spartan-2/E
140096: 09/04/28: Re: FPGA/DSP/Video Board
140180: 09/05/01: Re: ISE/EDK/SDK 11.1 licensing
140215: 09/05/04: Re: FIFO that latches data asynchronic manner
140573: 09/05/18: Re: XILINX license model restricts longtime availability
140574: 09/05/18: Re: sync vs async reset
140809: 09/05/26: Re: INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred ....
140812: 09/05/26: Re: Setting top level VHDL generics in XST
140852: 09/05/27: Re: INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred ....
140891: 09/05/28: Re: INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred ....
141145: 09/06/08: Re: Xilinx Block RAM Sim
141452: 09/06/24: Re: True dual-port RAM in VHDL: XST question
142012: 09/07/21: Re: How do you handle build variants in VHDL?
142027: 09/07/22: Xilinx ISE 11.x lossage
142099: 09/07/24: Re: Xilinx ISE 11.x lossage
142105: 09/07/24: Re: Xilinx ISE 11.x lossage
142189: 09/07/28: Re: Xilinx ISE 11.x lossage
142190: 09/07/28: Re: Xilinx ISE 11.x lossage
142437: 09/08/11: Re: Spartan-6 Boards - Your Wish List
142724: 09/08/28: Re: Is free-to-use IP included with downloadable FPGA tools?
142726: 09/08/28: Re: Is free-to-use IP included with downloadable FPGA tools?
142927: 09/09/08: Re: Mac OS X support for Sigasi HDT
143032: 09/09/15: Re: 8 phase clock output
143115: 09/09/21: Re: To Xilinx: Regarding the download manager
143250: 09/09/28: Re: USB programmable Open Source Hardware
143290: 09/09/29: Re: IP protection for FPGA users
143300: 09/09/30: Re: USB programmable Open Source Hardware
143403: 09/10/09: Re: foundation 2.1 - 3.1 sharing...
143545: 09/10/15: Re: problem while receiving negative integer in microblaze
143546: 09/10/15: Re: problem while receiving negative integer in microblaze
143795: 09/10/26: Re: problem while receiving negative integer in microblaze
144399: 09/12/03: Re: Where to go when Spartan-3A DSP 3400 is full?
144400: 09/12/03: Re: A new approach to FPGA and PCB System Development Platform, Santa
144454: 09/12/08: Re: A new approach to FPGA and PCB System Development Platform, Santa
145654: 10/02/17: Re: How a state machine is constructed using latches?
146046: 10/03/04: Re: Modelsim PE vs. Aldec Active-HDL (PE)
146048: 10/03/04: Re: Modelsim PE vs. Aldec Active-HDL (PE)
146049: 10/03/04: Re: Actel is now the only FPGA vendor with hard-core processor in the
146094: 10/03/05: Re: FSM in BlockRAM
146117: 10/03/05: Re: Modelsim PE vs. Aldec Active-HDL (PE)
146205: 10/03/08: Re: Modelsim PE vs. Aldec Active-HDL (PE)
146210: 10/03/08: Re: Modelsim PE vs. Aldec Active-HDL (PE)
146235: 10/03/09: Re: Modelsim PE vs. Aldec Active-HDL (PE)
146236: 10/03/09: Re: Modelsim PE vs. Aldec Active-HDL (PE)
146238: 10/03/09: Re: Some Active-HDL questions
146239: 10/03/09: Re: Modelsim PE vs. Aldec Active-HDL (PE)
146338: 10/03/12: Re: how can i add memory
146384: 10/03/15: Re: Tier Logic introduces the world's first 3D FPGA
146538: 10/03/22: Re: Changing Generics in Simulation
146541: 10/03/22: Re: Why doesn't this situation generate a latch?
146605: 10/03/23: Re: Why hardware designers should switch to Eclipse
146965: 10/04/05: Re: Multi-function pins in Spartan-6
147092: 10/04/13: Re: Implementing bidirectional bus inside the FPGA
147145: 10/04/15: Re: Implementing bidirectional bus inside the FPGA
147642: 10/05/11: Re: I'd rather switch than fight!
147683: 10/05/14: Re: Xilinx Synthesis Tool generates clock signals from combinatorial
147684: 10/05/14: Re: problem in clock input in virtexpro/spartan3a/spartan3 kit
147685: 10/05/14: Re: Expecting sequential output, but RTL shows concurrent
147880: 10/05/28: Re: Estimating resource utilization of cores (from Xilinx CoreGen)
147991: 10/06/10: Re: Alternative to Chipscope
148447: 10/07/23: Re: Using std_ulogic at synthesis level
148448: 10/07/23: Re: Dumb VHDL Question -- Type Conversion
148474: 10/07/26: Re: sdram stable clock
148691: 10/08/17: Re: Spartan3a: improving DCM performance and "To achieve optimal
149042: 10/09/23: Re: Virtex6 quote
149415: 10/10/22: Re: Combined Microprocessor and FPGA
150140: 10/12/17: Re: ISIM simulation speed
150179: 10/12/28: Re: Verilog inout, I2C
150814: 11/02/14: Re: Designing in Altium
Andy Peters (@ .):
31964: 01/06/09: Xilinx webpack annoyances (long and whiny)
Andy Peters <andy [@] exponentmedia:
31890: 01/06/07: Re: one state machine
32043: 01/06/12: Re: Xilinx webpack annoyances (long and whiny)
32044: 01/06/12: Re: Xilinx webpack annoyances (long and whiny)
32097: 01/06/13: Re: Xilinx webpack annoyances (long and whiny)
32098: 01/06/13: Re: USB for a new FPGA based product, which transciever ?
32382: 01/06/25: Re: IOB FF in Synplicity
32509: 01/06/28: Re: Synplify register replication
32861: 01/07/10: Re: Online threshold limit counter
33253: 01/07/20: Re: regarding the constraints while writing VHDL code
33255: 01/07/20: Re: Working Design - Anyone
33373: 01/07/24: Re: Xilinx Software free
33404: 01/07/25: Re: FPGA Express or Spectrum?
33450: 01/07/26: Re: Application obstacle course
33556: 01/07/30: Re: Can't Install Modelsim - Alternatives for Verilog Simulation???
33557: 01/07/30: Re: The Continuing Saga of Installing Modelsim software on Windows 2000
33560: 01/07/30: Re: Opinions on cypress warp 6.1 and devices?
33571: 01/07/30: Re: Windows ME and Foundation ISE?
33575: 01/07/30: Re: finite defect statistics
33609: 01/07/31: Re: finite defect statistics
33701: 01/08/02: Re: Spartan II and asynchronous memory interface
33702: 01/08/02: Re: Spartan II and asynchronous memory interface
33704: 01/08/02: Re: Duty cycle problem with Virtex-II
33705: 01/08/02: Re: Building ROM and RAM blocks - Xilinx Foundation Series 3.1i
33706: 01/08/02: Re: spartan & atmel eeproms
33707: 01/08/02: Re: a few xilinx fpga and hdl questions
33769: 01/08/03: Re: 4 (8) bit Microporcessor Implementation
33773: 01/08/03: Re: Duty cycle problem with Virtex-II
33841: 01/08/06: Re: Which is the best Design Toolchain?
33843: 01/08/06: Re: Choosing a verilog synthesis tool (Altera/Xilinx)
33844: 01/08/06: Re: General question on VHDL code
33845: 01/08/06: Re: Slightly off topic - PCs for running FPGA tools
33846: 01/08/06: Re: how to replicate the Logic through VHDL attribut ?
33887: 01/08/07: Re: Which is the best Design Toolchain?
33922: 01/08/08: Re: Which is the best Design Toolchain?
33923: 01/08/08: Re: URL for XILINX's free 314-page design and sythesis guide
33977: 01/08/09: Re: Spartan-II serial configuration problem from ATMEL device
33979: 01/08/09: Re: Install : Administrative privileges in Win2K
34001: 01/08/10: Re: Spartan-II serial configuration problem from ATMEL device
34072: 01/08/13: Re: Keep Xilinx Webpack from removing unused NETs?
34073: 01/08/13: Re: Fast Mux and low power voltage reference
34074: 01/08/13: Re: virtex2 Block Ram: dual port ram with different da
34076: 01/08/13: Re: Slightly off topic - PCs for running FPGA tools
34115: 01/08/14: Re: virtex2 Block Ram: dual port ram with different da
34221: 01/08/16: Re: Virtex-II and 5V devices
34223: 01/08/16: Re: Slowing PCI for FPGA
34224: 01/08/16: Re: Slowing PCI for FPGA
34225: 01/08/16: Re: Building a clock out of a PLD
34367: 01/08/22: Re: FPGA MP3 decoder
34399: 01/08/23: Re: Optical Bay Area Start-up! SW/HW Engs needed
34441: 01/08/24: Re: Principles of Verifiable RTL Design (2nd ed)
34442: 01/08/24: Re: Optical Bay Area Start-up! SW/HW Engs needed
34443: 01/08/24: Re: Reading Text in Verilog
34481: 01/08/27: Re: DRAM burst mode
34609: 01/08/30: Re: Defending Austin Franklin
34630: 01/08/31: Re: Ugly signal output...
34631: 01/08/31: Re: ISA(PC/104) BUS DECODE ASYNC or SYNC?
34632: 01/08/31: Re: timing delay problem
34634: 01/08/31: Re: Jbits: more info required
34635: 01/08/31: Re: FPGA: time_sim.sdf does not have the setup times f
34636: 01/08/31: Re: XC2V3000-4BF957
Andy Pimentel:
19039: 99/11/25: Ph.D. student position: Comp. Arch. Modelling & Simulation (Amsterdam)
Andy Ray:
38437: 02/01/14: Re: Homebrew computers using FPGA?
38439: 02/01/14: Re: variable declare
100268: 06/04/06: Re: Compressing DVI stream
102159: 06/05/11: Re: 64-point complex FFT with 32 bit floating-point representation
103004: 06/05/24: Re: FPGA : P&R problem - Help !
105539: 06/07/25: Re: An idea for a product (FPGA/ASIC based)
105911: 06/08/02: Re: generating sine-like waveforms
105919: 06/08/03: Re: Where are Huffman encoding applications?
105924: 06/08/03: Re: Where are Huffman encoding applications?
107589: 06/08/30: Re: Style of coding complex logic (particularly state machines)
110827: 06/10/24: Re: How to check if ROM got inferred from synth reports
111216: 06/10/31: Re: Dual Port RAM
113176: 06/12/07: Re: RTL Hardware design issue: Count Leading Zeros CLZ
Andy Ross:
139463: 09/03/30: Programming Digilent Nexys 2 from Linux
139508: 09/04/01: Re: Programming Digilent Nexys 2 from Linux
139536: 09/04/02: Re: Programming Digilent Nexys 2 from Linux
139541: 09/04/02: Re: Programming Digilent Nexys 2 from Linux
139745: 09/04/11: Re: Programming Digilent Nexys 2 from Linux
Andy Rushton:
33389: 01/07/25: Re: ModelSim and Cygwin
51199: 03/01/06: Re: Contracting in the UK
Andy Whitehouse:
6186: 97/04/23: Re: ISP CPLD from AMD or Cypress???
9030: 98/02/16: Re: Why altera CPLDS are slow to power-up?
9278: 98/03/05: Re: Analog crossbar switch matrix IC?
Andy Wilkins:
74874: 04/10/20: Chipscope Core Generator:VIO
Andy Wilson:
7433: 97/09/09: wanted: experiences with VCC "HOTworks"
7734: 97/10/08: Re: FPGA multiprocessors => vs. uniprocessors
7787: 97/10/15: FPGA based CPU ideas -> Atmel AT40K??
<andy.mcclelland@tesco.net>:
153545: 12/03/27: Re: FPGA communication with a PC (Windows)
153644: 12/04/09: Re: Watchdog reset for fpga designs
<andy730215@gmail.com>:
133193: 08/06/20: altera technical question?
<andy@hmsi.com>:
12912: 98/11/04: Re: New free FPGA CPU
<andy_ash@my-deja.com>:
19586: 00/01/03: Re: Using internal RAM in Altera Flex 10KE
19876: 00/01/15: Re: HW resources increased
AndyAtHome:
68936: 04/04/22: Best Xilinx toolchains for under $2,000 ?
69014: 04/04/25: Re: Best Xilinx toolchains for under $2,000 ?
69176: 04/04/29: Design development costs for FPGA on PCI board (sorry if slightly off-topic)
71190: 04/07/11: FPGA to PCI Bus Interface
71208: 04/07/12: Re: FPGA to PCI Bus Interface
<andyesquire@hotmail.com>:
78873: 05/02/09: Learning resources for Xilinx memory controllers
81290: 05/03/21: Xilinx ISE 7.1 - Can this get any worse?
83490: 05/05/01: PCI-X target chip with simple backend interface....
83530: 05/05/02: Re: PCI-X target chip with simple backend interface....
83827: 05/05/07: Re: newbie question
andyman:
50113: 02/12/02: Re: Interfacing DSP to PCI bridge using a FPGA
50115: 02/12/02: Re: MetaStability Issue on BRAMs
50728: 02/12/18: Re: MPEG FPGA
Andyman:
60578: 03/09/16: Re: fft size in fpga
62926: 03/11/11: DCM input clock
andyto@gmail.com:
126581: 07/11/27: Behavioral Simulation working but Post-route Simulation is not.
126592: 07/11/28: Re: Behavioral Simulation working but Post-route Simulation is not.
<anesserm>:
114789: 07/01/24: How to make a clock delay?
114797: 07/01/24: Re: How to make a clock delay?
Ang Zhi Ping:
156619: 14/05/14: Undriven outputs of a module in Quartus II Synthesis
156634: 14/05/17: Re: Undriven outputs of a module in Quartus II Synthesis
156637: 14/05/17: Re: Undriven outputs of a module in Quartus II Synthesis
156638: 14/05/17: Re: Undriven outputs of a module in Quartus II Synthesis
156914: 14/07/28: Primitive debuggable UART interface to a Nios within a multi-Nios
156917: 14/07/28: Re: Primitive debuggable UART interface to a Nios within a multi-Nios
156920: 14/07/28: Re: Primitive debuggable UART interface to a Nios within a multi-Nios
156924: 14/07/29: Re: Primitive debuggable UART interface to a Nios within a multi-Nios
156934: 14/07/30: Re: Primitive debuggable UART interface to a Nios within a multi-Nios
Angel:
26256: 00/10/10: Re: 68000 vhdl model
Angel Pino:
38282: 02/01/11: EXPAL language ?
38283: 02/01/11: Re: Core Generator
38318: 02/01/11: Re: EXPAL language ?
38443: 02/01/14: PAL Express Language
Angel Ramiro Manzano:
22816: 00/05/25: PCI core
Angela Macharia:
27361: 00/11/19: Invest $6 get $40,000
27362: 00/11/19: invest $6 get $40,000
Angela O:
148587: 10/08/03: Vendor Tool Stability
<angela@nospam.iwarfare.com>:
10861: 98/06/25: Year 2000 And Information Warfare News Briefs
Angelina Jolie:
<angeloaj@gmail.com>:
115287: 07/02/05: HI guys...about EDK
115340: 07/02/07: EDK and multipleprocessors - Virtex2p
115607: 07/02/14: ppc405_1 and LED in EDK
Angelos:
99859: 06/03/30: USB phy in dev board
angilberto:
86036: 05/06/20: Real Example of Xilinx IPCore Instantiation
86099: 05/06/21: Re: Real Example of Xilinx IPCore Instantiation
Angus:
144689: 09/12/23: Re: domain crossing and clock synchronisation for a high frequency
144698: 09/12/24: Re: Problem with Xilinx ISE and Spartan3
144789: 10/01/02: [Digilab IIE board]Cable autodetection failed
144796: 10/01/04: Re: Cable autodetection failed
144797: 10/01/04: Re: Cable autodetection failed
149551: 10/11/04: combinatorial process not simulating correctly
149557: 10/11/05: Re: combinatorial process not simulating correctly
149558: 10/11/05: Re: combinatorial process not simulating correctly
149559: 10/11/05: Re: combinatorial process not simulating correctly
149570: 10/11/05: Re: combinatorial process not simulating correctly
Angus Bryant:
49941: 02/11/26: XC5210 sourcing
Angus Thompson:
43489: 02/05/22: Routing in a 6200-like sea of gates
Aniket:
69823: 04/05/20: Xilinx hypertransport lite reference design.
Aniket Naik:
69692: 04/05/18: Malfunctioning dual port block ram.
anil:
80354: 05/03/04: problem using Modelsim Mxe3
80435: 05/03/05: Re: Planning to Build Complex Wireless SoC...Anybody interested??
80437: 05/03/05: Re: Planning to Build Complex Wireless SoC...Anybody interested??
86312: 05/06/24: doubt regarding code generator
88055: 05/08/08: Re: ModelSim Error
106311: 06/08/11: Invoking Cadence NC Sim within Xilinx ISE
114914: 07/01/26: Inferring Xilinx RAM's with Byte enable options
Anil:
32988: 01/07/14: Re: FPGA Express search path
68635: 04/04/11: Algorithm for delay testing
ANIL CELEBI:
115993: 07/02/27: ISE:Simulation
Anil Khanna:
59523: 03/08/20: Re: performance tweaking FPGA designs
59652: 03/08/25: Re: TIG Constraint
59655: 03/08/25: Re: Enhancing PAR with FPGA floorplanners
60234: 03/09/08: Re: New to FPGA, seeking advice
62073: 03/10/17: Signed Multiplication in a Virtex-II Multiplier.
62074: 03/10/17: Re: XST Timing report
62097: 03/10/19: Re: Signed Multiplication in a Virtex-II Multiplier.
62217: 03/10/22: Re: Signed Multiplication in a Virtex-II Multiplier.
62278: 03/10/23: Re: Timing analysis
62531: 03/10/31: Re: Xilinx XC95108 Chip
62724: 03/11/05: Infer DDR registers from RTL?
64079: 03/12/15: Re: Latches inferred ?
64081: 03/12/15: Re: Finding Multicyle Paths in a Design
68076: 04/03/25: Standard way of applying timing constraints in ISE?
69551: 04/05/13: Using a FDDRCPE primitive. VIRTEX-II
Anil T.L.N.:
7278: 97/08/21: Re: LogiBLOX components in VHDL?
9018: 98/02/14: Re: Walace tree???
anilcelebi:
130411: 08/03/22: High speed memory read and transfer via rocket IO..
130418: 08/03/23: Re: High speed memory read and transfer via rocket IO..
130419: 08/03/23: Re: High speed memory read and transfer via rocket IO..
130429: 08/03/23: Re: High speed memory read and transfer via rocket IO..
130685: 08/03/30: System Generator Error
<anilcelebi@gmail.com>:
123427: 07/08/28: VHDL clocking scheme VS Verilog clocking scheme
<anilmohan@hotmail.com>:
9527: 98/03/21: smart card OS
<aniruddha.nag@gmail.com>:
116942: 07/03/21: Re: Systemverilog preprocessor allow "..."?
anish:
41281: 02/03/24: question on LFSR
Anita Schreiber:
64037: 03/12/12: Re: 16-bit sdram and 32-bit opb bus
64038: 03/12/12: Re: byte order microblaze
Anjan:
43236: 02/05/16: interfacing dspand fpga
45519: 02/07/25: hold time
45551: 02/07/25: Re: Problem with mapping
45571: 02/07/26: Re: hold time
45718: 02/08/01: timing with load
45970: 02/08/12: capacitance
46229: 02/08/22: X on bus
46258: 02/08/22: Re: X on bus
46442: 02/08/29: tristate bus
46788: 02/09/08: X on bus
46897: 02/09/10: problem with tri state bus
53692: 03/03/19: Re: fpga implementation problems
61567: 03/10/06: ise 5.2 sp 3 for spartan 3
61807: 03/10/12: finding delay
62782: 03/11/07: spartan 3 queries
62849: 03/11/10: Re: ISE 5.2 to 6.1
64574: 04/01/07: spartan 3 sample
65271: 04/01/22: Re: Xilinx Spartan3 Timing Problems - Whats about the chips
67836: 04/03/20: Xilinx timing analyzer
Anjanette Gautier:
31776: 01/06/05: CMOS Analog Director of IC Design -Seattle
32083: 01/06/13: CMOS Analog Director of IC Design -Seattle
32116: 01/06/14: Hardware FPGA Eng. for Optical Net Co in Dallas
Ankit:
120808: 07/06/17: How to simulate testbenches using the ISE simulator in linux
120858: 07/06/19: Re: How to simulate testbenches using the ISE simulator in linux
120883: 07/06/19: Re: How to simulate testbenches using the ISE simulator in linux
120931: 07/06/20: Re: How to simulate testbenches using the ISE simulator in linux
120983: 07/06/21: Re: How to simulate testbenches using the ISE simulator in linux
121018: 07/06/22: Re: How to simulate testbenches using the ISE simulator in linux
124452: 07/09/22: Configuring Impact on any version of linux
130920: 08/04/04: Project Ideas
132507: 08/05/29: RGB video panel
Ankit Raizada:
82308: 05/04/10: Shared bus on FPGA
82309: 05/04/10: Re: Shared bus on FPGA
82472: 05/04/13: Simulation and actual FPGA implementation, how different it is?
84828: 05/05/29: Re: VHDL vs. Schematic Capture
Ankit Shah:
11876: 98/09/15: NEED: ideas on small project
ankur:
123091: 07/08/16: synthesis showing warning (replicated 1 time(s) to handle iob=true attribute.)
123092: 07/08/16: synthesis showing warning (replicated 1 time(s) to handle iob=true attribute.)
123804: 07/09/05: warning 1780 shown while synthesis, in xilinx 6.3i
<ankur101@gmail.com>:
101633: 06/05/03: Voltage Regulator on the XSA-50 board
ankyag:
108402: 06/09/10: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
108409: 06/09/10: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
<anl@completebbs.com>:
17365: 99/07/22: tiles-rus 8405
ann:
81677: 05/03/29: Re: hook up SRAM to Spartan3
110220: 06/10/12: power up delay in fpga
Ann:
51470: 03/01/14: Virtex, Virtex II and Virtex II Pro
78563: 05/02/03: Help on a FPGA design
78570: 05/02/03: Re: Help on a FPGA design
78576: 05/02/03: Re: Help on a FPGA design
78580: 05/02/03: Re: Help on a FPGA design
78581: 05/02/03: Re: Help on a FPGA design
78582: 05/02/03: Re: Help on a FPGA design
78620: 05/02/04: Re: Help on a FPGA design
79412: 05/02/18: Re: Make program stop
81668: 05/03/29: hook up SRAM to Spartan3
81744: 05/03/30: Instantiate RAM in Spartan3
81785: 05/03/31: Enable/Disable BSCAN_SPARTAN3
81854: 05/04/02: RAMB16_S9
81919: 05/04/04: Re: RAMB16_S9
81941: 05/04/04: Re: RAMB16_S9
81969: 05/04/05: Re: RAMB16_S9
81975: 05/04/05: Re: RAMB16_S9
82004: 05/04/05: Re: RAMB16_S9
82012: 05/04/05: Re: RAMB16_S9
128065: 08/01/14: Complex Multiply
128154: 08/01/16: Re: Complex Multiply
128424: 08/01/25: Re: Random Number Generation in VHDL
Anna Acevedo:
13698: 98/12/18: Re: VHDL books (seeking)
14338: 99/01/26: Re: Foundation V3.1 VHDL synthesis
17561: 99/08/10: Re: Newbie - what are the limitations of the student edition
22520: 00/05/10: Re: appropriate ASIC Prototyping Board
23776: 00/07/07: Re: FPGA Express/Foundation Error 470
23921: 00/07/14: Re: Silicon Valley Housing Nightmare?
24009: 00/07/20: Re: New Xilinx Student Edition
24940: 00/08/22: Re: Looks like Xilinx is at it again!
24902: 00/08/21: Re: Looks like Xilinx is at it again!
25900: 00/09/25: Re: Xilinx Student Edition 2.1i with "Digital Design:Principles and
27270: 00/11/16: Re: Xilinx Foundation Sudent Version 1.5
29175: 01/02/08: Re: Xilinx 4010E development kit
31942: 01/06/08: Pak & Donald
33115: 01/07/17: Re: I NEED XILINX FOUNDATION PROFESSIONAL
42008: 02/04/12: Re: FPGA eval/dev boards with *serial* interface?
44371: 02/06/18: Re: Pls Recommend a Xilinx development Board
44973: 02/07/08: Re: Xilinix or Altera - which dev-board?
65123: 04/01/20: Re: Good/Affordable Stater kits
69410: 04/05/10: Re: Which board to buy? Status of open source tools?
71232: 04/07/12: Re: Xilinx Student Edition 4.2i
Anna Schmitt:
20166: 00/01/29: picoJava & Xilinx
AnnapMicro:
2620: 96/01/12: Job Openings - Reconfigurable Computing
Annapolis Micro Systems, Inc.:
5090: 97/01/22: Annapolis
Anne:
116817: 07/03/19: QuickSilver's ACM architecture
117846: 07/04/11: POC at Element CXI
119302: 07/05/16: seeking insights for potential reconfigurable computing application platforms
119377: 07/05/17: Re: seeking insights for potential reconfigurable computing application platforms
anne:
148516: 10/07/29: USB3.0 device detection
Anne & Lynn Wheeler:
82256: 05/04/09: Re: ISA vs. patent/trademark
145363: 10/02/06: Re: using an FPGA to emulate a vintage computer
145377: 10/02/07: Re: using an FPGA to emulate a vintage computer
146115: 10/03/05: Re: using an FPGA to emulate a vintage computer
Anne Greene:
3701: 96/07/17: request for inclusion
Annette Van Benthum:
38485: 02/01/15: Flexbus and Altera
Anno:
32841: 01/07/10: FPGA on flex?
annoob:
20511: 00/02/12: [NEED HELP] Carry Select Adder?
Anom:
74969: 04/10/22: Looking for FPGA design services in India or similar
anon:
44777: 02/06/30: Re: XESS / Digilent / Trenz Board Experience ? Help.
44778: 02/06/30: Xilinx Virtex2-Pro: availability?
70554: 04/06/20: Atmel / Synplicity built-in macros
Anon:
41573: 02/04/02: Marquis of Queensbury Rules
Anon675301:
158594: 16/01/18: Re: remove Xilinx webtalk
158595: 16/01/18: Re: remove Xilinx webtalk
anon7864:
36375: 01/11/07: Quadrature Encoder Sampling Time
anony:
81493: 05/03/25: When will outsourcing hit FPGA'ers?
Anonyma:
111433: 06/11/02: digilent spartan-3 board sram timing
Anonymous:
9452: 98/03/14: Xilinx XACT 6.01 crack
9458: 98/03/15: Xilinx XACT 6.01 crack
9613: 98/03/26: XactStep6 - The cure for a dongle
13347: 98/11/29: Will XILINX survive?
32104: 01/06/13: Re: Xilinx webpack annoyances (long and whiny)
47541: 02/09/28: Ignore me - just a test
75602: 04/11/10: Re: FPGA configuration download - How is it done?
95677: 06/01/25: Re: dma on fpga pci card
94411: 06/01/11: best evm for virtex-4 and linux
94434: 06/01/11: Re: best evm for virtex-4 and linux
94520: 06/01/13: Re: best evm for virtex-4 and linux
94541: 06/01/13: Re: best evm for virtex-4 and linux
94745: 06/01/17: Re: best evm for virtex-4 and linux
94504: 06/01/12: Re: FPGA Journal Article
95674: 06/01/25: Re: porting linux on ml403
96293: 06/02/01: xilinx linux source?
96357: 06/02/02: Re: xilinx linux source?
96362: 06/02/02: Re: xilinx linux source?
96483: 06/02/04: multi-processor linux on xilinx
96496: 06/02/05: Re: multi-processor linux on xilinx
96506: 06/02/05: usb gadgets and xilinx
96536: 06/02/06: Re: porting linux on ml403
96540: 06/02/06: Re: usb gadgets and xilinx
96572: 06/02/06: Re: Software Defined Radio Transmitter Demo Board
96653: 06/02/08: Re: Software Defined Radio Transmitter Demo Board
97280: 06/02/20: Re: Cheating at homework (from "Re: FPGA - software or hardware?")
97887: 06/03/01: Re: PPC Linux SoC on Virtex4 in 4 hours !?
98053: 06/03/03: Re: why use an FPGA when a CPLD will do ??
99450: 06/03/24: linux on memec fx12 mini-module?
99606: 06/03/27: Re: Problem with LwIP and MicroBlaze
99607: 06/03/27: Re: Linux on ml403
99942: 06/03/31: Re: USB Interface to Virtex-4
100033: 06/04/01: Re: USB Interface to Virtex-4
100225: 06/04/05: Re: EDK7.1 - error in Libgen for Linux OS - Xilinx ML300 board
100291: 06/04/06: Re: USB Interface to Virtex-4
100323: 06/04/06: Re: USB Interface to Virtex-4
100379: 06/04/07: Re: USB Interface to Virtex-4
100495: 06/04/10: Re: NTSC video capture
101887: 06/05/08: Re: Strange power up issue on Virtex4
102010: 06/05/09: ml-403 and USB
102852: 06/05/22: xilinx pricing discrepancy
102869: 06/05/22: Re: xilinx pricing discrepancy
102935: 06/05/23: .hex or .svf file from Mediatronix picoBlaze IDE
103035: 06/05/24: Re: xilinx pricing discrepancy
103069: 06/05/25: Re: xilinx pricing discrepancy
104672: 06/07/03: PPC and Chipscope?
104708: 06/07/04: single pad to pad timing in ISE
104709: 06/07/04: Re: single pad to pad timing in ISE
104732: 06/07/05: Re: PPC and Chipscope?
105062: 06/07/12: reprogram xcf08 serial prom without jtag
105658: 06/07/28: Re: OT (2nd try): do you get paid for your travel time?
107588: 06/08/30: fx12 v fx20 static power?
107927: 06/09/02: linux 2.4 v 2.6 on xilinx
108572: 06/09/13: removing Ethernet_MAC kills mini-module project
108641: 06/09/14: Re: removing Ethernet_MAC kills mini-module project
109103: 06/09/20: MV4.0.1 and Avnet Mini-Module
109192: 06/09/21: Re: Dell Laptop for Embedded Work
109822: 06/10/05: Re: a clueless bloke tells Xilinx to get a move on
110247: 06/10/12: Re: VirTex 4 mini Module
110342: 06/10/13: Re: Xilinx FPGAs in battery-powered scenarios
110472: 06/10/16: Re: WiFi signal repeater using any virtix fpga
110580: 06/10/18: Re: New IP with EDK : how connect external NET ?
110617: 06/10/18: Re: Executing PPC code from external flash memory
111799: 06/11/10: Why 64-bit PLB?
111802: 06/11/10: Re: Why 64-bit PLB?
111810: 06/11/10: Re: Why 64-bit PLB?
111955: 06/11/13: Re: Virtex-4 : OCM
112013: 06/11/14: Re: Why 64-bit PLB?
112015: 06/11/14: DSP Library for PPC405?
112706: 06/11/27: opb master kills linux?
112879: 06/11/30: Re: opb master kills linux?
113269: 06/12/10: impossible opb_emc hack?
113281: 06/12/10: Re: impossible opb_emc hack?
113329: 06/12/11: Re: ISR Routine:Copying application in RAM and jumping in it ISR(s) don't start !(?)
113330: 06/12/11: Re: impossible opb_emc hack?
113380: 06/12/12: Re: ISR Routine:Copying application in RAM and jumping in it ISR(s) don't start !(?)
161393: 19/06/28: HOW TO READ A 64 BIT REGISTER IN 2 CLOCK CYCLES IN VERILOG
anonymous:
19242: 99/12/08: Is there two-read one-write asynchronous SRAM in FPGA?
45824: 02/08/06: fpga - pc
anonymous anonymous:
141942: 09/07/18: Re: FPGA editor in Fedora 11 x86_64
141945: 09/07/18: Re: FPGA editor in Fedora 11 x86_64
Anonymous Idiot:
30690: 01/04/23: Re: Any good sources for digital rf processing ?
30770: 01/04/27: Re: Input Pins and Synthesis
30771: 01/04/27: Re: C++ To Gates
30772: 01/04/27: Re: BlockRAM outputs and the Placer
30907: 01/05/02: FPGA application survey question
30937: 01/05/03: Re: FPGA application survey question
30938: 01/05/03: Re: FPGA based PCI cards
Anonymous via the Cypherpunks Tonga Remailer:
109139: 06/09/21: DCM and domain crossing
Anonymous4:
49395: 02/11/11: HDL vs RTL
49582: 02/11/15: DLL again :-)
49598: 02/11/16: Virtex is the 4th Xilinx Fpga generation
50900: 02/12/22: incomplete MNM specification???? timing not working
50901: 02/12/22: following to my previous email
51049: 02/12/28: VCC,GND with the new version of tool
51523: 03/01/15: implementation of a switcher
<anonymous@nowhere.you.know>:
121730: 07/07/12: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
AnonymousFC3:
75667: 04/11/11: Re: asynchronous bus transfers
84647: 05/05/23: QUARTUS on Linux.
AnonymousFC4:
100976: 06/04/21: Re: Microblaze & Linux tools. (repost)
100983: 06/04/22: Re: Microblaze & Linux tools. (repost)
100986: 06/04/22: Re: Microblaze & Linux tools. (repost)
Anoop Nannra:
21722: 00/03/30: 10 gbit/s input
25883: 00/09/25: 20 bit to 64 bit bus conversion
anoopjoseph:
142024: 09/07/22: ISERDES behaviour
<anoriaki@comp.ufscar.br>:
20079: 00/01/26: FPGA's reconfigurable modes
20248: 00/02/02: FPGA x DPGA x TSFPGA
<another_bbrekke@my-deja.com>:
20416: 00/02/09: Using Xilinx Serial EEPROMs
anotherUserName:
143126: 09/09/22: Altera logic programmer card (PLP6) problem
Ansgar Bambynek:
14191: 99/01/19: Re: Synthesis tools for Xilinx FPGAs
17897: 99/09/16: Re: xilinx v2.1i
28403: 01/01/11: Re: How to do simulation on Synopsys FPGA Express
34904: 01/09/13: Re: Using Synopsys Design Compiler to target Virtex-E FPGA
38409: 02/01/14: Re: .sdf question
40168: 02/03/01: Re: Synopsys Design Compiler
44628: 02/06/25: Re: FPGA to ASIC migration
48654: 02/10/22: Re: slow slew rate signal...
49855: 02/11/22: Re: Problems with simulation after synthesis
56884: 03/06/18: Re: FPGA to Custom ASIC ??
59053: 03/08/07: Re: Error Generate Statement
78204: 05/01/26: Re: Spartan III place fails
79028: 05/02/11: Re: second flop in asyn reset distribution
79697: 05/02/23: Re: How to select the architecture for synthesis?
Anshat:
93410: 05/12/21: lpc922
Anshuman Sharma:
21397: 00/03/21: FPGA related projects
21705: 00/03/29: VGA interface and VHDL
21760: 00/03/30: Adrian Thompson's and GA work on Xilinx
21893: 00/04/06: JBits
21923: 00/04/07: EHW
27028: 00/11/08: PLL vs DLL
ansiaviva:
98664: 06/03/14: Re: Manchester II encoder-decoder
Anson Ng:
84605: 05/05/22: Re: xilinx virtex 4 download cable
<Anson.Stuggart@gmail.com>:
118531: 07/04/29: debounce state diagram FSM
118538: 07/04/29: Re: debounce state diagram FSM
118551: 07/04/29: Re: debounce state diagram FSM
118557: 07/04/29: Re: debounce state diagram FSM
119471: 07/05/21: UART Receiver Parity Check
Anssi Saari:
143764: 09/10/24: Re: CPLD/FPGA with Linux
144083: 09/11/10: Re: How to script Xilinx ISE - xflow, batch file, tcl, ?
144914: 10/01/14: Re: Solved! Why my pins were being optimized out. How do I get the
144931: 10/01/16: Re: SystemVerilog Verification Example using Quartus and ModelSim
144939: 10/01/16: Re: Altera Quartus II on Debian GNU/Linux
144941: 10/01/16: Re: Altera Quartus II on Debian GNU/Linux
144962: 10/01/18: Re: Altera Quartus II on Debian GNU/Linux
144963: 10/01/18: Re: Altera Quartus II on Debian GNU/Linux
145175: 10/01/30: Re: In system memory editor of Altera for Xilinx
145235: 10/02/02: Re: What MAXIM chip is used on Spartan 3E 1600E Microblaze Board
145239: 10/02/03: Re: What MAXIM chip is used on Spartan 3E 1600E Microblaze Board
145725: 10/02/21: Re: BRAM16 error
145748: 10/02/22: Re: Quartus II IDE freezing on Arch 64
146110: 10/03/05: Re: Is an inout reg allowed
146222: 10/03/09: Re: using an FPGA to emulate a vintage computer
146964: 10/04/05: Re: Modelsim PE vs. Aldec Active-HDL (PE)
147040: 10/04/11: Re: Quartus: rpm: Command not found.
147066: 10/04/12: Re: Spartan 3 Starter Kit Example
147274: 10/04/21: Re: Xilinx no longer ships with Modelsim MXE?
147974: 10/06/09: Re: How to Disable IP Core after Evaluation Period
148081: 10/06/19: Re: Difficulty with Xilinx FPGA configuration using Platform Flash
148200: 10/06/27: Re: Free bitmap font
148321: 10/07/07: Re: FPGA Video processing board (HDMI).. who makes one?
148368: 10/07/15: Re: Another Xilinx webpack download rant
148719: 10/08/18: Re: Getting started with FPGA
148720: 10/08/18: Re: SDK example from Xilinx do not compile
149128: 10/10/04: Re: External Circuit to FPGA.
149348: 10/10/18: Re: Combined Microprocessor and FPGA
149350: 10/10/18: Re: Newbie question IO pin and Spartan6
149675: 10/11/16: Re: Good Dev Board
150418: 11/01/19: Re: Verilog Book for VHDL Users
150439: 11/01/21: Re: Verilog Book for VHDL Users
151282: 11/03/20: Re: Alternative To Altera's Cyclone III Starter Board
151673: 11/05/04: Re: Lattice Breakout Boards
152791: 11/10/23: Re: FPGA development
153468: 12/03/04: Re: configuring an Altera Cyclone 3
153766: 12/05/16: Re: Synthesis Problem
153792: 12/05/22: Re: Xilinx ISE Multiple Drivers Error
154989: 13/03/21: Re: Using Quartus II without GUI
155180: 13/05/23: Re: Development/Experimenter's kits
155432: 13/06/28: Re: FPGA Exchange
155552: 13/07/18: Re: Xilinx "Ultrascale" announcement leaves out low-cost devices
155582: 13/07/23: Re: Xilinx "Ultrascale" announcement leaves out low-cost devices
155674: 13/08/02: Re: Lattice Announces EOL for XP and EC/P Product Lines
155676: 13/08/02: Re: NiosII 8.0 make error Windows XP
155784: 13/09/04: Re: Actel Designer Warning: CMP201: Net drives no load
155787: 13/09/04: Re: Actel Designer Warning: CMP201: Net drives no load
157806: 15/03/31: Re: Intel in Talks to buy Altera
157810: 15/03/31: Re: Intel in Talks to buy Altera
157963: 15/06/05: Re: Free timing diagram drawing software
158217: 15/09/18: Re: low-level vs. high-level
159043: 16/07/06: Re: need some help with altera quartus
159380: 16/10/18: Re: Microsoft's FPGA Translates Wikipedia in less than a Tenth of a Second
159572: 17/01/02: Re: Slightly OT: Digital watch circuits
159638: 17/01/25: Re: VHDL Editors (esp. V3S)
159656: 17/01/26: Re: VHDL Editors (esp. V3S)
160573: 18/04/17: Re: FPGA selection recommendation
160710: 18/10/23: Re: FPGA Market Entry Barriers
161096: 19/02/01: Re: ARM + FPGA CPU Module running Yocto Linux?
161198: 19/03/13: Re: Anyone have files from the old Xilinx FTP?
161310: 19/03/27: Re: High-level synthesis
161319: 19/03/28: Re: Replaceme EPROM by CPLD/FPGA
161330: 19/03/29: Re: High-level synthesis
161340: 19/04/01: Re: High-level synthesis
161665: 20/02/19: Re: Code block in icestudio
161670: 20/02/21: Re: Code block in icestudio
161703: 20/05/07: Re: fixed point modeling tools
161705: 20/05/08: Re: fixed point modeling tools
ant:
17398: 99/07/24: How to get Foundation synthesis result(gate level layout)?
Anthony:
6235: 97/05/01: Viewlogic- PUSH VHDL
6291: 97/05/09: VHDL/FPGA Development
105879: 06/08/02: ISE8.2 + .ngo file + Leonardo
105929: 06/08/02: Re: ISE8.2 + .ngo file + Leonardo
Anthony C:
26778: 00/10/28: Re: Xilinx Spartan2 and VirtexE availability
26963: 00/11/06: Re: Spartan2 prototype boards
Anthony Collins:
91207: 05/11/01: Re: Virtex4 temperature-sensing feature... does it work?
Anthony Dozier:
5217: 97/01/31: US-GA-ATL- ASIC DESIGN ENGINEER
5298: 97/02/05: US-GA-ATL- ASIC DESIGN ENGINEER
5357: 97/02/10: US-GA-ATL- ASIC DESIGN ENGINEER
Anthony Ellis:
5868: 97/03/21: What tools for $8000?
30569: 01/04/17: Using BGA's
30840: 01/05/01: Renoir -> HDL designer?
31596: 01/05/31: PowerPC?
31814: 01/06/06: Re: PowerPC?
32415: 01/06/26: Re: Alpha Particle
33270: 01/07/21: Soldering Ceramic BGA's
38212: 02/01/09: ADPCM?
42604: 02/04/29: Xilinx-Synplicity-License issue?
42882: 02/05/06: PCI-32/Spartan II Pin Outs?
44406: 02/06/19: Xilinx/Simprims & Modelsim
44441: 02/06/20: How to get Unisims netlist?
44481: 02/06/21: Re: How to get Unisims netlist?
45022: 02/07/10: XST and Bidirectional I/O ports
45178: 02/07/15: Re: XST and Bidirectional I/O ports
45179: 02/07/15: How to add BUFG to an internal signal?
45192: 02/07/15: Re: How to add BUFG to an internal signal?
57140: 03/06/24: Microblaze : Modelsim errors
82048: 05/04/06: Spartan II/E Configuration readback
91451: 05/11/07: PCI test bench
91512: 05/11/07: PC Core AD(x) I/O Enable?
91515: 05/11/07: Re: PC Core AD(x) I/O Enable?
91568: 05/11/08: Re: PC Core AD(x) I/O Enable?
Anthony Ellis - LogicWorks:
13189: 98/11/19: VHDL Block Capture
14770: 99/02/16: Flex6016 config. problem.
15584: 99/04/01: Re: Schematic Capture & FPGA synthesis
15866: 99/04/17: Re: Altera 10K and High Density FLASH Memory
16761: 99/06/07: Any free timing diagram tools?
16882: 99/06/16: Altera/Synplicity TIMESTAMP?
16899: 99/06/16: Re: Altera/Synplicity TIMESTAMP?
17307: 99/07/20: What happened to Esprimo?
17436: 99/07/28: Re: Microcomputer buses for use inside FPGA/ASIC devices?
17453: 99/07/29: Re: Microcomputer buses for use inside FPGA/ASIC devices?
17759: 99/09/01: Re: Feasibility of 200 MHz, 12K design on FPGA
18394: 99/10/22: Re: Best FPGA for PCI ?
18919: 99/11/22: PADS Experience?
19953: 00/01/20: WebFitter???
19954: 00/01/20: Re: looping FIFO?
19984: 00/01/21: Re: Biphase mark decoder
19985: 00/01/21: Re: Biphase mark decoder
20228: 00/02/01: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
22462: 00/05/09: Spartan II
22463: 00/05/09: Spartan II support with Foundation Base Express
22464: 00/05/09: Spartan II support with Foundation Base Express
27335: 00/11/18: Altera 768 x 16 RAM?
28290: 01/01/05: WebPack-ISE .ucf problem?
Anthony Fremont:
79965: 05/02/27: Re: I2C protocol to communicate between FPGAs
79984: 05/02/28: Re: I2C protocol to communicate between FPGAs
80009: 05/02/28: Re: I2C protocol to communicate between FPGAs
80010: 05/02/28: Re: I2C protocol to communicate between FPGAs
135417: 08/10/01: Re: $99 XMOS Dev kit
135450: 08/10/02: Re: $99 XMOS Dev kit
Anthony J Bybell:
39246: 02/02/04: Re: solutions manuals, and no they are not for school
39514: 02/02/12: Re: solutions manuals, and no they are not for school
52142: 03/02/02: Re: Static Timing Analysis
61028: 03/09/26: Re: Synchronous Binary counter question.
Anthony M:
111488: 06/11/03: EDK Modelsim Simulation with RS232 Hook
Anthony Mahar:
82230: 05/04/08: ISE/Impact 7.1 Linux Driver problems
82237: 05/04/09: Re: ISE/Impact 7.1 Linux Driver problems
82510: 05/04/13: PPC405 Performance Monitoring
82535: 05/04/13: Re: PPC405 Performance Monitoring
82537: 05/04/13: Re: PPC405 Performance Monitoring
82573: 05/04/14: Re: PPC405 Performance Monitoring
Anthony Marchini:
6763: 97/06/25: Intel PLD programmer
8225: 97/12/01: Re: FPGAs for hobbyist, HELP
Anthony Quigley:
18217: 99/10/08: UK or Europe Des. Engs for California jobs
Anthony Rowe:
23034: 00/06/09: Fast Fourier Transform Processors
anthony staiti jr:
8963: 98/02/09: FPGA resource available
8964: 98/02/09: FPGA resource available
Anthony Stansfield:
2983: 96/03/08: Re: Reconfigurable Computing Languages
3151: 96/04/15: Re: FPGA->ASIC conversion
Anthony Tekatch:
25266: 00/09/03: XC3000A Configuration data
25274: 00/09/04: Re: XC3000A Configuration data
25280: 00/09/04: Re: XC3000A Configuration data
Antoine Lecerf:
10076: 98/04/25: Make a delay in Xilinx FPGAs (Help)?
10083: 98/04/26: Make a delay in Xilinx FPGAs (more Details)?
10104: 98/04/27: Re: Make a delay in Xilinx FPGAs (more Details)?
<antoine.vernay@gmail.com>:
120421: 07/06/06: FPGA / Virtex II Pro / LWIP
120478: 07/06/07: Re: FPGA / Virtex II Pro / LWIP
122914: 07/08/10: Xilinx Xilfatfs SystemACE library and partition format
Anton:
Anton Dischner:
913: 95/03/29: Re: Opinions on IBM PowerPC for Electronics CAD lab
Anton Erasmus:
18671: 99/11/06: Frequency Division in Altera AHDL ?
22155: 00/04/27: Verilog Compiler ?
43972: 02/06/07: Doing Trig Functions in FPGA, EPLD
44953: 02/07/08: Re: Communication between FPGA and PC
45107: 02/07/12: Re: Communication between FPGA and PC
78350: 05/01/30: Re: Cheap source for GAL's
78353: 05/01/30: Re: Using LM317S adjustable linear regulator for Spartan 3?
85861: 05/06/17: Re: Idea exploration - Image stabilization by means of software.
85961: 05/06/19: Re: Idea exploration - Image stabilization by means of software.
86011: 05/06/20: Re: Idea exploration - Image stabilization by means of software.
87112: 05/07/15: Re: Block Diagram Viewer / Hierarchy Parser for VHDL/Verilog?
89761: 05/09/25: Re: Getting started VHDL, VHDL for Dummies, Easy Steps for FPGA experiments
93555: 05/12/24: Re: RTL for Z8000 series CPU?
121931: 07/07/15: Re: highly-parallel highspeed connection between two FPGA boards
127091: 07/12/11: Re: PCI Parallel port card for JTAG / programming?
135778: 08/10/15: Re: XMOS XC-1 kits are shipping
Anton Ertl:
82183: 05/04/08: unaligned loads (was: ISA vs. patent/trademark)
Anton Kowalski:
126680: 07/11/29: EDK IPIF development workflow
Anton Scherer:
3737: 96/07/23: altera -> xilinx
Anton Zechner:
35908: 01/10/23: comp.arch.fpg : Reconfiguring of a virtex via JTAG
<antonin@my-deja.com>:
22219: 00/05/02: Re: maxplus2 lpm in renoir
Antonio:
32248: 01/06/21: Two's Complement conversion for FIR coefficients
32249: 01/06/21: Xilinx Software free
32725: 01/07/05: Core Generator IQ NCO
32821: 01/07/09: Two's complement to binary translation problem
32891: 01/07/11: Need to speed up VHDL accumulator on Xilinx
33031: 01/07/15: Polyphase filter question
33033: 01/07/16: DDS Xilinx Core
33077: 01/07/17: Re: I NEED XILINX FOUNDATION PROFESSIONAL
33086: 01/07/17: Interpolating Filter question
33246: 01/07/20: Modulator Sizing Questions
33347: 01/07/23: Again some question on a QPSK modulator
33544: 01/07/30: Re: Modulator Sizing Questions
33814: 01/08/06: Cordic NCO questions
33815: 01/08/06: General question on VHDL code
33820: 01/08/06: Polyphase and VHDL questions
33867: 01/08/06: What to do if a constrain is not met ???
33872: 01/08/07: Re: Polyphase and VHDL questions
33875: 01/08/07: Re: Cordic NCO questions
33940: 01/08/08: Re: Cordic NCO questions
33942: 01/08/08: Re: What to do if a constrain is not met ???
33943: 01/08/08: Map report question
34471: 01/08/27: Polyphase adjustment to keep it working
34842: 01/09/10: QPSK modulator with no multipliers
35018: 01/09/18: Re: QPSK modulator with no multipliers
35047: 01/09/19: Re: QPSK modulator with no multipliers
35048: 01/09/19: SquareRootRaisedCosine filter design
35145: 01/09/24: Coefficient scaling question
35381: 01/10/02: QPSK BER QUESTION
36087: 01/10/28: Re: Coefficient storing in VHDL
36791: 01/11/19: Synplify use question
36917: 01/11/25: Some question on Synplify
36947: 01/11/27: Re: Some question on Synplify
37002: 01/11/28: Need a Revision man for my project
37108: 01/11/30: Synplify and clk discovery
37109: 01/11/30: Re: Some question on Synplify
37178: 01/12/02: Synplify 7 and Xilinx 4.1 Pair
37179: 01/12/02: Multicycle Synplify question
37540: 01/12/13: The speedest FPGA
37629: 01/12/17: Hardware FPGA questions
37713: 01/12/19: clk_dll general question
37714: 01/12/19: Clocks and Synplify
37849: 01/12/21: Re: Michelangelo's Counter
38050: 02/01/02: Large ROM question
38074: 02/01/03: conv_integer problem ???
38145: 02/01/07: Synplify and Xilinx clock discovery
38214: 02/01/09: Re: ROM synthesis question
38404: 02/01/14: CLKDLL cascade questions
38406: 02/01/14: .sdf question
38417: 02/01/14: Some Aldec Questions
38506: 02/01/15: A strange Xilinx 4.1 parser error
38507: 02/01/15: Xilinx 4.1 Implementation report questions
38508: 02/01/15: Xilinx Timing report question
38899: 02/01/27: negative offset warning message
38901: 02/01/27: String manipulation in VHDL question
38902: 02/01/27: Problem with type definition
38920: 02/01/28: Architectural question regarding ROM and RAM
38922: 02/01/28: Re: negative offset warning message
38975: 02/01/29: Memory Question on Virtex
39018: 02/01/29: MUX with or without clk ??
39019: 02/01/29: ROM dimension question
39020: 02/01/29: Signal assignment mismatch with Aldec 5.1 problem
39021: 02/01/30: Re: Memory Question on Virtex
39075: 02/01/30: Re: Memory Question on Virtex
39195: 02/02/03: MUX seelction question
39196: 02/02/03: ClkEnable vs gated clock
39197: 02/02/03: RAM question
39251: 02/02/04: Re: MUX seelction question
39279: 02/02/05: Re: FPGA vs GAL : Lattice
39325: 02/02/06: CLKDLL x4 problem
39348: 02/02/06: Re: CLKDLL x4 problem
39371: 02/02/07: Ptractical polyphase filter question
39394: 02/02/07: Re: CLKDLL x4 problem
39548: 02/02/12: RAM CORE settings for maximum speed
39595: 02/02/13: Re: RAM CORE settings for maximum speed
39644: 02/02/14: RAM CORE result that I did not understand
39645: 02/02/14: Some doubts on FIFO CORE v.4.0
39730: 02/02/17: Edge selection with RAM
39731: 02/02/17: Some problem initializing a RAMB4S1
39813: 02/02/20: Re: Some problem initializing a RAMB4S1
39849: 02/02/21: Re: Some problem initializing a RAMB4S1
39925: 02/02/21: QPRO questions
40014: 02/02/24: Re: RAM question
40015: 02/02/25: Floorplanner and then ??
40016: 02/02/25: Synplify warning that I don't understand
40033: 02/02/25: Re: RAM question
40061: 02/02/25: Re: RAM question
40069: 02/02/26: Re: RAM question
40091: 02/02/26: Re: RAM question
40185: 02/03/01: clock nets use non-dedicated resources
40260: 02/03/03: Constraining help required for clk_enable
40261: 02/03/03: Other 2 constraining how to questions
40565: 02/03/10: First steps with clock enable constraining
40566: 02/03/10: floating pins
40567: 02/03/10: MPPR question
40636: 02/03/11: Re: floating pins
40658: 02/03/12: Re: MPPR question
40967: 02/03/19: FIFO general question
41041: 02/03/19: Re: FIFO general question
43008: 02/05/09: A special Thanks to :
61122: 03/09/29: Re: Partial Reconfiguration, ISE 6.1
61123: 03/09/29: FPGA : Partial reconfiguration of virtex2
62339: 03/10/27: Question about post-PAR simulation
Antonio =?iso-8859-1?Q?Mart=EDnez=20=C1lvarez?=:
20756: 00/02/20: Re: Divider
antonio bergnoli:
80783: 05/03/11: Re: Xilinx ISE 7.1 WebPack first impressions
80784: 05/03/11: Re: Xilinx ISE 7.1 WebPack first impressions
80892: 05/03/14: Re: Xilinx ISE7.1
94661: 06/01/16: programming devices using other tools
94707: 06/01/16: Re: programming devices using other tools
95737: 06/01/25: Re: open source fpga programmer programs
96368: 06/02/02: Re: Parallel Cable IV does not work with parallel to usb cable
98299: 06/03/08: Re: Does xilinx ise 8.1 support linux red hat 4.0??????(with device
98319: 06/03/08: printing schematics in ise 8.1 Linux .Solved [Was: Does xilinx ise
98671: 06/03/14: boundary scan example with spartan3
105259: 06/07/19: Re: Which PCI core for Cyclone II board?
105268: 06/07/19: Re: Which PCI core for Cyclone II board?
109411: 06/09/26: ise 8.2 partitions
111372: 06/11/02: Re: Xilinx ISE Webpack - Any usable simulator for the Linux platform
111792: 06/11/10: shaping aynchronous signal
Antonio D'Ottavio:
35858: 01/10/21: Interpolating in QPSK with f_IF = f_clk/4
36079: 01/10/28: Coefficient storing in VHDL
Antonio Di Bacco:
114533: 07/01/18: ISE Simulator Error 222: SuSE 10.1 Linux
114596: 07/01/20: Re: ISE Simulator Error 222: SuSE 10.1 Linux
Antonio Di Stefano:
51351: 03/01/11: Partial reconfiguration
67038: 04/03/04: EDK and LMB peripherals...
67085: 04/03/05: Re: EDK and LMB peripherals...
69375: 04/05/09: Re: OPB IPIF user logic
76461: 04/12/03: Re: How to direct download to SRAM on Xilinx Spartan3?
81419: 05/03/23: Re: WLAN in VHDL
Antonio Esteves:
1294: 95/05/29: Help on Programming FPGAs
1391: 95/06/13: HELP on programming XC3090A
Antonio Garcia:
19085: 99/11/28: Re: CIC Filters in FPGA
Antonio J A Esteves:
3371: 96/05/22: Re: Xilinx and Viewlogic
Antonio Joaquim A Esteves:
12806: 98/10/30: M0 M1 M2 * JTAG Programmer * Xchecker cable
20922: 00/02/28: PCI Core Problem
Antonio L Benci:
15995: 99/04/27: ORCAD ESP V4.21 (DOS & SDT V4) PLD problems
Antonio Martínez Álvarez:
41852: 02/04/09: Compiling the addone.c example from DK1
Antonio Pasini:
25111: 00/08/26: Newbie question about Xilinx Spartan PGCLK
36080: 01/10/28: Re: Verilog vs. VHDL
36245: 01/11/03: Re: Verilog vs. VHDL
43597: 02/05/25: Re: SDRAM controler for Virtex-II
50940: 02/12/23: ChipScope Pro not importing Inserter project
52015: 03/01/28: [help] timing closure problem on two slightly different xilinx designs
52072: 03/01/30: Re: [help] timing closure problem on two slightly different xilinx designs
55391: 03/05/06: Re: use of DRAM as massive FIFO
55392: 03/05/06: Re: use of DRAM as massive FIFO
55427: 03/05/07: Re: use of DRAM as massive FIFO
56816: 03/06/16: Re: spartan 2e dll locking
57497: 03/07/01: Re: fpga video evaluation board
63330: 03/11/19: Re: State Machines....
64203: 03/12/19: Re: Spartan3 availability
64212: 03/12/20: Re: Spartan3 availability
64603: 04/01/08: Re: Large/Fast static RAM
65970: 04/02/10: Re: sdram controller problems
69465: 04/05/11: Re: is it possible to design usb only with fpga?
70402: 04/06/15: Re: pulse generation using SRL16E on a Virtex-II
70531: 04/06/19: Re: compressing Xilinx bitstreams, some test data
75835: 04/11/16: Re: Soft Processor Core
76633: 04/12/07: Re: FPGA as host for a USB peripheral
78667: 05/02/05: Re: Orcad schematic and footprint libraries for Xilinx Spartan 3 FPGA's
79348: 05/02/17: Re: Fast counting in Spartan 3
79349: 05/02/17: Re: Efficient Voltage Regulators Spartan 3 Current Requirements
79651: 05/02/22: Re: Spartan3 Power Supply Circuits
79715: 05/02/23: Re: Efficient Voltage Regulators Spartan 3 Current Requirements
87118: 05/07/15: Re: NIOS II + USB 2.0 host
89034: 05/09/03: Re: CPLD - SimuCAD S/W CD
89731: 05/09/23: ML403 dcm phase shift reference design... anyone has a copy ?
90087: 05/10/04: Re: Xilinx dev board with high quality video?
90940: 05/10/25: Re: OSD implementation in FPGA
91658: 05/11/10: Re: Bus for Spartan3
91799: 05/11/13: Re: Bitstream compression
94781: 06/01/17: [RANT] Webpack 8.1 editor totally messed up ?
95949: 06/01/27: Re: Microblaze data cache question
95950: 06/01/27: Re: Multichannel Opb Memory Controller question
95058: 06/01/20: Re: OT:Shooting Ourselves in the Foot
121913: 07/07/15: Re: ESR Meter - design contest
122851: 07/08/08: Re: SDR SDRAM controller for Xilinx Spartan-3E
125321: 07/10/21: Re: Building a Huffman codebook in VHDL
125342: 07/10/22: Re: Building a Huffman codebook in VHDL
126322: 07/11/19: Re: Coolrunner in system programming - XAPP0058 - viable?
126338: 07/11/20: Re: Coolrunner in system programming - XAPP0058 - viable?
126339: 07/11/20: Re: Coolrunner in system programming - XAPP0058 - viable?
133752: 08/07/13: Re: ANNOUNCE: TimingAnalyzer version beta 0.86
133780: 08/07/14: Re: ANNOUNCE: TimingAnalyzer version beta 0.86
134207: 08/07/30: Re: ISE new file wizard
134208: 08/07/30: Re: Creating new operators
134577: 08/08/19: Re: Setting a control parameter in Active HDL
134578: 08/08/19: Re: Setting a control parameter in Active HDL
134750: 08/08/28: Re: need fast FPGA suggestions
134761: 08/08/29: Re: need fast FPGA suggestions
135187: 08/09/19: Re: Peter says Good Bye
Antonio Roldao Lopes:
96597: 06/02/07: Xilinx Spartan 3 LVDS Misbehaving
96671: 06/02/08: Re: Xilinx Spartan 3 LVDS Misbehaving
Antonio Rosa:
9463: 98/03/16: Ideas for an FPGA Project?
Antonio V:
157725: 15/02/18: Re: Open Source GPGPU core
Antonis Karvelas:
42294: 02/04/19: Multilinx: timing specs
Antonis Konstantinos:
62333: 03/10/27: Memory for FPGA based LCD Driver/Controller
Antony:
45004: 02/07/09: LUT and Xilinx Distributed SelectRam
45034: 02/07/10: Re: LUT and Xilinx Distributed SelectRam
83259: 05/04/26: Re: DDR SODIMM on Avnet Virtex II PRO development kit
83332: 05/04/27: Re: DDR SODIMM on Avnet Virtex II PRO development kit
83742: 05/05/06: Re: DDR SODIMM on Avnet Virtex II PRO development kit
131726: 08/04/30: XUPV2P and EDK 10.1
132444: 08/05/27: Re: XUPV2P and EDK 10.1
Antti:
65917: 04/02/10: sdram controller problems
66159: 04/02/13: Re: sdram controller problems
96658: 06/02/08: MicroBlaze in Spartan 3 playing tuxchess :)
96774: 06/02/10: ANTTI*HAPPY: building MicroBlaze uClinux on WinXP full sucess !!
96791: 06/02/10: Re: ANTTI*HAPPY: building MicroBlaze uClinux on WinXP full sucess !!
96903: 06/02/13: [ANN] MicroBlaze uClinux FPGA module (with microwindows) at Embedded
96905: 06/02/13: Re: MicroBlaze uClinux FPGA module (with microwindows) at Embedded
97035: 06/02/15: News from Embedded World in Nurnber
97036: 06/02/15: Re: spartan-3e starter kit
97039: 06/02/15: Re: News from Embedded World in Nurnber
97040: 06/02/15: Re: 8.1i SP2 download problems
97048: 06/02/15: Re: EDK Woes and Worries
97276: 06/02/20: Re: DVI - LVDS controller
97285: 06/02/20: Re: DVI - LVDS controller
97286: 06/02/20: Re: What is the best price you have gotten on for these FPGAs?
97357: 06/02/21: EDK 8.1 SP1 released, DDR2 support is now included !!
97438: 06/02/22: Re: How to make Customized IP which connected with Microblaze through FSL access the OPB bus?
97439: 06/02/22: Re: How to make Customized IP which connected with Microblaze through FSL access the OPB bus?
97440: 06/02/22: PowerPC based SoC design, getting it working from first attempt
97472: 06/02/22: Re: How to make Customized IP which connected with Microblaze through FSL access the OPB bus?
97473: 06/02/22: Re: PowerPC based SoC design, getting it working from first attempt
97490: 06/02/23: Re: virtex 4
97496: 06/02/23: Re: DDR2 Memory Design: Layout, timing
97510: 06/02/23: Re: Addressing BRAM in a V2 pro
97578: 06/02/23: Re: ironic Xcell journal 1Q2006 cover art, S3E Starter Kit
97582: 06/02/24: Re: ironic Xcell journal 1Q2006 cover art, S3E Starter Kit
97586: 06/02/24: Re: USB 2.0 OTG in FPGA
97593: 06/02/24: Re: USB 2.0 OTG in FPGA
97594: 06/02/24: Re: USB 2.0 OTG in FPGA
97597: 06/02/24: Re: PPC405 - FPGA interface design
97746: 06/02/27: Re: XC9500 JTAG Initialize problem
97752: 06/02/27: Re: VirtexII routing data widths
97834: 06/02/28: PPC Linux SoC on Virtex4 in 4 hours !?
97847: 06/02/28: Re: XUP Vertex II J5 Expansionheader Voltage
97876: 06/03/01: Re: PPC Linux SoC on Virtex4 in 4 hours !?
97879: 06/03/01: Re: Microblaze on Spartan3
97889: 06/03/01: Re: PPC Linux SoC on Virtex4 in 4 hours !?
97890: 06/03/01: Re: Virtex-4FX Mini Module TEMAC examples
97936: 06/03/01: Re: Virtex-4FX Mini Module TEMAC examples
97937: 06/03/01: Re: Anyone with Insight DS-V2LC Board Rev. 2 datasheet?
97938: 06/03/01: Re: i2c addressing
97947: 06/03/02: Re: Anyone with Insight DS-V2LC Board Rev. 2 datasheet?
98024: 06/03/03: Re: Virtex-4FX MiniModule Atmel Flash
98084: 06/03/04: Re: bscan_virtex4 device
98152: 06/03/06: Re: latticexp
98215: 06/03/07: Re: Atmel using Xilinx FPGAs
98221: 06/03/07: Re: Xilinx ISE8.1 & MIG1.5 crash
98225: 06/03/07: Re: bscan_virtex4 device
98273: 06/03/07: Re: Digilent Spartan-3 Starter Kit w/ JTAG-USB Problem/Solution
98388: 06/03/09: Re: slice macro replace the bus macro in the virtex-4 how to do that?????
98401: 06/03/09: Re: slice macro replace the bus macro in the virtex-4 how to do that?????
98458: 06/03/10: Re: Digilent Spartan-3 Starter Kit w/ JTAG-USB Problem/Solution
98505: 06/03/11: Re: (no subject)
98793: 06/03/16: Re: Urgent Help Needed!!!!!
98837: 06/03/16: Re: spartan-3e starter kit
98859: 06/03/17: Re: spartan-3e starter kit
98860: 06/03/17: Re: SerialATA with Virtex-II Pro
98865: 06/03/17: Re: SerialATA with Virtex-II Pro
98872: 06/03/17: Re: SerialATA with Virtex-II Pro
98898: 06/03/17: Re: SerialATA with Virtex-II Pro
98925: 06/03/17: Re: SerialATA with Virtex-II Pro
98977: 06/03/18: Re: SerialATA with Virtex-II Pro
99048: 06/03/19: Re: Spartan-3E Sample Pack
99086: 06/03/20: Re: SerialATA with Virtex-II Pro
99111: 06/03/20: Re: Xilinx programming cable; Linux notebook w/o parallel port; Am I doomed?
99226: 06/03/21: Re: SerialATA with Virtex-II Pro
99252: 06/03/21: Re: OpenSPARC released
99274: 06/03/22: Re: JTAG programing specs for XC18V01 PROM
99373: 06/03/23: Re: Lattice FPGA
99422: 06/03/23: Re: Lattice FPGA
99423: 06/03/23: Re: FPGA : Spartan-3e configuration failure
99447: 06/03/24: Re: Lattice FPGA
99452: 06/03/24: Re: linux on memec fx12 mini-module?
99472: 06/03/24: Re: Lattice FPGA
99531: 06/03/26: Re: BlockROM inference in XST - This is just plain silly
99581: 06/03/26: Re: Spartan 3e Starter Kit finally available? No, not really.
99582: 06/03/26: Re: chip reverse engineering
99584: 06/03/26: Re: Altera web site inaccessible
99708: 06/03/28: Re: basic doubts about chipscope pro
99938: 06/03/31: Re: hwicap can be used in the virtex4
100089: 06/04/03: Re: Spartan 3E SPI Programming
100098: 06/04/03: Re: Spartan 3E SPI Programming
100129: 06/04/04: Re: Cheap Spartan 3 PCI express starter kit
100139: 06/04/04: xilinx legacy input error
100223: 06/04/05: Re: I2C bus controller Implementation
100435: 06/04/09: Re: C-Compiler for free VHDL controller core ?
100476: 06/04/10: Re: LDPC
100570: 06/04/12: Re: Spartan3E readback, SPI programming
100581: 06/04/12: Re: Spartan3E readback, SPI programming
100587: 06/04/12: Re: Spartan3E readback, SPI programming
100616: 06/04/13: Re: Spartan3E readback, SPI programming
101000: 06/04/24: Xilinx EDK 8.1 DDR controller behavior
101187: 06/04/27: Working Altera Byteblaster compatible design published under GPL
101188: 06/04/27: Re: Working Altera USB-Blaster compatible design published under GPL
101212: 06/04/27: Re: UCF-mode for Emacs
101216: 06/04/27: Re: LED Driver
101269: 06/04/28: Re: Working Altera USB-Blaster compatible design published under GPL
101274: 06/04/28: Re: Xilinix SPI programming with USB Platform Cable
101282: 06/04/28: Re: Xilinix SPI programming with USB Platform Cable
101291: 06/04/28: Re: Working Altera USB-Blaster compatible design published under GPL
101292: 06/04/28: Re: Pull up resistors on Spartan 3 mode pins
101305: 06/04/28: Re: Pull up resistors on Spartan 3 mode pins
101319: 06/04/28: Re: Xilinix SPI programming with USB Platform Cable
101443: 06/05/01: Re: Xilinx PROM
101445: 06/05/01: Re: fpga programming
101453: 06/05/01: Re: ISE 8.1 Comment Bug, Very hideous
101526: 06/05/02: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
101527: 06/05/02: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
101529: 06/05/02: Re: Working Altera USB-Blaster compatible design published under GPL
101564: 06/05/03: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
101565: 06/05/03: Re: How to open an ISE 8.1 project in ISE 7.1?
101580: 06/05/03: Re: How to open an ISE 8.1 project in ISE 7.1?
101588: 06/05/03: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
101591: 06/05/03: Re: ML405 board
101594: 06/05/03: Measuring Light with LED and FPGA
101716: 06/05/05: Re: Xilinx SelectMAP Question
101724: 06/05/05: Re: Xilinx SelectMAP Question
101725: 06/05/05: Re: Xilinx SelectMAP Question
101729: 06/05/05: Re: Xilinx SelectMAP Question
101807: 06/05/07: Re: Measuring Light with LED and FPGA
101863: 06/05/07: Re: PCI Core compatibility
101866: 06/05/08: Re: Anyone use Xilinx ppc405 profiling tools?
101903: 06/05/08: Re: Strange power up issue on Virtex4
101909: 06/05/08: Re: Strange power up issue on Virtex4
101982: 06/05/09: Re: Chipscope and FPGA
102065: 06/05/10: Re: PCI Express and DMA
102089: 06/05/10: Re: CoolRunner XPLA3 getting axed?
102149: 06/05/11: MicroBlaze GPIO 1-bit [resistor], funny story :)
102150: 06/05/11: Re: XCFxxP Plaform Flash Device Questions
102175: 06/05/11: Re: CoolRunner XPLA3 getting axed?
102181: 06/05/11: Re: CoolRunner XPLA3 getting axed?
102276: 06/05/13: Re: altera cyclone memory example
102289: 06/05/14: Re: altera cyclone memory example
102309: 06/05/14: Re: getting good deals on small qty?
102310: 06/05/14: Re: Amontec Komodo board ?
102329: 06/05/15: Re: pull-ups and jtag questions
102351: 06/05/15: Re: Virtex 5 announced
102352: 06/05/15: Re: Virtex 5 announced
102354: 06/05/15: Re: Virtex 5 announced
102358: 06/05/15: Re: Virtex 5 announced
102360: 06/05/15: Re: Virtex 5 announced
102364: 06/05/15: Re: Virtex 5 announced
102366: 06/05/15: Re: Virtex 5 announced and sampling
102400: 06/05/15: Re: getting good deals on small qty?
102420: 06/05/15: Re: Actel Fusion FPGAs
102426: 06/05/16: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
102438: 06/05/16: Re: I can't connect to my Spartan 3 !!! ( Digilent starter kit )
102444: 06/05/16: Re: Virtex 5 announced
102445: 06/05/16: Re: Virtex 5 announced and sampling
102452: 06/05/16: Re: Actel Fusion FPGAs
102456: 06/05/16: Re: Virtex 5 announced and sampling
102459: 06/05/16: Re: Virtex 5 announced and sampling
102469: 06/05/16: Re: Actel Fusion FPGAs
102514: 06/05/17: Re: Virtex4 FX12 dynamic clock divider
102529: 06/05/17: Re: SystemACE bootloader for PowerPC on Virtex4 FX
102614: 06/05/17: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
102629: 06/05/18: Re: SystemACE bootloader for PowerPC on Virtex4 FX
102634: 06/05/18: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
102680: 06/05/19: Re: Spartan 3 Readback
102684: 06/05/19: EDK OPB DDR2 IP Core, looking for tested example
102697: 06/05/19: Re: Make a signal free for glitches?
102703: 06/05/19: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
102705: 06/05/19: Re: Spartan 3 Readback
102708: 06/05/19: Re: EDK OPB DDR2 IP Core, looking for tested example
102710: 06/05/19: Re: Use USB ports on ML401
102724: 06/05/19: Re: Xilinx-ise, invert input?
102733: 06/05/19: Re: Xilinx-ise, invert input?
102786: 06/05/20: Re: xilinx V4 obufds_25 and 3.3 V
102809: 06/05/21: Re: Quartus ByteBlaster in Active Serial Programming mode not working
102813: 06/05/21: Re: MicroBlaze as SubModule Problem
102814: 06/05/21: Re: MicroBlaze as SubModule Problem
102818: 06/05/21: Re: Have someone implementate the cpu86 or sparc embeded processor in the v-2 fpga
102821: 06/05/21: Re: Have someone implementate the cpu86 or sparc embeded processor in the v-2 fpga
102822: 06/05/21: How simple can FPGA design be? (Mission Possible 2006)
102833: 06/05/22: Re: DDR2 SDRAM controller + dual purpose pins
102838: 06/05/22: Re: Have someone implementate the cpu86 or sparc embeded processor in the v-2 fpga
102839: 06/05/22: Re: MicroBlaze and IIC
102848: 06/05/22: Re: Urgent help programming SPI-flash trough JTAG (Spartan3E)
102856: 06/05/22: Re: xilinx pricing discrepancy
102860: 06/05/22: Re: Unknown Processor Version (8)
102863: 06/05/22: Re: ispLEVER Starter 6.0 FPGA Design Software Available
102865: 06/05/22: Re: Building a board with Spartan 3 FPGA.
102871: 06/05/22: Re: Building a board with Spartan 3 FPGA.
102902: 06/05/22: Re: Urgent help programming SPI-flash trough JTAG (Spartan3E)
102904: 06/05/23: Re: Urgent help programming SPI-flash trough JTAG (Spartan3E)
102907: 06/05/23: ISE 8.1SP4 PN doesnt start
102916: 06/05/23: Re: ISE 8.1SP4 PN doesnt start
102926: 06/05/23: Re: ISE 8.1SP4 PN doesnt start
102971: 06/05/24: Most expensive 8051 in DIP40? here on my desk, labelled Virtex-4 V4LX25 :)
102972: 06/05/24: Re: Most expensive 8051 in DIP40? here on my desk, labelled Virtex-4 V4LX25 :)
102973: 06/05/24: Re: ISE 8.1SP4 PN doesnt start
102975: 06/05/24: Re: I2C on Xilinx V4
102977: 06/05/24: Re: Most expensive 8051 in DIP40? here on my desk, labelled Virtex-4 V4LX25 :)
102985: 06/05/24: Re: ISE 8.1SP4 PN doesnt start
103011: 06/05/24: Re: I2C on Xilinx V4
103099: 06/05/25: using Altium DXP2004 with Virtex4, also soft processors
103104: 06/05/25: Re: Xilinx ML321 (v2pro rocket io): Adding PCIe functionality
103124: 06/05/25: Re: Synthesizing VHDL delays [noob]
103140: 06/05/25: Re: Altium Livedesign eval boards - can you add a configuration prom?
103181: 06/05/27: Re: DVI connected to Virtex-4
103182: 06/05/27: Re: tft and uClinux
103193: 06/05/27: Re: Peripheral connected to multiple OPB buses
103199: 06/05/28: Re: tft and uClinux
103214: 06/05/28: Re: ISE 8.1 with 7.1
103217: 06/05/29: Re: ISE 8.1 with 7.1
103221: 06/05/29: Re: fpga uclinux, good starter board ?
103237: 06/05/29: Re: fpga uclinux, good starter board ?
103238: 06/05/29: Re: JTAG in-system programming of PROM devices
103246: 06/05/29: Re: fpga uclinux, good starter board ?
103247: 06/05/29: Re: Fast Serial I/O on Virtex-5
103257: 06/05/29: Re: Fast Serial I/O on Virtex-5
103269: 06/05/30: Re: PCI Header types !!!
103272: 06/05/30: Re: PCI Header types !!!
103283: 06/05/30: Re: generating IP cores
103284: 06/05/30: Re: tft and uClinux
103292: 06/05/30: Re: fpga uclinux, good starter board ?
103300: 06/05/30: Re: generating IP cores
103304: 06/05/30: Re: IOB IO Standards in Spartan 3
103326: 06/05/31: Re: Cardbus Power On Reset !!!!!!!!
103333: 06/05/31: Re: Cardbus Power On Reset !!!!!!!!
103335: 06/05/31: Re: Cardbus Power On Reset !!!!!!!!
103353: 06/05/31: Re: Virtex-4FX12MM: Any hardware MAC address accessable?
103368: 06/05/31: Re: Virtex-4FX12MM: Any hardware MAC address accessable?
103398: 06/06/01: Re: is anyone knew the new version of HWICAP "opb_hwicap_v1_00_c" for
103476: 06/06/03: Re: Have someone implementate the cpu86 or sparc embeded processor in the v-2 fpga
103496: 06/06/04: Re: FPGA board for USB experiments?
103502: 06/06/04: Re: FPGA board for USB experiments?
103517: 06/06/05: Re: FPGA board for USB experiments?
103518: 06/06/05: Re: FPGA board for USB experiments?
103970: 06/06/16: Re: ARM cores in FPGA ?
103971: 06/06/16: Re: Anyone get a Pictiva OLED to work?
103996: 06/06/16: Re: Floppy to FPGA?
104013: 06/06/16: Re: High speed differential to single ended
104053: 06/06/17: Re: Anyone get a Pictiva OLED to work?
104094: 06/06/18: Re: Anyone get a Pictiva OLED to work?
104095: 06/06/19: Re: High speed differential to single ended
104096: 06/06/19: Re: High speed differential to single ended
104098: 06/06/19: Re: Anyone get a Pictiva OLED to work?
104103: 06/06/19: Re: High speed differential to single ended
104114: 06/06/19: Re: High speed differential to single ended
104115: 06/06/19: Re: High speed differential to single ended
104117: 06/06/19: Re: Anyone get a Pictiva OLED to work?
104118: 06/06/19: Re: High speed differential to single ended
104120: 06/06/19: using Impulse-C free edition for VHDL only FPGA designs.
104144: 06/06/20: Re: using Impulse-C free edition for VHDL only FPGA designs.
104152: 06/06/20: Re: JTAG - Boundary Scan s/w using Byteblaster or Parallel 4 cable
104164: 06/06/20: Re: JTAG - Boundary Scan s/w using Byteblaster or Parallel 4 cable
104166: 06/06/20: Re: using Impulse-C free edition for VHDL only FPGA designs.
104207: 06/06/21: Actel FUSIN chips are real !
104475: 06/06/28: Re: Help in the platform studio(EDK)
104515: 06/06/29: Re: Help in the platform studio(EDK)
104609: 06/06/30: Re: Altium Designer LiveDesign Evaluation Kits (once again)
104622: 06/07/02: Re: Altium Designer LiveDesign Evaluation Kits (once again)
104623: 06/07/02: Re: How to comm with Altera JTAG UART (from custom host software)?
104624: 06/07/02: Re: Cyclone-II Configuration via a PCI bus
104632: 06/07/03: Re: Cyclone-II Configuration via a PCI bus
104633: 06/07/03: Re: how to use the xilinx 18v04 config fpga?
104638: 06/07/03: Re: Synthesis changes after ISE upgrade
104639: 06/07/03: next EDK service pack release date?
104641: 06/07/03: Re: Altium Designer LiveDesign Evaluation Kits (once again)
104649: 06/07/03: Re: can't read device ID xcv200....what about the PROGRAM pin
104651: 06/07/03: Re: Properties of some pins of Vertex4
104654: 06/07/03: Re: stable reset in fpga
104655: 06/07/03: Re: can't read device ID xcv200....what about the PROGRAM pin
104659: 06/07/03: Re: R: can't read device ID xcv200....what about the PROGRAM pin
104661: 06/07/03: Re: can't read device ID xcv200....what about the PROGRAM pin
104663: 06/07/03: Re: can't read device ID xcv200....what about the PROGRAM pin
104668: 06/07/03: Re: R: can't read device ID xcv200E....what about the PROGRAM pin
104681: 06/07/03: Re: PPC and Chipscope?
104689: 06/07/04: Re: Altium Live Desing Eval and Linux
104715: 06/07/04: Re: next EDK service pack release date?
104733: 06/07/05: Re: PPC and Chipscope?
104738: 06/07/05: Re: PPC and Chipscope?
104785: 06/07/06: Re: Altium Live Desing Eval and Linux
104844: 06/07/07: Re: detecting gnd
104864: 06/07/07: Re: Virtex4 Mini-Module GBL Phy
104866: 06/07/07: Re: FATAL ERROR IN EDK 7.1i
104906: 06/07/09: Re: SP305- PROM configuration
104907: 06/07/09: Weird JTAG lockup issue, where is the BUG?
104910: 06/07/09: Re: Weird JTAG lockup issue, where is the BUG?
104912: 06/07/09: Re: Weird JTAG lockup issue, where is the BUG?
104914: 06/07/09: Re: Weird JTAG lockup issue, where is the BUG?
104927: 06/07/09: Re: LUT4 INIT value to implement 2:1 MUX ?
104928: 06/07/09: Re: Weird JTAG lockup issue - PROBLEM SOLVED!
104933: 06/07/10: Re: Weird JTAG lockup issue, where is the BUG?
104943: 06/07/10: Re: PROM files: build .bin for daisy chain on the fly
104964: 06/07/11: Re: Implementing USB slow protocol into xilink XC95xxx..
104965: 06/07/11: Re: PROM files: build .bin for daisy chain on the fly
105046: 06/07/12: micron Flash controller VHDL disappeared ??
105053: 06/07/12: Re: Help with RBT file
105063: 06/07/12: Re: Help with RBT file
105071: 06/07/12: Re: reprogram xcf08 serial prom without jtag
105091: 06/07/13: Re: micron Flash controller VHDL disappeared ??
105097: 06/07/13: Re: Universal Scan with Xilinx's ML403
105166: 06/07/16: Re: An idea for a product (FPGA/ASIC based)
105169: 06/07/16: Xilinx System ACE Player available
105177: 06/07/17: OpenFire - public domain MicroBlaze clone in verilog
105182: 06/07/17: Re: OpenFire - public domain MicroBlaze clone in verilog
105228: 06/07/18: Re: OpenFire - public domain MicroBlaze clone in verilog
105230: 06/07/18: Re: NAND flash hangs
105257: 06/07/18: Re: Virtex 4 ACE Compact Flash configuration problem
105263: 06/07/19: Re: Which PCI core for Cyclone II board?
105278: 06/07/19: Re: PCIe: use 8*x1 PHY devices to form x8
105314: 06/07/19: Re: RHDL-0.5.0 released
105316: 06/07/20: Virtex-5: SoftCore processors at 200MHz !
105325: 06/07/20: Re: ISE 8.2i and EDK8.1i
105333: 06/07/20: Re: ISE 8.2i and EDK8.1i
105334: 06/07/20: Re: MIG DDR2 controller does not work (reset problems?)
105339: 06/07/20: Re: Creating EDIF from Verilog, then using VHDL wrapper
105376: 06/07/20: Re: ISE 8.2i and EDK8.1i
105443: 06/07/23: Re: KASUMI source code in VHDL
105451: 06/07/23: ANN: MicroBlaze simulator available
105511: 06/07/24: Re: EDK + Assembly Output Files + External Memory Usage
105512: 06/07/25: Re: impact.log files
105517: 06/07/25: Re: Calculate CRC in Virtex-Spartan II bitstream
105562: 06/07/25: Re: uClinux on Virtex-4 Mini-Module
105569: 06/07/26: Re: uClinux on Virtex-4 Mini-Module
105799: 06/08/01: Re: S3E USB2.0 port
105801: 06/08/01: Re: S3E USB2.0 port
105821: 06/08/01: Re: S3E USB2.0 port
105936: 06/08/03: Re: S3E USB2.0 port
105948: 06/08/03: coming soon: MB 5.0
105949: 06/08/03: Xilinx USB Blaster FX2 firmware and CPLD replacement under GPL released
105954: 06/08/03: Re: Chipscope
105955: 06/08/03: Re: MicroBlaze SPI interrupts
105962: 06/08/03: Re: 100m JTAG cable
105966: 06/08/03: Microblaze Sierro RTOS is no longer available??
105968: 06/08/03: Re: How can we fully utilize available BRAMs...
105975: 06/08/03: Re: Microblaze Sierro RTOS is no longer available??
106001: 06/08/04: Re: Chipscope
106014: 06/08/05: virtex ppclinux files
106078: 06/08/07: Re: virtex ppclinux files
106090: 06/08/07: Re: Xilinx USB Blaster FX2 firmware and CPLD replacement under GPL released
106106: 06/08/07: Re: verilog versus vhdl
106131: 06/08/08: Re: Open source Xilinx JTAG programmer with Digilent USB support
106163: 06/08/08: Re: 100 Mbit manchester coded signal in FPGA
106167: 06/08/08: Re: Who is your favourite FPGA guru?
106220: 06/08/09: Re: Xilinx PCI Core burst problem
106236: 06/08/09: Re: logic analyzer for Spartan3 starterkit, GPL VHDL and java based sw
106265: 06/08/10: Re: Real-world soft-cpu performance
106279: 06/08/10: Re: Real-world soft-cpu performance
106315: 06/08/11: (uc)Linux support for Xilinx FPGAs is going to next level
106325: 06/08/11: Re: (uc)Linux support for Xilinx FPGAs is going to next level
106383: 06/08/12: Re: JOP as SOPC component
106386: 06/08/12: Re: Gaisler on a Spartan 3E Starter Kit?
106402: 06/08/12: Re: virtex II inner organisation
106403: 06/08/12: Re: ISE Webpack 8.1 adder wierdness
106474: 06/08/13: Re: Real-world soft-cpu performance
106494: 06/08/14: Re: Virtex 4 could not work correct,is it damaged?
106568: 06/08/15: Re: Crystal input for FPGA
106606: 06/08/16: Re: (uc)Linux support for Xilinx FPGAs is going to next level
106607: 06/08/16: Re: Microblaze power estimation with external memory..
106608: 06/08/16: Re: High rate data transfer from off-chip mem to FSL co-proc...
106635: 06/08/16: Re: Open-source JTAG software?
106639: 06/08/16: Re: Open-source JTAG software?
106643: 06/08/16: Re: Open-source JTAG software?
106652: 06/08/16: Re: Crystal input for FPGA
106653: 06/08/16: Re: Crystal input for FPGA
106683: 06/08/17: Re: Open-source JTAG software?
106685: 06/08/17: Re: Open-source JTAG software?
106709: 06/08/17: Re: Using an FPGA as USB HOST without PHY
106716: 06/08/17: Re: Using an FPGA as USB HOST without PHY
106720: 06/08/17: Re: Using an FPGA as USB HOST without PHY
106745: 06/08/18: Re: Using an FPGA as USB HOST without PHY
106749: 06/08/18: Re: Open-source JTAG software?
106763: 06/08/18: Re: Problem Instantiating a DSP48E or RAMB36 for a Virtex5 in ISE 8.2 SP2
106775: 06/08/18: memec-avnet reference designs available
106813: 06/08/20: Xilinx ML501 availability
106820: 06/08/20: Re: CPU design
106834: 06/08/20: Re: CPU design
106850: 06/08/21: Re: CPU design
106851: 06/08/21: Re: Xilinx PowerPC run Program out of SDRAM
106869: 06/08/21: Xilinx EDK 8.2 released
106871: 06/08/21: Re: CPU design
106920: 06/08/22: Re: Microblaze - Writing to instruction store
106967: 06/08/23: Re: Open source Xilinx JTAG Programmer released on sourceforge.net
106968: 06/08/23: Re: Xilinx Virtual Platform
106973: 06/08/23: Re: Open source Xilinx JTAG Programmer released on sourceforge.net
106980: 06/08/23: Re: virtex4fx board and ethernet
106984: 06/08/23: Re: DCM vs. PLL
106992: 06/08/23: Re: virtex4fx board and ethernet
107067: 06/08/24: ANN: MicroBlaze platform simulator XSIM ver 1.1 released
107075: 06/08/24: Re: Why No Process Shrink On Prior FPGA Devices ?
107077: 06/08/24: Re: ISERDES strange simulation behaviour
107097: 06/08/24: Re: high level languages for synthesis
107170: 06/08/25: Re: Digilent USB support from Xilinx Impact (Programmer cable SDK for Impact)
107171: 06/08/25: Re: ISERDES strange simulation behaviour
107174: 06/08/25: Re: ISERDES strange simulation behaviour
107180: 06/08/25: Re: Linear priority encoder in Xilinx Virtex4
107200: 06/08/25: Re: Why No Process Shrink On Prior FPGA Devices ?
107213: 06/08/25: Re: Digilent USB support from Xilinx Impact (Programmer cable SDK for Impact)
107215: 06/08/25: Re: Digilent USB support from Xilinx Impact (Programmer cable SDK for Impact)
107216: 06/08/25: Re: I2C on Xilinx Virtex-4/ML403
107221: 06/08/25: Re: UltraController II + SystemAce
107234: 06/08/25: Re: I2C on Xilinx Virtex-4/ML403
107241: 06/08/25: Re: FPGA -> SATA?
107245: 06/08/25: Re: Digilent USB support from Xilinx Impact (Programmer cable SDK for Impact)
107293: 06/08/26: Re: FPGA -> SATA?
107355: 06/08/27: Re: FPGA -> SATA?
107371: 06/08/27: Re: FPGA -> SATA?
107393: 06/08/27: Re: FPGA -> SATA?
107397: 06/08/28: Re: FPGA -> SATA?
107401: 06/08/28: Re: placing addiional caps across existing caps to reduce noise
107405: 06/08/28: Spartan-4 ?
107409: 06/08/28: Re: Spartan-4 ?
107413: 06/08/28: Re: Spartan-4 ?
107433: 06/08/28: Re: Spartan-4 ?
107492: 06/08/29: Re: Actel Fusion?
107497: 06/08/29: Re: FPGA -> SATA?
107499: 06/08/29: Re: What is the truth about the Virtex5 ?
107500: 06/08/29: Re: What is the truth about the Virtex5 ?
107501: 06/08/29: Re: Undergrad project-8051 specifications??
107573: 06/08/30: Xilinx - one secret less, or how to use the PMV primitive
107578: 06/08/30: Virtex-4FX DCM autoshutdown failure, any suggestions
107586: 06/08/30: Re: Xilinx - one secret less, or how to use the PMV primitive
107590: 06/08/30: Re: fx12 v fx20 static power?
107596: 06/08/30: Re: Virtex-4FX DCM autoshutdown failure, any suggestions
107602: 06/08/30: Re: Virtex-4FX DCM autoshutdown failure, any suggestions
107603: 06/08/30: Re: Xilinx - no secret, you are not to use the PMV primitive
107606: 06/08/30: Re: Xilinx Spartan-3A
107618: 06/08/30: Re: Virtex-4FX DCM autoshutdown failure, any suggestions
107630: 06/08/30: Re: Virtex-4FX DCM autoshutdown failure, any suggestions
107650: 06/08/30: Re: Virtex-4FX DCM autoshutdown failure, any suggestions
107776: 06/09/01: Re: MicroBlaze and RAM Application
107777: 06/09/01: Re: Interface of 8051 microcontroller with FPGA Block RAM
107779: 06/09/01: Re: CPU design
107780: 06/09/01: Re: Open-source CableServer for Impact (no more need for Jungo driver on Linux)
107783: 06/09/01: Re: bidirectional connection between two bidirectional ports
107785: 06/09/01: Re: problem generate PCI-32/66MHz with Coregen
107790: 06/09/01: Re: Interface of 8051 microcontroller with FPGA Block RAM
107797: 06/09/01: Re: bidirectional connection between two bidirectional ports
107798: 06/09/01: V4 PPC-linux dlclose() SIGSEGV
107804: 06/09/01: Re: bidirectional connection between two bidirectional ports
107813: 06/09/01: Re: Higher voltages input, quick check....
107820: 06/09/01: Re: Higher voltages input, quick check....
107829: 06/09/01: Re: Higher voltages input, quick check....
107861: 06/09/01: Re: Read from Microblaze
107862: 06/09/01: Re: Impossible to download WebPACK?
107958: 06/09/03: Re: gpio help...
107959: 06/09/03: Re: Xilinx VSK (Video Starter Kit)
108007: 06/09/04: Re: linux 2.4 v 2.6 on xilinx
108075: 06/09/04: Re: linux 2.4 v 2.6 on xilinx
108097: 06/09/05: Re: Microblaze Programmers Reference Guide?
108102: 06/09/05: Re: Microblaze Programmers Reference Guide?
108104: 06/09/05: Re: sinmple DMA Example for ML403
108150: 06/09/06: Re: Open-source CableServer for Impact on sourceforge.net
108153: 06/09/06: Re: XPS : Compiler advanced options...
108157: 06/09/06: Re: Open-source CableServer for Impact on sourceforge.net
108179: 06/09/06: Re: Open-source CableServer for Impact on sourceforge.net
108186: 06/09/06: Re: Open-source CableServer for Impact on sourceforge.net
108196: 06/09/06: Re: Open-source CableServer for Impact on sourceforge.net
108201: 06/09/06: Re: Open-source CableServer for Impact on sourceforge.net
108343: 06/09/08: Re: Virtex4FX12 and Spartan3 lead time
108349: 06/09/08: Re: Virtex4FX12 and Spartan3 lead time
108355: 06/09/08: Re: Virtex4FX12 and Spartan3 lead time
108422: 06/09/11: Re: Problem with adding DCM to Spartan-3
108423: 06/09/11: Re: simplyrisc-s1 free core
108429: 06/09/11: Re: simplyrisc-s1 free core
108432: 06/09/11: Re: Xilinx Platform Studio 8.2i - Add custom peripheral, adress Space calculation
108439: 06/09/11: Lattice eval board with PCIe and SATA
108443: 06/09/11: Re: simplyrisc-s1 free core
108488: 06/09/11: Re: uclinux on spartan-3e starter kit
108489: 06/09/11: Re: Lattice eval board with PCIe and SATA
108494: 06/09/12: Re: Xilkernel: Problem with mutex
108496: 06/09/12: Re: microblaze startup problem
108500: 06/09/12: Re: Xilkernel: Problem with mutex
108506: 06/09/12: Re: linux 2.4 v 2.6 on xilinx
108561: 06/09/13: Re: Spartan-4 ?
108563: 06/09/13: Re: uclinux on spartan-3e starter kit
108567: 06/09/13: Re: Xilinx Platform Studio, build up System: "block-RAM components require the adjacent multiplier"
108683: 06/09/15: Re: Unwanted clock on output pin....
108696: 06/09/15: Re: Fusion
108720: 06/09/15: Re: Digilent 3S200 pcb + webpack ISE 8.2 + service pack
108727: 06/09/15: Re: Fusion
108780: 06/09/16: Re: simplyrisc-s1 free core
108781: 06/09/16: Re: http://www.srisc.com ?
108807: 06/09/17: SSFP16 GPL licensed 16 Fpga processor released
108809: 06/09/17: Re: problems with IOSTANDARD
108835: 06/09/18: Re: uclinux on spartan-3e starter kit
108838: 06/09/18: Re: microblaze startup problem
108842: 06/09/18: Re: SSFP16 GPL licensed 16 Fpga processor released
108845: 06/09/18: Re: Writing VHDL, Software dummy!
108859: 06/09/18: Re: Lattice ECP2/M
108875: 06/09/18: Re: Virtex4 Configuration ROM?
108902: 06/09/19: Re: New Lattice 32-bit Embedded Microprocessor Available Through Unique Open Source License
108906: 06/09/19: Re: New Lattice 32-bit Embedded Microprocessor Available Through Unique Open Source License
108912: 06/09/19: Re: New Lattice 32-bit Embedded Microprocessor Available Through Unique Open Source License
109011: 06/09/19: Re: New Lattice 32-bit Embedded Microprocessor Available Through Unique Open Source License
109017: 06/09/20: Re: Lattice .bit file format
109022: 06/09/20: Re: Lattice .bit file format
109040: 06/09/20: Re: Xilinx PowerPC slower than FPGA Design?
109048: 06/09/20: Re: Xilinx PowerPC slower than FPGA Design?
109053: 06/09/20: MicroFpga = program an FPGA as it would be a MCU !
109058: 06/09/20: Re: New Lattice 32-bit Embedded Microprocessor Available Through Unique Open Source License
109062: 06/09/20: Re: Xilinx PowerPC slower than FPGA Design?
109064: 06/09/20: Re: MPMC2 and MontaVista Linux
109067: 06/09/20: Re: MicroFpga = program an FPGA as it would be a MCU !
109069: 06/09/20: Re: MicroFpga = program an FPGA as it would be a MCU !
109073: 06/09/20: Re: New Lattice 32-bit Embedded Microprocessor Available Through Unique Open Source License
109074: 06/09/20: Re: New Lattice 32-bit Embedded Microprocessor Available Through Unique Open Source License
109082: 06/09/20: Re: MicroFpga = program an FPGA as it would be a MCU !
109084: 06/09/20: Re: xilinx or altera?
109088: 06/09/20: Re: Question about initializing on-chip block mem in XPS?
109093: 06/09/20: Re: Question about initializing on-chip block mem in XPS?
109098: 06/09/20: Re: Which soft core to use?
109100: 06/09/20: Re: MicroFpga = program an FPGA as it would be a MCU !
109124: 06/09/20: Re: Verification errors using Xilinx Spartan 3E board
109126: 06/09/21: Re: MicroFpga = program an FPGA as it would be a MCU !
109127: 06/09/21: Re: Lattice .bit file format
109130: 06/09/21: Re: Which soft core to use?
109218: 06/09/21: Re: Verification errors using Xilinx Spartan 3E board
109219: 06/09/21: Re: Xilinx - no secret, you are not to use the PMV primitive
109231: 06/09/22: Re: MicroFpga = program an FPGA as it would be a MCU !
109240: 06/09/22: Re: Spartan-3E USB for I/O?
109243: 06/09/22: Re: who can give me source code about ISA BUS ?
109249: 06/09/22: Re: Lattice .bit file format
109254: 06/09/22: Re: New Lattice 32-bit Embedded Microprocessor Available Through Unique Open Source License
109293: 06/09/23: Re: MV4.0.1 and Avnet Mini-Module
109299: 06/09/23: Re: edk 8.2 user needed
109300: 06/09/23: Re: Old vs. New FPGAs
109310: 06/09/23: Re: SSFP16 GPL licensed 16 Fpga processor released
109346: 06/09/25: Re: System ACE CF controller, can i do this
109352: 06/09/25: Re: MicroFpga = program an FPGA as it would be a MCU !
109355: 06/09/25: Re: Virtex-4 BSCAN
109357: 06/09/25: Re: MicroFpga = program an FPGA as it would be a MCU !
109427: 06/09/26: Re: Newbee question - how to upgrade to Xilinx ISE/EDK 8.2 from 8.1
109457: 06/09/27: ML501 where to order
109458: 06/09/27: Re: Configuration of Spartan 3 devices
109462: 06/09/27: Re: Are you ready for Virtex-5? We are...
109469: 06/09/27: Re: Configuration of Spartan 3 devices
109470: 06/09/27: Re: Configuration of Spartan 3 devices
109476: 06/09/27: Re: Configuration of Spartan 3 devices
109477: 06/09/27: Re: Configuration of Spartan 3 devices
109494: 06/09/27: Re: MicroBlaze : Linkerscript for splitting the text block into 64kByte blocks
109496: 06/09/27: Re: uBlaze prototype PCB UART issues
109511: 06/09/27: Re: Are you ready for Virtex-5? We are...
109512: 06/09/27: Re: uBlaze prototype PCB UART issues
109516: 06/09/27: Re: Is it worth learning SOPC Builder, DSP Builder & Nios Processor?
109517: 06/09/27: Virtex-5: small little things.
109536: 06/09/28: Re: ML501 where to order
109569: 06/09/29: Re: Interfacing second bram port to user logic?
109574: 06/09/29: Re: Interfacing second bram port to user logic?
109576: 06/09/29: Re: MicroBlaze : Linkerscript for splitting the text block into 64kByte blocks
109590: 06/09/29: Re: Virtex-5: small little things.
109591: 06/09/29: Re: Are you ready for Virtex-5? We are...
109593: 06/09/29: Re: Are you ready for Virtex-5? We are...
109612: 06/10/01: Re: System ACE woes
109632: 06/10/02: Re: Are you ready for Virtex-5? We are...
109633: 06/10/02: LatticeMico32 extremly poor performance without caches
109634: 06/10/02: Re: New Lattice 32-bit Embedded Microprocessor Available Through Unique Open Source License
109636: 06/10/02: Re: Help with ISE WebPack 8.2i (moving project files)
109638: 06/10/02: Re: Help with ISE WebPack 8.2i (moving project files)
109642: 06/10/02: Re: LatticeMico32 extremly poor performance without caches
109646: 06/10/02: Re: LatticeMico32 extremly poor performance without caches
109648: 06/10/02: Re: I2S serial to parallel conversion and generating C,V and Z bits
109666: 06/10/02: Re: Modules for IO on BSD indi processor ideas?
109690: 06/10/03: Re: LatticeMico32 extremly poor performance without caches
109695: 06/10/03: Re: LatticeMico32 extremly poor performance without caches
109719: 06/10/04: Re: free CAN field bus IP for EDK ?
109740: 06/10/04: Re: free CAN field bus IP for EDK ?
109757: 06/10/05: Re: Just a matter of time
109778: 06/10/05: Re: Are you ready for Virtex-5? We are...
109780: 06/10/05: Virtex-5 FX when ?
109844: 06/10/06: Re: BSD indi processor IP compiles at ($13.30)
109846: 06/10/06: Re: Virtex-5 FX when ?
109879: 06/10/06: Re: BSD indi processor IP compiles at ($13.30)
109897: 06/10/07: Re: BSD indi processor IP compiles at 283 LEs
109917: 06/10/07: Re: System ACE woes
109922: 06/10/08: Spartan3A - internal flash configuration or not?
109925: 06/10/08: Re: Spartan3A - internal flash configuration or not?
109955: 06/10/08: Re: Antifuse, lower cost?
110101: 06/10/11: Xilinx MicroBlaze 4.00.a source codes released by Xilinx !?
110106: 06/10/11: Re: longest webcase record
110118: 06/10/11: Re: Two instances of Microblaze ...
110126: 06/10/11: Re: Xilinx MicroBlaze 4.00.a source codes released by Xilinx !?
110130: 06/10/11: Re: Simulink Co-simulation,parallel-door or platform cable USB
110133: 06/10/11: Re: Release Status of Spartan3E
110141: 06/10/11: Re: longest webcase record
110142: 06/10/11: Re: EDK Bug
110153: 06/10/11: Re: 75Mhz Spartan3e microblaze
110189: 06/10/12: Re: longest webcase record -- understandably so
110201: 06/10/12: Am I blind or? (Virtex-4 issues)
110202: 06/10/12: Re: EDK speed optimisation
110203: 06/10/12: Re: Functional Languages in Hardware
110209: 06/10/12: Re: Am I blind or? (Virtex-4 issues)
110210: 06/10/12: Re: Am I blind or? (Virtex-4 issues)
110211: 06/10/12: Re: LatticeMico32 extremly poor performance without caches
110221: 06/10/12: Re: power up delay in fpga
110228: 06/10/12: Re: Am I blind or? (Virtex-4 issues)
110275: 06/10/13: Last ISE version that supports XC95xxXL ?
110283: 06/10/13: Re: LatticeMico32 extremly poor performance without caches
110284: 06/10/13: Re: Last ISE version that supports XC95xxXL ?
110285: 06/10/13: Re: [ISE8.2] DIFF_TERM and unused pin
110288: 06/10/13: Re: Last ISE version that supports XC95xxXL ?
110291: 06/10/13: Virtex-5 LXT orderable?
110292: 06/10/13: Re: Virtex-5 LXT orderable?
110295: 06/10/13: Re: Last ISE version that supports XC95xxXL ?
110296: 06/10/13: Re: LatticeMico32 extremly poor performance without caches
110301: 06/10/13: Re: Are you ready for Virtex-5? We are...
110305: 06/10/13: Re: Are you ready for Virtex-5? We are...
110306: 06/10/13: Re: Virtex-5 LXT orderable?
110309: 06/10/13: Re: Xilinx FPGAs in battery-powered scenarios
110323: 06/10/13: Re: Xilinx FPGAs in battery-powered scenarios
110352: 06/10/14: Re: Xilinx V4 not registering T at OLOGIC
110401: 06/10/15: Re: 75Mhz Spartan3e microblaze
110402: 06/10/15: Re: Xilinx documentation typos
110409: 06/10/15: Re: how to change cclk frequency ?
110410: 06/10/15: Re: [ISE8.2] DIFF_TERM and unused pin
110411: 06/10/15: Re: ML501 finally released
110413: 06/10/15: Platform USB Cable schematic
110417: 06/10/15: Re: Libero 7.2
110418: 06/10/15: Virtex-5 DSP48E with xilinx simulator, minor bug and fix
110432: 06/10/15: Re: SPAM or Not - Re: Platform USB Cable schematic
110437: 06/10/15: uClinux for MicroBlaze ver 5.0
110450: 06/10/16: virtex-5 sysmon, really nice to monitor supply and temp
110457: 06/10/16: Re: SPAM or Not - Re: Platform USB Cable schematic
110466: 06/10/16: Virtex-5 LXT launched today !
110467: 06/10/16: Re: Virtex-5 LXT launched today !
110474: 06/10/16: Re: 75Mhz Spartan3e microblaze
110515: 06/10/17: Re: Virtex-5 LXT launched today !
110521: 06/10/17: Re: Block Memory Generator: Wrong data in BRAM after initialization with *.ceo File
110524: 06/10/17: Re: Virtex-5 LXT launched today !
110535: 06/10/17: Re: Block Memory Generator: Wrong data in BRAM after initialization with *.ceo File
110543: 06/10/17: Re: Virtex-5 LXT launched today !
110545: 06/10/17: Re: virtex-5 sysmon, really nice to monitor supply and temp
110552: 06/10/17: Re: Virtex-5 LXT launched today !
110555: 06/10/17: playing with ML501, first impressions
110579: 06/10/18: Re: Virtex-5 LXT launched today !
110591: 06/10/18: Re: Virtex-5 LXT launched today !
110666: 06/10/19: Re: Xilinx ISE Problems with combinatorial loops - software bug?
110714: 06/10/20: Re: JTAG pins of the xc2s200E for user I/O
110722: 06/10/20: Re: i486 FPGA replacement
110727: 06/10/20: Re: JTAG pins of the xc2s200E for user I/O
110768: 06/10/21: Re: Potential problem w/EDK's Microblaze and the Spartan-3E Starter Kit?
110769: 06/10/21: Re: Xilinx PCIe 8-lane endpoint constraints
110776: 06/10/22: Re: Potential problem w/EDK's Microblaze and the Spartan-3E Starter Kit?
110788: 06/10/23: Re: Spartan 3 Configuration Questions
110790: 06/10/23: Re: Spartan 3 Configuration Questions
110837: 06/10/24: Re: Xilinx Virtex4 DDR clock output
110849: 06/10/24: Re: Xilinx Virtex4 DDR clock output
110853: 06/10/24: Re: Survey on Quartus SOPC/Nios-II
110857: 06/10/24: Avnet virtex-5 board
110861: 06/10/24: Re: Virtex4 debug bitstream generation problem
110882: 06/10/25: V5LXT support for ISE released yesterday
110901: 06/10/25: Re: Survey on Quartus SOPC/Nios-II
110907: 06/10/25: Re: Survey on Quartus SOPC/Nios-II
110910: 06/10/25: Re: OT: FPGA soft-core humor
110913: 06/10/25: Re: OT: FPGA soft-core humor
110914: 06/10/25: Re: Survey on Quartus SOPC/Nios-II
110926: 06/10/25: Re: OT: FPGA soft-core humor
110928: 06/10/25: Re: can someone recommend a board?
110931: 06/10/25: Re: OT: FPGA soft-core humor
110933: 06/10/25: Re: can someone recommend a board?
110935: 06/10/25: Re: Xilinx MIG 1.6 doesn't launch
110937: 06/10/25: Re: Meta-stable problem with MAX-II ?
110940: 06/10/25: Re: can someone recommend a board?
110944: 06/10/25: xilinx sync fifo with first word fall-through
110945: 06/10/25: Re: can someone recommend a board?
110968: 06/10/26: Re: xilinx sync fifo with first word fall-through
110969: 06/10/26: Re: V5LXT support for ISE released yesterday
110975: 06/10/26: Re: OPB to SPI clock frequency ratio
110983: 06/10/26: Re: xilinx sync fifo with first word fall-through
110999: 06/10/26: Re: xilinx sync fifo with first word fall-through
111001: 06/10/26: Re: Survey on Quartus SOPC/Nios-II
111017: 06/10/27: Re: Problema when upgrading from Xilinx 8.1 to Xilinx 8.2
111027: 06/10/27: Re: EDK 8.2.01i:Spartan3E BSB Problem...
111028: 06/10/27: Re: Implementing Direct Memory Access for Peripheral (Xilinx Virtex 2 Pro)
111031: 06/10/27: Re: EDK 8.2.01i:Spartan3E BSB Problem...
111808: 06/11/10: Stratix-III announced
111812: 06/11/10: Re: Why 64-bit PLB?
111814: 06/11/10: Re: C3188A - 1/3"Digital Output Colour Camera Module
111817: 06/11/10: Re: Area Constraints in Xilinx
111819: 06/11/10: Re: Stratix-III announced
111826: 06/11/10: Re: C3188A - 1/3"Digital Output Colour Camera Module
111865: 06/11/11: Re: Stratix-III announced
111910: 06/11/13: Re: Stratix-III announced
111916: 06/11/13: Re: MPMC2: MPMC2 with DDR2 SDRAM
111946: 06/11/13: Re: FPGA Debug Tool
111948: 06/11/13: Re: FPGA Debug Tool
111950: 06/11/13: IEEE 1149.6 support in Virtex-5
111976: 06/11/13: Re: MPMC2: MPMC2 with DDR2 SDRAM
111982: 06/11/14: Re: Stratix-III announced
112117: 06/11/16: Re: XCF02S + Spartan 2e JTAG config problems
112148: 06/11/17: Re: XCF02S + Spartan 2e JTAG config problems
112151: 06/11/17: combinatorical divide by 2 in FPGA
112159: 06/11/17: Re: combinatorical divide by 2 in FPGA
112161: 06/11/17: Re: combinatorical divide by 2 in FPGA
112167: 06/11/17: Re: combinatorical divide by 2 in FPGA
112173: 06/11/17: memory init in Altera bitfiles, (like data2mem) is it possible?
112174: 06/11/17: Re: combinatorical divide by 2 in FPGA
112178: 06/11/17: Re: Warnings in Xilinx 8.2i
112186: 06/11/17: Re: Warnings in Xilinx 8.2i
112193: 06/11/17: Re: Warnings in Xilinx 8.2i
112194: 06/11/17: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112198: 06/11/17: Re: Warnings in Xilinx 8.2i
112199: 06/11/17: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112208: 06/11/17: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112209: 06/11/17: Re: combinatorical divide by 2 in FPGA
112210: 06/11/17: Re: combinatorical divide by 2 in FPGA
112237: 06/11/18: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112238: 06/11/18: Re: IDELAY Calibration - Virtex 4
112240: 06/11/18: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112250: 06/11/18: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112253: 06/11/18: EDK 8.2 Block RAM error
112254: 06/11/18: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112260: 06/11/18: Re: EDK 8.2 Block RAM error
112271: 06/11/18: Re: spartan-3e starter kit and ethernet
112307: 06/11/19: Re: IDELAY Calibration - Virtex 4
112317: 06/11/20: Re: Spartan3E price update ?
112377: 06/11/21: Re: Parallax Stratix Smartpack accessories?
112388: 06/11/21: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112391: 06/11/21: Re: EDK 8.2 Block RAM error
112392: 06/11/21: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112430: 06/11/21: Re: ISE 8.2 & XC9500XL family
112439: 06/11/22: Xilinx DDR2 IP core performance
112443: 06/11/22: Re: EDK 8.2 Block RAM error
112484: 06/11/23: Re: EDK 8.2 Block RAM error
112492: 06/11/23: Re: Problems connecting MicroBlaze to custom IP
112501: 06/11/23: Re: Xilinx EDK Problem
112532: 06/11/24: Re: jtag loader for picoblaze
112550: 06/11/24: MPMC2 DDR2 simulation
112610: 06/11/26: EDK 8.2 STUPID STUPID BUG (minor)
112654: 06/11/27: Re: MPMC2 DDR2 simulation
112657: 06/11/27: Re: Pullups and pulldowns in EDK?
112660: 06/11/27: Re: playing test SVF files for Spartan-3 Starter Board (using iMPACT ? or a test software?)
112665: 06/11/27: Re: playing test SVF files for Spartan-3 Starter Board (using iMPACT ? or a test software?)
112673: 06/11/27: Re: Microblaze Code and XMP functions
112678: 06/11/27: Re: nios2 toolchain sources
112683: 06/11/27: Re: What's the speed grade for the XC5VLX50 on xilinx ML501 evaluation board?
112690: 06/11/27: Re: nios2 toolchain sources
112694: 06/11/27: Re: Mico32, how good is it?
112697: 06/11/27: Re: Mico32, how good is it?
112725: 06/11/28: Re: run a counter without a clock
112731: 06/11/28: Xilinx FIFOs round 2 - BUG-BUG in MPMC2
112733: 06/11/28: Re: What's the status regarding MicroBlaze, Lynuxworks and uClinux 2.6?
112743: 06/11/28: Re: EDK Bug
112749: 06/11/28: Re: Xilinx ML555 availability
112780: 06/11/29: Re: Mico32, how good is it?
112781: 06/11/29: Re: MPMC2: MPMC2 with DDR2 SDRAM
112782: 06/11/29: Re: EDK 8.2 Block RAM error
112859: 06/11/29: Re: Xilinx FIFOs round 2 - BUG-BUG in MPMC2
112916: 06/12/01: Re: MPMC2: MPMC2 with DDR2 SDRAM
112949: 06/12/02: Re: MPMC2: MPMC2 with DDR2 SDRAM
112985: 06/12/04: Re: EDk and DCM
112987: 06/12/04: Re: EDk and DCM
112991: 06/12/04: Re: EDk and DCM
113003: 06/12/04: Re: Can you configure an Altera Stratix without the nStatus line?
113019: 06/12/05: Spartan-3A launched
113020: 06/12/05: Re: Spartan-3A launched
113022: 06/12/05: Re: Spartan-3A launched
113024: 06/12/05: Re: Spartan-3A launched
113078: 06/12/06: Re: Spartan-3A launched
113083: 06/12/06: Re: Spartan-3A launched
113087: 06/12/06: Re: Altera starter kits
113096: 06/12/06: Re: EDK 8.2, MDM, and ChipScope....
113378: 06/12/12: Re: linking two fpga boards
113392: 06/12/12: Re: ISP interface
113395: 06/12/12: Re: ISP interface
113478: 06/12/14: Re: what are your current SoC design for ?
113522: 06/12/15: Re: Spartan-3A launched
113557: 06/12/16: Re: Spartan-3A launched
113561: 06/12/16: Re: PowerPC_EDK to ISE
113609: 06/12/18: Re: VHDL CODE FOR SDRAM IN SPARTAN 3E
113656: 06/12/19: Re: jtag reset seq
113669: 06/12/19: Re: jtag reset seq
113673: 06/12/19: Xilinx Quiz: 150/3 = ?
113706: 06/12/19: Re: Slightly OT: Need a USB-to-LPT adapter for Xilinx Parallel IV Cable
113716: 06/12/19: Re: jtag reset seq
113729: 06/12/20: Re: Spartan 3E Starter Kit Woes
113741: 06/12/20: Re: MICROBLAZE AND OPB: TOO SLOW FOR VGA
113754: 06/12/20: Re: ANN: PicoBlaze C: compile to bitstream!
113759: 06/12/20: Re: Spartan 3E Starter Kit Woes
113761: 06/12/20: Re: Spartan 3E Starter Kit Woes
113777: 06/12/20: Re: MICROBLAZE AND OPB: TOO SLOW FOR VGA
113823: 06/12/23: Re: Simple questions on IDELAYCTRL vs DCM
114241: 07/01/08: Re: Build an FPGA programmer cable
114468: 07/01/16: Re: small, free simple state machine processor suggestions?
114510: 07/01/18: Re: Generation of Divided-by-3 clock
114512: 07/01/18: Xilinx website login problems
114523: 07/01/18: Re: Xilinx website login problems
114659: 07/01/22: Xilinx doing a re-entry in non-volatile FPGA arena!!!
114664: 07/01/22: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
114666: 07/01/22: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
114669: 07/01/22: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
114679: 07/01/22: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
114680: 07/01/22: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
114696: 07/01/23: Re: low speed USB interface for FPGAs
114711: 07/01/23: Re: First Picture of Craignell Modules
114713: 07/01/23: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
115430: 07/02/10: Re: Virtex 4 SATA redux
115476: 07/02/12: MPMC2 for Virtex-5 when?
115940: 07/02/26: Spartan-3AN
115943: 07/02/26: Re: Spartan-3AN
115944: 07/02/26: Re: Spartan-3AN
115949: 07/02/26: Re: Spartan-3AN
115950: 07/02/26: Re: Spartan-3AN
115955: 07/02/26: Re: Spartan-3AN
115959: 07/02/26: Re: Spartan-3AN
115966: 07/02/26: Re: Spartan-3AN
116714: 07/03/15: Re: Programming XCF from MicroBlaze over JTAG???
117828: 07/04/11: ERROR: ::xilinx::Dpm::TOE::execInterrupt doesn't know what to do.
117829: 07/04/11: Re: Xilinx WebCase support
117998: 07/04/16: Re: How to design a SDIO peripheral card?
118227: 07/04/20: ABC - Actel's PicoBlaze :) - anybody success with coreconsole?
118245: 07/04/20: Re: Free Hardware
118247: 07/04/20: Re: Stratix II - Cyclone II GATE COUNT
118248: 07/04/20: Re: FPGA Full Custum Design
118412: 07/04/26: Re: Virtex-5 FX when ? (II)
118506: 07/04/28: How many Xilinx devkits does one need?
118566: 07/04/30: Xilinx software quality - how low can it go ?!
118570: 07/04/30: Re: Xilinx software quality - how low can it go ?!
118572: 07/04/30: Re: Xilinx software quality - how low can it go ?!
118575: 07/04/30: DDR2 with Spartan-3A anybody having success??
118611: 07/04/30: Re: DDR2 with Spartan-3A anybody having success??
118612: 07/04/30: Re: Xilinx software quality - how low can it go ?!
118617: 07/05/01: Re: Open source Programmer, Logic Analyzer and In-Circuit Emulator Project
118675: 07/05/01: Re: Xilinx software quality - how low can it go ?!
118677: 07/05/01: Re: DDR2 with Spartan-3A anybody having success??
118680: 07/05/02: Re: How many Xilinx devkits does one need?
118685: 07/05/02: Re: Unused Pin setting on per-pin basis
118696: 07/05/02: Re: DDR2 with Spartan-3A anybody having success??
118697: 07/05/02: Xilinx 9.x SW == Total Frustration (so far..)
118700: 07/05/02: Re: Xilinx 9.x SW == Total Frustration (so far..)
118706: 07/05/02: My Dear Spartan-3A, Please Please WAKE UP!
118708: 07/05/02: Re: DDR2 with Spartan-3A anybody having success??
118725: 07/05/02: Re: My Dear Spartan-3A, Please Please WAKE UP! SUCCESS!!
118747: 07/05/03: Re: My Dear Spartan-3A, Please Please WAKE UP! SUCCESS!!
118749: 07/05/03: First MicroBlaze demo design for Spartan-3A Starterkit
118751: 07/05/03: Re: Video scaler for Spartan 3E?
118759: 07/05/03: Re: Wait-for / until won't work ? Xilinx Spartan 3
118761: 07/05/03: Re: Wait-for / until won't work ? Xilinx Spartan 3
118766: 07/05/03: Re: Wait-for / until won't work ? Xilinx Spartan 3
118768: 07/05/03: Re: Wait-for / until won't work ? Xilinx Spartan 3
118773: 07/05/03: Re: Xilinx software quality - how low can it go ?!
118780: 07/05/03: Re: Xilinx software quality - how low can it go ?!
118782: 07/05/03: Re: Xilinx software quality - how low can it go ?!
118789: 07/05/03: Re: Xilinx software quality - how low can it go ?!
118790: 07/05/03: Re: Xilinx software quality - how low can it go ?!
118799: 07/05/03: Re: Select pullup, pulldown or none via embedded S/W
118816: 07/05/04: Re: JTAG Loader tools won't execute
118818: 07/05/04: Re: Spartan 3A Starter Kit Multiboot Demo Config 4 Display Problem
118825: 07/05/04: Re: JTAG Loader tools won't execute
118873: 07/05/04: Re: Spartan 3A Starter Kit Multiboot Demo Config 4 Display Problem
118883: 07/05/05: EDK OPB_SPI in slave mode
118896: 07/05/06: Re: Spartan 3A Starter Kit Multiboot Demo Config 4 Display Problem
118898: 07/05/07: Re: My Dear Spartan-3A, Please Please WAKE UP!
118900: 07/05/07: Re: Disable Readback (XILINX)?
118902: 07/05/07: Re: My Dear Spartan-3A, Please Please WAKE UP!
118958: 07/05/08: An Open-Source suggestion for Xilinx
118959: 07/05/08: Re: My Dear Spartan-3A, Please Please WAKE UP!
118960: 07/05/08: Re: Xilinx software quality - how low can it go ?!
118962: 07/05/08: Re: Chipscope with custom cable?
118963: 07/05/08: Re: Xilinx software quality - how low can it go ?!
118965: 07/05/08: Re: Xilinx software quality - how low can it go ?!
118971: 07/05/08: Re: First MicroBlaze demo design for Spartan-3A Starterkit
118975: 07/05/08: Re: First MicroBlaze demo design for Spartan-3A Starterkit
118978: 07/05/08: Re: Xilinx software quality - how low can it go ?!
119004: 07/05/09: Re: First MicroBlaze demo design for Spartan-3A Starterkit
119017: 07/05/09: Re: An Open-Source suggestion for Xilinx
119044: 07/05/09: Re: Chipscope with custom cable?
119050: 07/05/10: Re: Gain and Offset Correction
119054: 07/05/10: Re: Gain and Offset Correction
119057: 07/05/10: Altera enters as second the low-cost multigigabit tranceiver FPGA scene!!
119059: 07/05/10: Re: Accessing SRAM on the Spartan-3 Starter Board
119149: 07/05/13: Re: An Open-Source suggestion for Xilinx
119152: 07/05/14: Re: Digital gain and offset correction
119153: 07/05/14: Spartan-3A StarterKit, DDR2, WebServer EVERYTHING WORKS, tested ;)
119155: 07/05/14: Re: Xilinx software quality - how low can it go ?!
119159: 07/05/14: Re: Spartan-3A StarterKit, DDR2, WebServer EVERYTHING WORKS, tested ;)
119160: 07/05/14: Re: Xilinx software quality - how low can it go ?!
119162: 07/05/14: Re: Digital gain and offset correction
119167: 07/05/14: Re: Spartan-3A StarterKit, DDR2, WebServer EVERYTHING WORKS, tested ;)
119213: 07/05/15: Re: How low DDR2 Clock Frequency can be? To make it work on FPGA.
119217: 07/05/15: Re: Digital gain and offset correction
119224: 07/05/15: debit- xilinx bitstream decompiler project has been vanished? or does someone know the URL
119228: 07/05/15: Re: How low DDR2 Clock Frequency can be? To make it work on FPGA.
119230: 07/05/15: Re: reading IDCODE from parallel bus?
119232: 07/05/15: Re: Xilinx EDK: Slow OPB write speeds
119280: 07/05/16: Re: Video scaler for Spartan 3E?
119282: 07/05/16: Re: how to delay a signal in virtex FPGA
119422: 07/05/18: Single Chip MSX computer full schematic and VHDL sources
119441: 07/05/18: releasing some FPGA tools-ip as open-source
119448: 07/05/19: Re: releasing some FPGA tools-ip as open-source
119456: 07/05/20: Re: releasing some FPGA tools-ip as open-source
119468: 07/05/21: Re: Single Chip MSX computer full schematic and VHDL sources
119474: 07/05/21: Re: Single Chip MSX computer full schematic and VHDL sources
119495: 07/05/21: Re: Single Chip MSX computer full schematic and VHDL sources
119517: 07/05/21: Re: Atmel release Metal Programmable Cell Fabric uC ARM9
119529: 07/05/22: Re: using FPGA JTAG as GPIO
119579: 07/05/23: Re: Config PROM for Spartan II
119580: 07/05/23: Re: JTAG FPGA Debugging
119622: 07/05/23: Altera Cyclone II - used in 100USD Laptop
119629: 07/05/24: Re: SATA OOB detection with Virtex5
119638: 07/05/24: Re: Altera Cyclone II - used in 100USD Laptop
119641: 07/05/24: Re: 6502 and CPU licences in general
119647: 07/05/24: Re: How can i command bit Inputs in an FPGA board?
119721: 07/05/25: Re: Use BRAM as ROM (Xilinx)
119728: 07/05/25: Re: How can I perform Boundary Scan Testing on Altera Cyclone II FPGAs using JTAG?
119737: 07/05/25: Re: Has anyone used Sundance Boards?.
119739: 07/05/25: Re: ML505 : beginners problems
119750: 07/05/25: Re: Use BRAM as ROM (Xilinx)
119752: 07/05/25: Re: Has anyone used Sundance Boards?.
119773: 07/05/25: Re: PC to JTAG
119777: 07/05/25: Re: PC to JTAG
119778: 07/05/25: Re: Interfacing EDK application code with Specific BRAMs on FPGA
119779: 07/05/25: Re: HI EVERYBODY PLEASE.... HELP REGARDING DDR 2 CONTROLLER
119782: 07/05/25: Re: Interfacing EDK application code with Specific BRAMs on FPGA
119852: 07/05/28: Re: Atmel FPSLIC users out there?
119865: 07/05/28: Re: accesing JTAG ports on GPIOs
119889: 07/05/29: Re: ML505 : beginners problems
119891: 07/05/29: Re: ML505 : beginners problems
119892: 07/05/29: Re: ML505 : beginners problems
119897: 07/05/29: Re: Microchip ICD on FPGA
119963: 07/05/30: Re: ML505 : beginners problems
119964: 07/05/30: Re: accesing JTAG ports on GPIOs
120092: 07/05/31: Re: accesing JTAG ports on GPIOs
120093: 07/05/31: s3 starterkit problem
120094: 07/05/31: Actel Cortex M1, any info on license fee?
120095: 07/05/31: Re: Cyclone 3 Starter Board Question
120097: 07/05/31: Re: accesing JTAG ports on GPIOs
120099: 07/06/01: Re: VHDL core for Hitachi H8S or H8/300H CPU?
120108: 07/06/01: Re: Actel Cortex M1, any info on license fee?
120127: 07/06/01: Re: Bootloader in BRAM to run a program loaded in the DDR
120131: 07/06/01: Re: Bootloader in BRAM to run a program loaded in the DDR
120142: 07/06/01: Re: Cyclone 3 Starter Board Question
120163: 07/06/01: Re: xilinx parallel cable troubles
120234: 07/06/04: Lattice XP2 finally announced
120238: 07/06/04: Re: Lattice XP2 finally announced
120300: 07/06/05: Re: Lattice XP2 finally announced
120310: 07/06/05: Re: Lattice XP2 finally announced
120323: 07/06/05: Re: ARM in FPGA's?
120332: 07/06/05: Re: ARM in FPGA's?
120519: 07/06/08: FPGA with ARM+CAN+USB+ethernet+ADC
120528: 07/06/08: Re: FPGA with ARM+CAN+USB+ethernet+ADC
120529: 07/06/08: Re: Lattice's Online Store Now Sells Silicon - No Minimum Order Quantity
120548: 07/06/09: Re: Lattice's Online Store Now Sells Silicon - No Minimum Order Quantity
120559: 07/06/10: Re: Lattice's Online Store Now Sells Silicon - No Minimum Order Quantity
120632: 07/06/12: Re: Lattice's Online Store Now Sells Silicon - No Minimum Order Quantity
120707: 07/06/14: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
120821: 07/06/18: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
120859: 07/06/19: Re: spartan 3A : DDR2 controller
120862: 07/06/19: Re: Could I use the opencore ddr_sdr core (for SDRAM) in Xilinx Platform Studio (C code)?
120867: 07/06/19: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
120871: 07/06/19: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
120873: 07/06/19: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
120874: 07/06/19: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
120909: 07/06/20: Re: How to use UART on Spartan 3E Starter Kit
120955: 07/06/21: Re: Can anyone identify the manufacturer of this Chip ?
120956: 07/06/21: Re: Does anyone modify the opencore ddr_sdr for DDR Sdram for internal feedback?
120959: 07/06/21: Re: Can anyone identify the manufacturer of this Chip ?
120960: 07/06/21: Re: Does anyone modify the opencore ddr_sdr for DDR Sdram for internal feedback?
120963: 07/06/21: Re: Can anyone identify the manufacturer of this Chip ?
120964: 07/06/21: Re: Does anyone modify the opencore ddr_sdr for DDR Sdram for internal feedback?
120966: 07/06/21: Re: Can anyone identify the manufacturer of this Chip ?
120970: 07/06/21: Re: Can anyone identify the manufacturer of this Chip ?
120975: 07/06/21: Re: Can anyone identify the manufacturer of this Chip ?
120976: 07/06/21: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
120984: 07/06/21: Re: Can anyone identify the manufacturer of this Chip ?
120985: 07/06/21: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
120988: 07/06/21: Re: Can anyone identify the manufacturer of this Chip ?
120989: 07/06/21: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
120990: 07/06/21: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
120991: 07/06/21: Re: Can anyone identify the manufacturer of this Chip ?
120999: 07/06/21: Re: Can anyone identify the manufacturer of this Chip ?
121074: 07/06/25: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
121075: 07/06/25: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
121126: 07/06/26: Re: Amontec chameleon
121165: 07/06/27: Re: Adding opb AC97 Controler in Xilinx EDK 8.2
121391: 07/07/03: Re: Spartan-3e JTAG no device id
121397: 07/07/03: Re: Spartan-3e JTAG no device id
121466: 07/07/05: Re: Spartan-3e JTAG no device id
121501: 07/07/05: Re: SOLVED: Spartan-3e JTAG no device id
121503: 07/07/05: Re: Xilinx ISE, EDK and some ground roules in software development
121561: 07/07/08: Re: USB analyzer evaluation
121674: 07/07/11: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121678: 07/07/11: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121723: 07/07/12: Re: Altera MAX III Status ?
122000: 07/07/17: Xilinx S3 Starterkit, how hot it is supposed to be?
122063: 07/07/18: Re: Xilinx S3 Starterkit, how hot it is supposed to be?
122087: 07/07/19: Re: Xilinx S3 Starterkit, how hot it is supposed to be?
122105: 07/07/19: Re: Xilinx S3 Starterkit, how hot it is supposed to be?
122123: 07/07/19: Re: How do I use Lattice Mico32's debug-engine on a non-Lattice FPGA?
122135: 07/07/19: Re: Xilinx S3 Starterkit, how hot it is supposed to be?
122136: 07/07/20: Re: SDRAM vs DDR2 on Spartan3E
122297: 07/07/25: Re: Virtex-5 and powerpc
122314: 07/07/25: Re: Virtex-5 and powerpc...its alive....
122320: 07/07/25: Re: Virtex-5 and powerpc...its alive....
122428: 07/07/27: Re: Can Xilinx and Altera be on the same JTAG chain for programming?
122484: 07/07/28: Re: spartan-3e spi problems
122493: 07/07/29: Xilinx something happening with Spartan-3?
122494: 07/07/29: Re: spartan-3e spi problems
122495: 07/07/29: Re: EDK 9.1.02i warnings flood
122512: 07/07/30: Re: Microblaze Interrupt Handler
122518: 07/07/30: Re: completely open source fpga toolchain
122525: 07/07/30: Re: Website
122545: 07/07/31: Re: Looking for 2 simple Xilinx examples of FSL
122554: 07/07/31: Re: Looking for 2 simple Xilinx examples of FSL
122555: 07/07/31: Re: Looking for PLD with embedded memory
122573: 07/07/31: Re: Upgrading from EDK 8.1 to EDK 9.1i
122651: 07/08/02: Re: DOSFS for EDK
122653: 07/08/02: Re: DOSFS for EDK
122734: 07/08/05: Re: OpenSPARC
122751: 07/08/06: Re: new to the group
122762: 07/08/06: Re: Need suggestion for my project
122787: 07/08/07: Re: Need suggestion for my project
122968: 07/08/13: Xilinx 13th August opportunity
122969: 07/08/13: Re: New Xilinx forum.
122971: 07/08/13: Re: New Xilinx forum.
122975: 07/08/13: Re: Xilinx 13th August opportunity
122980: 07/08/13: Re: New Xilinx forum.
122983: 07/08/13: Re: New Xilinx forum.
122984: 07/08/13: Re: New Xilinx forum.
122987: 07/08/13: Re: Xilinx 13th August opportunity
123002: 07/08/14: new xilinx forums
123005: 07/08/14: Re: edk + spi
123089: 07/08/16: Re: DDR2 @ 400 MHz and Xilinx Spartan-3A[N] kits
123098: 07/08/16: Re: Fighting with Compact Flash
123149: 07/08/17: Re: Actel APA1000 and JTAG
123150: 07/08/17: Re: Slice equation in bitstream
123154: 07/08/17: Re: Slice equation in bitstream
123160: 07/08/17: Re: Slice equation in bitstream
123168: 07/08/17: Re: Minimal power?
123210: 07/08/20: Re: MCS -> BIT
123220: 07/08/20: Re: GPIO_performance
123687: 07/09/01: Re: Memory bandwidth of the 3A kit
123688: 07/09/01: Re: Chip Designing made Easy
124420: 07/09/21: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
124421: 07/09/21: Re: how interfacing of cpld and cpu done?
124423: 07/09/21: Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
124483: 07/09/24: Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
124616: 07/09/28: FPGA NTSC signal with 2 resistors and PWM
124618: 07/09/28: Re: FPGA NTSC signal with 2 resistors and PWM
124620: 07/09/28: Re: FPGA NTSC signal with 2 resistors and PWM
124625: 07/09/28: Re: FPGA NTSC signal with 2 resistors and PWM
124629: 07/09/28: 2 leg crystal on FPGA: Lattice vs Xilinx
124631: 07/09/28: Re: Programming the ARM7 used to download our Xilinx FPGA
124649: 07/09/29: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
124651: 07/09/29: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
124652: 07/09/29: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
124653: 07/09/29: Re: FPGA NTSC signal with 2 resistors and PWM
124674: 07/09/29: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
124680: 07/09/30: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
124681: 07/09/30: www.fpga-games.com website died?
124712: 07/10/01: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
124753: 07/10/03: Re: FPGA NTSC signal with 2 resistors and PWM
124878: 07/10/09: Re: Need suggestion on FPGA kit
125006: 07/10/15: FPGA quiz: what can be wrong
125009: 07/10/15: Re: FPGA quiz: what can be wrong
125013: 07/10/15: Re: FPGA quiz: what can be wrong
125015: 07/10/15: Re: FPGA quiz: what can be wrong
125018: 07/10/15: Re: FPGA quiz: what can be wrong
125020: 07/10/15: Re: FPGA quiz: what can be wrong
125036: 07/10/16: Re: FPGA quiz: what can be wrong
125037: 07/10/16: Re: FPGA quiz: what can be wrong
125038: 07/10/16: Re: FPGA quiz: what can be wrong
125039: 07/10/16: Re: FPGA quiz: what can be wrong
125040: 07/10/16: Re: FPGA quiz: what can be wrong
125041: 07/10/16: Re: FPGA quiz: what can be wrong
125042: 07/10/16: Re: FPGA quiz: what can be wrong
125045: 07/10/16: Re: FPGA quiz: what can be wrong
125047: 07/10/16: FPGA quiz2: spartan3A return Virtex JTAGID. Also prizes for quiz1 and quiz2
125053: 07/10/16: Re: FPGA quiz: what can be wrong
125059: 07/10/16: Re: FPGA quiz: what can be wrong
125060: 07/10/16: Re: FPGA quiz: what can be wrong
125061: 07/10/16: Re: FPGA quiz2: spartan3A return Virtex JTAGID. Also prizes for quiz1 and quiz2
125062: 07/10/16: Re: FPGA quiz: what can be wrong
125063: 07/10/16: Re: FPGA quiz: what can be wrong
125086: 07/10/16: Re: FPGA quiz: what can be wrong
125089: 07/10/16: Re: FPGA quiz: what can be wrong
125090: 07/10/16: Re: FPGA quiz: what can be wrong
125093: 07/10/16: Re: FPGA quiz: what can be wrong
125096: 07/10/16: Re: FPGA quiz: what can be wrong
125097: 07/10/16: Re: FPGA quiz: what can be wrong
125098: 07/10/16: Re: FPGA quiz: what can be wrong
125099: 07/10/16: Re: FPGA quiz: what can be wrong
125100: 07/10/16: Re: FPGA quiz2: spartan3A return Virtex JTAGID. Also prizes for quiz1 and quiz2
125105: 07/10/16: Re: FPGA quiz: what can be wrong
125107: 07/10/16: Re: FPGA quiz: what can be wrong
125108: 07/10/16: Re: FPGA quiz: what can be wrong
125111: 07/10/16: Re: FPGA quiz: what can be wrong
125112: 07/10/16: Re: FPGA quiz: what can be wrong
125114: 07/10/16: Re: FPGA quiz: what can be wrong
125115: 07/10/16: Re: FPGA quiz: what can be wrong
125127: 07/10/16: Re: FPGA quiz2: spartan3A return Virtex JTAGID. Also prizes for quiz1 and quiz2
125128: 07/10/16: Re: FPGA quiz: what can be wrong
125141: 07/10/16: Re: FPGA quiz: what can be wrong
125146: 07/10/16: Re: FPGA quiz: what can be wrong
125151: 07/10/16: Re: FPGA quiz: what can be wrong
125157: 07/10/17: Re: FPGA quiz: what can be wrong
125160: 07/10/17: Re: FPGA quiz: what can be wrong
125162: 07/10/17: Re: FPGA quiz: what can be wrong
125164: 07/10/17: Re: FPGA quiz: what can be wrong
125165: 07/10/17: Re: FPGA quiz: what can be wrong
125172: 07/10/17: Re: FPGA quiz: what can be wrong
125177: 07/10/17: Re: FPGA quiz2: spartan3A return Virtex JTAGID. Also prizes for quiz1 and quiz2
125178: 07/10/17: FPGA quiz 1&2, we have the answers and winners
125193: 07/10/17: Re: FPGA quiz 1&2, we have the answers and winners
125194: 07/10/17: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround
125195: 07/10/17: Re: FPGA quiz 1&2, we have the answers and winners
125200: 07/10/17: Re: xil_printf and %u specifier
125202: 07/10/17: Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround
125216: 07/10/18: Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround
125219: 07/10/18: Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround
125220: 07/10/18: Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround
125226: 07/10/18: Re: xilinx Edititons
125228: 07/10/18: Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround
125231: 07/10/18: Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround
125233: 07/10/18: Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround
125235: 07/10/18: Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround
125236: 07/10/18: Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround
125238: 07/10/18: Re: Dynamic Reconfiguration books
125270: 07/10/18: Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround
125314: 07/10/20: Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround
125326: 07/10/22: Re: microprocessor on fpga problems
125346: 07/10/22: Re: microprocessor on fpga problems
125356: 07/10/23: Re: Nios II, ThreadX, NetX Anyone?
125368: 07/10/24: Re: Changing refresh rate for DRAM while in operation?
125373: 07/10/24: Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround
125395: 07/10/24: Re: Programming Atmel dataflash with xilinx impact
125416: 07/10/25: Re: xilinx spi flash programming
125421: 07/10/25: Re: xilinx spi flash programming
125422: 07/10/25: is Quartus 7.1 really that S*** !?
125428: 07/10/25: Re: xilinx spi flash programming
125429: 07/10/25: Re: is Quartus 7.1 really that S*** !?
125469: 07/10/26: Re: is Quartus 7.1 really that S*** !?
125471: 07/10/26: Re: Changing refresh rate for DRAM while in operation?
125476: 07/10/26: Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
125477: 07/10/26: "SPI indirect" programming for any FPGA/CPLD
125485: 07/10/26: Re: is Quartus 7.1 really that S*** !?
125490: 07/10/26: Re: is Quartus 7.1 really that S*** !?
125509: 07/10/26: Re: XMD with CableServer OR remote EDK solution
125523: 07/10/27: Re: Bitfile checking
125557: 07/10/29: Re: FPGA Configuration
125569: 07/10/29: Re: XMD with CableServer OR remote EDK solution
125577: 07/10/29: Re: Bitfile checking
125579: 07/10/29: Re: Is it possible to check how cache memories are mapped to FPGA block rams?
125592: 07/10/29: Re: Bitfile checking
125606: 07/10/30: Re: FPGA Configuration
125607: 07/10/30: Re: IDE to Flash memory
125610: 07/10/30: X3100A design with Synplify 8.8 and foundation 1.5 possible?
125632: 07/10/30: Re: X3100A design with Synplify 8.8 and foundation 1.5 possible?
125651: 07/10/31: Re: IDE to Flash memory
125653: 07/10/31: Re: Is it possible to debug a vhdl design over jtag?
125665: 07/10/31: Re: Capability of a FPGA device.
125669: 07/10/31: Re: xilinx bmm file problem
125813: 07/11/06: Re: Linux capable free/GPL SOFT CPU for XC3S500E?
125932: 07/11/09: Re: Xilinx Parallel Cable IV, API spec
125963: 07/11/10: Re: Xilinx Parallel Cable IV, API spec
125997: 07/11/12: Re: Xilinx Parallel Cable IV, API spec
126173: 07/11/16: Re: USR_ACCESS_VIRTEX4 usage
127354: 07/12/19: Re: BGA reflow soldering using vapor phase
127363: 07/12/19: Re: BGA reflow soldering using vapor phase
127428: 07/12/24: cable IV and platform USB cable API now officially public
127941: 08/01/10: Re: cable IV and platform USB cable API now officially public
127945: 08/01/10: Re: Can you help me about SAS IP core implementing
127947: 08/01/10: Re: Can you help me about SAS IP core implementing
128421: 08/01/25: Re: Initialize RAM in IGLOO
128425: 08/01/25: Re: Initialize RAM in IGLOO
128482: 08/01/28: My first Flash FPGA
128500: 08/01/28: Re: My first Flash FPGA
128501: 08/01/28: Re: My first Flash FPGA
128674: 08/02/03: Re: spartan3a support DVI ?
128675: 08/02/03: Re: My first Flash FPGA
128786: 08/02/06: Re: My first Flash FPGA
128834: 08/02/07: Re: Prom alternatives for xilinx
128849: 08/02/07: Re: I/O mode to use for USB ..?
128868: 08/02/07: Re: I/O mode to use for USB ..?
128901: 08/02/09: ANN CPLD add-on module for Nintendo DS game console
128909: 08/02/09: Re: ANN CPLD add-on module for Nintendo DS game console
128915: 08/02/09: Re: Prom alternatives for xilinx
128950: 08/02/11: Re: Virtex5 DCM lower limit
128985: 08/02/12: Re: XiRisc softcore processor
129160: 08/02/16: Re: Ballpark PLB frequency
129170: 08/02/17: Embedded in Nurnberg
129191: 08/02/18: MicroBlaze simulator, software ownership rights for SALE
129202: 08/02/18: Re: Antti needs a job
129203: 08/02/18: Re: Ballpark PLB frequency
129204: 08/02/18: Re: V4FX100 PowerPC PLB issues (and EDK 9.2)
129208: 08/02/18: Re: Ballpark PLB frequency
129281: 08/02/19: Re: Ballpark PLB frequency
129287: 08/02/20: Re: FPGA Programming solution
129292: 08/02/20: Re: FPGA Programming solution
129293: 08/02/20: Re: Antti needs a job
129294: 08/02/20: Re: Ballpark PLB frequency
129299: 08/02/20: Re: FPGA Programming solution
129307: 08/02/20: Re: MicroBlaze simulator, software ownership rights for SALE
129346: 08/02/21: Re: Reconfiguration (on the fly) using SPARTAN 3A
129351: 08/02/21: Re: Reconfiguration (on the fly) using SPARTAN 3A
129370: 08/02/22: Re: Reconfiguration (on the fly) using SPARTAN 3A
129379: 08/02/22: Xilinx self-termination
129384: 08/02/22: Re: Reconfiguration (on the fly) using SPARTAN 3A
129389: 08/02/22: Re: ICAP in SPARTAN 3A
129391: 08/02/22: Re: Reconfiguration (on the fly) using SPARTAN 3A
129395: 08/02/22: Actel FPGA programming using libero 8.1 generated SVF files
129396: 08/02/22: Re: Reconfiguration (on the fly) using SPARTAN 3A
129397: 08/02/22: Re: Actel FPGA programming using libero 8.1 generated SVF files
129420: 08/02/22: Re: Reconfiguration (on the fly) using SPARTAN 3A
129449: 08/02/24: Re: more microblaze firmware blues. tool chain version problem?
129467: 08/02/25: Re: Xilinx parallel cable 4 clone
129534: 08/02/27: Re: How to connect FPGA to a ASIC Board?
129536: 08/02/27: Re: How to connect FPGA to a ASIC Board?
129539: 08/02/27: Re: SPI indirect programming using spartan 3e
129544: 08/02/27: Tomorrow at Embeded in Nurnberg: Portable XSVF player demo
129553: 08/02/27: Re: SPI indirect programming using spartan 3e
129583: 08/02/27: Re: sd card slave interface
129617: 08/02/28: Re: Is there any way to disable JTAG for Sptantan3AN
129622: 08/02/29: Re: Is there any way to disable JTAG for Sptantan3AN
129642: 08/03/01: FPGA's be afraid, very afraid, of my wife!
129645: 08/03/01: Re: FPGA's be afraid, very afraid, of my wife!
129678: 08/03/02: Re: Is there any way to disable JTAG for Sptantan3AN
129679: 08/03/02: Virtex-5 FXT coming soon?
129683: 08/03/03: Re: Virtex-5 FXT coming soon?
129685: 08/03/03: Re: Is there any way to disable JTAG for Sptantan3AN
129696: 08/03/03: Re: Virtex-5 FXT coming soon?
129707: 08/03/03: my Spartan-4 wishlist
129716: 08/03/03: Re: my Spartan-4 wishlist
129745: 08/03/04: Re: my Spartan-4 wishlist
129765: 08/03/04: Re: my Spartan-4 wishlist
129776: 08/03/05: Re: my Spartan-4 wishlist
129787: 08/03/05: Anyone to open "FPGA museum" ? Here is first item :)
129790: 08/03/05: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
129794: 08/03/05: Re: Anyone to open "FPGA museum" ? Here is first item :)
129795: 08/03/05: Re: Spartan-3E + SPI EEPROM
129820: 08/03/05: Re: Anyone to open "FPGA museum" ? Here is first item :)
129821: 08/03/05: Re: Anyone to open "FPGA museum" ? Here is first item :)
129823: 08/03/05: Re: Anyone to open "FPGA museum" ? Here is first item :)
129859: 08/03/07: Re: Spartan-3E + SPI EEPROM
129884: 08/03/07: Re: SiliconBlue enters the FPGA fray
130002: 08/03/12: Re: SiliconBlue enters the FPGA fray
130006: 08/03/12: Re: SiliconBlue enters the FPGA fray
130048: 08/03/13: Actel PA3 with DirectC or SVF, anybody had any success?
130051: 08/03/14: Re: Actel PA3 with DirectC or SVF, anybody had any success?
130053: 08/03/14: Re: DDR3 speed, Altera vs Xilinx
130059: 08/03/14: Re: Actel PA3 with DirectC or SVF, anybody had any success?
130062: 08/03/14: Re: Actel PA3 with DirectC or SVF, anybody had any success?
130065: 08/03/14: Re: Xilinx S3DSP + EDK Board, too good to be true?
130070: 08/03/14: Re: DDR3 speed, Altera vs Xilinx
130084: 08/03/14: Re: DDR3 speed, Altera vs Xilinx
130085: 08/03/14: Re: Actel PA3 with DirectC or SVF, anybody had any success?
130087: 08/03/14: Re: Xilinx S3DSP + EDK Board, too good to be true?
130089: 08/03/14: Re: SiliconBlue enters the FPGA fray
130090: 08/03/14: Re: DDR3 speed, Altera vs Xilinx
130092: 08/03/14: Re: Xilinx S3DSP + EDK Board, too good to be true?
130095: 08/03/14: Re: DDR3 speed, Altera vs Xilinx
130096: 08/03/14: Re: DDR3 speed, Altera vs Xilinx
130117: 08/03/15: Re: DDR3 speed, Altera vs Xilinx
130124: 08/03/15: Re: SiliconBlue enters the FPGA fray
130128: 08/03/15: Re: SiliconBlue enters the FPGA fray
130130: 08/03/16: Re: Problem with Spartan 3 StarterKit
130131: 08/03/16: ISE 9.2SP4 error
130132: 08/03/16: Re: ISE 9.2SP4 error
130134: 08/03/16: Re: Need help in SDR
130135: 08/03/16: Xilinx impact, boldly going into nightmareland
130142: 08/03/16: Re: Wondering about "LatticeMico32 Open Source Licensing"
130143: 08/03/16: Re: DDR3 speed, Altera vs Xilinx
130152: 08/03/17: Re: ISE 9.2SP4 error
130157: 08/03/17: Re: ISE 9.2SP4 error
130162: 08/03/17: Re: Designing CPU
130165: 08/03/17: Re: ISE 9.2SP4 error
130166: 08/03/17: Re: Wondering about "LatticeMico32 Open Source Licensing"
130173: 08/03/17: Re: Xilinx Webcase Workflow
130210: 08/03/17: Re: DDR3 speed, Altera vs Xilinx
130217: 08/03/18: Re: Designing CPU
130261: 08/03/18: A Challenge for serialized processor design and implementation
130307: 08/03/20: Re: A Challenge for serialized processor design and implementation
130316: 08/03/20: Re: Configure Spartan-3E w SD-Card?
130319: 08/03/20: Re: Configure Spartan-3E w SD-Card?
130325: 08/03/20: Re: Configure Spartan-3E w SD-Card?
130328: 08/03/20: Re: Configure Spartan-3E w SD-Card?
130391: 08/03/21: Re: A Challenge for serialized processor design and implementation
130407: 08/03/22: Re: Actel PA3 with DirectC or SVF, anybody had any success?
130458: 08/03/24: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
130459: 08/03/24: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
130461: 08/03/25: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
130462: 08/03/25: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
130467: 08/03/25: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
130468: 08/03/25: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
130471: 08/03/25: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
130481: 08/03/25: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
130486: 08/03/25: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
130490: 08/03/25: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
130492: 08/03/25: new Virtex-5 info
130641: 08/03/29: async clk input, clock glitches
130656: 08/03/29: Re: async clk input, clock glitches
130657: 08/03/29: Re: async clk input, clock glitches
130662: 08/03/29: Re: async clk input, clock glitches
130674: 08/03/30: Re: ISE 10.1 - Initial experience
130675: 08/03/30: Re: async clk input, clock glitches
130676: 08/03/30: Re: async clk input, clock glitches
130678: 08/03/30: Re: async clk input, clock glitches
130683: 08/03/30: Re: async clk input, clock glitches
130684: 08/03/30: Re: async clk input, clock glitches
130688: 08/03/30: Re: ISE 10.1 - Initial experience
130693: 08/03/30: Re: async clk input, clock glitches
130697: 08/03/30: Re: async clk input, clock glitches
130701: 08/03/30: Re: async clk input, clock glitches
130703: 08/03/30: Re: async clk input, clock glitches
130710: 08/03/30: Re: fpga reset (re-initialize) of spartan3e
130727: 08/03/31: Re: A Challenge for serialized processor design and implementation
130730: 08/03/31: Re: ISE 10.1 - Initial experience
130731: 08/03/31: Re: fpga reset (re-initialize) of spartan3e
130733: 08/03/31: Re: ISE 10.1 - Initial experience
130736: 08/03/31: Re: JTAG: First of 4 Spartan-3E always UNKNOWN
130741: 08/03/31: Re: JTAG: First of 4 Spartan-3E always UNKNOWN
130742: 08/03/31: Re: Impact won't program XC3S200, does program XC3SD1800A
130745: 08/03/31: Re: ISE 10.1 - Initial experience
130767: 08/04/01: Re: JTAG: First of 4 Spartan-3E always UNKNOWN
130783: 08/04/01: Re: Antii, can you give us an update?
130789: 08/04/01: Re: Antii, can you give us an update?
130815: 08/04/02: Re: Antii, can you give us an update?
130834: 08/04/03: EDK 10.1 first impressions
130835: 08/04/03: Re: EDK 10.1 first impressions
130837: 08/04/03: Re: Protecting design from being downloaded on other (similar) FPGA
130862: 08/04/03: Re: EDK 10.1 first impressions
130881: 08/04/04: Re: Protecting design from being downloaded on other (similar) FPGA
130882: 08/04/04: Re: Protecting design from being downloaded on other (similar) FPGA
130921: 08/04/04: Re: Antii, can you give us an update?
130929: 08/04/05: Re: Antii, can you give us an update?
130933: 08/04/05: Re: Protecting design from being downloaded on other (similar) FPGA
130943: 08/04/06: Re: Antii, can you give us an update?
130957: 08/04/06: Xilinx xilfatfs and systemACE speed issue
130968: 08/04/07: Re: FPGA configuration mode on ML310
130980: 08/04/07: Re: Xilinx xilfatfs and systemACE speed issue
130995: 08/04/08: Re: Modify POF with new ESB (ROM) content?
130996: 08/04/08: Re: Xilinx xilfatfs and systemACE speed issue
131000: 08/04/08: Re: Modify POF with new ESB (ROM) content?
131006: 08/04/08: Re: Modify POF with new ESB (ROM) content?
131016: 08/04/08: Re: Modify POF with new ESB (ROM) content?
131024: 08/04/08: Re: Modify POF with new ESB (ROM) content?
131075: 08/04/09: Re: A Challenge for serialized processor design and implementation
131144: 08/04/12: CF (systemace) SD card, etc performance
131154: 08/04/13: Re: CF (systemace) SD card, etc performance
131517: 08/04/24: Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860
131524: 08/04/24: Re: HydraXC + EDK
131525: 08/04/24: Re: video stream transfer via UART and Bluetooth in FPGA
131532: 08/04/24: Re: video stream transfer via UART and Bluetooth in FPGA
131706: 08/04/29: Re: how can i recover my unencrypted bitstream starting from
131707: 08/04/29: Re: HydraXC + EDK
131710: 08/04/29: Re: HydraXC + EDK
131755: 08/05/01: ARM Cortex for Altera available
131758: 08/05/01: Re: ARM Cortex for Altera available
131814: 08/05/02: Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
132308: 08/05/21: Re: Stratix IV Announced
132339: 08/05/22: Re: Stratix IV Announced
132555: 08/05/31: Re: New Xilinx device package options for S3E & S3A
133818: 08/07/16: Re: Low cost solution to program Spartan 3AN DSP development board
133915: 08/07/18: Re: The littlest CPU
133939: 08/07/19: Re: The littlest CPU
133944: 08/07/20: Re: The littlest CPU
134466: 08/08/11: Re: Development board with SD card.
134470: 08/08/12: Re: SDIO open source code
134520: 08/08/16: Re: Development board with SD card.
134612: 08/08/21: Re: Xilinx extends Spartan 3A series
134632: 08/08/21: Re: Xilinx extends Spartan 3A series
134635: 08/08/22: Re: Xilinx extends Spartan 3A series
134646: 08/08/23: Re: Scripting xsvf generation?
134730: 08/08/28: Re: Genode FPGA graphics project launched
134771: 08/08/29: Re: Format of Actel's SVF files
134792: 08/09/01: Re: FPGA on a DIMM module, performing encryption
134794: 08/09/01: ED 9.2 too new cygwin error
134797: 08/09/01: Re: ED 9.2 too new cygwin error
134805: 08/09/01: Re: ED 9.2 too new cygwin error
134806: 08/09/01: Re: ED 9.2 too new cygwin error
134810: 08/09/02: FPGA package size chart (smallest) Xilinx holds 8th place
134814: 08/09/02: Re: FPGA package size chart (smallest) Xilinx holds 8th place
134891: 08/09/04: Re: uClinux / Microblaze -- Min. Requirements
134897: 08/09/05: Re: uClinux / Microblaze -- Min. Requirements
134917: 08/09/06: Re: Some feedback on the Xilinx web site
135084: 08/09/15: Re: Ultra low power FPGAs
135724: 08/10/13: Re: writing files to micro-SD with spartan 3e
135771: 08/10/15: Re: writing files to micro-SD with spartan 3e
137051: 08/12/21: Programming Actel A3P with SVF files
137055: 08/12/21: Re: Programming Actel A3P with SVF files
137172: 08/12/30: Xilinx QUIZ 2008
137174: 08/12/30: Re: Xilinx QUIZ 2008
137178: 08/12/30: Re: FPGA/CPLD Design Group on LinkedIn
137180: 08/12/30: Re: Digilent
137186: 08/12/30: Re: FPGA/CPLD Design Group on LinkedIn
137203: 09/01/02: Re: Xilinx QUIZ 2008
137204: 09/01/02: Re: Xilinx QUIZ 2008
137223: 09/01/04: Re: Xilinx QUIZ 2008
137229: 09/01/04: Re: Xilinx QUIZ 2008
137418: 09/01/15: MPMC2 v1.9 question: IMMEDIATE cash reward 500EUR for the solution.
137435: 09/01/16: Re: Actel IGLOO FPGA has lower power consumption then Xilinx
137528: 09/01/21: Re: FPGA granularity
137551: 09/01/21: Re: FPGA granularity
137576: 09/01/22: IDEA: boxing sacks with "XILINX" logo
137578: 09/01/22: Re: MPMC2 v1.9 question: IMMEDIATE cash reward 500EUR for the
137579: 09/01/22: Re: Xilinx QUIZ 2008
137598: 09/01/23: Spartan-6
137607: 09/01/23: Re: Spartan-6
137628: 09/01/24: Xilinx web broken again?
137635: 09/01/25: MPCM3/XPS_LL_TEMAC with SFP/1000base-X
137643: 09/01/26: Re: dual MIG controller on spartan 3A DSP
137660: 09/01/26: Re: MPCM3/XPS_LL_TEMAC with SFP/1000base-X
137677: 09/01/27: Re: dual MIG controller on spartan 3A DSP
137716: 09/01/28: Re: MPCM3/XPS_LL_TEMAC with SFP/1000base-X
137724: 09/01/28: Re: Spartan-6
137730: 09/01/28: Re: Replace MAC block with SGMII
137734: 09/01/28: Re: What software do you use for PCB with FPGA ?
137769: 09/01/29: Re: Spartan-6
137836: 09/01/30: Re: Spartan-6
137843: 09/01/31: Actel CoreABC not working in Libero 8.5
137844: 09/01/31: Re: Actel CoreABC not working in Libero 8.5
137860: 09/02/01: Re: Selecting a starter FPGA board
137867: 09/02/01: Re: Actel CoreABC not working in Libero 8.5
137884: 09/02/01: Re: Selecting a starter FPGA board
137893: 09/02/02: Re: Selecting a starter FPGA board
137896: 09/02/02: Re: Selecting a starter FPGA board
137908: 09/02/02: Re: Selecting a starter FPGA board
137911: 09/02/02: Re: Selecting a starter FPGA board
137920: 09/02/02: Re: Spartan-6
137947: 09/02/02: Re: Spartan-6
137962: 09/02/03: Re: Spartan-6
138039: 09/02/04: Re: REWARD $$$ Xilinx USB Platform Cable problems
138041: 09/02/04: Re: Spartan-6
138044: 09/02/04: Antti-Brain issue 5 released
138049: 09/02/04: Re: rs232 uart: testbench vs real world, and the missing first
138051: 09/02/04: Re: Antti-Brain issue 5 released
138073: 09/02/05: Re: FPGA/altera / Configuration logic,decryptor
138079: 09/02/05: Re: dual MIG controller on spartan 3A DSP
138094: 09/02/06: Re: clock generation by divide and reset
138113: 09/02/06: OPB_LCD missing char? quiz+answer :)
138157: 09/02/08: Re: C-NIT source
138162: 09/02/08: Re: Is this phase accumulator trick well-known???
138163: 09/02/08: Re: Is this phase accumulator trick well-known???
138164: 09/02/08: Re: Is this phase accumulator trick well-known???
138167: 09/02/08: Re: Is this phase accumulator trick well-known???
138170: 09/02/08: Re: Is this phase accumulator trick well-known???
138185: 09/02/08: Re: Is this phase accumulator trick well-known???
138209: 09/02/09: Re: Is this phase accumulator trick well-known???
138210: 09/02/09: Re: pulser problem
138213: 09/02/09: Re: Is this phase accumulator trick well-known???
138257: 09/02/10: Re: Xilinx FAT FS library
138280: 09/02/12: Xilinx SGMII/1000Base-X refdesign (PingResponer/Echo server)
138311: 09/02/15: Re: Microblaze (7.10d) Interrupt Handler problems
138317: 09/02/15: Re: UART RS232 "hello world" really taking shape now.
138319: 09/02/16: Re: Microblaze (7.10d) Interrupt Handler problems
138326: 09/02/16: Re: Virtex 5 slave serial config
138332: 09/02/16: DDR3 with Spartan-3
138363: 09/02/17: Re: DDR3 with Spartan-3
138373: 09/02/18: Re: Virtex 5 slave serial config
138385: 09/02/18: Re: Any Experiences with the GN4124 PCI Express - FPGA bridge?
138394: 09/02/19: Re: Spartan-6
138406: 09/02/20: FPGA Stamp
138556: 09/02/27: C.A.F. hello at Embedded World
138566: 09/02/27: ARM11 in Spartan-6
138585: 09/03/01: Antti-Brain issue 6 released
138746: 09/03/07: Embedded World 2009: Antti Brain special issue
138792: 09/03/11: FPGA LVDS for AC-decoupled transmit over CAT-5 cable
138876: 09/03/13: DMCA and Google Groups
139084: 09/03/20: Silicon Blue Warm-Boot not working properly
139145: 09/03/22: Silicon Blue last datesheet correct URL
139200: 09/03/23: Altera's free ColdFire v1 IP core anybody used it?
139243: 09/03/24: Antti Processor
139284: 09/03/25: SiliconBlue on Wikipedia
139349: 09/03/27: best soft core(s) that have C compiler support
139494: 09/04/01: Altera flash FPGA with ColdFire hard core
139619: 09/04/07: ANN: Antti-Brain March issue released
139687: 09/04/08: opencores again with problems?
139716: 09/04/10: S3A starterkit weird behaviou (mini quiz)
139867: 09/04/17: Virtex-6 shipping?
139997: 09/04/23: TODAY, April 27th, says Xilinx
140023: 09/04/24: some soft-processors
140058: 09/04/26: way to go Altera!
140077: 09/04/27: ISE 11.1 drops support for Virtex-2/Pro and Spartan-2/E
140362: 09/05/11: verilog in TV show (soon)
140416: 09/05/13: xilinx 1000-base-X drivers XPS_LL_TEMAC
140469: 09/05/14: ISE multiple UCF files from commandline
140494: 09/05/14: actel block RAM initial value
140557: 09/05/17: soft processor report
140572: 09/05/18: SD card bootstrap code in 55 instructions
140747: 09/05/24: VHDL synthesis difference bwetween tools
140760: 09/05/25: V5 GTX clocking
140935: 09/05/30: patent free ARM cores
140963: 09/06/01: Peter Alfke's 6 EASY
141014: 09/06/02: Xilinx GbE performance
141207: 09/06/11: opencores shut down?
141269: 09/06/15: Xilinx bitstream decompiler has been made and working
141331: 09/06/18: Lattice XP3 any infos leaked? ;)
141450: 09/06/24: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
141508: 09/06/25: opencores again with problems?
141546: 09/06/27: 6/6 infos
141553: 09/06/27: Xilinx USB CABLE SCHEMATIC NOW OFFICIALLY PUBLISED !!!! ::) yippii
141624: 09/07/01: FPGA as FM RADIO transmitter
141928: 09/07/17: Xilinx Platinum Support - I found it! This is me :)
141955: 09/07/19: FM radio with Spartan3A kit, demo
141976: 09/07/20: VIRTEX-6 FXT announced soon?
141994: 09/07/21: VIRTEX-6 FXT announced soon?
142215: 09/07/29: Antti-Brain, should I keep going?
142275: 09/07/31: Antti-Brain JULY Issue released
142415: 09/08/10: delta-signa DAC with FPGA
142532: 09/08/16: Soft Processor IP core report
142632: 09/08/23: xc3sprog support for Altera Byteblaster
142834: 09/09/03: Spartan-6 boards now REALLY in online shops
142993: 09/09/13: Spartan-6 stocked at Digikey
142994: 09/09/14: virtex-6 CXT announced
143045: 09/09/17: WARP PLD's are back in new shape
143083: 09/09/18: Actel dropped ARM7, when comes Xilinx ARM enabled silicon?
143118: 09/09/22: VHDL question
143135: 09/09/22: Estonian Electronics meeting 3 october 2009
143252: 09/09/28: Xilinx RTL view question
143299: 09/09/30: Antti-Brain one year anniversary
143445: 09/10/12: Altera USB blasters as USB-SPI interface with ponyprog
143593: 09/10/17: Re: Any interest in a group Xilinx FPGA board build/buy ??
143595: 09/10/17: Re: Any interest in a group Xilinx FPGA board build/buy ??
143606: 09/10/17: Re: Any interest in a group Xilinx FPGA board build/buy ??
143621: 09/10/18: Re: FPGA programming - Linux
143676: 09/10/20: Re: External IO Port without using Xilinx's GPIO IP
143680: 09/10/20: Re: Done pin won't go high
143736: 09/10/22: Re: External IO Port without using Xilinx's GPIO IP
143759: 09/10/23: Re: ISe 10.1 nightmare bug
143804: 09/10/27: Re: ISe 10.1 nightmare bug
143805: 09/10/27: ANN: new FPGA based USB development tool
143883: 09/10/31: 50+ pages fresh from Antti's brain
143891: 09/11/02: Re: 50+ pages fresh from Antti's brain
143895: 09/11/02: Re: 50+ pages fresh from Antti's brain
143897: 09/11/02: Re: Need some help creating a ring oscillator on a Spartan-3AN
143905: 09/11/02: Re: 50+ pages fresh from Antti's brain
143909: 09/11/02: Re: probelms in EDK/ISE
143912: 09/11/02: Re: 50+ pages fresh from Antti's brain
143915: 09/11/02: Re: Need some help creating a ring oscillator on a Spartan-3AN
143916: 09/11/02: Re: probelms in EDK/ISE
143918: 09/11/03: Re: probelms in EDK/ISE
143934: 09/11/03: Cyclone IV announced
143954: 09/11/04: Re: Cyclone IV announced
143958: 09/11/04: Re: Cyclone IV announced
143961: 09/11/05: CPLD + MCU SoC from Cypress, free samples too!
143972: 09/11/05: Re: Need some help creating a ring oscillator on a Spartan-3AN
143973: 09/11/05: Re: Cyclone IV announced
143975: 09/11/05: Re: Need some help creating a ring oscillator on a Spartan-3AN
143978: 09/11/05: Re: Need some help creating a ring oscillator on a Spartan-3AN
143984: 09/11/05: Re: CPLD + MCU SoC from Cypress, free samples too!
143987: 09/11/05: Re: OK Xilinx users, it's time I was let in on the joke...
144002: 09/11/06: Re: CPLD + MCU SoC from Cypress, free samples too!
144014: 09/11/07: Re: Microblaze performance in V6
144021: 09/11/07: Re: free software/open source projects and FPGA?
144049: 09/11/09: Re: Microblaze performance in V6
144050: 09/11/09: Re: CPLD + MCU SoC from Cypress, free samples too!
144054: 09/11/09: Re: CPLD + MCU SoC from Cypress, free samples too!
144065: 09/11/09: Re: XPLA3 coolrunner programming tool?
144067: 09/11/10: NIOS II/e is FULLY FREE NOW !!!!
144074: 09/11/10: Re: NIOS II/e is FULLY FREE NOW !!!!
144095: 09/11/11: Re: XPLA3 coolrunner programming tool?
144101: 09/11/11: Re: How to interface sgmii core to copper media ?
144129: 09/11/12: Re: what is ngc file
144165: 09/11/16: Re: who have a usb3.0 pipe3 wrapper for xilinx V5/V6 FPGA?
144173: 09/11/17: Too Easy: Actel FPGA's! :)
144178: 09/11/17: Re: Too Easy: Actel FPGA's! :)
144185: 09/11/18: Re: Fast stratix3 JTAG programming?
144209: 09/11/19: Re: ML605 Evaluation Kit and FPGA Mezzanine Connectors (FMC) ?
144211: 09/11/20: Re: Fast stratix3 JTAG programming?
144235: 09/11/21: Re: Stop ISE from trimming signals for a ring oscillator?
144242: 09/11/22: Re: Stop ISE from trimming signals for a ring oscillator?
144321: 09/11/26: Re: 32KHz RTC for FPGA
144326: 09/11/26: Re: some issues with canned oscillators (was Re: 32KHz RTC for FPGA)
144355: 09/11/30: Re: ASIC Prototyping
144402: 09/12/03: Re: A new approach to FPGA and PCB System Development Platform, Santa
144515: 09/12/12: Re: Does a 1-bit mux glitch if only one input is known to change at
144606: 09/12/19: Re: Memory Latency
144612: 09/12/21: Please help, Xilinx FIFO problem!
144614: 09/12/21: Re: Please help, Xilinx FIFO problem!
144616: 09/12/21: Re: Please help, Xilinx FIFO problem!
144620: 09/12/21: Re: Please help, Xilinx FIFO problem!
144621: 09/12/21: Re: Please help, Xilinx FIFO problem!
144624: 09/12/21: Re: Please help, Xilinx FIFO problem!
144632: 09/12/21: Re: Please help, Xilinx FIFO problem!
144636: 09/12/21: Re: Please help, Xilinx FIFO problem!
144638: 09/12/21: Re: Please help, Xilinx FIFO problem!
144642: 09/12/21: Re: Please help, Xilinx FIFO problem!
144648: 09/12/21: Re: Please help, Xilinx FIFO problem!
144650: 09/12/21: Re: H.264 on Spartan3A DSP
144651: 09/12/21: Re: H.264 on Spartan3A DSP
144659: 09/12/21: Re: Please help, Xilinx FIFO problem!
144661: 09/12/21: Re: Please help, Xilinx FIFO problem!
144664: 09/12/21: Re: Please help, Xilinx FIFO problem!
144676: 09/12/22: Re: Please help, Xilinx FIFO problem!
144679: 09/12/22: Re: Please help, Xilinx FIFO problem!
144682: 09/12/22: Re: Please help, Xilinx FIFO problem!
144701: 09/12/25: Re: Altera FPGA configuration using JTAG
144804: 10/01/05: Re: EPCS vs SPI Flash
145097: 10/01/27: Re: Please help, Xilinx FIFO problem!
145105: 10/01/27: Re: Please help, Xilinx FIFO problem!
145106: 10/01/27: Re: Please help, Xilinx FIFO problem!
145114: 10/01/28: Re: Please help, Xilinx FIFO problem!
145130: 10/01/28: Re: DPA vs FPGA Security?
145138: 10/01/29: Re: In system memory editor of Altera for Xilinx
145143: 10/01/29: Re: In system memory editor of Altera for Xilinx
145145: 10/01/29: Re: In system memory editor of Altera for Xilinx
145148: 10/01/29: Re: In system memory editor of Altera for Xilinx
145149: 10/01/29: Re: In system memory editor of Altera for Xilinx
145152: 10/01/29: Re: In system memory editor of Altera for Xilinx
145154: 10/01/29: Re: synthesizing a completely empty design for an FPGA to measure
145157: 10/01/29: Re: synthesizing a completely empty design for an FPGA to measure
145167: 10/01/29: Re: synthesizing a completely empty design for an FPGA to measure
145168: 10/01/29: Re: synthesizing a completely empty design for an FPGA to measure
145170: 10/01/30: Re: synthesizing a completely empty design for an FPGA to measure
145172: 10/01/30: Re: synthesizing a completely empty design for an FPGA to measure
145176: 10/01/30: Re: In system memory editor of Altera for Xilinx
145179: 10/01/30: Re: In system memory editor of Altera for Xilinx
145191: 10/02/01: Re: In system memory editor of Altera for Xilinx
145193: 10/02/01: Re: In system memory editor of Altera for Xilinx
145210: 10/02/01: Re: In system memory editor of Altera for Xilinx
145216: 10/02/01: Re: In system memory editor of Altera for Xilinx
145221: 10/02/01: Re: In system memory editor of Altera for Xilinx
145222: 10/02/01: Re: In system memory editor of Altera for Xilinx
145224: 10/02/01: Re: Help Please - Xilinx message
145470: 10/02/11: Re: Actel FPGA corePWM IP
145495: 10/02/12: Re: Actel FPGA corePWM IP
145615: 10/02/15: EDK 11,1 on Windows 7, 32 Bit
145640: 10/02/16: Re: EDK 11,1 on Windows 7, 32 Bit
145643: 10/02/17: Re: EDK 11,1 on Windows 7, 32 Bit
145670: 10/02/18: Re: EDK 11,1 on Windows 7, 32 Bit
145818: 10/02/25: antti alive message
145855: 10/02/25: Re: antti alive message
146040: 10/03/04: Re: Antti....
146041: 10/03/04: Actel is now the only FPGA vendor with hard-core processor in the
146081: 10/03/05: Re: Actel is now the only FPGA vendor with hard-core processor in the
146092: 10/03/05: Re: FSM in BlockRAM
146138: 10/03/06: Re: FSM in BlockRAM
146264: 10/03/10: Re: Tier Logic introduces the world's first 3D FPGA
146361: 10/03/14: Re: Nu Horizons Spartan 3A DSP board
146369: 10/03/14: Re: Nu Horizons Spartan 3A DSP board
146390: 10/03/15: Re: Nu Horizons Spartan 3A DSP board
146417: 10/03/17: Re: Xilinx Spartan6 Virtex6 Rollout
146439: 10/03/18: Re: FPGA's with on-chip PROM?
146446: 10/03/18: Re: Xilinx only on Avnet now
146705: 10/03/26: Re: USB 3.0 implementation on FPGA
146715: 10/03/26: Re: Ring Oscillator -> counter differences
147466: 10/04/28: xilinx arm finally announced
148021: 10/06/14: Re: Altera Quartus - how to create small roms & rams for Cyclone 3
148096: 10/06/21: Xilinx BULLSHITIX-8, when?
148114: 10/06/21: Re: Programming the Actel Smartfusion Eval Kit in Linux
148277: 10/07/04: xilinx leadtimes
148327: 10/07/07: Re: FPGA Video processing board (HDMI).. who makes one?
148415: 10/07/20: Re: Cortex-M1 in Actel in strait VHDL?
148662: 10/08/15: Re: How to use VIO and core inserter at the same time.
148665: 10/08/16: Re: How to use VIO and core inserter at the same time.
150098: 10/12/13: Re: Lattice XO2 video
150117: 10/12/15: Re: Lattice XO2 video
150135: 10/12/16: Re: Lattice XO2 video
150826: 11/02/15: lattice machXO2 VCCP pin
150832: 11/02/15: Re: lattice machXO2 VCCP pin
150833: 11/02/15: Re: lattice machXO2 VCCP pin
150839: 11/02/15: Re: lattice machXO2 VCCP pin
150926: 11/02/22: Re: lattice machXO2 VCCP pin
152240: 11/07/26: FPGA security, Actel down, now Xilinx too?
152544: 11/09/12: Lattice XP2 getting hot and/or reading 0's as JTAG ID
152546: 11/09/12: Re: Lattice XP2 getting hot and/or reading 0's as JTAG ID
152549: 11/09/12: Re: Lattice XP2 getting hot and/or reading 0's as JTAG ID
152550: 11/09/12: Re: Lattice XP2 getting hot and/or reading 0's as JTAG ID
155935: 13/10/17: Re: Zynq devices, boards and suppliers
155940: 13/10/18: Re: Zynq devices, boards and suppliers
157362: 14/11/28: Re: Low-end FPGA mezzanine standard
157363: 14/11/28: Re: MIPI M-PHY and FPGA?
157365: 14/11/28: Re: Low-end FPGA mezzanine standard
157369: 14/11/29: Re: Low-end FPGA mezzanine standard
157459: 14/12/11: Re: Using FPGA to feed 80386
157583: 14/12/19: Re: MIPI M-PHY and FPGA?
157599: 14/12/24: Re: Low-end FPGA mezzanine standard
161149: 19/02/05: Re: Xilinx Artix-7 SoM with 8 x GTPs
Antti Karttunen (remove .fo from the address):
77308: 05/01/04: EU patent debate, any effects on FPGA-design?
77325: 05/01/04: Re: EU patent debate, any effects on FPGA-design?
Antti Karttunen (remove the trailing .do from the address):
73978: 04/10/02: Capabilities of Spartan-3 Starter Kit (XC3S200).
74082: 04/10/04: Differences between Xilinx ISE Foundation and WebPACK.
74163: 04/10/05: Features of Xilinx ISE WebPACK & Altera's Quartus II.
74194: 04/10/06: Xilinx ISE WebPACK vs. Altera's Quartus II Web Edition.
Antti Lukats:
29582: 01/02/27: Re: Partial Reconfig using JBits
56012: 03/05/27: Xilinx Spartan download with Parallel III cable
56060: 03/05/27: Re: Xilinx Spartan download with Parallel III cable
56062: 03/05/27: Re: JTAG madness
56065: 03/05/28: Re: Xilinx Spartan download with Parallel III cable
56068: 03/05/28: Re: Xilinx Spartan download with Parallel III cable
56136: 03/05/29: Simplest PCI - VHDL core (BIOS Post port80 Tester)
56150: 03/05/29: Re: Xilinx Spartan download with Parallel III cable
56200: 03/05/30: Re: Programming Altera EPC1 and EPC1441
56548: 03/06/09: Xilinx XST synthesis, BUG ?
56553: 03/06/09: Re: Info on Spartan-II PCI Development Kit
56571: 03/06/09: Re: Info on Spartan-II PCI Development Kit
56572: 03/06/09: Re: Xilinx Parallel Cable IV and non-captive software
56638: 03/06/10: Re: Recovering Data from MACH210 PLDs with Securty Fuse blown
56992: 03/06/20: Virtex II Pro FF896 socket
57358: 03/06/28: Re: Microblaze uP as component
57360: 03/06/28: Re: Xilinx EDK examples from Website
57361: 03/06/28: Re: Virtex II Pro FF896 socket
57362: 03/06/28: Re: Recovering Data from MACH210 PLDs with Securty Fuse blown
57394: 03/06/29: Re: cyclone on pci?
57429: 03/06/30: Re: Xilinx EDK examples from Website
57488: 03/07/01: EDK/XPS/Virtex2Pro - TFT core not avaialble
57494: 03/07/01: Re: Xilinx ML300 JTAG Configuration Problem
57579: 03/07/02: Virtex 2Pro, ML300, VP2PDK, EDK, etc..
57707: 03/07/04: Re: Virtex 2Pro, ML300, VP2PDK, EDK, etc..
57708: 03/07/04: Re: create JAM-File for Xilinx device
57709: 03/07/04: Re: Virtex 2Pro, ML300, VP2PDK, EDK, etc..
57716: 03/07/04: Re: Virtex 2Pro, ML300, VP2PDK, EDK, etc..
57721: 03/07/04: Re: PDP11/40 Compatible CPU on an FPGA
57740: 03/07/05: Re: Virtex 2Pro, ML300, VP2PDK, EDK, etc..
57945: 03/07/10: Re: PROM JTAG download cable for Xilinx Spartan II + Webpack
57981: 03/07/11: Re: PROM JTAG download cable for Xilinx Spartan II + Webpack
58116: 03/07/15: JTAG Boundary scan during configuration
58163: 03/07/16: Re: JTAG Boundary scan during configuration
58164: 03/07/16: Re: "ML300 Embedded" Mapping Help
58184: 03/07/16: Re: "ML300 Embedded" Mapping Help
58185: 03/07/16: Re: vertex2 pci pinout
58222: 03/07/17: Re: device selection for game system
58223: 03/07/17: Re: vertex2 pci pinout
58294: 03/07/19: Re: "ML300 Embedded" Mapping Help
58295: 03/07/19: Re: CPLD Interface to PC's requirements
58297: 03/07/19: Re: using block rams in FPGAs
58460: 03/07/23: Re: device selection for game system
58584: 03/07/27: Re: "ML300 Embedded" Mapping Help
58588: 03/07/28: ZX Spectrum on V2Pro/ML300
58590: 03/07/28: Re: GL85 synthesizable code
58592: 03/07/28: Re: "ML300 Embedded" Mapping Help
58598: 03/07/28: Re: xilinx programing interface
58616: 03/07/29: Re: Spartan IIE max pin switching
58656: 03/07/30: Re: "ML300 Embedded" Mapping Help
58764: 03/08/01: Re: Tiny TCP/IP stack and tiny MAC controller on FPGA for direct download to S(D)RAM memory
58765: 03/08/01: Re: Spartan 3 support in Webpack
58888: 03/08/03: Re: opencores.org - Question on project licensing?
58902: 03/08/04: Re: reconfiguration VirtexE via JTAG (full or partial)
59095: 03/08/08: Re: Size does matter
59158: 03/08/10: Re: Atmel CPLD programming tools
59201: 03/08/12: Re: GL85 synthesizable code
59291: 03/08/13: Re: Update on Virtex II Pro Linux
59299: 03/08/14: Actel: Libero/Synplify "Run" button disabled
59300: 03/08/14: Re: Old Xilinx FPGAs
59428: 03/08/19: Re: "sniffing" signals
59436: 03/08/19: Re: Parallel interface to an FPGA
59468: 03/08/19: Re: Xilinx FPGA pin locking/assignment
59538: 03/08/21: Xilinx Platform Flash Engineering Sample PLEEAASE
59575: 03/08/22: V2Pro, ML300 Linux reference design
59623: 03/08/25: Re: [ann] Microblaze uClinux Demo released
59624: 03/08/25: Re: Reusing CCLK line after configuration for Spartan-II
59683: 03/08/25: Re: [ann] Microblaze uClinux Demo released
59829: 03/08/28: Re: pricing, cyclone or spartan
59849: 03/08/29: Re: pricing, cyclone or spartan
59944: 03/09/02: Re: EDK problem!
59992: 03/09/03: Re: EDK problem!
59998: 03/09/03: Re: Newbie CAN Core question - Student
59999: 03/09/03: Re: How to extend a pulse width without clock!
60071: 03/09/04: Re: More EDK Problems..... :-(
60102: 03/09/04: Re: Flex6K configuration PROM
60111: 03/09/05: Re: Suitable FPGA architecture for Robots..
60131: 03/09/05: Re: Q: Xilinx PROM file generation
60149: 03/09/05: Re: EDK problem!
60151: 03/09/05: Re: Schematic simulation and then FPGA programming?
60215: 03/09/08: Re: FPGA start?
60219: 03/09/08: Re: IP-Core CAN-Controller
60222: 03/09/08: Xilinx Platform Configuration, really cool devices (and avaialble!)
60324: 03/09/10: Re: Embedded/Microcontroller FPGA and Software Defined Radio
60422: 03/09/12: Re: Error when downloading with EDK
60457: 03/09/13: Re: Embedded/Microcontroller FPGA and Software Defined Radio
60460: 03/09/13: Spartan 3 ICAP primitive
60461: 03/09/13: Re: ATLV256 for Spartan 2
60462: 03/09/13: Re: Error when downloading with EDK
60463: 03/09/13: Re: Reconfiguration standards
60471: 03/09/14: Re: Embedded/Microcontroller FPGA and Software Defined Radio
60487: 03/09/15: Re: Spartan 3 ICAP primitive
60533: 03/09/16: Re: Xilinx ISE 6.1i
60534: 03/09/16: Re: USB transceiver for FPGA
60557: 03/09/16: Re: MICROBLAZE: Using external instruction memory
60560: 03/09/16: Re: USB transceiver for FPGA
60569: 03/09/16: Re: USB transceiver for FPGA
60591: 03/09/16: Re: platform flash as storage?
60606: 03/09/17: Re: platform flash as storage?
60672: 03/09/18: Re: Reconfiguration, Spartan 3, Compressed bit stream, ICAP
60678: 03/09/19: Re: Parallel JTAG cable on a USB-only W2K laptop?
60684: 03/09/19: Re: Xilinx Parallel Cable 4 (PC4) and Platform Flash JTAG
60743: 03/09/21: Re: Xilinx Parallel Cable 4 (PC4) and Platform Flash JTAG
60810: 03/09/22: Re: Xilinx Parallel Cable 4 (PC4) and Platform Flash JTAG
60811: 03/09/22: Re: USB 1.1/2.0 Implementation
60815: 03/09/23: Re: Regarding XC6216
60821: 03/09/23: Re: PPC access to PROM using Virtex @ pro
60822: 03/09/23: Re: Added Keyboard controller to C-NIT
60823: 03/09/23: Re: Location constraint
60845: 03/09/23: Re: Added Keyboard controller to C-NIT
60868: 03/09/23: Re: Xilinx Parallel Cable 4 (PC4) and Platform Flash JTAG
60869: 03/09/23: Re: Regarding XC6216
60870: 03/09/23: Re: FPGA implementation in (V)HDL
60871: 03/09/23: Re: IEEE 1284 Core for Xilinx
60873: 03/09/24: Re: IEEE 1284 Core for Xilinx
60876: 03/09/24: Re: USB 1.1/2.0 Implementation
60878: 03/09/24: Re: Regulator for Spartan 2
60926: 03/09/24: Re: IEEE 1284 Core for Xilinx | Reading Japanese FPGA pages
60952: 03/09/25: Re: chipscope pro and jtag
60978: 03/09/25: Re: chipscope pro and jtag
60979: 03/09/25: Re: IEEE 1284 Core for Xilinx | Reading Japanese FPGA pages
61514: 03/10/06: Re: MicroBlaze size
61925: 03/10/15: Re: USB Core (Japanese Version) Revisited ;o(
61993: 03/10/15: Re: USB Core (Japanese Version) Revisited ;o(
62096: 03/10/19: Re: xilinx System ACE solution
62118: 03/10/19: Re: USB 2.0 controller using ISP1581 device
62203: 03/10/22: Re: USB 2.0 controller using ISP1581 device
62363: 03/10/27: Re: chipscope pro and jtag
62508: 03/10/31: Re: chipscope pro and jtag
62648: 03/11/03: Re: Building the 'uber processor'
62737: 03/11/06: Re: Announcement
63409: 03/11/20: Re: Xilinx microblaze : SRAM external mem controller
64133: 03/12/17: Re: Xilinx .ucf
64905: 04/01/15: Re: Please help with Xilinx ISE Schematic question
65020: 04/01/18: Re: Deriving 36MHz from a 40MHz crystal using DCM?
65048: 04/01/19: Re: Trouble using ChipsCope Pro with MicroBlaze
65103: 04/01/20: Re: Good/Affordable Stater kits
65134: 04/01/20: Re: Altera/Xilinx Distributor in Europe?
65139: 04/01/20: Re: Good/Affordable Stater kits
65429: 04/01/28: Re: Altera Active Serial
65471: 04/01/29: Re: Altera Active Serial
65472: 04/01/29: Re: Where to get FPGA devices for testing?
65499: 04/01/30: Re: Where to get FPGA devices for testing?
65501: 04/01/30: Re: Where to get FPGA devices for testing?
65506: 04/01/31: Re: Altera Active Serial
65507: 04/01/31: New USB chip for fast FPGA bitstream download
65520: 04/01/31: Re: Altera Active Serial
65521: 04/01/31: Re: New USB chip for fast FPGA bitstream download
65522: 04/01/31: Re: Experiences with Microblaze and Nios
65530: 04/02/01: Re: Experiences with Microblaze and Nios
65531: 04/02/01: Re: New USB chip for fast FPGA bitstream download
65533: 04/02/01: MicroBlaze smallest system implemntation report
65590: 04/02/02: Re: Differences between Xilinx ISE and Altera Quartus software
65591: 04/02/02: Re: Differences between Xilinx ISE and Altera Quartus software
65603: 04/02/03: Re: Altera programming
65722: 04/02/05: Re: PS/2 Keyboard opencore (keyboard side) available ???
65771: 04/02/06: Re: Xilinx ILA -> supported FPGA ?
65850: 04/02/08: 32 Bit APEX optimized RISC
65892: 04/02/09: Re: JAM and Xilinx/Altera CPLDs
65993: 04/02/10: Microblaze uLinux bootloader for SystemACE/CompactFlash
66091: 04/02/12: Re: Spartan-3 shipping, or perhaps not!
66092: 04/02/12: Re: Xilinx Platform Flash Prom
66168: 04/02/13: Re: Sensible starter FPGA board
66216: 04/02/14: Re: regarding opto isolators
66357: 04/02/18: Re: Can FPGA bootstrap itself?
66530: 04/02/21: Re: Serial ATA with Xilinx RocketIO (Virtex 2 Pro)??
66532: 04/02/21: FPGA info from Embedded World 2004/Nuerrnberg
66606: 04/02/23: Re: Free PCI-bridge in VHDL for Spartan-IIE
66622: 04/02/24: Re: ML300 EDK 6.1 Simulations
66706: 04/02/25: Re: SmartMedia writer (implments using VHDL)....
67259: 04/03/09: Re: copy protection on FPGA using embedded serial number
67310: 04/03/10: Quartus II version 4 (Web Edition) DOES NOT WORK AT ALL !?
67368: 04/03/10: Re: Quartus II version 4 (Web Edition) DOES NOT WORK AT ALL !?
67388: 04/03/10: Re: Quartus II version 4 (Web Edition) DOES NOT WORK AT ALL !?
67461: 04/03/12: Comparing ISE 6.1 and QII-v4 on small design, fatal errors
67462: 04/03/12: Re: Virtex 2 P -> PPC write to block RAM
67786: 04/03/19: Re: Spartan III availability ROTFL
67890: 04/03/22: XCV2000E survived 3.3V core voltage!
67940: 04/03/22: Re: opb, plb routing resources?
67945: 04/03/23: Fried a XC2S200!
67949: 04/03/23: Re: Fried a XC2S200!
68018: 04/03/24: Re: Fried a XC2S200!
68084: 04/03/25: DIY 2M Gates IP Core verification system for $49 !!!
68097: 04/03/26: Using V2Pro RocketIO MGT's to make a buzzer beeep....
68310: 04/03/31: Re: Msg for Rudolf Usselmann
68559: 04/04/07: Re: Msg for Rudolf Usselmann
68620: 04/04/09: Re: Spartan-3 LC Development Kit from Insight with USB 2.0 Port
68621: 04/04/09: Re: [OT] Is anyone alive at Opencores.org?
68638: 04/04/12: using MicroBlaze SoC with OPB_DDR in ISE flow
68660: 04/04/13: Re: using MicroBlaze SoC with OPB_DDR in ISE flow
70037: 04/05/28: Re: Trying to build simple demo using XPS and XC2VP20
70153: 04/06/05: Re: USB OTG high speed
70328: 04/06/12: Re: Costs of IPs
70343: 04/06/13: Re: Costs of IPs
70645: 04/06/22: Re: JTAG - XC2S200E-PQ208
70661: 04/06/22: EDK 6.2 ISE verilog toplevel possible ?
70692: 04/06/23: Re: EDK 6.2 ISE verilog toplevel possible ?
70702: 04/06/23: Re: EDK 6.2 ISE verilog toplevel possible ?
70838: 04/06/29: Re: EDK 6.2 ISE verilog toplevel possible ?
70980: 04/07/03: FPGAs starting with incorrect bitstream !?
70983: 04/07/03: Re: FPGAs starting with incorrect bitstream !?
71022: 04/07/05: Re: FPGAs starting with incorrect bitstream !?
71153: 04/07/09: Xilinx bitstream AutoCRC algorithm
71451: 04/07/18: Re: FPGAs starting with incorrect bitstream !?
71462: 04/07/19: Re: FPGAs starting with incorrect bitstream !?
71723: 04/07/28: Re: I need a cheap PC/104 FPGA module
71809: 04/07/30: Xilinx is still in YEAR 2003 ?
71929: 04/08/03: Re: ISE WebPack and IPs (no CoreGen)Xilinx
72010: 04/08/05: Re: ChipScope Pro Loading Memory
72095: 04/08/08: RocketIO in full bypass mode
72216: 04/08/11: Re: How crate symbol from VHD?
72220: 04/08/11: ADV: 2M Gate FPGA Protosystem (DIY - selfmade) for sale (0.99 starting no reserve)
72230: 04/08/11: Re: ISE 6.2 : Place problem with V2PRO
72234: 04/08/11: Re: ISE 6.2 : Place problem with V2PRO
72337: 04/08/15: Re: Free Spartan3 download program for GNU/Linux
72397: 04/08/17: V2PRo: Rocket IO Question
72400: 04/08/17: Re: Xilinx WebPack Spartan3 DCM implementation problem
72498: 04/08/20: How to make ByteBlaster II
72579: 04/08/25: Re: Any experience with Actel Flash-FPGAs ?
72623: 04/08/26: Re: EPM7064LC44-7 - Not there in Quartus II...
72705: 04/08/29: Re: EDK core wrapping and include files
72811: 04/09/02: Re: EDK core wrapping and include files
73737: 04/09/28: MicroBlaze is no available as Open-Source!! (from independant 3rd party)
73741: 04/09/28: Re: MicroBlaze is no available as Open-Source!! (from independant 3rd party)
73742: 04/09/28: Re: Co-Processor for Microblaze or PowerPC Processor
73833: 04/09/29: Re: Chipscope Pro and VHDL
73971: 04/10/01: Open-Source MicroBlaze IP-Core working in FPGA :)
73983: 04/10/01: Re: MicroBlaze is no available as Open-Source!! (from independant 3rd party)
73985: 04/10/01: Re: COMMA_ALIGN_MSB being ignored?
73991: 04/10/01: Re: FSL link beginner question
74028: 04/10/02: Re: Open-Source MicroBlaze IP-Core working in FPGA :)
74029: 04/10/02: Re: Open-Source MicroBlaze IP-Core working in FPGA :)
74051: 04/10/02: Re: Open-Source MicroBlaze IP-Core working in FPGA :)
72867: 04/09/06: Xilinx PCI Express Solution: 2 Questions.
73027: 04/09/10: Re: Simple FPGA board
73032: 04/09/10: Re: Simple FPGA board
73045: 04/09/11: Re: Need some help with some technical claims...
73159: 04/09/14: Re: Virtex 4 released today
73194: 04/09/15: Re: Virtex 4 released today
73201: 04/09/15: Re: Xilinx Core Gen Question
73206: 04/09/15: Re: altera quartus II handbook is wrong??
73218: 04/09/15: Re: Virtex 4 released today
73219: 04/09/15: Re: Virtex 4 released today
73321: 04/09/19: Re: Xilinx Core Gen Question
73633: 04/09/26: XILINX FIX UP THE WEBPACK 6.3 DOWNLOAD !!!
73634: 04/09/26: Re: XILINX FIX UP THE WEBPACK 6.3 DOWNLOAD !!!
73651: 04/09/27: Re: XILINX FIX UP THE WEBPACK 6.3 DOWNLOAD !!!
74972: 04/10/22: Re: Introducing MANIK - a 32 bit Soft-Core RISC Processor
74986: 04/10/22: Re: Introducing MANIK - a 32 bit Soft-Core RISC Processor
74987: 04/10/22: Re: Altera Cubic Cyclonium
74994: 04/10/23: Re: configuring FPGA Spartan2
75010: 04/10/24: Re: Hello Xilinx folks -- please answer
75020: 04/10/24: Re: Virtex-II Pro DDR Memory Controller
75036: 04/10/25: Re: ISE Mapping problem
75048: 04/10/25: Re: FPGA board checking
75052: 04/10/25: Re: Introducing MANIK - a 32 bit Soft-Core RISC Processor
75141: 04/10/26: Re: JTAG Registers
75145: 04/10/27: SPARC V8 SoC in FPGA? Its already cost effective!
75175: 04/10/28: Re: Question to TBUS-Placement in SPARTAN3 again!
75208: 04/10/29: Re: Do you know this board?
75285: 04/11/01: Re: Question on Xilinx VirtexProII PCMCIA support (FPGA boards).... please
75335: 04/11/02: Re: XST - Memory Problems
74074: 04/10/03: M*Blaze in Cyclone ! End of What? ;)
74091: 04/10/03: Re: FPGA servo motor controller
74128: 04/10/04: Re: M*Blaze in Cyclone ! End of What? ;)
74140: 04/10/04: Re: XC2V1000 Block RAM size
74152: 04/10/04: Re: Chipscope and BlockRam
74153: 04/10/04: Re: Is it possible to Reverse-Engineer an FPGA Output file?
74456: 04/10/11: MicroBlaze Platform simulator is available (can run uCLinux!)
74457: 04/10/11: Re: Student SATA project
74458: 04/10/11: Re: Student SATA project
74706: 04/10/16: Re: Introducing MANIK - a 32 bit Soft-Core RISC Processor
74727: 04/10/17: NI*S II-verilog in Virtex FPGA
74733: 04/10/17: Re: Open-Source MicroBlaze IP-Core working in FPGA :)
74734: 04/10/17: Re: Open-Source MicroBlaze IP-Core working in FPGA :)
74754: 04/10/18: Re: NI*S II-verilog in Virtex FPGA
74779: 04/10/18: Re: Introducing MANIK - a 32 bit Soft-Core RISC Processor
74805: 04/10/19: Re: Open-Source MicroBlaze IP-Core working in FPGA :)
74851: 04/10/20: Re: Introducing MANIK - a 32 bit Soft-Core RISC Processor
74905: 04/10/21: Re: Open-Source MicroBlaze IP-Core working in FPGA :)
75408: 04/11/04: Re: chipscope pro problem (par)
75416: 04/11/05: Re: chipscope pro problem (par)
75421: 04/11/05: Re: chipscope pro problem (par)
75436: 04/11/05: Re: chipscope pro problem (par)
75480: 04/11/07: Re: Mixed RTL ,XILINX EDK
75485: 04/11/07: Why Xilinx ChipScope (or similar FPGA OCI tool) is a *MUST* Have tool
75488: 04/11/07: Re: FPGA Network Encryption Engine
75490: 04/11/07: Re: Why Xilinx ChipScope (or similar FPGA OCI tool) is a *MUST* Have
75492: 04/11/07: Re: Why Xilinx ChipScope (or similar FPGA OCI tool) is a *MUST* Have
75499: 04/11/08: Re: Why Xilinx ChipScope (or similar FPGA OCI tool) is a *MUST* Have
75500: 04/11/08: Re: XST Question
75512: 04/11/08: Re: SDRAM sustained bursts
75522: 04/11/08: Re: Why Xilinx ChipScope (or similar FPGA OCI tool) is a *MUST* Have
75524: 04/11/08: Re: chipscope pro problem (par)
75525: 04/11/08: Re: chipscope pro problem (par)
75544: 04/11/09: Re: Why Xilinx ChipScope (or similar FPGA OCI tool) is a *MUST* Have
75560: 04/11/09: Re: Where to find very basic FPGAs
75571: 04/11/10: Re: Why Xilinx ChipScope (or similar FPGA OCI tool) is a *MUST* Have tool
75704: 04/11/12: Re: std_logic_vector(0 downto 0)
75732: 04/11/13: Re: PWM using FPGA
75733: 04/11/13: FPGA's at Electronica 2004
75739: 04/11/13: Re: Digital LP filter in multiplier free FPGA
75787: 04/11/15: Re: Electronica 2004 - munich - Altera ???
75800: 04/11/15: Re: Soft Processor Core
75826: 04/11/16: Re: JTAG boundary scan xc2v6000
75905: 04/11/18: Re: Extending chipscope capture memory by using external async SRAM
75920: 04/11/19: Re: microblaze: execute program from external memory
75921: 04/11/19: Re: RocketIO clock recovery
75922: 04/11/19: Re: NIOSII problems?
75954: 04/11/20: Re: FPGA development board
75962: 04/11/20: Re: Microblaze: reading files using sysace compactflash
75975: 04/11/21: Re: Custom Megafunctions in Quartus II
76002: 04/11/22: Re: Low cost million gate Spartan 3 board?
76125: 04/11/25: Re: Programming flash connected to CPLD via JTAG
76140: 04/11/25: Re: 386 IP Core
76145: 04/11/25: Re: 386 IP Core
76157: 04/11/26: Re: how to evaluate the needed number of gate?
76185: 04/11/28: Re: When JTAG programming Xilinx FPGA, should other pins be constrained?
76204: 04/11/28: Re: When JTAG programming Xilinx FPGA, should other pins be constrained?
76227: 04/11/29: Re: fpga prices
76228: 04/11/29: Re: CPLD + CAN bus
76233: 04/11/29: Re: CPLD + CAN bus
76237: 04/11/29: Re: jtag / platform flash/ spartan 3 config questions
76242: 04/11/29: Re: two I/O markers on the same wire
76257: 04/11/29: Re: CPLD + CAN bus
76432: 04/12/02: Re: block ram and bmm files
76434: 04/12/02: Re: Stupid tools question...
76435: 04/12/02: Re: Does Easypath make sense for a XC2S15 @ 20K units?
76490: 04/12/04: Re: SD Cards
76498: 04/12/04: Re: SD Cards
76503: 04/12/04: Re: RocketIO success?
76509: 04/12/05: Re: Experiences with Memec V2Pro Board
76512: 04/12/05: Re: how to speed up my accumulator ??
76513: 04/12/05: Re: Stupid tools question...
76518: 04/12/05: Re: how to speed up my accumulator ??
76519: 04/12/05: Re: Experiences with Memec V2Pro Board
76525: 04/12/05: Re: how to speed up my accumulator ??
76528: 04/12/05: Re: how to speed up my accumulator ??
76537: 04/12/06: Re: internal tristates and busses
76564: 04/12/06: Re: Xilinx 6.2 to 6.3 upgrade brakes soc
76566: 04/12/06: Re: xess boards
76574: 04/12/06: Re: how to speed up my accumulator ??
76615: 04/12/07: Re: FPGA as host for a USB peripheral
76622: 04/12/07: Re: Performance claims
76670: 04/12/08: Re: Open source FPGA EDA Tools
76675: 04/12/08: Re: Open source FPGA EDA Tools
76696: 04/12/09: Re: Atari 10-in-1 Joystick
76700: 04/12/09: Re: BurchED FPGA Newsletter, December 2004
76752: 04/12/10: Re: Trying to get 4 LUTs, MUXF5, MUXF6 in Spartan-3
76761: 04/12/10: Re: PCI design with vhdl
76765: 04/12/10: Re: Trying to get 4 LUTs, MUXF5, MUXF6 in Spartan-3
76768: 04/12/10: Re: Trying to get 4 LUTs, MUXF5, MUXF6 in Spartan-3
76783: 04/12/11: Re: Trying to get 4 LUTs, MUXF5, MUXF6 in Spartan-3
76793: 04/12/12: Xilinx Christmas present: EDK 6.3 !
77030: 04/12/20: edk-chipscope 6.2 to 6.3 update
77275: 05/01/03: Re: Free IP-Core for FPGA Config from MMC-Cards
77903: 05/01/19: Re: Comparison of LEON2, Microblaze and Openrisc processors
78132: 05/01/25: Re: Impact errors programing V4LX25
78240: 05/01/26: ProASIC=?ISO-8859-1?Q?=A7?= Released
78243: 05/01/27: Re: ProASIC=?ISO-8859-1?Q?=A7?= Released
78254: 05/01/27: Re: Impact errors programing V4LX25
78257: 05/01/27: Re: Impact errors programing V4LX25
78259: 05/01/27: Re: Impact errors programing V4LX25
78267: 05/01/27: Re: ProASIC=?ISO-8859-1?Q?=A7?= Released
78268: 05/01/27: Re: EDK--If I'm not using a vendor's board
78269: 05/01/27: Re: looking for the opb_core_ssp0_ref
78670: 05/02/05: new MicroBlaze uClinux build platform anybody having full success ?
78672: 05/02/05: Re: Spartan-3 Starter Kit supplier in the UK?
78730: 05/02/07: Xilinx makes dreams true :)
78732: 05/02/07: Re: Xilinx makes dreams true :)
78733: 05/02/07: Re: See Peter's High-Wire Act next Tuesday
78735: 05/02/07: Re: Cyclone configuration device
78742: 05/02/07: Re: Xilinx makes dreams true :)
78745: 05/02/07: Re: Cyclone configuration device
78748: 05/02/07: Re: Cyclone configuration device
78755: 05/02/07: Re: xilinx parallel cable IV
78760: 05/02/07: Re: Xilinx makes dreams true :)
78796: 05/02/08: Re: SimmStick FPGA module
78799: 05/02/08: V4LX25-ES and systemACE
78803: 05/02/08: Re: SimmStick FPGA module
78805: 05/02/08: Re: Microblaze and Picoblaze
78808: 05/02/08: Re: SimmStick FPGA module
78814: 05/02/08: Re: SimmStick FPGA module
78818: 05/02/08: Re: V4LX25-ES and systemACE
78826: 05/02/08: Re: V4LX25-ES and systemACE
78830: 05/02/08: Re: Impact errors programing V4LX25
78831: 05/02/08: Re: SATA and RocketIO
78833: 05/02/08: Re: BRAM utilization - how to calculate
78854: 05/02/09: Re: V4LX25-ES and systemACE
78855: 05/02/09: Re: V4LX25-ES and systemACE
78856: 05/02/09: Re: usb 2.0 micromodule
78858: 05/02/09: Re: SATA and RocketIO
78912: 05/02/09: Re: usb 2.0 micromodule
78914: 05/02/10: Re: In need of some life-changing advice
78915: 05/02/10: Re: ProAsic3 (PA3)
78924: 05/02/10: Re: Newbie : Xilinx Ml310 platform
78925: 05/02/10: Re: Flash problem
78928: 05/02/10: Re: V4LX25-ES and systemACE
78930: 05/02/10: Writing IP-Cores while sleeping ;)
78932: 05/02/10: Re: Writing IP-Cores while sleeping ;)
78936: 05/02/10: Re: Writing IP-Cores while sleeping ;)
78938: 05/02/10: Re: Writing IP-Cores while sleeping ;)
78962: 05/02/10: Re: GEMAC and MGT on ML300
79011: 05/02/11: Re: ProAsic3 (PA3)
79018: 05/02/11: Re: V4LX25-ES and systemACE
79021: 05/02/11: Re: RocketIO in 32-bit Mode
79037: 05/02/11: Re: ProAsic3 (PA3)
79095: 05/02/14: Re: SATA and RocketIO
79147: 05/02/14: Re: Weird Mircroblaze programm execution
79153: 05/02/15: Re: Weird Mircroblaze programm execution
79157: 05/02/15: Re: OPB <-> WhishBone wrapper (opb_wb_wrapper at opencores)
79212: 05/02/15: Re: OPB <-> WhishBone wrapper (opb_wb_wrapper at opencores)
79462: 05/02/19: Antti Lukats: all my past live projects to be published...
79463: 05/02/19: Re: EMC and Shared SRAM/FLASH Bus
79471: 05/02/19: Re: Any suggestion for an IP project
79566: 05/02/21: Re: Antti Lukats: all my past live projects to be published...
79567: 05/02/21: Re: Nios performance
79568: 05/02/21: Re: Antti Lukats: all my past live projects to be published...
79574: 05/02/21: Reconfigure your dreams: fully reconfigurable computer in DIP40 !
79576: 05/02/21: Re: Reconfigure your dreams: fully reconfigurable computer in DIP40 !
79598: 05/02/21: Re: Reconfigure your dreams: fully reconfigurable computer in DIP40 !
79601: 05/02/21: Re: Antti Lukats: all my past live projects to be published...
79615: 05/02/22: Re: Reconfigure your dreams: fully reconfigurable computer in DIP40 !
79675: 05/02/23: Re: SD Card and FPGA
79709: 05/02/23: Re: SD Card and FPGA
79710: 05/02/23: Re: Spartan-3 partial reconfiguration trouble
79711: 05/02/23: Re: Spartan-3 partial reconfiguration trouble
79714: 05/02/23: Re: SD Card and FPGA
79729: 05/02/23: embedded 2005 in Nuernburg
79739: 05/02/23: Re: Frustrated with Altera
79767: 05/02/24: Re: embedded 2005 in Nuernburg
79864: 05/02/25: Re: NiosII Vs MicroBlaze
79868: 05/02/25: Re: IP unnecessarily using Spartan-3 DCM?
79873: 05/02/25: Re: IP unnecessarily using Spartan-3 DCM?
79885: 05/02/25: Virtex-4 performance, where is it?
79893: 05/02/25: Re: Virtex-4 performance, where is it?
79896: 05/02/25: Re: Virtex-4 performance, where is it?
79929: 05/02/26: Re: embedded 2005 in Nuernburg
80002: 05/02/28: Re: livedesign or ise
80145: 05/03/02: Re: Frustration on Xilinx Device Drivers API
80148: 05/03/02: Re: Spartan-3E and SPI Flash bootstrap
80170: 05/03/02: Re: Xilinx ISE7.1
80179: 05/03/02: Lattice lowcost flash FPGAs announced
80202: 05/03/02: Re: spartan3E price
80205: 05/03/02: Re: spartan3 development board in Europe?
80213: 05/03/02: Re: Spartan-3E and SPI Flash bootstrap
80611: 05/03/09: Re: Differences among the FPGA development tools.
80688: 05/03/10: Re: Xilinx vs Altera high-end solutions
80695: 05/03/10: Re: Virtex 4 USER1 ~ USER4 JTAG commands
80760: 05/03/11: Re: Xilinx vs Altera high-end solutions
80774: 05/03/11: Re: How to make a stdout peripheral?
80781: 05/03/11: Re: Xilinx vs Altera high-end solutions
80785: 05/03/11: Re: Xilinx ISE 7.1 WebPack first impressions
80792: 05/03/11: FPGA tech enhancement idea for sale at ebay any takers?
81345: 05/03/22: PowerPC soft-core?
81376: 05/03/22: Re: PowerPC soft-core?
81409: 05/03/23: divide by 2^n, n=21..37 ==> 3 Virtex Slices !!
81411: 05/03/23: Re: Chipscope and Virtex4 LX25 ES
81412: 05/03/23: Re: PowerPC soft-core?
81413: 05/03/23: Re: PowerPC soft-core?
81520: 05/03/26: Re: divide by 2^n, n=21..37 ==> 3 Virtex Slices !!
81522: 05/03/26: free 8 Channel Frequency meter for all FPGA owners :)
81525: 05/03/26: Re: iMPACT Boundary-Scan Error
81537: 05/03/26: some +. for Altera
81546: 05/03/27: using FPGA JTAG pins as general purpose I/O
81578: 05/03/28: Mini Contest with for the best SRL16 based ipcore/idea
81582: 05/03/28: Re: User I/O via Altera MAX7000S JTAG?
81620: 05/03/29: Re: divide by 2^n, n=21..37 ==> 3 Virtex Slices !!
81627: 05/03/29: Re: What type of IO to use
81631: 05/03/29: Re: some +. for Altera
81632: 05/03/29: Re: free 8 Channel Frequency meter for all FPGA owners :)
81636: 05/03/29: Re: some +. for Altera
81639: 05/03/29: Re: some +. for Altera
81642: 05/03/29: Re: divide by 2^n, n=21..37 ==> 3 Virtex Slices !!
81647: 05/03/29: Re: some +. for Altera
81651: 05/03/29: Re: some +. for Altera
81662: 05/03/29: Altera MAX2 optimized serial RISC interim source code files released
81693: 05/03/30: Re: Initializing Altera MEGARAMs in simulation
81698: 05/03/30: Re: C compiler for Picoblaze - FPGA
81701: 05/03/30: Re: C compiler for Picoblaze - FPGA
81707: 05/03/30: Re: Xilinx EDK tool flow
81709: 05/03/30: Re: FPGA programming via Slave-Serial-Mode
81715: 05/03/30: Re: Using the Xilinx JTAG Interface as a General-Purpose Communication Port
81717: 05/03/30: Re: Program flash memory XC18V01 from FPGA
81753: 05/03/31: Re: Achieving required speed in Virtex-II Pro FPGA
81760: 05/03/31: Re: WTB NIOS-II kit
81763: 05/03/31: Re: WTB NIOS-II kit
81766: 05/03/31: Re: WTB NIOS-II kit
81783: 05/03/31: use your FPGA as frequency meter, free application download available
81795: 05/03/31: Re: Enable/Disable BSCAN_SPARTAN3
81805: 05/04/01: Re: use your FPGA as frequency meter, free application download available
81813: 05/04/01: Xilinx tools, bugs all around?
81824: 05/04/01: Re: 4/1
81830: 05/04/01: Re: Achieving required speed in Virtex-II Pro FPGA
81833: 05/04/01: Re: Achieving required speed in Virtex-II Pro FPGA
81928: 05/04/04: Re: Xilinx tools, bugs all around?
81949: 05/04/05: Re: Open PowerPC Core?
81966: 05/04/05: Re: Open PowerPC Core?
81974: 05/04/05: Re: Open PowerPC Core?
81993: 05/04/05: Re: ISA vs. patent/trademark
82005: 05/04/05: 80x86 verilog (not complete!) sources released
82051: 05/04/06: Re: HWICAP BRAM access (with EDK)
82058: 05/04/06: Re: A "simple" problem...
82075: 05/04/06: Re: FPGA with 2 JTAG ports
82081: 05/04/06: Re: A "simple" problem...
82083: 05/04/06: Re: FPGA with 2 JTAG ports
82122: 05/04/07: Re: 80x86 verilog (not complete!) sources released
82133: 05/04/07: Re: A "simple" problem...
82134: 05/04/07: 8 pit PWM generator in one Xilinx Slice !
82135: 05/04/07: Re: 8 pit PWM generator in one Xilinx Slice !
82177: 05/04/08: Re: Clock Jitter on Xilinx FPGA
82179: 05/04/08: Re: Clock Jitter on Xilinx FPGA
82186: 05/04/08: Re: FPGA Configuration Simulation
82208: 05/04/08: Re: PicoBlaze JTAG Program Loader problems
82210: 05/04/08: Re: Altera programming via Embedded processor
82240: 05/04/09: Re: PicoBlaze JTAG Program Loader problems
82246: 05/04/09: Re: ise 7.1 sp1 BEWARE !
82267: 05/04/10: Re: ISE 7.1 won't play with EDK 6.3 ????
82269: 05/04/10: Spartan-3E based board available now? or is Memec advertizing vaporware ?
82272: 05/04/10: Re: Spartan-3E based board available now? or is Memec advertizing vaporware ?
82273: 05/04/10: Re: A PCI FPGA card I found on ebay
82277: 05/04/10: Re: A PCI FPGA card I found on ebay
82287: 05/04/10: Re: edk annual renewal cost?
82289: 05/04/10: Re: implement the JTAG MASTER --ACT8990 by using FPGA
82292: 05/04/10: Re: edk annual renewal cost?
82298: 05/04/10: Re: edk annual renewal cost?
82312: 05/04/11: Re: re:implement the JTAG MASTER --ACT8990 by using FPGA
82321: 05/04/11: Re: LVDS for lcd panel and RocketIO
82330: 05/04/11: Re: Xilinx Platform Studio - Vertex II Pro board
82339: 05/04/11: Re: DC component removal in FPGA
82382: 05/04/12: Re: Xilinx VirtexII master serial mode problem(cclk)
82389: 05/04/12: Xilinx PCI Express solution with PX1011A PHY any closer info available?
82392: 05/04/12: Re: Import user Core with a Tri-state Port to EDK
82399: 05/04/12: Re: How do I disable Microblaze on-chip hw debug
82403: 05/04/12: Re: How do I disable Microblaze on-chip hw debug
82409: 05/04/12: Re: Ethnet samples using EDK??
82414: 05/04/12: Re: How do I disable Microblaze on-chip hw debug
82419: 05/04/12: Re: Ethnet samples using EDK??
82427: 05/04/12: Re: re:implement the JTAG MASTER --ACT8990 by using FPGA
82432: 05/04/12: Re: General question about soft CPUs
82434: 05/04/12: Re: DC component removal in FPGA
82463: 05/04/13: Re: How do I disable Microblaze on-chip hw debug
82475: 05/04/13: Re: Regarding driving of SCL and SDA pins of I2C
82482: 05/04/13: Re: virtex4 reconfiguration time
82502: 05/04/13: Re: virtex4 reconfiguration time
82558: 05/04/14: Re: virtex4 reconfiguration time
82559: 05/04/14: Re: Regarding driving of SCL and SDA pins of I2C
82566: 05/04/14: Re: Fitting functionality in an XC2VP30 FPGA.
82596: 05/04/14: Re: free-ip
82607: 05/04/14: Re: free-ip
82628: 05/04/15: Re: Fitting functionality in an XC2VP30 FPGA.
82631: 05/04/15: Re: Fitting functionality in an XC2VP30 FPGA.
82632: 05/04/15: Re: Soft CPU vs Hard CPU's
82633: 05/04/15: Re: re:implement the JTAG MASTER --ACT8990 by using FPGA
82639: 05/04/15: Re: different I/O buffers available inXilinx FPGA
82660: 05/04/15: Re: different I/O buffers available inXilinx FPGA
83210: 05/04/26: Re: Help creating a System Ace file
83238: 05/04/26: Re: MAX II UFM data specification and programming
83241: 05/04/26: Re: ISE wishlist
83243: 05/04/26: Re: Experience with Hitech Global & Xilinx
83313: 05/04/27: Re: MAX II UFM data specification and programming
83317: 05/04/27: Re: XC4k parts obsolete ?
83328: 05/04/27: Re: MAX II UFM data specification and programming
83330: 05/04/27: Re: XC4k parts obsolete ?
83370: 05/04/28: Re: Flexray ip core
83487: 05/05/01: Re: current price for (small quantity) XC4VFX12/FF668
83502: 05/05/01: Re: Virtex4 and ISE reality check?
83503: 05/05/01: Re: PCI-X target chip with simple backend interface....
83507: 05/05/01: Re: current price for (small quantity) XC4VFX12/FF668
83508: 05/05/01: Re: Virtex4 and ISE reality check?
83526: 05/05/02: Re: Xilinx 6.2i EDK
83555: 05/05/03: Re: Xilinx 6.2i EDK
83556: 05/05/03: Re: Performing Readback from Impact
84003: 05/05/11: Re: Any Virtex 4 development/prototyping boards out there???
84004: 05/05/11: Re: An FPGA eval board at $49!!
84073: 05/05/12: EDK 7.1 XMD and platform USB cable
84115: 05/05/12: EDK 7.1 with xilinx ML401 ref design
84162: 05/05/13: Re: Whats going on here?
84168: 05/05/13: Re: "Mine is bigger than yours..."
84170: 05/05/13: Re: V4 vs. Stratix-II...fabric only thread...LUT details...
84179: 05/05/13: microblaze and 64 bit memory over PLB bus
84182: 05/05/13: Re: Whats going on here?
84292: 05/05/17: Re: microblaze and 64 bit memory over PLB bus
84298: 05/05/17: Re: Is a gated oscillator using NAND okay within a Cyclone FPGA?
84337: 05/05/17: open support question to Xilinx. should be fairly simple to answer.
84338: 05/05/17: Re: Virtex-2 JTAG problem
84343: 05/05/17: Re: Jam Byte-Code Player for 8051
84352: 05/05/17: Re: "Mine is bigger than yours..."
84372: 05/05/18: Re: Detaching the schematic viewer under ISE Webpack
84380: 05/05/18: Re: Jam Byte-Code Player for 8051
84382: 05/05/18: Re: Xilinx IP: PCI Express
84391: 05/05/18: Re: For accessing my SDRAM,what should i do?
84432: 05/05/19: Re: open support question to Xilinx. should be fairly simple to answer.
84433: 05/05/19: Re: Virtex-2 JTAG problem
84465: 05/05/19: Re: open support question to Xilinx. should be fairly simple to answer.
84484: 05/05/19: Re: Spartan 3 CPI
84489: 05/05/19: Re: Jam Byte-Code Player for 8051
84491: 05/05/19: Re: Spartan 3 CPI
84623: 05/05/23: more and more and more issues with Xilinx tools
84628: 05/05/23: Re: more and more and more issues with Xilinx tools
84635: 05/05/23: Re: more and more and more issues with Xilinx tools
84640: 05/05/23: Re: Jobs going in New Zealand
84649: 05/05/24: Re: more and more and more issues with Xilinx tools
84662: 05/05/24: Xilinx Answer Record 21127
84675: 05/05/24: Re: Xilinx Answer Record 21127
84695: 05/05/24: Re: more and more and more issues with Xilinx tools
84714: 05/05/25: Re: Xilinx Answer Record 21127
84782: 05/05/27: ISE 7.1 small advice about project files (.ISE extension)
84840: 05/05/30: Re: ISE 6.1 - Fatal Error
84955: 05/06/01: Re: C-1 how to reflash..
85071: 05/06/03: Re: ispLSI1016
85097: 05/06/04: Re: Query - ChipScope Pro analyzer
85139: 05/06/06: Microblaze 4.0 with uClinux is ok or not?
85168: 05/06/06: Re: Microblaze 4.0 with uClinux is ok or not?
85175: 05/06/06: Re: Pissed off with Xilinx - Spartan 3
85279: 05/06/07: Lattice and Mentor seminar info pieces...
85302: 05/06/07: Re: faster Spartan III adder
85312: 05/06/07: Re: Lattice and Mentor seminar info pieces... & ST's new 'uC'+FPGA
85374: 05/06/08: Re: QuickLogic FPGA : In-Circuit Programming
85405: 05/06/09: Re: anyone tried the Actel ProASIC3 Starter Kit?
85406: 05/06/09: DDR desing with FPGA
85409: 05/06/09: Re: Motion controller design with CPLD
85410: 05/06/09: Re: DDR desing with FPGA
85431: 05/06/09: Re: DDR desing with FPGA
85519: 05/06/10: Re: ISE/EDK 6.3 vs 7.1...
85537: 05/06/10: Re: Microblaze 4.0 with uClinux is ok or not?
85582: 05/06/11: Re: X-Fest devkit order leadtimes & software silliness....
85636: 05/06/13: Re: Searching FPGA board for private use
85648: 05/06/13: Xilinx QUIZ: 4=4 or 4=3 ?? EDK C compiler bugs again !!
85649: 05/06/13: Re: Xilinx QUIZ: 4=4 or 4=3 ?? EDK C compiler bugs again !!
85652: 05/06/13: Re: Xilinx QUIZ: 4=4 or 4=3 ?? EDK C compiler bugs again !!
85653: 05/06/13: Re: X-Fest devkit order leadtimes & software silliness....
85661: 05/06/13: Re: never seen XST error
85754: 05/06/15: Re: Xilinx seminar is free AND low cost!
85787: 05/06/16: Re: Availability of Spartan3
85815: 05/06/16: Re: BGA Rework/Prototype Placement Anyone?
85867: 05/06/17: Re: PCI in a PCI-X slot
85869: 05/06/17: Re: AbusivepPricing information in marketing publications
85870: 05/06/17: Free Xilinx Cable III for owners of Altera MAX2 Starterkit.
86108: 05/06/22: Re: JTAG port access in Cyclone
86110: 05/06/22: Re: JTAG port access in Cyclone
86122: 05/06/22: Re: JTAG port access in Cyclone
86138: 05/06/22: Re: JTAG port access in Cyclone
86140: 05/06/22: disappointed with Altera this time
86161: 05/06/22: Re: JTAG port access in Cyclone
86171: 05/06/22: Re: Virtex 4 and reconfigurable computer
86180: 05/06/22: Re: Spartan-3 XC3S50 through XC3S1500 Back on Xilinx Online Store (www.xilinx.com/store)
86282: 05/06/24: Re: Spartan-3e order of availability?
86284: 05/06/24: Re: Need help for Xilinx FPGA
86289: 05/06/24: Re: Spartan-3e order of availability?
86338: 05/06/25: Re: Updating FPGA SPROM firmware over the IP network?
86348: 05/06/26: dedicated NEWS server for FPGA world
86373: 05/06/27: Re: good bye nios (o;
86412: 05/06/27: Re: USB 2.0 core with 1.1 tranceiver problem
86413: 05/06/27: Re: Good FPGA for an encryptor
86456: 05/06/28: Re: Good FPGA for an encryptor
86461: 05/06/28: Re: Good FPGA for an encryptor
86464: 05/06/28: V4 and NBTI question, again..
86468: 05/06/28: Re: Good FPGA for an encryptor
86471: 05/06/28: Re: V4 and NBTI answer
86496: 05/06/29: Re: Small FPGA
86499: 05/06/29: Re: Small FPGA
86501: 05/06/29: Re: Small FPGA
86539: 05/06/29: Re: Good FPGA for an encryptor
86568: 05/06/30: Re: TDI routing in Virtex E FPGA.
86569: 05/06/30: from email into FPGA !!
86635: 05/07/01: Re: Avnet V4 - XC4VLX25
86718: 05/07/05: Re: Connecting ADC to Opb_Spi core
86721: 05/07/05: Re: nios2 toolchain sources...
86723: 05/07/05: Re: Connecting ADC to Opb_Spi core
86730: 05/07/05: Re: Connecting ADC to Opb_Spi core
86734: 05/07/05: Spartan-3E, ISE 7.1 some issues - solved (BUFG insertion problem)
86752: 05/07/06: Re: fastest FPGA speed grade?
86761: 05/07/06: Re: virtex4 evaluation board
86893: 05/07/08: ISE 7.1 SP3, Spartan3-E readiness ??
86895: 05/07/08: Re: ISE 7.1 SP3, Spartan3-E readiness ??
86924: 05/07/09: Re: re:Spartan-3E, ISE 7.1 some issues - solved (BUFG insertion pro
86946: 05/07/11: new PLD and FPGA devices from Lattice
86947: 05/07/11: Re: Search for FPGA
86952: 05/07/11: Re: Wishbone RTL simulator
86957: 05/07/11: Re: stupid question about XPS peripheral filenames
86969: 05/07/11: Re: Any Scope/LogicAnalyzer that can decode 8b/10b signals in the Rocket IO?
86974: 05/07/11: Re: Bazix introduce FPGA based One Chip computer system
86983: 05/07/12: Re: Quartus 5.0sp1 -- Error: Unexpected error in JTAG server -- error code 33
86991: 05/07/12: Xilinx PLEASE HELP
86999: 05/07/12: Re: Bazix introduce FPGA based One Chip computer system
87023: 05/07/13: Re: NIOS2 toolchain sources...
87031: 05/07/13: Re: Xilinx PLEASE HELP
87032: 05/07/13: Re: Xilinx PLEASE HELP
87034: 05/07/13: Re: Implement a JTAG controller in an FPGA
87035: 05/07/13: Re: Xilinx PLEASE HELP, thanks issue solved by reverse engineering...
87038: 05/07/13: Re: Problems programing FPGAs..
87040: 05/07/13: Re: ise 7.1 Input clk is never used.
87041: 05/07/13: IEEE1532 question, with Xilinx devices
87044: 05/07/13: Re: Implement a JTAG controller in an FPGA
87045: 05/07/13: Re: virtex 4 : how can I know the clock region coverage?
87047: 05/07/13: MachXO - not released, but already supported by Aldec !!
87056: 05/07/14: Re: virtex 4 : how can I know the clock region coverage?
87065: 05/07/14: Re: Wanted: I2C RAM pre-loader VHDL module
87066: 05/07/14: Re: why my programm has no response after i added some opb_bram_if_ctrl core my project?
87101: 05/07/15: Re: NIOS II + USB 2.0 host
87104: 05/07/15: Xilinx: Clock speeds 420MHz+ tested in Spartan-3
87119: 05/07/15: Re: NIOS II + USB 2.0 host
87122: 05/07/15: Re: Xilinx: Clock speeds 420MHz+ tested in Spartan-3
87143: 05/07/17: Re: Serial vs Chipscope
87155: 05/07/18: Re: "Tbufs don't exist"
87156: 05/07/18: Re: chips with partial reconfig other than atmel & xilinx?
87159: 05/07/18: Sparan S3E availability update
87161: 05/07/18: Re: Virtex-4 5V tolerance
87166: 05/07/18: Lattice MachXO is LAUNCHED NOW!
87172: 05/07/18: Re: pricing of Virtex-4
87175: 05/07/18: Virtex-4 breaking the 1GHz clocking barrier in general purpose FPGA fabric (e.g non dedicated circuits)
87182: 05/07/18: Re: EHLO, board designers
87192: 05/07/19: Re: Driving the FPGA output.
87194: 05/07/19: Re: EDK 7.1 with ML401 (paging Antti)
87197: 05/07/19: Re: Lattice MachXO is LAUNCHED NOW!
87209: 05/07/19: Re: ISE7.1 Map:Portability/export/Port_Main.h:127:1.22.234.1
87216: 05/07/19: Re: Xilinx equivalent of simplify constrains.
87217: 05/07/19: Re: ChipScope Pro : how to set up trigger
87219: 05/07/19: Re: July 20th Altera Net Seminar: Stratix II Logic Density
87480: 05/07/25: Re: DCM.
87490: 05/07/25: Re: Update contacts at Altera
87493: 05/07/25: Re: Excalibur full strip simulation on solaris.
87498: 05/07/25: Re: verilog to blif(lut)
87515: 05/07/25: Re: Excalibur full strip simulation on solaris.
87519: 05/07/25: Re: July 20th Altera Net Seminar: Stratix II Logic Density
87521: 05/07/25: Re: Excalibur full strip simulation on solaris.
87523: 05/07/25: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now)
87530: 05/07/25: Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now)
87534: 05/07/25: Re: Free 8 bit micro for fpga
87539: 05/07/25: Re: VHDL soft-core portability to Xilinx, Altera, Atmel....
87540: 05/07/26: Re: Excalibur full strip simulation on solaris.
87542: 05/07/26: Re: VHDL soft-core portability to Xilinx, Altera, Atmel....
87544: 05/07/26: Re: Free 8 bit micro for fpga
87566: 05/07/26: Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now)
87567: 05/07/26: Re: Virtex 2 Pro Routing Constraints
87579: 05/07/26: Re: [JTAG] How to force a FPGA to reprogram itself from a prom with JTAG ?
87583: 05/07/26: Re: chipscope on opb bus
87593: 05/07/26: Re: Soft IPs licensing
87597: 05/07/26: Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now)
87599: 05/07/26: Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now)
87612: 05/07/27: Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now)
87633: 05/07/27: Re: [JTAG] How to force a FPGA to reprogram itself from a prom with JTAG ?
87634: 05/07/27: Re: bmm file and ramb16
87638: 05/07/27: Re: bmm file and ramb16
87652: 05/07/27: Re: chipscope/impact Virtex4 problem
87659: 05/07/27: Re: isplever and GAL
87661: 05/07/27: Re: Delay Generators in FPGAs
87697: 05/07/28: Re: [JTAG] How to force a FPGA to reprogram itself from a prom with JTAG ?
87766: 05/08/01: Re: Digilent's JTAG-USB cable with chipscope
87819: 05/08/02: Re: Digilent's JTAG-USB cable with chipscope
87820: 05/08/02: Re: Xilinx Multiple Spartan 3
87826: 05/08/02: Re: AVNET Xilinx Spartan3 board, example problem
87837: 05/08/02: Re: Sparan S3E availability update
87870: 05/08/03: Re: Porting Actel code
87871: 05/08/03: Re: Sparan S3E availability update
87872: 05/08/03: Re: Digilent's JTAG-USB cable with chipscope
87936: 05/08/04: Re: Where can i find GeneticFPGA toolkit
88004: 05/08/05: Re: about the Hold signal of serial flash .
88050: 05/08/08: Re: Spartan-3: Own P&R, generate bitstream from
88084: 05/08/09: Re: can use bram for VGA
88126: 05/08/10: Re: Hiding data inside a FPGA
88131: 05/08/10: Re: Hiding data inside a FPGA
88132: 05/08/10: Re: Spartan-3: Own P&R, generate bitstream from
88133: 05/08/10: Re: Welcome back Mr. Knapp
88141: 05/08/10: Xilinx Forge compiler is discontinued ??
88181: 05/08/11: Re: Xilinx Forge compiler is discontinued ??
88186: 05/08/11: Re: LatticeXP availability
88197: 05/08/11: creating HARD MACROs broken in ISE 7.1 SP3 ?
88210: 05/08/12: Re: creating HARD MACROs broken in ISE 7.1 SP3 ?
88217: 05/08/12: Re: creating HARD MACROs broken in ISE 7.1 SP3 ?
88220: 05/08/12: Re: high speed image capture
88222: 05/08/12: Re: Welcome back Mr. Knapp
88230: 05/08/12: Re: Welcome back Mr. Knapp
88238: 05/08/12: Re: Atmel AT40k/94k Configuration Format Documentation
88240: 05/08/12: Re: creating HARD MACROs broken in ISE 7.1 SP3 ?
88253: 05/08/13: Re: creating HARD MACROs broken in ISE 7.1 SP3 ?
88254: 05/08/13: Re: ASIC suggestions
88256: 05/08/13: Re: creating HARD MACROs broken in ISE 7.1 SP3 ?
88279: 05/08/14: Re: creating HARD MACROs broken in ISE 7.1 SP3 ?
88280: 05/08/14: Re: Avnet spartan3E development board
88352: 05/08/16: Re: Clock for serializer with a Spartan3
88360: 05/08/16: Re: Peter Alfke's SPDT Switch Debouncer
88373: 05/08/16: Re: Peter Alfke's SPDT Switch Debouncer
88374: 05/08/16: Antti's last comp.arch.fpga posting
89908: 05/09/30: Antti is back
89909: 05/09/30: Re: High Speed Newbie: Xilinx Spartan3 DCM CLK2X is not locked if CLKIN > 140MHz
89910: 05/09/30: Re: very urgent
89912: 05/09/30: best SPI flash configuration solution for Xilinx FPGA's
89913: 05/09/30: Re: CPLD program editing
89914: 05/09/30: Re: 16-bit microprocessor dore for Actel
89915: 05/09/30: Re: I am planning to purchase a Virtex-4 Eval board.
89918: 05/09/30: Altera why so QUIET !?
89922: 05/09/30: Re: 16-bit microprocessor dore for Actel
89925: 05/09/30: Help! I lost my life (Again)!
89927: 05/09/30: Re: Preloading SDRAM?
89929: 05/09/30: looking for 1 beta-tester for PLD2HDL (XPLA3 edition) tool
89930: 05/09/30: Re: Prob in Synthesizing and Simulating large Mux
89931: 05/09/30: Re: Using LogicCORE on development board with Web ISE
89932: 05/09/30: Spartan II, Platfrom Flash, ISE 7.1 - SERIOUS PROBLEM
89934: 05/09/30: Re: Prob in Synthesizing and Simulating large Mux
89936: 05/09/30: Re: Power on reset generation in FPGA
89950: 05/09/30: Re: Lattice XP availability
89952: 05/09/30: Re: Lattice XP availability
89953: 05/09/30: I, Wish: I had an Spartan-3e NOW!
89991: 05/10/01: Re: Xilinx dev board with high quality video?
89992: 05/10/01: Re: ISE does not initialize the bitstream of a EDK project
90031: 05/10/03: Re: Xilinx dev board with high quality video?
90036: 05/10/03: Re: High Speed Newbie: Xilinx Spartan3 DCM CLK2X is not locked if CLKIN > 140MHz
90056: 05/10/04: Re: Xilinx dev board with high quality video?
90057: 05/10/04: Re: Xilinx dev board with high quality video?
90067: 05/10/04: Re: High Load
90075: 05/10/04: Re: Xilinx dev board with high quality video?
90118: 05/10/05: Re: Where to get informations about Virtex 4 FX Engineering Samples
90185: 05/10/06: Re: ACTEL ProASIC plus mixed-voltage I/O macro's in Designer 6.2 ....?
90232: 05/10/07: Re: Virtex4 shift register layout: Horizontal or vertical?
90236: 05/10/07: Re: DDR constraints in Xilinx/UCF, Synplicity?
90238: 05/10/07: Re: FPGA behaviour when its used resource is >90% ?
90263: 05/10/07: Re: Xilinx WebPack and command line
90309: 05/10/10: Re: 16-bit microprocessor dore for Actel
90317: 05/10/10: Re: 16-bit microprocessor dore for Actel
90354: 05/10/11: Re: Xilinx Chipscope VIO Core Utilization
90482: 05/10/14: Re: FPGA : PCI core needed
90575: 05/10/17: Re: XChecker cable and chipscope
90626: 05/10/18: Re: clock timing
90665: 05/10/18: Re: Xilinx USB cable
90671: 05/10/18: Re: Xilinx USB cable
90702: 05/10/19: Re: which is Low power FPGA?
90792: 05/10/21: Re: Avnet Technical Support Terrible!!!
90807: 05/10/21: Re: Avnet Technical Support Terrible!!!
90866: 05/10/24: Re: 24 to 32 8-bit PWM outputs
90876: 05/10/24: Re: SoC Processor design at gate level for edu
90910: 05/10/25: Re: System ACE equivalent for CPLDs
90923: 05/10/25: Re: Xilinx ML403 Many warnings
90943: 05/10/25: Re: Anyone have experience with Linux in V2Pro?
90975: 05/10/26: Re: SDRAM in EDK
91018: 05/10/27: Re: Cost to go from FPGA to ASIC
91037: 05/10/27: another FPGA/asic vendor dead :(
91039: 05/10/27: Re: locking hdl to a particular fpga
91044: 05/10/27: Re: another FPGA/asic vendor dead :(
91049: 05/10/27: Re: another FPGA/asic vendor dead :(
91067: 05/10/28: Re: Cost to go from FPGA to ASIC
91080: 05/10/28: Re: System ACE equivalent for CPLDs
91104: 05/10/29: Re: Spartan-3E starter kit
91105: 05/10/29: Re: Xilinx ML403 Virtex 4 IIC uses bitbang test?
91106: 05/10/29: ISE 8.1, EDK 8.1 any pre-release info available?
91124: 05/10/30: Re: Cost to go from FPGA to ASIC
91141: 05/10/31: Re: SystemACE parts wanted
91147: 05/10/31: Re: SystemACE parts wanted
91164: 05/10/31: Re: SystemACE parts wanted
91165: 05/10/31: Re: Spartan-3E starter kit
91174: 05/10/31: Re: Spartan-3E starter kit
91175: 05/10/31: Re: SystemACE parts wanted
91188: 05/11/01: Re: question on sw tools for xilnx FPGA
91196: 05/11/01: Re: Spartan-3E starter kit
91197: 05/11/01: Re: Spartan-3E starter kit
91201: 05/11/01: Re: Thank-you Xilinx!
91242: 05/11/02: Re: FPGA : PCI-CORE
91243: 05/11/02: Re: differential clock in EDK
91251: 05/11/02: Re: FPGA : PCI-CORE
91256: 05/11/02: Re: FPGA : PCI-CORE
91329: 05/11/03: Re: Memec Insight Spartan-3 LC Development Kit USB drivers needed! Help!
91336: 05/11/03: Actel SoftARM IP core generator tools finally available !!!
91337: 05/11/03: Re: Memec Insight Spartan-3 LC Development Kit USB drivers needed! Help!
91343: 05/11/03: Re: Spartan-3E starter kit
91393: 05/11/04: Re: Anybody understand this ISE 7.1 error, and what to do about it???
91401: 05/11/05: Why Spartan-3e is the best
91403: 05/11/05: Re: FPGA : PCI-CORE
91405: 05/11/05: Re: Why Spartan-3e is the best
91426: 05/11/06: Re: Anybody understand this ISE 7.1 error, and what to do about it???
91443: 05/11/07: Re: Why Spartan-3e is the best
91444: 05/11/07: Re: Anybody understand this ISE 7.1 error, and what to do about it???
91459: 05/11/07: Re: Xilinx Package/Logic Options
91465: 05/11/07: Re: BRAMs readback
91530: 05/11/08: Re: old xilinx components
91532: 05/11/08: Re: Bus for Spartan3
91581: 05/11/09: EDK 7.1, Virtex4 GPIO PULLIP problem
91752: 05/11/11: Re: FPGA KIT recommendation
91773: 05/11/12: Re: AVNET's Spartan3 400 dev board & PCI
91786: 05/11/13: Re: Viretx4 FX chip availability
91809: 05/11/14: Re: ISE, JTAG and ChipScopePro.
91812: 05/11/14: Re: Viretx4 FX chip availability
92110: 05/11/22: Re: Disabling Xilinx clock enable usage...
92117: 05/11/22: Re: Disabling Xilinx clock enable usage...
92194: 05/11/23: Re: Xilinx DCM_ADV 280MHz no lock
92247: 05/11/24: Re: XC2000
92254: 05/11/24: Re: XC2000
92256: 05/11/24: FPGA ARM IP Core
92258: 05/11/24: Re: XC2000
92338: 05/11/28: Re: XC4VFX20 samples
92466: 05/11/30: Re: Virtex 4 Tapped Delay Lines
92474: 05/11/30: Re: ISE Simulator not present in Linux?
92479: 05/11/30: Re: ISE Simulator not present in Linux?
92482: 05/11/30: Re: ISE Simulator not present in Linux?
92596: 05/12/02: Virtex-4 FX60 based products are already shipping now !
92613: 05/12/02: Spartan3E availability update
92616: 05/12/02: Re: Virtex-4 FX60 based products are already shipping now !
92631: 05/12/02: Re: What if....
92657: 05/12/03: Re: internal clock
92660: 05/12/03: Re: Using RiscWatch with Xilinx FPGA's for powerpc
92661: 05/12/03: Re: Virtex 4 Tapped Delay Lines
92686: 05/12/05: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92691: 05/12/05: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92694: 05/12/05: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92695: 05/12/05: Re: programming flash memeory
92706: 05/12/05: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92707: 05/12/05: ISE 8.1 release delayed?
92788: 05/12/07: Re: xilinx research labs
92792: 05/12/07: Re: ISE 8.1 release delayed?
92796: 05/12/07: Re: How to connect 2 FPGA?
92799: 05/12/07: Re: I2C controller chipset to interface with FPGA
92803: 05/12/07: Re: How to connect 2 FPGA?
92807: 05/12/07: Re: FPGA development board with digital image camera
92812: 05/12/07: Re: FPGA development board with digital image camera
92813: 05/12/07: Re: VGA controller
92815: 05/12/07: Free x86 IP-Core is really working!
92820: 05/12/07: Re: Problem programming CoolRunner II xc2c256_tq144 CPLD using IMPACT
92826: 05/12/07: Re: FPGA development board with digital image camera
92831: 05/12/07: Re: A stupid question about constraints
92834: 05/12/07: Re: Embedded ppc405 w/o RAM?
92836: 05/12/07: some new PCIe products
92857: 05/12/08: Re: I2C controller chipset to interface with FPGA
92863: 05/12/08: Re: Free x86 IP-Core is really working!
92877: 05/12/08: Re: FPGA development board with digital image camera
92905: 05/12/09: Re: FPGA : MAP slice logic into BLOCK RAM
92906: 05/12/09: Re: Experiences with Actel ProAsic3E and toolchain?
92908: 05/12/09: Re: some new PCIe products
92916: 05/12/09: Re: Spartan3E availability update
92918: 05/12/09: Re: ISE 8.1 release delayed?
92920: 05/12/09: Re: partial reconfig of Virtex-4 : iMPACT warning makes the chip pause
92928: 05/12/09: Re: ISE purchase
92929: 05/12/09: Re: XC4VFX12 -- availability?
92932: 05/12/09: Re: XC4VFX12 -- availability?
92938: 05/12/09: Re: No, not FIFOs again...
92940: 05/12/09: Re: Adding "super-LUTs" to FPGA, good idea ?
92945: 05/12/09: Re: Xilinx ML40x VGA Documentation
92947: 05/12/09: Re: Adding "super-LUTs" to FPGA, good idea ?
92955: 05/12/10: First IP-core designed for and tested with Spartan-3E
92958: 05/12/10: Re: First IP-core designed for and tested with Spartan-3E
92971: 05/12/10: Re: Problem with ChipScope Pro 6.2
92989: 05/12/11: Re: MMC(MultiMedia Card) interfacing with FPGA
92992: 05/12/11: Re: Free x86 IP-Core is really working!
92993: 05/12/11: Re: About Spartan 3
92995: 05/12/11: Re: MMC(MultiMedia Card) interfacing with FPGA
93016: 05/12/12: Re: Question about Xilinx UCF files
93019: 05/12/12: Re: MMC(MultiMedia Card) interfacing with FPGA
93020: 05/12/12: Re: MMC(MultiMedia Card) interfacing with FPGA
93050: 05/12/13: Re: re:MMC(MultiMedia Card) interfacing with FPGA
93056: 05/12/13: mixed signal flash FPGAs launched!
93062: 05/12/13: Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
93066: 05/12/13: Re: mixed signal flash FPGAs launched!
93070: 05/12/13: Re: some new PCIe products
93077: 05/12/13: Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
93087: 05/12/13: Re: who can help me? i want to know the bitsream format of Virtex-II
93090: 05/12/13: Re: fiddling directly with LUT bits on Xilinx
93113: 05/12/14: Re: J Tag Protocol
93115: 05/12/14: Re: ISE WebPack 8.1i
93117: 05/12/14: Re: ISE WebPack 8.1i
93146: 05/12/14: Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
93155: 05/12/14: Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
93168: 05/12/15: Re: J Tag Protocol
93176: 05/12/15: Re: How to simulate a .NMC macro?
93179: 05/12/15: Re: Digilent SRAM Controller
93181: 05/12/15: Re: How to simulate a .NMC macro?
93187: 05/12/15: Re: Digilent SRAM Controller
93208: 05/12/15: Re: Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?
93223: 05/12/16: Re: Avnet hav2 s3e starter kit?
93224: 05/12/16: Re: Avnet hav2 s3e starter kit?
93228: 05/12/16: Re: Interfacing externally clocked data to an FPGA (Spartan 3)
93232: 05/12/16: Re: ISE 8.1i on Fedora Core 4 (64-bit)
93243: 05/12/16: Re: Avnet hav2 s3e starter kit?
93255: 05/12/16: Re: Avnet hav2 s3e starter kit?
93258: 05/12/16: Re: How to simulate Virtex-4 PPC, MAC, etc. ?
93261: 05/12/16: Re: Avnet hav2 s3e starter kit?
93273: 05/12/18: Re: rs232 and picoblaze :)
93292: 05/12/19: Re: Differential Pin Pairs in Lattice EC FPGAs
93327: 05/12/20: Re: Differential Pin Pairs in Lattice EC FPGAs
93333: 05/12/20: Re: Virtex-4 clocking
93344: 05/12/20: Re: Virtex-4 clocking
93359: 05/12/20: Re: Virtex II Pro XC2VP100
93386: 05/12/21: Re: Is there anyboay work on the subject with the embeded system in the fpga?
93393: 05/12/21: Re: Is there anyboay work on the subject with the embeded system in the fpga?
93397: 05/12/21: Re: Is there anyboay work on the subject with the embeded system in the fpga?
93411: 05/12/21: Re: Spartan 3 Digilent Board Expansion Connectors
93441: 05/12/22: Re: Cypress FX2 bandwidth problem
93442: 05/12/22: Re: Is there anyboay work on the subject with the embeded system in the fpga?
93444: 05/12/22: Re: Xilinbx Online store XC2C32A, XC2C64A missing ?
93446: 05/12/22: Re: Opencores Can Controller
93469: 05/12/22: Re: Synplicity and the EDK
93499: 05/12/23: Re: Is there anybody that have ported the linux to the nios or microblaze?
93500: 05/12/23: Spartan3e and ChipScope
93501: 05/12/23: Re: RTL for Z8000 series CPU?
93505: 05/12/23: Re: Spartan3e and ChipScope
93506: 05/12/23: Re: SystemACE problem
93508: 05/12/23: Re: Spartan3e and ChipScope
93510: 05/12/23: Re: RTL for Z8000 series CPU?
93517: 05/12/23: Re: SystemACE problem
93524: 05/12/23: Re: Spartan3e and ChipScope
93526: 05/12/23: FREE Spartan 3e Sample Pack
93552: 05/12/24: Re: Xilinx ISE Simulator
93560: 05/12/24: Re: Cypress FX2 bandwidth problem
93564: 05/12/24: Re: Spartan3e and ChipScope
93565: 05/12/24: Re: Spartan3e and ChipScope
93569: 05/12/24: Re: re:Virtex-4FX and ethernet mac
93575: 05/12/25: Re: Can somone work on the pci express project?
93578: 05/12/25: Re: Can somone work on the pci express project?
93581: 05/12/25: Re: Is the microblaze or nios2 free?
93584: 05/12/25: Re: how to use ICAP on Virtex-II XC2V1000-FG456-4?
93601: 05/12/26: Re: XILINX I2C controller core in FPGA and multisource problem.
93603: 05/12/26: Re: XILINX I2C controller core in FPGA and multisource problem.
93605: 05/12/26: Re: Spartan-3 Starter Kit newbie question
93628: 05/12/27: Re: XILINX I2C controller core in FPGA and multisource problem.
93632: 05/12/27: Re: Microblaze in a EDK pcore
93633: 05/12/27: Re: Download to board with RS232
93635: 05/12/27: DDR2 support for EDK
93640: 05/12/27: Re: Download to board with RS232
93646: 05/12/27: Re: USB 2.0 testbench available?
93684: 05/12/28: Re: DDR2 support for EDK
93685: 05/12/28: Re: CP2101 <-> Printer?
93724: 05/12/29: Re: USB Printer Interface
93740: 05/12/29: Spartan3E Parallel Flash Programming (with free Spartan 3e Sample Pack)
93746: 05/12/29: Re: Spartan3E Parallel Flash Programming (with free Spartan 3e Sample Pack)
93750: 05/12/29: Re: Actel Fusion
93751: 05/12/29: Re: S3e starter kits available
93753: 05/12/29: Re: Spartan3E Parallel Flash Programming (with free Spartan 3e Sample Pack)
93763: 05/12/30: Re: PPC405 on ISE
93767: 05/12/30: Re: Brute Force Examination of a PLD
93773: 05/12/30: Re: XILINX I2C controller core in FPGA and multisource problem.
93777: 05/12/30: Re: call for papers,Expresscard specification?
93780: 05/12/30: Re: call for papers,Expresscard specification?
93784: 05/12/30: Re: using internal POR
93789: 05/12/30: Easy and fun: Worlds smallest FPGA module.
93790: 05/12/30: Re: How do I instantiate an ADSU8 in ISE7.1i?
93792: 05/12/30: Re: S3e starter kits available
93794: 05/12/30: Re: S3e starter kits available
93807: 05/12/31: Re: Low cost PCI FPGA cards for reconfigurable computing
93843: 06/01/02: Re: Easy and fun: Worlds smallest FPGA module.
93849: 06/01/02: Re: Start up condition of flip flops in FPGA?
93850: 06/01/02: FPGA DVI output with CH7301
93851: 06/01/02: Re: FPGA DVI output with CH7301
93857: 06/01/02: Re: FPGA DVI output with CH7301
93860: 06/01/02: Re: FPGA DVI output with CH7301
93894: 06/01/03: Re: FPGA DVI output with CH7301
93907: 06/01/03: Re: FPGA DVI output with CH7301
93992: 06/01/04: Re: FPGA DVI output with CH7301
93926: 06/01/03: Re: FPGA DVI output with CH7301
93855: 06/01/02: Re: fx12
93865: 06/01/02: Re: Easy and fun: Worlds smallest FPGA module.
93867: 06/01/02: CPU86 (Intel 8086) VHDL now available (thanks to HT-LAB !)
93876: 06/01/03: Re: CPU86 (Intel 8086) VHDL now available (thanks to HT-LAB !)
93899: 06/01/03: Re: CPU86 (Intel 8086) VHDL now available (thanks to HT-LAB !)
93881: 06/01/03: Re: optimization tips (badly) needed
93886: 06/01/03: Re: optimization tips (badly) needed
93913: 06/01/03: Re: optimization tips (badly) needed
95072: 06/01/20: Re: Actel Fusion
95928: 06/01/27: Re: Actel Fusion
93880: 06/01/03: Re: What is the best solution vor PCIe today ?
93884: 06/01/03: Re: What is the best solution vor PCIe today ?
93888: 06/01/03: Xilinx new year Puzzle: binary counter 0,5,2,3,4,1,6,7...
93890: 06/01/03: Re: Xilinx new year Puzzle: binary counter 0,5,2,3,4,1,6,7...
94062: 06/01/05: Re: Xilinx new year Puzzle: binary counter 0,5,2,3,4,1,6,7...
94067: 06/01/05: Re: Xilinx new year Puzzle: binary counter 0,5,2,3,4,1,6,7...
93897: 06/01/03: Xilinx Spartan3E Sample Pack: Real fun for all Ages!
93914: 06/01/03: Re: Xilinx Spartan3E Sample Pack: Real fun for all Ages!
94026: 06/01/04: Re: Xilinx Spartan3E Sample Pack: Real fun for all Ages!
94081: 06/01/05: Re: Xilinx Spartan3E Sample Pack: Real fun for all Ages!
93929: 06/01/03: Re: Spartan3e and ChipScope -issue solved
93934: 06/01/03: Re: XST error Xst:2035
93936: 06/01/03: Re: S3e starter kits available
93968: 06/01/04: Re: S3e starter kits available
94199: 06/01/07: Re: S3e starter kits available
94200: 06/01/07: Re: S3e starter kits available
94248: 06/01/09: Re: S3e starter kits available
94393: 06/01/11: Re: S3e starter kits available
94018: 06/01/04: Re: Xilinx Spartan3E Starter Kit, a photo?
94055: 06/01/05: Re: Virtex 2 configuration problem
94076: 06/01/05: Re: EDK 8.1i
94077: 06/01/05: urgently needed: DDR2 test design
94084: 06/01/05: Re: Do you name your FPGA?
94163: 06/01/06: Re: FPGA -> ASIC`
94175: 06/01/06: Re: Programming Xilinx PowerPC
94177: 06/01/06: Re: Programming Xilinx PowerPC
94256: 06/01/09: Re: Xilinx USB Platform Cable not working anymore
94257: 06/01/09: Re: Xilinx USB Platform Cable not working anymore
94303: 06/01/09: Re: Xilinx USB Platform Cable not working anymore
94262: 06/01/09: Re: spartan3 differential I/O
94263: 06/01/09: Re: Does Xilinx's step1 chips is the ES?
94266: 06/01/09: Re: ISE 8.1Evaluation
94269: 06/01/09: Re: ISE 8.1Evaluation
94367: 06/01/10: Re: ISE 8.1Evaluation
94276: 06/01/09: Re: how to speed up the program running in ddr sdram
94352: 06/01/10: Re: tcam implemented in fpga
94425: 06/01/11: Re: Altera MAX-II: User logic access to USERCODE_REGISTER?
94858: 06/01/18: Re: Altera MAX-II: User logic access to USERCODE_REGISTER?
94368: 06/01/10: Re: Downloading WebPack-8.1, server maxes out at 30 kB / second (= > 7 hours)?
94394: 06/01/11: Xilinx Spartan3E Sample Pack 3rd party programing support now available
94418: 06/01/11: Re: Xilinx Spartan3E Sample Pack 3rd party programing support now available
94433: 06/01/11: Re: Xilinx Spartan3E Sample Pack 3rd party programing support now available
94430: 06/01/11: Re: Xilinx Spartan3E Sample Pack 3rd party programing support now available
94400: 06/01/11: Re: FPGA and video generation
94414: 06/01/11: Re: FPGA and video generation
94406: 06/01/11: Re: Samples
94441: 06/01/11: Re: Samples
94410: 06/01/11: Re: Verilog Code for echo on Serial Port
94422: 06/01/11: Re: best evm for virtex-4 and linux
94523: 06/01/13: Re: best evm for virtex-4 and linux
94551: 06/01/13: Re: best evm for virtex-4 and linux
94445: 06/01/11: Re: best evm for virtex-4 and linux
94420: 06/01/11: Re: UCF-File problem
94423: 06/01/11: Re: UCF-File problem
94486: 06/01/12: Re: Newbe Startup Time Question
94497: 06/01/12: Re: FPGA Journal Article
94659: 06/01/16: Re: FPGA Journal Article
94931: 06/01/19: Re: FPGA Journal Article
94937: 06/01/19: Re: FPGA Journal Article
94674: 06/01/16: Re: FPGA Journal Article
95471: 06/01/23: Re: FPGA Journal Article
94639: 06/01/15: Re: FPGA Journal Article
94524: 06/01/13: Re: Xilinx 8.i and ML402
94527: 06/01/13: Re: PCI e clocking
94547: 06/01/13: Re: PCI e clocking
94560: 06/01/13: Re: Xilinx ISE 8.i Editor
94564: 06/01/13: Re: Xilinx ISE 8.i Editor
94610: 06/01/14: Re: FPGA Altair Advice
94614: 06/01/14: Re: Any FPGA with programming info available?
94660: 06/01/16: Re: Any FPGA with programming info available?
94662: 06/01/16: Re: programming devices using other tools
94672: 06/01/16: Re: Displays an image in the XS Board RAM on a VGA monitor
94687: 06/01/16: Re: Displays an image in the XS Board RAM on a VGA monitor
94728: 06/01/17: Re: Just want to program Xilinx CPLD device from JEDEC file using ISE8.1
94734: 06/01/17: Re: Just want to program Xilinx CPLD device from JEDEC file using ISE8.1
94816: 06/01/18: Re: Just want to program Xilinx CPLD device from JEDEC file using ISE8.1
95031: 06/01/20: Re: Just want to program Xilinx CPLD device from JEDEC file using ISE8.1
94789: 06/01/17: Re: Just want to program Xilinx CPLD device from JEDEC file using ISE8.1
94738: 06/01/17: S3e slower than S3
94755: 06/01/17: Re: S3e slower than S3
94771: 06/01/17: Re: S3e slower than S3
94776: 06/01/17: Re: S3e slower than S3
94782: 06/01/17: Re: S3e slower than S3
94817: 06/01/18: Re: S3e slower than S3
94859: 06/01/18: Re: S3e slower than S3
94747: 06/01/17: xilinx free Sample Pack info now also on Xilinx own webpages
94759: 06/01/17: Re: xilinx free Sample Pack info now also on Xilinx own webpages
94819: 06/01/18: Re: xilinx free Sample Pack info now also on Xilinx own webpages
94770: 06/01/17: Re: Spartan3 initialization with DSP
94783: 06/01/17: Re: [RANT] Webpack 8.1 editor totally messed up ?
94820: 06/01/18: Re: [RANT] Webpack 8.1 editor totally messed up ?
94790: 06/01/17: Re: Raggedstone specifications ...
94847: 06/01/18: Re: Data2Mem with CRC for Virtex FPGAs
94951: 06/01/19: Re: Data2Mem with CRC for Virtex FPGAs
95413: 06/01/23: Re: Data2Mem with CRC for Virtex FPGAs
94944: 06/01/19: Re: EDK 8.1
94945: 06/01/19: Re: data2bram and coregen
94871: 06/01/18: Re: Spartan-3E MultiBoot (was Re: xilinx free Sample Pack info now also on Xilinx own webpages)
94903: 06/01/19: Re: How much do you trust your CAD Program?
94942: 06/01/19: Re: DDR Memory Access Interfact by Virtex-4 FX12
94948: 06/01/19: Re: DDR Memory Access Interfact by Virtex-4 FX12
95414: 06/01/23: Re: V4 not packing registers into IOBs
94994: 06/01/20: Re: Loading Data from Prom
95073: 06/01/20: Re: First Impressions of Actel Fusion?
95349: 06/01/22: Re: Reading user data from PROM
95177: 06/01/21: Re: working with XDL
95298: 06/01/22: Re: working with XDL
95171: 06/01/21: Re: Creating Multiple Configuration PROM File
95202: 06/01/21: Re: Creating Multiple Configuration PROM File
95210: 06/01/21: Re: Creating Multiple Configuration PROM File
95299: 06/01/22: Re: Creating Multiple Configuration PROM File
95500: 06/01/23: Re: Creating Multiple Configuration PROM File
95563: 06/01/24: Re: Creating Multiple Configuration PROM File
95562: 06/01/24: Re: Creating Multiple Configuration PROM File
95570: 06/01/24: Re: Creating Multiple Configuration PROM File
95172: 06/01/21: Re: Hi :-) Someone build a parallel JTAG cable like the xilinx one ?
95203: 06/01/21: Re: Xilinx Partial Reconfiguration add-on module
95204: 06/01/21: Re: ISE BaseX customers
95308: 06/01/22: Re: post-fit simulation failed
95312: 06/01/22: Re: post-fit simulation failed
95342: 06/01/22: Re: post-fit simulation failed
95311: 06/01/22: PicoLA: FPGA based logic analyzer
95318: 06/01/22: self repairing FPGA s !?
95386: 06/01/23: Re: Starting with LVDS
95389: 06/01/23: Re: Starting with LVDS
95346: 06/01/22: Re: Starting with LVDS
95348: 06/01/22: Re: Starting with LVDS
95394: 06/01/23: Reconfigurable Array of Array
95411: 06/01/23: Re: Reconfigurable Array of Array
95410: 06/01/23: Re: Reconfigurable Array of Array
95418: 06/01/23: Re: Configuration Spartan 3
95472: 06/01/23: Re: Configuration Spartan 3
95430: 06/01/23: Re: Configuration Spartan 3
95575: 06/01/24: Re: rocket IOs with web pack
95670: 06/01/25: Re: encryption
95685: 06/01/25: Re: encryption
95703: 06/01/25: Re: encryption
95707: 06/01/25: Re: encryption
95795: 06/01/26: Re: So what happened to JHDLBits?
95862: 06/01/26: Re: So what happened to JHDLBits?
95810: 06/01/26: Re: So what happened to JHDLBits?
95817: 06/01/26: Re: So what happened to JHDLBits?
95822: 06/01/26: Re: So what happened to JHDLBits?
95672: 06/01/25: Re: How to generate ILA with ChipScope pro in Linux
95814: 06/01/26: Re: open source fpga programmer programs
95691: 06/01/25: Re: Spartan-3 Starter Board
95921: 06/01/27: Re: Spartan-3 Starter Board
95819: 06/01/26: Re: DDR2 SDRAM controller
95860: 06/01/26: Re: So Xilinx, is XDL and related libraries an available open source interface?
95863: 06/01/26: Re: So Xilinx, is XDL and related libraries an available open source interface?
95924: 06/01/27: Re: So Xilinx, is XDL and related libraries an available open source interface?
95847: 06/01/26: Re: So Xilinx, is XDL and related libraries an available open source interface?
95961: 06/01/27: Re: So Xilinx, is XDL and related libraries an available open source interface?
95867: 06/01/26: Re: Current to sink PROG_B low?
95931: 06/01/27: Re: Xilinx OBUF attributes on Spartan3
95940: 06/01/27: Re: Xilinx OBUF attributes on Spartan3
95933: 06/01/27: Re: Multichannel Opb Memory Controller question
95936: 06/01/27: Re: Multichannel Opb Memory Controller question
95939: 06/01/27: Re: Multichannel Opb Memory Controller question
95947: 06/01/27: Impact 8.1 problems with non xilinx device in chain
95979: 06/01/27: Re: Impact 8.1 problems with non xilinx device in chain
95984: 06/01/27: Re: Impact 8.1 problems with non xilinx device in chain
96004: 06/01/27: Re: Impact 8.1 problems with non xilinx device in chain
96024: 06/01/28: Re: Impact 8.1 problems with non xilinx device in chain
96056: 06/01/29: Re: Impact 8.1 problems with non xilinx device in chain
96005: 06/01/27: Lattice high end FPGAs to be announced soon
96025: 06/01/28: Re: Lattice high end FPGAs to be announced soon
96029: 06/01/28: Re: Debugging Spartan3 slave serial configuration
96226: 06/02/01: Re: Debugging Spartan3 slave serial configuration
96043: 06/01/28: Re: Serial flash configuration with "Xilinx platform cable USB"
96061: 06/01/29: Re: XDL Tools wiki site
96080: 06/01/30: Re: XDL Tools wiki site
96159: 06/01/31: Re: Open source access to generate netlists into Altera tools? Others?
96152: 06/01/31: Re: Impact 8.1 problems=> uClinux rules on MicroBlaze !!!
96163: 06/01/31: Re: Impact 8.1 problems=> uClinux rules on MicroBlaze !!!
96162: 06/01/31: Re: Impact 8.1 problems=> uClinux rules on MicroBlaze !!!
96184: 06/01/31: Re: URGENT: Need to get the USB Balster Driver for the UNIX machines which has FT245BM
96178: 06/01/31: Re: ERROR message when programming FPGA with Altium Designer 2004
96237: 06/02/01: Re: Parallel Cable IV does not work with parallel to usb cable
96272: 06/02/01: Re: Parallel Cable IV does not work with parallel to usb cable
96361: 06/02/02: Re: Die Area
96282: 06/02/01: microblaze GNU tools for win32 binaries (from 8.1 build) for download
96474: 06/02/04: Re: Parallel Cable IV does not work with parallel to usb cable
96553: 06/02/06: Re: fpga hardware "breakpoint"
96666: 06/02/08: Re: MicroBlaze in Spartan 3 playing tuxchess :)
96670: 06/02/08: Re: MicroBlaze in Spartan 3 playing tuxchess :)
96916: 06/02/13: Re: Question about using LMB to connect BRAM in MicroBlaze
97166: 06/02/17: Re: News from Embedded World in Nurnber
97176: 06/02/18: Re: ISE Simulator Price
97189: 06/02/18: using ISE and GNU tools for Xilinx V2Pro/V4FX PowerPC
97193: 06/02/18: Re: Xilinx HardMacro "configurable" ?
97198: 06/02/18: Re: Xilinx HardMacro "configurable" ?
97204: 06/02/18: Re: Xilinx HardMacro "configurable" ?
97530: 06/02/23: Re: 8051 IP core with JTAG debugger for FPGA?
97619: 06/02/24: Re: FPGA Selection Question
97688: 06/02/26: Re: A dev board supporting partial/dynamic reconf.
97849: 06/02/28: Re: PPC Linux SoC on Virtex4 in 4 hours !?
97871: 06/03/01: Re: PPC Linux SoC on Virtex4 in 4 hours !?
97898: 06/03/01: Re: Virtex-4FX Mini Module TEMAC examples
97904: 06/03/01: Re: PPC Linux SoC on Virtex4 in 4 hours !?
98081: 06/03/04: Re: can I port ppclinux to virtex4-fx?
98082: 06/03/04: Re: Virtex-4FX MiniModule Atmel Flash
98085: 06/03/04: Re: Virtex-4FX MiniModule Atmel Flash
98093: 06/03/04: Re: can I port ppclinux to virtex4-fx?
98094: 06/03/04: Re: Virtex-4FX MiniModule Atmel Flash
98124: 06/03/06: Re: can I port ppclinux to virtex4-fx?
98161: 06/03/06: Re: Question for the EDK ppc users ...
98503: 06/03/11: Re: Plateform FLASH PROM configuration using a Microblaze.
98512: 06/03/11: Re: Plateform FLASH PROM configuration using a Microblaze.
98531: 06/03/12: Re: Plateform FLASH PROM configuration using a Microblaze.
98532: 06/03/12: Re: LEON processor core
98535: 06/03/12: Re: LEON processor core
98543: 06/03/12: Re: LEON processor core
98549: 06/03/12: Re: Plateform FLASH PROM configuration using a Microblaze.
98616: 06/03/13: Re: Why does Xilinx hate version control?
98989: 06/03/18: Re: Historical Fpga Resources
99032: 06/03/19: Re: Does support Partial Reconfiguration FPGA other companies except for Xilinx?
99053: 06/03/19: Re: Does support Partial Reconfiguration FPGA other companies except for Xilinx?
99474: 06/03/24: Re: Lattice FPGA
99492: 06/03/25: Re: Spartan-3E 500 and PCI 33/66 design
99535: 06/03/26: Re: chip reverse engineering
99545: 06/03/26: Re: chip reverse engineering
99636: 06/03/27: Re: deglitching a clock
99642: 06/03/27: Re: deglitching a clock
100054: 06/04/02: Re: hwicap can be used in the virtex4
100440: 06/04/09: Re: C-Compiler for free VHDL controller core ?
100441: 06/04/09: Re: C-Compiler for free VHDL controller core ?
100592: 06/04/12: Re: Spartan3E readback, SPI programming
100602: 06/04/13: Re: Spartan3E readback, SPI programming
100638: 06/04/14: Re: PROG_B and JTAG
100677: 06/04/15: Re: Where is the xilinx online store gone?
100692: 06/04/16: Re: Where is the xilinx online store gone?
100706: 06/04/16: Re: Petition about the xilinx online store ?
100710: 06/04/16: Re: Where is the xilinx online store gone?
100717: 06/04/17: Re: Where is the xilinx online store gone?
101047: 06/04/25: Re: Xilinx EDK 8.1 DDR controller behavior
101048: 06/04/25: Re: Spartan 3 documentation confusing...
101327: 06/04/29: Re: Working Altera USB-Blaster compatible design published under GPL
101340: 06/04/29: Re: Working Altera USB-Blaster compatible design published underGPL
101360: 06/04/29: Re: Working Altera USB-Blaster compatible design published underGPL
101380: 06/04/30: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
101401: 06/04/30: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
101404: 06/04/30: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
101405: 06/04/30: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
101408: 06/04/30: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
101409: 06/04/30: Re: design optimization
101412: 06/04/30: Re: design optimization
101435: 06/05/01: Re: Question about the ip I developed
101598: 06/05/03: Re: Measuring Light with LED and FPGA
101602: 06/05/03: Re: xst segmentation fault
101762: 06/05/05: Re: Xilinx SelectMAP Question
102117: 06/05/10: Re: CoolRunner XPLA3 thriving for many years to come
102119: 06/05/10: Re: 87C52 & 87C51 core
102386: 06/05/15: Re: Virtex 5 announced and sampling
102387: 06/05/15: Re: Virtex 5 announced and sampling
102395: 06/05/15: Re: Virtex 5 announced and sampling
102399: 06/05/15: Re: Virtex 5 announced and sampling
102549: 06/05/17: Re: SystemACE bootloader for PowerPC on Virtex4 FX
102568: 06/05/17: Re: SystemACE bootloader for PowerPC on Virtex4 FX
102569: 06/05/17: Re: SystemACE bootloader for PowerPC on Virtex4 FX
102774: 06/05/20: Re: ispLEVER Starter 6.0 FPGA Design Software Available
102775: 06/05/20: Re: xilinx V4 obufds_25 and 3.3 V
103255: 06/05/29: Re: Fast Serial I/O on Virtex-5
103263: 06/05/30: Re: IOB IO Standards in Spartan 3
103363: 06/05/31: Re: Virtex-4FX12MM: Any hardware MAC address accessable?
103513: 06/06/05: Re: FPGA board for USB experiments?
103939: 06/06/15: Re: Anyone get a Pictiva OLED to work?
103940: 06/06/15: Re: ARM cores in FPGA ?
105192: 06/07/17: ISE 8.2 WebPack does not support Virtex-5 at all?
105193: 06/07/17: Re: EDK PowerPC ISS : download errors?
105196: 06/07/17: Re: ISE 8.2 WebPack does not support Virtex-5 at all?
105197: 06/07/17: Re: ISE 8.2 WebPack does not support Virtex-5 at all?
105233: 06/07/18: Re: OpenFire - public domain MicroBlaze clone in verilog
105239: 06/07/18: Re: Which PCI core for Cyclone II board?
105244: 06/07/18: ISE 8.2 - time to crash 20 minutes
105255: 06/07/19: Re: ISE 8.2 - time to crash 20 minutes
105295: 06/07/19: Re: Which PCI core for Cyclone II board?
105300: 06/07/19: Yet another MicroBlaze clone !!
105599: 06/07/27: Re: uClinux on Virtex-4 Mini-Module
105625: 06/07/27: Re: Rocket IO as a high speed sampler
105630: 06/07/27: Re: Rocket IO as a high speed sampler
105632: 06/07/27: Re: Rocket IO as a high speed sampler
105959: 06/08/03: Re: Virtex-5: SoftCore processors at 200MHz !
106165: 06/08/08: Re: 100 Mbit manchester coded signal in FPGA
106170: 06/08/08: logic analyzer for Spartan3 starterkit, GPL VHDL and java based sw
106201: 06/08/09: Re: 100 Mbit manchester coded signal in FPGA
106351: 06/08/12: Re: JOP as SOPC component
106367: 06/08/12: Re: JOP as SOPC component
106423: 06/08/13: Re: JOP as SOPC component
106725: 06/08/18: Re: Using an FPGA as USB HOST without PHY
106736: 06/08/18: Re: Using an FPGA as USB HOST without PHY
106791: 06/08/19: Re: xc2vp30-6ff1152
106931: 06/08/22: Re: Xilinx Virtual Platform
106954: 06/08/23: Re: ISE 8.2i and EDK 8.1i
106955: 06/08/23: Re: uclinux on spartan-3e starter kit
107014: 06/08/23: Re: uclinux on spartan-3e starter kit
107015: 06/08/23: Re: virtex4fx board and ethernet
107017: 06/08/23: Re: DCM vs. PLL
107035: 06/08/23: Re: Xilinx ML501 availability
107036: 06/08/23: Re: USB PHYs and drivers that folks have used
107052: 06/08/24: Re: uclinux on spartan-3e starter kit
107294: 06/08/26: Re: FPGA -> SATA?
107329: 06/08/26: Re: FPGA -> SATA?
107351: 06/08/27: Re: FPGA -> SATA?
107352: 06/08/27: Re: FPGA -> SATA?
107354: 06/08/27: Re: is ISE coded in Java?
107359: 06/08/27: Re: FPGA -> SATA?
107370: 06/08/27: Re: FPGA -> SATA?
107504: 06/08/29: Re: Quartus software and dual-purpose pins
107974: 06/09/03: Re: gpio help...
108037: 06/09/04: Re: Virtex2Pro: Xilinx PCI core mapping error
108041: 06/09/04: Re: gpio help...
108124: 06/09/05: Re: Serial I/O Question
108597: 06/09/13: Re: Microblaze development without EDK?
108758: 06/09/16: Re: http://www.srisc.com ?
109295: 06/09/23: Re: Spartan-3E USB for I/O?
109452: 06/09/27: Re: uBlaze prototype PCB UART issues
109602: 06/09/30: Re: DDR RAM
109653: 06/10/02: Re: LatticeMico32 extremly poor performance without caches
109675: 06/10/03: Re: Modules for IO on BSD indi processor ideas?
110140: 06/10/11: Re: boundary scan
110426: 06/10/15: Re: Xilinx documentation typos
110709: 06/10/20: Virtex-5 DSP48 - fun while sick at home
110718: 06/10/20: Re: JTAG pins of the xc2s200E for user I/O
110730: 06/10/20: Re: System ACE and remotely reconfiguring an XUP board?
110735: 06/10/20: Re: JTAG pins of the xc2s200E for user I/O
110802: 06/10/23: Re: Spartan 3 Configuration Questions
111038: 06/10/27: Re: uBlaze ISR : Steps to write/implement an ISR...
111849: 06/11/11: MPMC2 with Virtex-5
111857: 06/11/11: Re: Virtex-5 Webpack?
111931: 06/11/13: Re: FPGA Debug Tool
112111: 06/11/16: Re: use boundary scan in spartan-3
112144: 06/11/17: Re: Warnings in Xilinx 8.2i
112272: 06/11/19: Re: memory init in Altera bitfiles, (like data2mem) is it possible?
112273: 06/11/19: Re: combinatorical divide by 2 in FPGA
112282: 06/11/19: Re: spartan-3e starter kit and ethernet
112405: 06/11/21: Re: EDK 8.2 Block RAM error
112528: 06/11/24: Re: Are FPGAs available with ADCs onchip ?
112854: 06/11/30: Re: MPMC2: MPMC2 with DDR2 SDRAM
112855: 06/11/30: Re: Xilinx FIFOs round 2 - BUG-BUG in MPMC2
112888: 06/11/30: Re: Xilinx FIFOs round 2 - BUG-BUG in MPMC2
113040: 06/12/05: Re: Spartan-3A launched
113044: 06/12/05: Re: Spartan-3A launched
113047: 06/12/05: Re: Spartan-3A launched
113049: 06/12/05: Re: Spartan-3A launched
113050: 06/12/05: Re: Spartan-3A launched
113052: 06/12/05: Re: Xilinx MPMC2 "External Ports" question
113061: 06/12/05: Re: Spartan-3A launched
113062: 06/12/06: Re: Xilinx MPMC2 "External Ports" question
113117: 06/12/06: Re: EDK 8.2, MDM, and ChipScope....
113118: 06/12/06: Re: EDK 8.2, MDM, and ChipScope....
113125: 06/12/06: Re: Spartan-3A launched
113283: 06/12/10: Re: impossible opb_emc hack?
113341: 06/12/11: Re: FPGA+Ethernet
113350: 06/12/11: Re: Tarfessock1
113355: 06/12/11: Re: Tarfessock1
113560: 06/12/16: Re: Simple questions on IDELAYCTRL vs DCM
113599: 06/12/18: Re: Xilins ISE Re-Creating Projects
113691: 06/12/19: ANN: PicoBlaze C: compile to bitstream!
113704: 06/12/19: Re: ANN: PicoBlaze C: compile to bitstream!
113752: 06/12/20: Re: Spartan 3E Starter Kit Woes
113788: 06/12/21: Re: ANN: PicoBlaze C: compile to bitstream!
113821: 06/12/23: Re: Virtex-5 Webpack?
113832: 06/12/23: PicoChristmas - 112 Free PicoBlaze KCPSM based MicroFpga's released
113854: 06/12/25: Re: moving from xlinx 8.1 to 8.2 or better wait ?
113856: 06/12/26: Impact with non-standard LPT base addresses
113865: 06/12/26: Re: Impact with non-standard LPT base addresses
113941: 06/12/29: Re: PicoBlaze C: compile to bitstream!
115297: 07/02/06: Re: low speed USB interface for FPGAs
Antti.Lukats@googlemail.com:
138544: 09/02/26: Re: mb-gcc producing incorrect code ???
138565: 09/02/27: Re: FPGA Stamp
138567: 09/02/27: Re: ARM11 in Spartan-6
138568: 09/02/27: Re: Lattice announces ECP3
138588: 09/03/01: Re: New person to CPLD programming
138595: 09/03/01: Re: New person to CPLD programming
138607: 09/03/01: Re: Character generator ROM and VGA controller for Spartan 3E
138608: 09/03/01: Re: Send data from FPGA to PC via USB
138632: 09/03/02: Re: Antti-Brain issue 6 released
138738: 09/03/06: Re: Craignell2 and Mulldonnoch2
138745: 09/03/06: Re: Making static C libraries in Xilinx EDK
138791: 09/03/10: Re: Xilinx TEMAC Core
138802: 09/03/11: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138805: 09/03/11: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138824: 09/03/11: Re: A Builder for Component-based and Partial Runtime Reconfigurable
138825: 09/03/11: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138826: 09/03/12: Re: FPGA LVDS for AC-decoupled transmit over CAT-5 cable
138834: 09/03/12: Re: DDR2 MEMORY INTERFACING INTERFACING WITH HARWARE CORE AND
138839: 09/03/12: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138846: 09/03/12: Re: FPGA LVDS for AC-decoupled transmit over CAT-5 cable
138849: 09/03/12: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138852: 09/03/12: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138854: 09/03/12: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138859: 09/03/12: Re: FPGA LVDS for AC-decoupled transmit over CAT-5 cable
138861: 09/03/12: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138866: 09/03/12: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138880: 09/03/13: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138882: 09/03/13: Re: MPCM3/XPS_LL_TEMAC with SFP/1000base-X
138886: 09/03/13: Re: What happens at opencores.org?
138890: 09/03/13: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138904: 09/03/14: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138908: 09/03/14: Re: OT Re: DMCA and Google Groups
138913: 09/03/14: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138920: 09/03/14: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138930: 09/03/14: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138937: 09/03/15: Re: Virtex 5 LVDS
138948: 09/03/16: Re: Getting started with FPGA
138966: 09/03/17: Re: How to load an image onto system ace compact flash embedded on
138970: 09/03/17: Re: Zero operand CPUs
138973: 09/03/17: Re: Zero operand CPUs
138976: 09/03/17: Re: Zero operand CPUs
138979: 09/03/17: Re: Zero operand CPUs
138998: 09/03/18: Re: Zero operand CPUs
139003: 09/03/18: Re: Zero operand CPUs
139005: 09/03/18: Re: Zero operand CPUs
139007: 09/03/18: Re: Documenting a simple CPU
139012: 09/03/18: Re: Zero operand CPUs
139014: 09/03/18: Re: Bullshit! - Re: Zero operand CPUs
139024: 09/03/18: Re: Zero operand CPUs
139026: 09/03/18: Re: Zero operand CPUs
139059: 09/03/19: Re: Zero operand CPUs
139065: 09/03/19: Re: Zero operand CPUs
139085: 09/03/20: Re: Documenting a simple CPU
139096: 09/03/20: Re: FPGA users, Please take a few seconds to report SPAM
139122: 09/03/21: Re: DVI in FPGA
139124: 09/03/21: Re: plb_emc with flash and datawidth matching
139131: 09/03/21: Re: plb_emc with flash and datawidth matching
139142: 09/03/22: Re: Silicon Blue Warm-Boot not working properly
139143: 09/03/22: Re: Silicon Blue Warm-Boot not working properly
139144: 09/03/22: Re: camera module microblaze and sdram
139153: 09/03/22: Re: DVI in FPGA
139195: 09/03/23: Re: How big is my vhdl and am I approaching some size limitation on
139201: 09/03/23: Re: Silicon Blue last datesheet correct URL
139203: 09/03/23: Re: How big is my vhdl and am I approaching some size limitation on
139204: 09/03/23: Re: Altera's free ColdFire v1 IP core anybody used it?
139207: 09/03/23: Re: Silicon Blue last datesheet correct URL
139221: 09/03/23: Re: Silicon Blue last datesheet correct URL
139260: 09/03/24: Re: Silicon Blue Warm-Boot not working properly
139264: 09/03/24: Re: Silicon Blue last datesheet correct URL
139277: 09/03/24: Re: Silicon Blue last datesheet correct URL
139278: 09/03/24: Re: Which ISE Webpack version for S3A..?
139279: 09/03/24: Re: Antti Processor
139288: 09/03/25: Re: Antti Processor
139293: 09/03/25: Re: Which ISE Webpack version for S3A..?
139295: 09/03/25: Re: USB PHY
139300: 09/03/25: Re: USB PHY
139306: 09/03/25: Re: USB PHY
139345: 09/03/27: Re: Dynamic reconfiguration in Spartan 3
139353: 09/03/27: Re: Using LVDS in Lattice ECP3
139356: 09/03/27: Re: Dynamic reconfiguration in Spartan 3
139358: 09/03/27: Re: PLL in Actel Igloo part
139367: 09/03/27: Re: Best way to export Xilinx EDK project in ISE and how to
139373: 09/03/27: Re: best soft core(s) that have C compiler support
139386: 09/03/27: Re: Where to find a xc6200 xilinx fpga?
139387: 09/03/27: Re: best soft core(s) that have C compiler support
139389: 09/03/27: Re: best soft core(s) that have C compiler support
139396: 09/03/28: Re: best soft core(s) that have C compiler support
139397: 09/03/28: Re: best soft core(s) that have C compiler support
139398: 09/03/28: Re: best soft core(s) that have C compiler support
139426: 09/03/29: Re: best soft core(s) that have C compiler support
139446: 09/03/30: Re: Silicon Blue Warm-Boot not working properly
139450: 09/03/30: Re: Fiber optics protocols for mid range speed
139465: 09/03/30: Re: initialize BRAM contents
139470: 09/03/31: Re: SiliconBlue on Wikipedia
139471: 09/03/31: Re: SiliconBlue on Wikipedia
139476: 09/03/31: Re: initialize BRAM contents
139490: 09/03/31: Re: Altera's free ColdFire v1 IP core anybody used it?
139491: 09/04/01: Re: Silicon Blue Warm-Boot not working properly
139492: 09/04/01: Re: clock distribution on VITA 57 (FMC)
139520: 09/04/02: Re: delays in XC95144XL CPLD
139524: 09/04/02: Re: Can I capture the jtag TDO pin of a Spartan3AN
139534: 09/04/02: Re: Can I capture the jtag TDO pin of a Spartan3AN
139604: 09/04/07: Re: pll
139618: 09/04/07: Re: Virtex6 software
139624: 09/04/07: Re: Modulo-10 counter
139637: 09/04/07: Re: Chipscope problem
139655: 09/04/08: Re: want to see and use Commands used by Xilinx ISE
139682: 09/04/08: Re: ANN: Antti-Brain March issue released
139686: 09/04/08: Re: Programming in Microblaze
139688: 09/04/09: Re: opencores again with problems?
139714: 09/04/10: Re: Noise in Stratix3?
139722: 09/04/10: Re: Strange order of BRAM data bus connections
139734: 09/04/10: Re: Avnet spartan 3A design issue
139736: 09/04/11: Re: S3A starterkit weird behaviou (mini quiz)
139739: 09/04/11: Re: warning:impact:2217 error shows in the status register, CRC Error
139744: 09/04/11: Re: warning:impact:2217 error shows in the status register, CRC Error
139771: 09/04/13: Re: Stupid question about COE files
139785: 09/04/13: Re: Stupid question about COE files
139787: 09/04/13: Re: Low-cost Altera FPGA roadmap
139789: 09/04/14: Re: Low-cost Altera FPGA roadmap
139791: 09/04/14: Re: Mobile low power DDR SDRAM and MIG
139795: 09/04/14: Re: Low-cost Altera FPGA roadmap
139796: 09/04/14: Re: Mobile low power DDR SDRAM and MIG
139812: 09/04/14: Re: Low-cost Altera FPGA roadmap
139827: 09/04/15: Re: S3A starterkit weird behaviou (mini quiz)
139864: 09/04/17: Re: best soft core(s) that have C compiler support
139868: 09/04/17: Re: Virtex-6 shipping?
139873: 09/04/17: Re: FPGA Buying
139878: 09/04/17: Re: Dual-frequency quartz oscillator with a FPGA ?
139880: 09/04/17: Re: Dual-frequency quartz oscillator with a FPGA ?
139881: 09/04/17: Re: Dual-frequency quartz oscillator with a FPGA ?
139894: 09/04/18: Re: Why is XST optimizing away my registers and how do I stop it?
139917: 09/04/19: Re: Atari VCS 2600 FPGA Cartridge
139933: 09/04/19: Re: PLL ratios (was Re: Dual-frequency quartz oscillator with a FPGA
139964: 09/04/21: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139967: 09/04/21: Re: new FPGA vendor
139971: 09/04/21: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139998: 09/04/23: Re: fpga locks up with slow signal, spartan chip, pin type issues.
139999: 09/04/23: Re: TODAY, April 27th, says Xilinx
140003: 09/04/23: Re: fpga locks up with slow signal, spartan chip, pin type issues.
140004: 09/04/23: Re: fpga locks up with slow signal, spartan chip, pin type issues.
140006: 09/04/23: Re: (Actel)Want Clock on Global Network , but input is normal I/O
140009: 09/04/23: Re: How to put area routing constraints in a xilinx flow
140013: 09/04/23: Re: How to put area routing constraints in a xilinx flow
140015: 09/04/23: Re: (Actel)Want Clock on Global Network , but input is normal I/O
140024: 09/04/24: Re: some soft-processors
140054: 09/04/25: Re: actel libero
140062: 09/04/26: Re: way to go Altera!
140088: 09/04/27: Re: ISE 11.1 drops support for Virtex-2/Pro and Spartan-2/E
140090: 09/04/28: Re: ISE 11.1 drops support for Virtex-2/Pro and Spartan-2/E
140093: 09/04/28: Re: ISE 11.1 Webpack: How to install for Suse 64 Bits?
140097: 09/04/28: Re: ISE 11.1 drops support for Virtex-2/Pro and Spartan-2/E
140136: 09/04/29: Re: best soft core(s) that have C compiler support
140161: 09/04/30: Re: ISE/EDK/SDK 11.1 licensing
140164: 09/05/01: Re: ISE/EDK/SDK 11.1 licensing
140186: 09/05/01: Re: ISE/EDK/SDK 11.1 licensing
140198: 09/05/02: Re: best soft core(s) that have C compiler support
140252: 09/05/05: Re: Spartan3E Starter Kit MISO and Flash pin shared
140260: 09/05/06: Re: some soft-processors
140361: 09/05/11: Re: which low cost fpga for space?
140382: 09/05/12: Re: which low cost fpga for space?
140395: 09/05/12: Re: XCF32P programming via JTAG
140418: 09/05/13: Re: cheapest FPGA?
140434: 09/05/13: Re: XCF32P programming via JTAG
140435: 09/05/13: Re: cheapest FPGA?
140453: 09/05/13: Re: Open source processors
140461: 09/05/14: Re: XCF32P programming via JTAG
140471: 09/05/14: Re: ISE multiple UCF files from commandline
140495: 09/05/14: Re: XILINX license model restricts longtime availability
140532: 09/05/15: Re: sdio lab testing help needed
140533: 09/05/15: Re: some soft-processors
140540: 09/05/16: Re: Access to BSCAN_SPARTANx or BSCAN_VIRTEXx from Python without
140542: 09/05/16: Re: Access to BSCAN_SPARTANx or BSCAN_VIRTEXx from Python without
140544: 09/05/16: Re: sdio lab testing help needed
140556: 09/05/17: Re: some soft-processors
140575: 09/05/18: Re: XILINX license model restricts longtime availability
140584: 09/05/19: Re: SD card bootstrap code in 55 instructions
140609: 09/05/20: Re: Actel Low Cost Programming Stick (IGLOO kits)
140612: 09/05/20: Re: Actel Low Cost Programming Stick (IGLOO kits)
140643: 09/05/20: Re: please recommend a soft processor for small image processing
140644: 09/05/20: Re: some soft-processors
140645: 09/05/20: Re: Open source processors
140656: 09/05/21: Re: please recommend a soft processor for small image processing
140674: 09/05/21: Re: Nibz VHDL Processor (Version G-spot)
140677: 09/05/21: Re: please recommend a soft processor for small image processing
140692: 09/05/21: Re: Nibz VHDL Processor (Version G-spot)
140693: 09/05/21: Re: Open source processors
140761: 09/05/25: Re: V5 GTX clocking
140804: 09/05/26: Re: 11.1 & USB cable drivers
140832: 09/05/27: Re: how i can to send a sequence of bytes to the FPGA ?
140848: 09/05/27: Re: how i can to send a sequence of bytes to the FPGA ?
140875: 09/05/27: Re: Nibz (Version P)
140876: 09/05/27: Re: Cyclone III == Spartan ?
140889: 09/05/28: Re: verilog in TV show (soon)
140901: 09/05/28: Re: ISE USB Slave Parallel programming
140902: 09/05/28: Re: phase locking a slow (2Mhz) signal.
140934: 09/05/30: Re: Has ST's FPGA project GOSPL transformed to Morpheus ?
140937: 09/05/30: Re: VHDL synthesis difference bwetween tools
140949: 09/05/30: Re: patent free ARM cores
140964: 09/06/01: Re: phase locking a slow (2Mhz) signal.
140971: 09/06/01: Re: Maximum tilemap size for Virtex6 devices?
140976: 09/06/01: Re: Peter Alfke's 6 EASY
140978: 09/06/01: Re: Maximum tilemap size for Virtex6 devices?
140981: 09/06/01: Re: Maximum tilemap size for Virtex6 devices?
141004: 09/06/02: Re: verilog in TV show (soon)
141020: 09/06/02: Re: Xilinx GbE performance
141024: 09/06/02: Re: Xilinx GbE performance
141026: 09/06/02: Re: Xilinx GbE performance
141027: 09/06/02: Re: Xilinx GbE performance
141028: 09/06/02: Re: Xilinx GbE performance
141030: 09/06/02: Re: VHDL synthesis difference bwetween tools
141067: 09/06/04: Re: ACTEL 8051s core
141133: 09/06/08: Re: Where are new Xilinx FPGAs ?
141172: 09/06/10: Re: async. SRAM control signal generation
141199: 09/06/10: Re: Virtex 5 LUT Outpus
141209: 09/06/11: Re: opencores shut down?
141218: 09/06/11: Re: Latest Xilinx Discontinuations
141240: 09/06/11: Re: Latest Xilinx Discontinuations
141259: 09/06/12: Re: async. SRAM control signal generation
141260: 09/06/12: Re: async. SRAM control signal generation
141271: 09/06/15: Re: Xilinx bitstream decompiler has been made and working
141365: 09/06/20: Re: TimingAnalyzer is now freeware
141377: 09/06/22: Re: Using SERDES to detect very high-speed pulse.
141447: 09/06/24: Re: Virtex-6 shipping?
141455: 09/06/24: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
141463: 09/06/24: Re: Virtex-6 shipping?
141474: 09/06/25: Re: SRAM vs Flash based FPGA one more time
141479: 09/06/25: Re: Has anybody tried ISE for Virtex-6/Spartan-6?
141480: 09/06/25: Re: Has anybody tried ISE for Virtex-6/Spartan-6?
141483: 09/06/25: Re: Has anybody tried ISE for Virtex-6/Spartan-6?
141490: 09/06/25: Re: Has anybody tried ISE for Virtex-6/Spartan-6?
141507: 09/06/25: Re: Virtex-6 shipping?
141518: 09/06/26: Re: opencores again with problems?
141519: 09/06/26: Re: SPARTAN-3AN open-drain at vccio1.8V
141522: 09/06/26: Re: Using Xilinx tools with ft2232 based programming cable.
141523: 09/06/26: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
141525: 09/06/26: Re: Using Xilinx tools with ft2232 based programming cable.
141529: 09/06/26: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
141543: 09/06/26: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
141544: 09/06/26: Re: Lattice Universal File Writer - command line problems
141548: 09/06/27: Re: 6/6 infos
141551: 09/06/27: Re: 6/6 infos
141559: 09/06/27: Re: Xilinx USB CABLE SCHEMATIC NOW OFFICIALLY PUBLISED !!!! ::)
141568: 09/06/28: Re: Xilinx USB CABLE SCHEMATIC NOW OFFICIALLY PUBLISED !!!! ::)
141570: 09/06/28: Re: Spartan3E or Cyclone III ?
141572: 09/06/28: Re: usefulness of Virtex-II devices
141578: 09/06/28: Re: FPGA / CPLD Group on LinkedIn -- Networking Group
141584: 09/06/28: Re: 6/6 infos
141591: 09/06/29: Re: STA Problem on Asynchronous FIFO
141628: 09/07/01: Re: FPGA as FM RADIO transmitter
141638: 09/07/01: Re: Cheapest FPGA with decent PCI- e interface ?
141646: 09/07/02: Re: Sign up for Multimedia SoC project
141705: 09/07/03: Re: 50 000 registered users at OpenCores.org
141714: 09/07/04: Re: 50 000 registered users at OpenCores.org
141717: 09/07/04: Re: 50 000 registered users at OpenCores.org
141721: 09/07/04: Re: 50 000 registered users at OpenCores.org
141728: 09/07/05: Re: Spartan-3A Device DNA ...
141730: 09/07/05: Re: Spartan-3A Device DNA ...
141736: 09/07/05: Re: Spartan-3A Device DNA ...
141779: 09/07/08: Re: Breakdown of utilisation
141789: 09/07/09: Re: Virtex 4 and 5
141835: 09/07/11: Re: Why do both Xilinx and Altera DPS use 18*18?
141839: 09/07/11: Re: Why do both Xilinx and Altera DPS use 18*18?
141850: 09/07/13: Re: xilinx mfs
141897: 09/07/15: Re: How to implementa an FSM in block ram
141899: 09/07/15: Re: How to implementa an FSM in block ram
141954: 09/07/19: Re: How to integerate Firmware into an FPGA
141968: 09/07/20: Re: Strange FPGA behavior
141995: 09/07/21: Re: VIRTEX-6 FXT announced soon?
141997: 09/07/21: Re: FM radio with Spartan3A kit, demo
141998: 09/07/21: Re: VIRTEX-6 FXT announced soon?
142046: 09/07/23: Re: DONE pin does'nt go high in SPARTAN - 3AN
142051: 09/07/23: Re: Laser marking / custom graphics on blank FPGA?
142056: 09/07/23: Re: Strange FPGA behavior
142118: 09/07/25: Re: How to implementa an FSM in block ram
142130: 09/07/26: Re: How to implementa an FSM in block ram
142149: 09/07/27: Re: mpmc kills plb bus on v4fx20
142164: 09/07/27: Re: OT? Something is wrong with this NG..
142165: 09/07/27: Re: how to access brams in FPGA
142175: 09/07/28: Re: Daisychaining fpga with SPI flash?
142183: 09/07/28: Re: Daisychaining fpga with SPI flash?
142216: 09/07/29: Re: PCIE2.0-based 1G/2G/2.5G ethenret NIC controller
142239: 09/07/29: Re: PCIE2.0-based 1G/2G/2.5G ethenret NIC controller
142246: 09/07/30: Re: Daisychaining fpga with SPI flash?
142248: 09/07/30: Re: Antti-Brain, should I keep going?
142272: 09/07/31: Re: Xilinx USB CABLE SCHEMATIC NOW OFFICIALLY PUBLISED !!!! ::)
142315: 09/08/03: Re: Program Memory Space for Microblaze Processor in Spartan-3A
142330: 09/08/05: Re: AES encryption of bitstream - is my design secure?
142338: 09/08/05: Re: AES encryption of bitstream - is my design secure?
142341: 09/08/05: Re: AES encryption of bitstream - is my design secure?
142395: 09/08/09: Re: EVERAGE ?
142396: 09/08/09: Re: EVERAGE ?
142401: 09/08/09: Re: Spartan-6 Boards - Your Wish List
142450: 09/08/11: Re: Is it possible to use OSERDES and ISERDES primitives internal to
142471: 09/08/12: Re: System gates: Altera <-> Actel
142474: 09/08/12: Re: Is it possible to use OSERDES and ISERDES primitives internal to
142489: 09/08/12: Re: Can I suppress invoking Block SelectRAMs in virtex5?
142497: 09/08/13: Re: JTAGkey-Tiny with Altera/Xilinx FPGA?
142520: 09/08/14: Re: Is it possible to generate double data rate stream in the Virtex4
142521: 09/08/14: Re: Is it possible to generate double data rate stream in the Virtex4
142534: 09/08/16: Re: Soft Processor IP core report
142536: 09/08/16: Re: Soft Processor IP core report
142544: 09/08/16: Re: Soft Processor IP core report
142553: 09/08/16: Re: Soft Processor IP core report
142558: 09/08/17: Re: Soft Processor IP core report
142587: 09/08/18: Re: Xilinx 3E design programs fine with 500E but fails with 250E
142591: 09/08/19: Re: Help with crystal oscillator (MG-7010SA replacement)?
142604: 09/08/20: Re: Xilinx 3E design programs fine with 500E but fails with 250E
142615: 09/08/21: Re: Xilinx 3E design programs fine with 500E but fails with 250E
142616: 09/08/21: Re: Xilinx 3E design programs fine with 500E but fails with 250E
142619: 09/08/21: Re: FM Broadcast receiver on Lyrtech SFF SDR Kit using vertex 4
142622: 09/08/21: Re: Soft Processor IP core report
142630: 09/08/22: Re: FM Broadcast receiver on Lyrtech SFF SDR Kit using vertex 4
142631: 09/08/22: Re: Need support for LVDS to Tmds translation on altera device
142634: 09/08/23: Re: Yet Another Graphics Controller
142639: 09/08/23: Re: Suitable starter kit for learning VHDL
142640: 09/08/23: Re: Soft Processor IP core report
142641: 09/08/23: Re: Yet Another Graphics Controller
142643: 09/08/23: Re: Operating the Spartan 3A FPGA at maximum speed (320 MHz)
142646: 09/08/24: Re: Operating the Spartan 3A FPGA at maximum speed (320 MHz)
142648: 09/08/24: Re: Help with crystal oscillator (MG-7010SA replacement)?
142651: 09/08/24: Re: Yet Another Graphics Controller
142653: 09/08/24: Re: Yet Another Graphics Controller
142680: 09/08/25: Re: Reading from ADC and writing to DAC at same time
142684: 09/08/25: Re: Reading from ADC and writing to DAC at same time
142717: 09/08/27: Re: program spartan3 under linux
142720: 09/08/28: Re: usb3.0 PHY wrapper for Xilinx V5/V6 device
142735: 09/08/28: Re: sharing sdram and parallel nor flash address/data bus using
142743: 09/08/29: Re: usb3.0 PHY wrapper for Xilinx V5/V6 device
142749: 09/08/30: Re: program spartan3 under linux
142750: 09/08/30: Re: program spartan3 under linux
142757: 09/08/30: Re: program spartan3 under linux
142758: 09/08/30: Re: program spartan3 under linux
142763: 09/08/31: Re: usb3.0 PHY wrapper for Xilinx V5/V6 device
142764: 09/08/31: Re: Virtex 5 HDMI
142776: 09/08/31: Re: usb3.0 PHY wrapper for Xilinx V5/V6 device
142786: 09/09/01: Re: Wants an update on FPGA development IDE/toolchains
142788: 09/09/01: Re: Wants an update on FPGA development IDE/toolchains
142791: 09/09/01: Re: Wants an update on FPGA development IDE/toolchains
142798: 09/09/01: Re: usb3.0 PHY wrapper for Xilinx V5/V6 device
142818: 09/09/02: Re: usb3.0 PHY wrapper for Xilinx V5/V6 device
142861: 09/09/04: Re: xc3sprog support for Altera Byteblaster
142864: 09/09/04: Re: Spartan-6 boards now REALLY in online shops
142870: 09/09/04: Re: Spartan-6 boards now REALLY in online shops
142872: 09/09/04: Re: Spartan-6 boards now REALLY in online shops
142929: 09/09/08: Re: Bidirectional Bus
142933: 09/09/08: Re: Bidirectional Bus
142935: 09/09/08: Re: Xilinx USB CABLE SCHEMATIC NOW OFFICIALLY PUBLISED !!!! ::)
142940: 09/09/09: Re: Bidirectional Bus
142946: 09/09/09: Re: Bidirectional Bus
142947: 09/09/09: Re: Bidirectional Bus
142952: 09/09/09: Re: Bidirectional Bus
142965: 09/09/10: Re: An email from Altera
142970: 09/09/10: Re: Bidirectional Bus
142978: 09/09/11: Re: Bidirectional Bus
142987: 09/09/13: Re: ANN: Coding style guidance for FPGA memory
142989: 09/09/13: Re: Spartan-6 - Pre-release Information on Drigmorn3.
142992: 09/09/13: Re: Spartan-6 - Pre-release Information on Drigmorn3.
142995: 09/09/14: Re: virtex-6 CXT announced
143012: 09/09/14: Re: 8 phase clock output
143016: 09/09/14: Re: To Xilinx: Regarding the download manager
143020: 09/09/15: Re: ANN: Coding style guidance for FPGA memory
143022: 09/09/15: Re: To Xilinx: Regarding the download manager
143028: 09/09/15: Re: 8 phase clock output
143031: 09/09/15: Re: 8 phase clock output
143040: 09/09/16: Re: 8 phase clock output
143043: 09/09/16: Re: 8 phase clock output
143051: 09/09/17: Re: WARP PLD's are back in new shape
143064: 09/09/17: Re: 8 phase clock output
143090: 09/09/19: Re: Actel dropped ARM7, when comes Xilinx ARM enabled silicon?
143096: 09/09/19: Re: Actel dropped ARM7, when comes Xilinx ARM enabled silicon?
143121: 09/09/22: Re: VHDL question
143134: 09/09/22: Re: USB programmable Open Source Hardware
143146: 09/09/23: Re: USB programmable Open Source Hardware
143147: 09/09/23: Re: USB programmable Open Source Hardware
143150: 09/09/23: Re: USB programmable Open Source Hardware
143151: 09/09/23: Re: Shift left arithmetic?
143154: 09/09/23: Re: Shift left arithmetic?
143155: 09/09/23: Re: 8 phase clock output
143158: 09/09/23: Re: USB programmable Open Source Hardware
143159: 09/09/23: Re: USB programmable Open Source Hardware
143161: 09/09/23: Re: 8 phase clock output
143162: 09/09/23: Re: 8 phase clock output
143173: 09/09/23: Re: 8 phase clock output
143178: 09/09/24: Re: USB programmable Open Source Hardware
143179: 09/09/24: Re: Virtex 4 configruation frame internal details
143191: 09/09/24: Re: USB programmable Open Source Hardware
143207: 09/09/25: Re: Super Small MIPS-compatible Altera-Based Soft Processor and
143225: 09/09/27: Re: USB programmable Open Source Hardware
143226: 09/09/27: Re: USB programmable Open Source Hardware
143233: 09/09/27: Re: USB programmable Open Source Hardware
143234: 09/09/27: Re: USB programmable Open Source Hardware
143235: 09/09/27: Re: USB programmable Open Source Hardware
143236: 09/09/27: Re: USB programmable Open Source Hardware
143237: 09/09/27: Re: USB programmable Open Source Hardware
143244: 09/09/28: Re: USB programmable Open Source Hardware
143245: 09/09/28: Re: USB programmable Open Source Hardware
143251: 09/09/28: Re: USB programmable Open Source Hardware
143259: 09/09/28: Re: Xilinx RTL view question
143260: 09/09/28: Re: USB programmable Open Source Hardware
143264: 09/09/28: Re: USB programmable Open Source Hardware
143277: 09/09/29: Re: SP601 HDL source files available?
143278: 09/09/29: Re: SP601 HDL source files available?
143282: 09/09/29: Re: USB programmable Open Source Hardware
143296: 09/09/30: Re: USB programmable Open Source Hardware
143297: 09/09/30: Re: USB IP block vendors?
143301: 09/09/30: Re: USB programmable Open Source Hardware
143302: 09/09/30: Re: USB programmable Open Source Hardware
143311: 09/10/01: Re: Antti-Brain one year anniversary
143315: 09/10/01: Re: Implement ARM cores on a FPGA chip?
143329: 09/10/02: Re: Antti-Brain one year anniversary
143338: 09/10/02: Re: Implement ARM cores on a FPGA chip?
143349: 09/10/04: Re: Implement ARM cores on a FPGA chip?
143352: 09/10/04: Re: Implement ARM cores on a FPGA chip?
143381: 09/10/07: Re: 8 phase clock output
143422: 09/10/11: Re: Getting started...
143438: 09/10/11: Re: 8 phase clock output
143439: 09/10/11: Re: Getting started...
143444: 09/10/12: Re: Getting started...
143447: 09/10/12: Re: Implement ARM cores on a FPGA chip?
143450: 09/10/12: Re: FPGA ruined (?)
143469: 09/10/12: Re: Win a Dev Kit--Join Us on Twitter & Facebook
<Antti.Lukats@xilant.com>:
94369: 06/01/10: Re: Altera MAX-II: User logic access to USERCODE_REGISTER?
94386: 06/01/10: Re: Will ISE 8.1 work together with EDK 7.1?
95208: 06/01/21: Re: Reading user data from PROM
96337: 06/02/02: Re: microblaze GNU tools, OutOfTree compile for uClinux on Win32
<antti.tyrvainen@luukku.com>:
103053: 06/05/25: Quartus and Cygwin X-server
103210: 06/05/28: Re: Quartus and Cygwin X-server
103561: 06/06/05: Re: Quartus and source control
105075: 06/07/13: Re: Micorblaze post place and route simulation...
105077: 06/07/13: Re: Micorblaze post place and route simulation...
106684: 06/08/17: Re: Reinstalled Quartus + Nios II => cygwin1.dll hell :-(
106753: 06/08/18: Re: Quartus and source control (continued)
129526: 08/02/26: Re: Does Altera has some analogous file like XDL of Xilinx?
antyfire:
anudeep:
151042: 11/03/01: Re: encryption in FPGA
Anuja:
89697: 05/09/22: downlaoding bit files to Xilinx FPGA
89713: 05/09/23: Re: downlaoding bit files to Xilinx FPGA
89715: 05/09/23: Re: downlaoding bit files to Xilinx FPGA
89738: 05/09/23: Re: downlaoding bit files to Xilinx FPGA
89782: 05/09/26: Re: downlaoding bit files to Xilinx FPGA
89869: 05/09/28: Re: downlaoding bit files to Xilinx FPGA
90202: 05/10/06: Verification using Chipscope
126860: 07/12/04: converting verilog to vhdl
126928: 07/12/06: Re: converting verilog to vhdl
126937: 07/12/06: Re: converting verilog to vhdl
126969: 07/12/07: Re: converting verilog to vhdl
126973: 07/12/07: Re: converting verilog to vhdl
126979: 07/12/07: Re: converting verilog to vhdl
126990: 07/12/07: Re: converting verilog to vhdl
126992: 07/12/07: Re: converting verilog to vhdl
127302: 07/12/17: multidimensional arrays in VHDL?
127305: 07/12/17: Re: multidimensional arrays in VHDL?
127306: 07/12/17: Re: multidimensional arrays in VHDL?
127317: 07/12/18: Re: multidimensional arrays in VHDL?
127328: 07/12/18: Re: multidimensional arrays in VHDL?
128126: 08/01/16: Quartus II Incremental compilation?
128153: 08/01/16: Re: Quartus II Incremental compilation?
128725: 08/02/05: Re: Scaling data
128806: 08/02/06: Re: function/process to generate sine and cosine wave
Anukul:
62250: 03/10/22: Fatal error while compiling code
anup:
25217: 00/08/31: Re: Xilinx and CD databooks (rant)
25564: 00/09/14: Advertisement of a new e-Group/mailing list --
25813: 00/09/21: Is Incremental Routing Supported in Xilinx -Foundation 3.1
27767: 00/12/07: Need help regarding Partial reconfiguration
27785: 00/12/08: Re: Need help regarding Partial reconfiguration
27817: 00/12/10: Re: Need help regarding Partial reconfiguration
81116: 05/03/17: Performance evaluation of Distributed Arithmetic architectures for FIR filters
81120: 05/03/17: Re: Performance evaluation of Distributed Arithmetic architectures for FIR filters
88702: 05/08/25: On a different note: Unable to write edif files in Synopsys Design Compiler
anup chandak:
55155: 03/04/29: general: vhdl
anup kumar raghavan:
18056: 99/09/27: About Evolvable Hardware
18057: 99/09/27: VCC.com
18112: 99/10/01: Are all SRAM based FPGAs -Reconfigurable devices.
18584: 99/11/02: XNF file formats ???
18687: 99/11/08: Re: looking for XNF Grammar
18724: 99/11/10: where can I find fitter algorithms
18755: 99/11/12: What are the steps involved in the developement of a CAD tool
20875: 00/02/25: FPGA Express Synthesis Now Available Over The Internet
Anup Kumar Raghavan:
49696: 02/11/19: Input / Output flop in IOB + Virtex II
52201: 03/02/05: Re: Xilinx's XDL
53201: 03/03/07: Week Keepers and Pull ups
57781: 03/07/07: Spartan XL Tool Support
57929: 03/07/10: Spartan XL Prom Selection
58042: 03/07/14: Re: Spartan XL Prom Selection
58043: 03/07/14: Virtex Bitstream verification
63691: 03/12/01: XC2VP70 FPGA board suggestions
Anup Raghavan:
49471: 02/11/12: Tristate buffers + leonardo Spectrum
63628: 03/11/26: Phy IP for Giga ethernet for Virtex -II Pro
71406: 04/07/17: FPGA Development board with onboard Ethernet PHY
71417: 04/07/17: Re: FPGA Development board with onboard Ethernet PHY
93004: 05/12/12: Re: Problem with ChipScope Pro 6.2
<anup@ece.ucsb.edu>:
91545: 05/11/08: Wirelength information from Xilinx ISE 6.1
anupam:
91060: 05/10/27: hex rep. in VHDL
91132: 05/10/30: Re: hex rep. in VHDL
91312: 05/11/03: Re: Using inout ports in VHDL
96709: 06/02/09: Re: Open Verification Libiary Free Download
96710: 06/02/09: Re: Open Verification Libiary Free Download
99690: 06/03/28: Re: Verilog, PSL or SystemVerilog of OVL?
anupr:
64013: 03/12/12: Re: Embedded Powerpc in xilinx
Anurag:
16970: 99/06/21: Re: PLL for FPGA
16971: 99/06/21: FPGA in Wireless Designs
17107: 99/07/01: FPGAs v/s DSPs in Cell phones
41274: 02/03/24: RTP & Aggregation design
anurag:
15905: 99/04/20: FPGA for PC Cards
20388: 00/02/08: MP3 & Wavelet on FPGA
20437: 00/02/10: FPGA IP complexity
Anurag Tiwari:
21512: 00/03/23: debugger
21580: 00/03/25: DLL
21820: 00/04/01: RISC/CISC Processor with Reconfigurable Logic
22547: 00/05/11: Re: FPGA emulators?
23693: 00/07/05: Timing Simulation on wildforce board
26240: 00/10/09: 68000 vhdl model
anushina:
141060: 09/06/04: Need help VHDL code 5-to-7 decoder (Xilinx)
141069: 09/06/04: Re: Need help VHDL code 5-to-7 decoder (Xilinx)
anvesh:
98794: 06/03/16: risc processor in altera up3 kit
99777: 06/03/29: Re: risc processor in altera up3 kit
any2letters:
114902: 07/01/25: Timing Diagram Tool
<anyone@anywhere.com>:
59421: 03/08/19: Re: ALTERA Byte BlasterII <--Link Inside
<aosik5@gmail.com>:
81671: 05/03/29: Spartan II-e PCB
82772: 05/04/17: SPROM JTAG confusion!
83025: 05/04/21: JTAG and SPROM for Spartan II-e
<aoui0r93809@asadszlkjaslkjz.net>:
18565: 99/11/01: Inkjets 4 you!
AP:
4000: 96/09/01: *** FREE INTERNET! *** Forever!
38731: 02/01/23: IDT7204 Using CoreGen
38768: 02/01/24: Re: IDT7204 Using CoreGen
39384: 02/02/07: Schema Schematic Capture/ C models
54486: 03/04/11: Quartus II and user libraries
54510: 03/04/12: Re: Quartus II and user libraries
54546: 03/04/14: Re: Quartus II and user libraries
54704: 03/04/16: Re: Quartus II and user libraries
55210: 03/04/30: DDR SDRam Controller on ACEX1K
55213: 03/04/30: Defining I/O pin as registered on Quartus II (v2.2)
55232: 03/05/01: Re: Defining I/O pin as registered on Quartus II (v2.2)
55322: 03/05/04: Re: DDR SDRam Controller on ACEX1K
56592: 03/06/10: Altera static timing analisys
apai:
72933: 04/09/08: EDIF generation from Verilog in ISE 6.2i
apalopohapa:
144556: 09/12/14: Best clock output pin in Spartan-3
apda:
4038: 96/09/05: test
Apeak:
42124: 02/04/16: Synario v2.3
42420: 02/04/23: PAL and GAL
<apeters@noao.edu>:
24893: 00/08/21: Re: Looks like Xilinx is at it again!
<aphedorov@yandex.ru>:
109029: 06/09/20: Xilinx System Generator -> Block RAM
Aphraton:
156183: 14/01/10: Looking for a simple SPDIF to I2S audio convertor IP.
Apinetr Unakul:
14659: 99/02/09: Re: Board for XC4085XL
Apllehead:
35592: 01/10/11: Re: Virtex2 DCM: frequenqy synthesis
<apodgorny@my-dejanews.com>:
14834: 99/02/19: DPLL&ADPLL tutorials needed.
Apollo:
41737: 02/04/05: Debussy warnings!
45829: 02/08/06: Xilinx TIG
53630: 03/03/18: Strict Priority scheduling
53738: 03/03/20: how do implement the exponential algorithm in fpga?
53744: 03/03/21: how do implement the exponential algorithm in fpga?
53771: 03/03/21: how do implement the algorithm in verilog?
53783: 03/03/22: Re: how do implement the algorithm in verilog?
Apolonio B. Sanches:
5807: 97/03/17: PLC
Apostol:
94700: 06/01/16: Xilinx HW-SPAR3_CPLD-DK kit
APP01:
6353: 97/05/17: Re: FPGA gate counting: No truth in advertising
6352: 97/05/17: Re: universal PCI-Interface with FPGA?
6354: 97/05/17: Re: VHDL PCI FPGA Implementation
7860: 97/10/24: Wallace Tree Multipliers
7906: 97/10/29: Re: ORCA Foundry Back Annotation Quesiton
7975: 97/11/05: Re: 64 BIT PCI bridge in FPGA?
9365: 98/03/07: Re: crossbar switch
9841: 98/04/09: Re: USB bus interface (12 mbit/sec) in an FPGA - how difficult?
11735: 98/09/05: Re: FPGA Manufacturer's gate counts
16121: 99/05/05: Looking for Vhdl/verilog functions
apple:
63270: 03/11/18: Does anyone know anything about DC-FPGA?
147988: 10/06/10: Alternative to Chipscope
apple88888:
36727: 01/11/17: Does anybody knows where have a free(open hardware) FPGA PCI Development board whith PCB data.....?
Applications Division:
2811: 96/02/12: Re: 8274 Inside FPGA?
<appu.iitm@gmail.com>:
138527: 09/02/25: Required MCS file and SVF File details
APS:
7880: 97/10/26: Re: XILINX pin compatible replacements
7948: 97/11/01: Re: Pin compatible
7939: 97/11/01: Re: Questions about FPGA hardware design
7946: 97/11/01: Re: 'compatible' fpgas
7999: 97/11/06: LOW COST XILINX/LUCENT PACKAGES
10265: 98/05/08: Re: Low power FPGA design
10266: 98/05/08: Synopsys Xpress and numeric_std.lib
10279: 98/05/09: ANNOUNCEMENT: XILINX 208pin QFP board page
10280: 98/05/09: Re: Help: 25Mhz XC4025E-2 FPGA having hold time errors during simulation
10401: 98/05/16: Re: available eda environments
10489: 98/05/23: Re: Xilinx Foundation Student Edition
10490: 98/05/23: Announce: X208 Board Ram pattern Generator VHDL Example
10596: 98/06/04: Announce: Free On-Line EDA Newsletter Release
10932: 98/07/04: Re: Spartan test-board
10934: 98/07/04: Re: complete testing
10933: 98/07/04: Re: Consultants
11103: 98/07/19: CRC Implementation
11104: 98/07/19: Re: Floorplanning Intro?....seems to be HDL v schematics sort of ;-)
11105: 98/07/19: Re: Floorplanning Intro?....seems to be HDL v schematics sort of ;-)
11212: 98/07/26: Re: C- interface
11439: 98/08/13: Re: Newbie seeks cheap fun w/FPGAs
11547: 98/08/22: Re: Example Code
11548: 98/08/22: Re: FPGA beginner searching for the proper direction
11670: 98/08/30: Re: CPLD/FPGA software
11671: 98/08/30: Re: (req)I'm looking for foundation
11713: 98/09/03: Re: Wait statements and while loops
11871: 98/09/15: Free Newsletter and VHDL/FPGA tutorial tech notes
11927: 98/09/19: Re: Xilinx Configuration Info
11928: 98/09/19: Re: VHDL Tools
12063: 98/09/26: Free FPGA/HDL Newsletter Announcement
13074: 98/11/14: Re: Software tool
13075: 98/11/14: Re: Board for FPGA ?
13918: 99/01/02: XILINX PC104 FPGA card Now available from APS
14300: 99/01/24: Re: Synthesis tools for Xilinx FPGAs
14456: 99/01/30: Announce: Stackable XILINX FPGA Modules PC104 or standalone
14735: 99/02/13: Derived Clocks and Clock enables in XILINX parts
14736: 99/02/13: Re: Board for XC4085XL
14737: 99/02/13: Re: Board for XC4085XL
14738: 99/02/13: Re: Q: How to add contstraints in synopsys->Xilinx?
15277: 99/03/17: Re: Want to learn about FPGA.
15371: 99/03/21: Re: Bit Error Rate Test
15372: 99/03/21: Re: From VHDL to FPGA?
15373: 99/03/21: Re: Free Xilinx Vendor Tools ... NOT :-(
15545: 99/03/30: Re: VHDL source code
15734: 99/04/10: Free FPGA-HDL Newsletter Release
15766: 99/04/12: Re: Viewlogic FPGA Express vs Xilinx FPGA Express....any difference?
15996: 99/04/26: APS Free EDA Newsletter Released Q199
16497: 99/05/25: Re: DSP Board for PC/104 Bus
16992: 99/06/22: Re: UART Design
16993: 99/06/22: Re: FPGA board for ISA bus wanted
16995: 99/06/22: Re: Simple PCI card prototyping.
16996: 99/06/22: Re: PLL for FPGA
<aps@associatedpro.com>:
6863: 97/07/03: FREE Q2 EDA NEWSLETTER RELEASED
<apsolar@gmail.com>:
89339: 05/09/13: Tree Representation of Logic Circuits
<apsolar@rediffmail.com>:
87524: 05/07/25: How to implement Evolvable Hardware ?
87933: 05/08/03: Where can i find GeneticFPGA toolkit
87948: 05/08/04: Re: Where can i find GeneticFPGA toolkit
88022: 05/08/05: Re: Where can i find GeneticFPGA toolkit
88053: 05/08/08: Re: Where can i find GeneticFPGA toolkit
88123: 05/08/09: Re: Where can i find GeneticFPGA toolkit
88214: 05/08/12: Re: Where can i find GeneticFPGA toolkit
88292: 05/08/14: Re: Where can i find GeneticFPGA toolkit
88389: 05/08/16: Evolutionary VHDL code example
88432: 05/08/18: Re: Evolutionary VHDL code example
88624: 05/08/24: Software simulation of hardware evolution
aptecelectronics:
92651: 05/12/02: Re: Pal programming requirement
<apunte@apunte.es>:
21477: 00/03/23: AUTOVITRINA.COM
APURVA A BRAHMBHATT:
3572: 96/06/27: HELP:Foundation VHDL on WIN95
apurvewarrior@gmail.com:
93250: 05/12/16: FPGA Implementation Of Real Time Data Compression
<ar679deja@my-deja.com>:
17640: 99/08/17: Quartus Problems
17681: 99/08/23: Re: JTAG 1149 Info
18495: 99/10/27: Re: Altera UNIX licence
<ar_kf@yahoo.com>:
92470: 05/11/30: DSP vs FPGA
ARABIAN:
<arafeeq@my-deja.com>:
18885: 99/11/20: Synplify vs. FPGA Compiler II (v3.3)
18909: 99/11/21: Synplify vs. FPGA Compiler II (v3.3)
19052: 99/11/25: Xilinx Virtex design (xcv-800) into production
Aragorc:
148595: 10/08/04: Generic parameters in Actel Libero SmartDesign Components
Aragorn:
129686: 08/03/03: Re: Random Number Generation in VHDL
arant:
106595: 06/08/15: Reset asynchronous assertion synchronous deassertion
106615: 06/08/16: Re: Reset asynchronous assertion synchronous deassertion
107419: 06/08/28: Re: Arbiter design problem?
<ararghNOSPAM@NOT.AT.enteract.com>:
56044: 03/05/27: Re: JTAG madness
56053: 03/05/27: Re: JTAG madness
56056: 03/05/27: Re: JTAG madness
Arash:
111809: 06/11/10: I look for a wideband SERDES chip
111841: 06/11/10: Re: I look for a wideband SERDES chip
111863: 06/11/11: Re: I look for a wideband SERDES chip
Arash Majd:
98415: 06/03/09: a problem with coolrunner CPLD (XC2C256) GCK0 pin
98442: 06/03/10: Re: a problem with coolrunner CPLD (XC2C256) GCK0 pin
98472: 06/03/10: Re: a problem with coolrunner CPLD (XC2C256) GCK0 pin
99529: 06/03/26: Re: a problem with coolrunner CPLD (XC2C256) GCK0 pin
100153: 06/04/04: Re: a problem with coolrunner CPLD (XC2C256) GCK0 pin
Arash Partow:
111562: 06/11/06: Schifra Reed-Solomon ECC Library
133088: 08/06/17: Re: FPGA to solve the two most annoying problems on usenet -
Arash Salarian:
38908: 02/01/28: FPGA or Micro-controller in Lowpower designs?
38982: 02/01/29: Re: FPGA or Micro-controller in Lowpower designs?
38983: 02/01/29: Re: FPGA or Micro-controller in Lowpower designs?
39028: 02/01/30: Re: FPGA or Micro-controller in Lowpower designs?
39039: 02/01/30: Re: 18bit counter
40708: 02/03/13: Synthesis tools comparison?
40735: 02/03/14: Re: Synthesis tools comparison?
42616: 02/04/29: Re: FlexLM
43514: 02/05/22: Re: Difference between Altera and Xilinx.
44022: 02/06/10: Re: Power supply caps on PCB
44817: 02/07/02: Power consumtion simulation for FPGA?
44819: 02/07/02: Re: Power consumtion simulation for FPGA?
44870: 02/07/03: Re: Power consumtion simulation for FPGA?
44905: 02/07/05: Re: Could someone please simplify Synplify for me...
45213: 02/07/16: problem porting sync write, async read RAM to Xilinx...
45214: 02/07/16: Re: problem porting sync write, async read RAM to Xilinx...
45215: 02/07/16: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
45233: 02/07/17: Re: problem porting sync write, async read RAM to Xilinx...
45234: 02/07/17: Re: AT40K / FPSLIC - Place & Route tools (3rd party)?
45801: 02/08/06: how to mix singed and unsigned signals in verilog?
47890: 02/10/07: Re: FPGA with an EPROM on it?
47891: 02/10/07: Re: Goertzel algorithm tone detector
47941: 02/10/08: Re: FPGA with an EPROM on it?
48115: 02/10/11: Re: Verilog vs VHDL discussion on comp.arch.verilog group
52042: 03/01/29: Re: Reading External .txt files in Quartus II
52068: 03/01/30: Re: Reading External .txt files in Quartus II
52511: 03/02/12: Re: Quartus / ModelSim
53585: 03/03/17: Re: comp.arch.fpga : VCC shorted to GND within FPGA???
54154: 03/04/03: What is DA and SLR16?
54176: 03/04/04: Re: What is DA and SLR16?
55762: 03/05/19: Re: a (PC) workstation for FPGA development
57244: 03/06/26: Low-power FPGA
63046: 03/11/13: Re: Frequency Doubler - VHDL/Verilog
63992: 03/12/11: Re: Soldering of FPGAs
64091: 03/12/16: Re: FLEX 10K50E, which software support it?
71593: 04/07/23: Re: Altera FPGA's
71594: 04/07/23: Re: Resources on FPGA wanted...
71877: 04/08/03: Re: Best tool(s) for filter float->fixed->VHDL flow?
73124: 04/09/14: ERSA low cost BGA assembly system?
74482: 04/10/12: EP1C12 or XC3S400?
74512: 04/10/13: Re: EP1C12 or XC3S400?
74514: 04/10/13: Re: EP1C12 or XC3S400?
74515: 04/10/13: Re: EP1C12 or XC3S400?
74523: 04/10/13: Re: EP1C12 or XC3S400?
74563: 04/10/14: Re: EP1C12 or XC3S400?
74564: 04/10/14: Re: EP1C12 or XC3S400?
74621: 04/10/15: Re: EP1C12 or XC3S400?
74743: 04/10/18: Re: How many Altera LE's to Xilinx Slices????
74845: 04/10/20: Re: Anyone routing signals between balls in FBGA?
74846: 04/10/20: Re: Experiences with SPARTAN3?
74847: 04/10/20: Re: Internal Capture of clock in FPGA
74848: 04/10/20: Re: counter skrews up design
74849: 04/10/20: Re: unstable fpga design
74852: 04/10/20: Re: How To Provide External Input & Output To Startix 1S40..?
74906: 04/10/21: Re: interfacing a PC based program with a FPGA
75689: 04/11/12: Re: digital analog conversion
76555: 04/12/06: Re: Connecting a spartan2 FPGA to an ISA bus
76611: 04/12/07: Re: Connecting a spartan2 FPGA to an ISA bus
76888: 04/12/15: Re: algorithm: square operation
80492: 05/03/07: Re: state encoding in FSM for simple cases ?
87024: 05/07/13: Re: 16-bit Acesses on ISA bus
87025: 05/07/13: Re: Unrolled Pipeline Implementation
87026: 05/07/13: Re: Safe State Machine Design in AHDL
87027: 05/07/13: Re: Testbenching and verification
87195: 05/07/19: Re: EHLO, board designers
108632: 06/09/14: Re: Prefered ieee libraries?
aravind:
111142: 06/10/30: Picoblaze simulation
111147: 06/10/30: Re: PC configuration for best Xilinx ISE performance
111235: 06/10/31: SPDIF receiver
111292: 06/10/31: Re: SPDIF receiver
111306: 06/11/01: Re: SPDIF receiver
112668: 06/11/27: edk evaluation
114909: 07/01/25: how do you code this?
114917: 07/01/26: Re: how do you code this?
114940: 07/01/27: Re: how do you code this?
114968: 07/01/28: Re: how do you code this?
124296: 07/09/18: Tristate bus on spartan FPGA
124343: 07/09/18: Re: Tristate bus on spartan FPGA
125252: 07/10/18: Fast Sampling of digital signals
125258: 07/10/18: Re: Fast Sampling of digital signals
127313: 07/12/17: Darnaw module
127345: 07/12/18: Re: Darnaw module
129463: 08/02/25: Xilinx parallel cable 4 clone
arb name:
28216: 01/01/01: Re: Fpga:How can I specify RLOC constraint in Leonardo
Arbitrary:
41323: 02/03/26: Re: Can't detect Altera MAX7000s using JTAG
41325: 02/03/26: Re: Can't detect Altera MAX7000s using JTAG
41362: 02/03/26: ByteblasterMV EPM7064S voltage problem
41381: 02/03/27: Re: ByteblasterMV EPM7064S voltage problem
41625: 02/04/03: Re: ByteblasterMV EPM7064S voltage problem
Arbour:
14194: 99/01/19: jobs@arbour.co.uk - UK permanent vacancies for embedded software and hardware engineers
Arcadius A.:
65433: 04/01/29: FPGA basics
arcdoos:
142214: 09/07/29: PCIE2.0-based 1G/2G/2.5G ethenret NIC controller
142236: 09/07/29: Re: PCIE2.0-based 1G/2G/2.5G ethenret NIC controller
Arch^Mage:
19203: 99/12/05: Schematic Help Please....
archana:
121626: 07/07/10: configuring vertex4 FPGA
121629: 07/07/10: slave serial configuration of Vertex FPGA using a microcontroller
122371: 07/07/26: Programing Vertex 4 FPGA by PIC
122745: 07/08/06: how to test the FPGA on the board
130885: 08/04/04: loop back on a MARVELL switch
Archer Lawrence:
6338: 97/05/16: File Format for Xilinx bitstream
archilleswaterland@hotmail.com:
82919: 05/04/19: OV6620 PCLK CLK
89242: 05/09/08: Timing Violation Quartus "__Z" issue
Arena.Yang:
44222: 02/06/13: I am a novice at FPGA.Please take care of me.THX!
Ares Rao:
150799: 11/02/13: LDPC Decoder IP core
argee:
125869: 07/11/07: Custom processor developement issues
125874: 07/11/07: Re: Custom processor developement issues
125886: 07/11/08: Re: Custom processor developement issues
126790: 07/12/02: Re: can't genarate block memory cores in ISE 7.1i
131244: 08/04/17: Wishbone, TSK3000 and endianness problem
135275: 08/09/23: Simulating BRAMs using ISE simulator?
135305: 08/09/25: Re: wishbone interface
141288: 09/06/16: Re: Ethernet y MicroBlaze with Spartan 3e starter kit
Argirhs Diamanths:
1001: 95/04/11: Device XC7336 not in XACT device list
Arguo:
36642: 01/11/13: SDRAM Module vs. SDRAM
46510: 02/09/02: high-speed design rule on FPGAs?
ARH:
120335: 07/06/05: Re: Topics and Ideas for BS Project
120353: 07/06/05: Re: Topics and Ideas for BS Project
120397: 07/06/06: Re: Topics and Ideas for BS Project
120456: 07/06/07: Re: verilog HDL problem
120502: 07/06/07: Re: HELP with Asynch RAM
arie:
87479: 05/07/24: Excalibur full strip simulation on solaris.
87536: 05/07/25: Re: Excalibur full strip simulation on solaris.
87594: 05/07/26: Re: Excalibur full strip simulation on solaris.
Arie Zychlinski:
10722: 98/06/12: book on ASIC
Arie de Muynck:
9772: 98/04/04: Re: Smoking Crater in a Xilinx 3k FPGA
22580: 00/05/12: Re: OT ANNOUNCE: Embedded Systems Glossary and Bibliography
53967: 03/03/28: Re: Anyone have difficulty downloading this core?
53991: 03/03/30: Re: Anyone have difficulty downloading this core?
53992: 03/03/30: Re: Anyone have difficulty downloading this core?
56131: 03/05/29: Re: JTAG madness
142067: 09/07/23: Re: DONE pin does'nt go high in SPARTAN - 3AN
151777: 11/05/17: Re: Scoping a glitch
Arie Zychlinski:
36912: 01/11/25: ALTERA's Mercury CDR
59343: 03/08/15: comp.lang.vhdl
69985: 04/05/26: Re: SDRAM controller
69986: 04/05/26: SystemC book
Arif Khan:
611: 95/01/18: Question on Xilinx Development System
arif tumer:
4294: 96/10/11: Make Money
arik:
142185: 09/07/28: Re: PAR runs successfully, simulation fails
Arin Kjempenes:
608: 95/01/18: pci source code
arincm@hotmail.com:
89272: 05/09/09: creating a custom opb bus master
arithos.designs2008@gmail.com:
134765: 08/08/29: Weekend DSP + DIP +VLSI front end training starting from 6th
arjen:
8097: 97/11/17: 100.000gates
Arkadiusz Grzywna:
57423: 03/06/30: Re: Asynchronous RESET?
Arkady Skorokhod:
22730: 00/05/20: What is ASIC and FPGA?
Arkaitz:
60539: 03/09/16: MICROBLAZE: Using external instruction memory
arkaitz:
53111: 03/03/04: Multi cpu Nios processor through SoPC Builder
54144: 03/04/03: Internal net names on ISE Foundation
56270: 03/06/02: NIOS-GERMS
60010: 03/09/03: MICROBLAZE: user core problem
61659: 03/10/08: Re: MICROBLAZE: Using external instruction memory
61698: 03/10/08: Re: MICROBLAZE: Using external instruction memory
61713: 03/10/09: Re: MICROBLAZE: Using external instruction memory
61763: 03/10/10: Re: MICROBLAZE: Using external instruction memory
62037: 03/10/17: MICROBLAZE: executing program from external memory
62120: 03/10/20: Re: MICROBLAZE: executing program from external memory
63279: 03/11/19: XPS - Compiliing Core Generator's components
63827: 03/12/04: VHDL: Different direction buses
63838: 03/12/05: Re: VHDL: Different direction buses
63840: 03/12/05: Dual-port and single-port BlockRAM instantiation
63847: 03/12/05: "PIPELINE MODEL" constant in EDK 6.1
63921: 03/12/09: Re: Dual-port and single-port BlockRAM instantiation
63923: 03/12/09: Re: Different direction buses
64026: 03/12/12: Analyzing the design with ChipScope Pro
64142: 03/12/18: Exporting a EDK design to Project Navigator
65031: 04/01/19: Trouble using ChipsCope Pro with MicroBlaze
65084: 04/01/20: Re: Trouble using ChipsCope Pro with MicroBlaze
65156: 04/01/21: Re: Trouble using ChipsCope Pro with MicroBlaze
65220: 04/01/22: Re: Trouble using ChipsCope Pro with MicroBlaze
65221: 04/01/22: Post-Place & Route simulation with MicroBlaze
65275: 04/01/23: Re: Post-Place & Route simulation with MicroBlaze
65387: 04/01/27: Interruptions in MicroBlaze
65776: 04/02/06: Trouble with interrupt controller
67642: 04/03/16: Core Generator path
68843: 04/04/20: Trouble with rising edge signals in functional simulation
68881: 04/04/21: Re: Trouble with rising edge signals in functional simulation
68922: 04/04/21: Re: Trouble with rising edge signals in functional simulation
69060: 04/04/26: Simulating two clock domains
69097: 04/04/27: Re: Simulating two clock domains
69173: 04/04/29: Post-Place & Route Simulation with ISE
69210: 04/04/29: Re: Post-Place & Route Simulation with ISE
69399: 04/05/10: Instantiating subblock signals with VHDL
69496: 04/05/12: Mapping port for simulation only in VHDL
69533: 04/05/13: Re: Mapping port for simulation only in VHDL
arko:
130140: 08/03/16: Re: Virtex-5 FX when ? (III)
133042: 08/06/15: Will Modelsim XE 6.3c (Win32) run in Linux/WINE?
135069: 08/09/12: Re: Quartus II compile speedup with New Quad Core Intel machine (compared with old dual XEON workstation)
Arlan Lucas de Souza:
12236: 98/10/06: ADC & 8253 timer
Arlen:
69090: 04/04/26: Xilinx Block RAM Init
Arlet:
80425: 05/03/05: XST block ram init in include files
84591: 05/05/22: Re: How to make a 1.44MHz clock?
91840: 05/11/14: Re: Having trouble Detecting ethernet packets using ethereal
91877: 05/11/15: Re: Having trouble Detecting ethernet packets using ethereal
92422: 05/11/29: Re: Slow FIFO using external SRAM
98381: 06/03/09: Re: delay in altera cyclone about led
98389: 06/03/09: Re: delay in altera cyclone about led
100297: 06/04/06: Xst warning, dangling RAMB16B output
100927: 06/04/21: Re: Video circle generator
128900: 08/02/09: Re: My first verilog/cpld project
Arlet Ottens:
127584: 08/01/03: Re: WebPack on GNU/Linux
127586: 08/01/03: Re: WebPack on GNU/Linux
127590: 08/01/03: Re: WebPack on GNU/Linux
127624: 08/01/04: Re: WebPack on GNU/Linux
127627: 08/01/04: Re: WebPack on GNU/Linux
127720: 08/01/06: Re: Spartan 3E Sarter Kit Ethernet
127732: 08/01/06: Re: Spartan 3E Sarter Kit Ethernet
127745: 08/01/07: Re: MicroBlaze floating point precision issues
128061: 08/01/14: Re: sine and cosine wave generation
128366: 08/01/23: Re: Pwm Sine Generation
128377: 08/01/23: Re: Pwm Sine Generation
128678: 08/02/03: Re: Starting problems with ISE 9.2.04i (WebPack+ServicePack)...unable
129064: 08/02/13: Re: My first verilog/cpld project
129643: 08/03/01: Re: FPGA's be afraid, very afraid, of my wife!
131143: 08/04/12: Re: Need help on UNISIM.Vcomponents.all
131885: 08/05/06: Re: How program PROM from msc file
132027: 08/05/10: Re: getting samples from an RF board onto the system
132240: 08/05/19: Re: 2-bit Pseudo Random Number Generator
150326: 11/01/10: Re: FPGA to PHY/MAC chip
150330: 11/01/10: Re: FPGA to PHY/MAC chip
150972: 11/02/25: Re: Simulating mutiplication of 'X' with '0'
151657: 11/05/03: Re: help with a power pc processor based software
151663: 11/05/03: Re: help with a power pc processor based software
151937: 11/06/10: Re: Variable Optimized Away
152881: 11/10/29: Re: FPGA development
153549: 12/03/27: Re: FPGA communication with a PC (Windows)
153553: 12/03/27: Re: FPGA communication with a PC (Windows)
153556: 12/03/27: Re: FPGA communication with a PC (Windows)
153732: 12/05/02: Re: Smallest GPL UART
154296: 12/09/24: Re: Xilinx CPLD XC95144 for Driving Sigma Delta DAC
155023: 13/03/30: Re: MISC - Stack Based vs. Register Based
155026: 13/03/31: Re: MISC - Stack Based vs. Register Based
155027: 13/03/31: Re: MISC - Stack Based vs. Register Based
155034: 13/04/02: Re: MISC - Stack Based vs. Register Based
155050: 13/04/04: Re: MISC - Stack Based vs. Register Based
155052: 13/04/04: Re: MISC - Stack Based vs. Register Based
155055: 13/04/04: Re: MISC - Stack Based vs. Register Based
155074: 13/04/05: Re: MISC - Stack Based vs. Register Based
155077: 13/04/05: Re: MISC - Stack Based vs. Register Based
arlington:
37576: 01/12/16: FPGA-Conversion. IP Cores
37630: 01/12/18: Altera vs Xilinx
37939: 01/12/26: Re: Look for FPGA Starterkit
ARMAITY BHARUCHA:
10228: 98/05/05: Re: Cartoons For Engineers
<armandolou@googlemail.com>:
124705: 07/10/01: Count Leading Zero (CLZ) possible by MicroBlaze??
124728: 07/10/02: Re: Count Leading Zero (CLZ) possible by MicroBlaze??
Armin Mueller:
13934: 99/01/03: Gamma correction in YUV space
14196: 99/01/19: Re: Free max+plus ll simulator on win95
16310: 99/05/14: Re: Bitstream Compression
17793: 99/09/04: Flex8000 trouble
17978: 99/09/20: Re: Problems with Lattice download
18225: 99/10/08: Re: Can't detect Flex 10K Altera device through JTAG port
18255: 99/10/10: Re: Can't detect Flex 10K Altera device through JTAG port
18783: 99/11/15: Strongest/Fastest Logic Reduction?
19022: 99/11/24: Re: implementing TCP/IP on PLD
19315: 99/12/13: Re: Lattice ispLSI Security
19609: 00/01/04: Re: Design security
20839: 00/02/23: Re: ALTERA BitBlaster
23537: 00/06/29: Free PCI core
35222: 01/09/26: Re: How does Altera FLEX 10k communicate with PC?
Armin Steinhoff:
7121: 97/08/02: Incremental changes of FPGA's possibel ?
7140: 97/08/05: Re: Incremental changes of FPGA's possibel ?
Arnaldo Oliveira:
15666: 99/04/07: EEPROM for XC4010XL
60420: 03/09/12: Transistor count
60421: 03/09/12: Foundation 3.1 to ISE 5.2
Arnaud:
70742: 04/06/25: Using a BlockRam in an async FIFO for bus width conversion ?
70750: 04/06/26: Re: Using a BlockRam in an async FIFO for bus width conversion ?
70768: 04/06/27: Re: Post-Map Simulation
97611: 06/02/24: Problem after P&R using Xilinx Viterbi Decoder IP
104551: 06/06/29: Re: Synplify prepending Z's to top level signal names in Verilog
105690: 06/07/28: Re: Xilinx Corgen & Synplicity... Anyone? Help?
113514: 06/12/15: Re: How to get ISE to create a _bd.bmm file for BRAM initialization
115438: 07/02/11: Re: ModelSim - Do Files
Arnaud Dion:
34057: 01/08/13: Re: Map report question
34924: 01/09/14: Re: Block RAM initialization
35028: 01/09/18: Re: Specifing global clocks on a Spartan II (Newbee Quest)
48329: 02/10/16: Re: Notation for Xilinx *.UCF files
62747: 03/11/06: Re: How to protect fpga based design against cloning?
Arnd Sluiter:
25746: 00/09/19: JTAG CPLD FPGA
28479: 01/01/15: Re: Synplify Pro6.13
Arne:
149419: 10/10/23: xilinx spartan3e clock domain crossing or synchronizing two clocks
Arne Burghardt:
47702: 02/10/02: Moving average filter
47706: 02/10/02: Re: Moving average filter
47887: 02/10/07: Re: Moving average filter
Arne Demmers:
93503: 05/12/23: SystemACE problem
93515: 05/12/23: Re: SystemACE problem
93516: 05/12/23: Re: Image processing libraries and VHDL
Arne Pagel:
153347: 12/02/04: Xilinx Artix-7 availability
153683: 12/04/21: VHDL syntheses timestamp
153686: 12/04/22: Re: VHDL syntheses timestamp
157565: 14/12/16: Re: Monitor connections
Arnie Buck:
7578: 97/09/23: Global Reset w/ VHDL & Xilinx
10331: 98/05/12: Re: Chicken & egg problem in PCI/CardBus designs using FPGA
Arnie Frisch:
4840: 96/12/19: Re: ASICs Vs. FPGA in Safety Critical Apps.
4880: 96/12/23: Re: ASICs Vs. FPGA in Safety Critical Apps.
Arnim:
111709: 06/11/08: Re: Graphics-2-FPGA
124757: 07/10/03: Re: Tcl - Xilinx - ISE - WindowsXP
125694: 07/11/01: Re: xilinx bmm file problem
133686: 08/07/09: Re: JTAG IR length detection
137094: 08/12/23: Re: Bit width in CPU cores
137242: 09/01/05: Re: MAX7000 power and slew rate control
138158: 09/02/08: Re: Recommended Xilinx USB JTAG cable?
139735: 09/04/11: Re: S3A starterkit weird behaviou (mini quiz)
139737: 09/04/11: Re: S3A starterkit weird behaviou (mini quiz)
144258: 09/11/23: Re: Initializing color bars on CH7301
144289: 09/11/24: Re: Initializing color bars on CH7301
Arnim Littek:
18: 94/07/28: PPR vs NeoCAD (vs. APR)
3310: 96/05/13: Re: Looking for free FPGA softw./Xilinx
3469: 96/06/05: Re: RS422 Connections and Pin-outs
3521: 96/06/14: Re: UART for Actel FPGA
4074: 96/09/08: Re: INDUSTRY GADFLY: EDA Goes OJ
7953: 97/11/02: Re: XILINX pin compatible replacements
7968: 97/11/04: Re: Anyone using Protel Schematic 3 for XILINX?
8644: 98/01/16: Re: Xilinx Stock
9540: 98/03/22: Re: Linux and Xchecker
9545: 98/03/22: Re: Xilinx XACT 6.01 crack
9753: 98/04/03: Re: XactStep6 - The cure for a dongle
10473: 98/05/20: Re: Minimal ALU instruction set.
Arnold Beland:
13056: 98/11/13: Alternative to EPM5128 OTP
13061: 98/11/13: Re: Alternative to EPM5128 OTP
13113: 98/11/16: Is there an alternative to Altera EPM5128 OTP?
13141: 98/11/17: Re: Is there an alternative to Altera EPM5128 OTP?
13156: 98/11/17: Re: Is there an alternative to Altera EPM5128 OTP?
13170: 98/11/18: Re: Is there an alternative to Altera EPM5128 OTP?
13624: 98/12/14: Parallel Port Pass Through Specs?
13643: 98/12/15: Re: Parallel Port Pass Through Specs?
18723: 99/11/09: CAN tools reccomendations?
22652: 00/05/16: SMT 7 segment display ??
Arnold Columbo:
6849: 97/07/02: Re: inexpensive Xilinx 3042A development
<arobe100@jaguar.com>:
110216: 06/10/12: ANN: FPGA image processing camera
Aroen (nospam):
50225: 02/12/05: Looking for older version Xilinx Foundation
50247: 02/12/06: Looking for older version Xilinx Foundation
52314: 03/02/06: Parsic
Aroul:
83675: 05/05/04: How to add DCM as customized IP using FSL channel
arpit.desai:
39530: 02/02/12: Re: Altera's new family Stratix
40673: 02/03/12: Re: DPRAM implementation in altera
41032: 02/03/19: Re: simple Free FPGA tool
47832: 02/10/04: Re: Parallel asyncronous configuration of an Altera FPGA
Arrigo Benedetti:
882: 95/03/20: FPGA accelerated engines for volume rendering
909: 95/03/28: Opinions on IBM PowerPC for Electronics CAD lab
1034: 95/04/19: Re: $40 Million For NeoCAD & A New FPGA Synthesis Tool
1105: 95/04/28: Looking for XNF format definition
1369: 95/06/08: Reconfigurable hardware architectures for image processing
2182: 95/10/27: Low cost board prototyping for FPGA
2402: 95/11/29: Opinions on Cadence FPGA designer
2649: 96/01/19: Virtual Computer Corp. still in business?
3751: 96/07/25: Signed digit arithmetic on FPGA's
6210: 97/04/27: Global GSR net in a Xilinx design (Synopsys)
6241: 97/05/01: Implementing three state output MUXes with Synopsys
6310: 97/05/14: Instatiating large RAM arrays in VHDL
6407: 97/05/21: Glitches in timing simulation of Xilinx FPGAs with Synopsys
6880: 97/07/05: Re: How to describe XC4000EX/XL FIFOs/RAMs in VHDL?
6964: 97/07/16: Problem simulating 3-state output with M1 and Synopsys
8041: 97/11/10: switching between clock domains in Xilinx FPGA's
8076: 97/11/14: FPGA vs. ASIC for PCI bus interface
9581: 98/03/24: Want to share room at FCCM'98?
10119: 98/04/28: Re: Make a delay in Xilinx FPGAs (Help)?
10450: 98/05/19: FPGA market distribution
12379: 98/10/10: Re: clock divider chips
12951: 98/11/06: Re: FPGA Decouple Capacitor values
12859: 98/11/02: Re: Q: 3.3 V regulators suitable for XILINX - ?
13134: 98/11/16: Xilinx Virtex and ZBT SRAM
14122: 99/01/14: FPGAs in die form
14675: 99/02/10: Supercomputer uses 280 Xilinx FPGAs
15707: 99/04/09: Re: ZBT to Virtex Interface at +100M
15800: 99/04/14: Problems with high pin count FPGA systems
16809: 99/06/09: Looking for Xilinx Virtex devices
18545: 99/10/29: need reference to first paper on FPGA
19122: 99/11/30: Re: FPGA vs DSP vs PENTIUM MMX
19970: 00/01/20: odd behavior of Virtex RAM Block model
20422: 00/02/09: Re: odd behavior of Virtex RAM Block model
20868: 00/02/24: Automatic retiming in FPGA Express
20872: 00/02/24: Re: Automatic retiming in FPGA Express
21949: 00/04/08: Re: Retiming for Virtex FPGA with synopsys
23177: 00/06/16: Block level incremental synthesis (?)
24105: 00/07/26: Re: Retiming for Virtex with FC2
24292: 00/08/02: Re: 32-input AND and 100-input OR - can I do it fast?
24746: 00/08/17: Re: Accessing internal signals and ports for writing to a file using testbench
24995: 00/08/23: Re: Mealy vs Moore FSM model
27260: 00/11/16: Xilinx coregen problems
27279: 00/11/16: Re: Xilinx coregen problems
27434: 00/11/21: Re: Xilinx coregen problems
27567: 00/11/28: question on initial states of FFs and GSR in Virtex
27670: 00/12/01: Re: Synplify Benchmarks
27719: 00/12/04: getting 100% timing path coverage
28143: 00/12/22: Re: driving color VGA from FPGA ??
28370: 01/01/10: Re: grey code counters
29407: 01/02/19: meeting high hold time input requirement with Virtex
34885: 01/09/12: Re: Fixed or Floating point for MP3 algorithim?
44847: 02/07/02: Chameleon Systems
45120: 02/07/12: Webpack under Linux ?
60037: 03/09/04: Re: FPGA/DSP Expert - business partner for innovative FFT
60084: 03/09/04: Re: FPGA/DSP Expert - business partner for innovative FFT
60809: 03/09/22: Re: Italy is out of FPGA world?
ARRON:
83884: 05/05/09: Uart16550 can't receive data over 16byte a time
84022: 05/05/11: Re: Uart16550 can't receive data over 16byte a time
84141: 05/05/13: Re: Uart16550 can't receive data over 16byte a time
84143: 05/05/13: how can i save my received data into the SDRAM?
84150: 05/05/13: Re: how can i save my received data into the SDRAM?
84212: 05/05/14: Re: Uart16550 can't receive data over 16byte a time
84214: 05/05/14: Re: how can i save my received data into the SDRAM?
84390: 05/05/18: For accessing my SDRAM,what should i do?
84424: 05/05/18: Re: For accessing my SDRAM,what should i do?
84538: 05/05/20: Re: For accessing my SDRAM,what should i do?
84585: 05/05/21: Re: For accessing my SDRAM,what should i do?
84678: 05/05/24: Re: For accessing my SDRAM,what should i do?
84930: 05/06/01: why can't i use opb_spi core in EDK6.3?
84964: 05/06/01: Re: why can't i use opb_spi core in EDK6.3?
84974: 05/06/02: Re: why can't i use opb_spi core in EDK6.3?
85025: 05/06/02: how can i extend my code space to extern memory?
85158: 05/06/06: Re: how can i extend my code space to extern memory?
85343: 05/06/08: why my SDRAM test failed in EDK7.1i?
103527: 06/06/05: The simulation of Xilinx DDC(Digital Down Convert) IP Core can't gain the result
125366: 07/10/23: Re: ERROR:NgdBuild:604 with user ipcore
ARSDMTHE:
151950: 11/06/14: Re: Area Optimization
151953: 11/06/14: Re: Area Optimization
<arsh@x-stream.se>:
19883: 00/01/15: Partly reprogrammable FPGAs
arsonperbuilding@gmail.com:
134686: 08/08/26: Re: AES decryption (ASIC)
135155: 08/09/18: Re: Random Mask Generation on FPGAs
Art:
85250: 05/06/07: Re: How do I find out the connection of the LCD I took out from a digital camera?
Art Marriott:
3627: 96/07/05: Re: INDUSTRY GADFLY "Why I Hate Wally"
5613: 97/02/28: Re: Customizing Viewdraw in Workview Office 7.3 ... Is it possible?
Art Stamness:
93319: 05/12/19: Re: More beginner's verilog questions
99740: 06/03/28: Re: OpenSPARC released
99747: 06/03/28: Re: OpenSPARC released
99752: 06/03/28: Re: OpenSPARC released
99816: 06/03/29: Re: OpenSPARC released
99828: 06/03/29: Re: OpenSPARC released
<artaaron@my-deja.com>:
25761: 00/09/19: Re: Freelance Designer Needed: Protel & FPGA
Artenz:
76722: 04/12/09: Trying to get 4 LUTs, MUXF5, MUXF6 in Spartan-3
76770: 04/12/10: Re: Trying to get 4 LUTs, MUXF5, MUXF6 in Spartan-3
76775: 04/12/10: Re: Trying to get 4 LUTs, MUXF5, MUXF6 in Spartan-3
76778: 04/12/11: Re: Trying to get 4 LUTs, MUXF5, MUXF6 in Spartan-3
76784: 04/12/11: Re: Trying to get 4 LUTs, MUXF5, MUXF6 in Spartan-3
76852: 04/12/14: Re: Trying to get 4 LUTs, MUXF5, MUXF6 in Spartan-3
Arthur:
28310: 01/01/05: Re: WebPack-ISE .ucf problem?
30008: 01/03/20: Re: Do I need to tie unused CPLD pins to GND?
30343: 01/04/03: Re: No inputs on XC9536XL
34863: 01/09/11: Re: Xilinx Foundation Base(DS-ISE-XB2). Exactly what do you get?
35368: 01/10/01: Re: Hitop Warning hi434
37349: 01/12/07: Re: For Sale: Huge Xilinx FPGA lots
37350: 01/12/07: Re: Can WebPack and Student Edition Co-exist?
39115: 02/01/31: Re: WebPack 4.1 ISE Errors with Insight Demo files
41159: 02/03/21: Re: Can't program XC4010 with JTAG without BSCAN???
41224: 02/03/22: Re: Can't program XC4010 with JTAG without BSCAN???
43433: 02/05/21: Re: Using Impact with XCR5064 coolrunner?
43434: 02/05/21: Re: Xilinx WP test vectors in Jedec file
48696: 02/10/22: Re: clock divider
56627: 03/06/10: Re: XC95288 programming problem
56951: 03/06/19: Re: applying SCHMITT_TRIGGER to CoolRunner-II CPLD's
57090: 03/06/23: Re: applying SCHMITT_TRIGGER to CoolRunner-II CPLD's
57091: 03/06/23: Re: Programming xc95144 using parallel IV cable
58928: 03/08/04: Re: Design fits XC9536 but not XC9536XL
63400: 03/11/20: Re: CPLD : Generating reset signal
63565: 03/11/25: Re: XC9500 design does not fit into Coolrunner
72899: 04/09/07: Re: Xilinx Xpower Issues - Help from xilinx team please
82531: 05/04/13: Re: Xilinx ISE 7.1i / stuck down XCR3064 outputs
Arthur Agababyan:
12472: 98/10/13: books
29189: 01/02/09: verilog book
Arthur Dardia:
17913: 99/09/16: Xilinx XC4005E
Arthur F. Ross:
23883: 00/07/14: i2c VHDL code
Arthur Herbert:
54867: 03/04/21: Complex FIR in FPGA
54897: 03/04/21: Re: Complex FIR in FPGA
Arthur J. O'Dwyer:
109421: 06/09/26: Re: An algorithm with Minimum vertex cover without considering its performance
Arthur Sharp:
35638: 01/10/12: Small FPGA proto boards
36060: 01/10/27: Distributed ROM init
36774: 01/11/20: Re: Modelsim
60406: 03/09/12: DCM not locking in XC2V4000
60481: 03/09/15: Re: DCM not locking in XC2V4000
61568: 03/10/07: Installing Xilinx 6.1 under Linux
61616: 03/10/08: Re: Installing Xilinx 6.1 under Linux
61705: 03/10/09: Re: Installing Xilinx 6.1 under Linux
68622: 04/04/10: Problems installing ISE 6.2 under Linux
68623: 04/04/10: Re: Problems installing ISE 6.2 under Linux
68655: 04/04/13: Re: Problems installing ISE 6.2 under Linux
73467: 04/09/22: ISE 6.3 Suse 9.1 installation problem
73468: 04/09/22: Re: ISE 6.3 Suse 9.1 installation problem
73470: 04/09/22: Re: ISE 6.3 Suse 9.1 installation problem
Arthur Smilkstinsh:
5012: 97/01/12: "NEED CASH $$$$$ READ HERE $$$$$"
Arthur T. Murray:
4763: 96/12/12: Re: Call for Papers: CAMP '97
18263: 99/10/11: Re: GNU License for Hardware
Arthur Yang:
26713: 00/10/25: Re: Jtag programing 18V02 prom
31387: 01/05/21: Re: Xilinx Service Pack 8 Now Available
ArtO (spam-not):
53427: 03/03/13: AMD Temp Specs
Artur:
34438: 01/08/24: Set associative mapping in VHDL
Artur Leung:
3953: 96/08/24: Want to learn FPGA! Please advise......
16778: 99/06/08: FA: VHDL for Programmable Logic
17589: 99/08/11: Annapolis Micro WildForce analog interface
18760: 99/11/12: ROM Magafunction for Altera MAX7000 Series
24601: 00/08/14: Re: Non-disclosures in job interviews
24637: 00/08/15: Digital PLL design in FPGA
24696: 00/08/16: Implementing an All Digital PLL in FPGA
24791: 00/08/18: Re: Implementing an All Digital PLL in FPGA
Arturo Rios:
70260: 04/06/10: Cores into fpga
Arul:
65759: 04/02/05: Symmetric encryption mechanism in smart cards
81725: 05/03/30: Read Data from BlockRAM
81790: 05/03/31: Re: Read Data from BlockRAM
Arun:
68730: 04/04/15: ICAP with microblaze
68951: 04/04/22: Re: OPB bus burst transfer support?
72477: 04/08/20: Re: Can PPC in V2P reconfig the FPGA slices?
74481: 04/10/12: Initializing Block Ram of a partial Bitstream
100464: 06/04/10: get the data from tranceiver
arvan:
84660: 05/05/24: Re: QUARTUS on Linux.
Arve Ronning:
15181: 99/03/11: Re: Virtex Programming Weirdness
17513: 99/08/04: Re: Xilinx/Synopsys License Problem
arvi:
90981: 05/10/26: Condition Coverage Using ModelSim
Arvin Patel:
822: 95/03/07: Re: Questions of implementing asynchronous circuits using FPGAs.
39224: 02/02/04: Xilinx synthesis tools
39289: 02/02/05: Re: Xilinx synthesis tools
39381: 02/02/07: Re: Multiple clock domein synchronization.
arvind:
46454: 02/08/30: problem configration spartan2 with prom.
51348: 03/01/11: Help for Generating Video Clock synchronous to Hsync of the Video..........
67788: 04/03/19: Why It Is not Recommended to Infer latches in VLSI Design...
70062: 04/06/01: Configration............problem..............
Arvind Kumar:
39980: 02/02/22: Re: Orca FPSC synthesizing issue
39981: 02/02/22: Re: Faster designs
40040: 02/02/25: Re: Synplify warning that I don't understand
40043: 02/02/25: Re: unisims simprims
40044: 02/02/25: Re: Question about multiple Virtex DLLs locking management after configuration
59380: 03/08/18: Re: Data Structure Viewer
<as@asic.cc>:
22252: 00/05/03: Digital Design/systems/CAD Engineer (MSEE) looking for position in California, USA
Asa Kalavade:
15851: 99/04/16: partial reconfiguration
17744: 99/08/29: size of configuration data?
<asa1002@my-dejanews.com>:
11693: 98/09/01: Re: Wait statements and while loops
<asa@lan.novsu.ac.ru>:
5777: 97/03/14: PCI user_defined project on ALTERA FLEX chips. E-mail <rastr@lan.novsu.ac.ru>
asap:
16216: 99/05/10: Synopsys DC & Modelsim
Asawaree Kalavade:
14568: 99/02/04: Synplify/Xilinx4085XLA question
<asax@my-dejanews.com>:
14003: 99/01/06: How to use Special Pins as IO on Xilinx FPGA???
ascaples:
97959: 06/03/02: coregen on webpack 8.1
<asd>:
6773: 97/06/26: Tight Teen Snatch * teen1.jpg
<asdlfjsadl@0w9fasfusd.com>:
7631: 97/09/29: -Hot Young Girls -hhhot.jpg
<asdofjasd>:
6782: 97/06/27: Young cheerleader fucking and sucking cock
<ASE1000@1stfamily.com>:
6809: 97/06/30: World Wide Free Internet Access .
Asfandyar Khan:
31900: 01/06/07: Re: Download problems
31901: 01/06/07: Re: Tutorial
31935: 01/06/08: Re: Download problems
31936: 01/06/08: Re: Download problems
asfsdfrewrew:
31277: 01/05/16: Re: Avnet Virtex-E Development Kit
31278: 01/05/16: Re: FREE IP CORES
31327: 01/05/18: Re: Digital PLL (DPLL) design help
31328: 01/05/18: Re: Can anyone comment on the difference between modelsim PE and XE
Asger Sporring:
6232: 97/04/30: FPGA chip on Khepera robot
Ash:
44485: 02/06/21: Re: Does anyone have experience with HandelC and Celoxica's RC1000 with VirtexE
47475: 02/09/26: Re: Handel-C: Unhandled exception: uncaught exception in compiler
65157: 04/01/21: Reference Designators naming standard...
<ash.ok7@gmail.com>:
84169: 05/05/13: Re: how can i save my received data into the SDRAM?
Ashant:
69527: 04/05/12: synthesising VHDL for Xilinx FPGAs using ISE 6.1i
69622: 04/05/16: Re: synthesising VHDL for Xilinx FPGAs using ISE 6.1i
<ashasravanthi@gmail.com>:
117655: 07/04/05: virtex 4vfx12 evaluation kit schematics
117997: 07/04/16: vpw/pwm controller
118121: 07/04/17: Re: vpw/pwm controller
118562: 07/04/30: SAE j1850 pwm protocol controller ip core
Asher C. Martin:
17062: 99/06/28: ALTERA GDF to VHDL QUESTION
17240: 99/07/14: MULTIPLE PIN ASSIGNMENTS QUESTION (ALTERA MAX+PLUS II)
17275: 99/07/15: SOLUTION: MULTIPLE PIN ASSIGNMENTS QUESTION (ALTERA MAX+PLUS II)
17384: 99/07/23: CAN WE HAVE SIGNALS WITH MULTIPLE SOURCES IN VHDL?
17560: 99/08/10: VHDL OPTIMIZATION FOR FPGA's: (Anyone have suggestions?)
17571: 99/08/11: Re: VHDL OPTIMIZATION FOR FPGA's: (Anyone have suggestions?)
20513: 00/02/12: Where can I get PLCC sockets for Xilinx 4005e???
20514: 00/02/12: How do you program the Xilinx 4005e?
20518: 00/02/13: Re: How do you program the Xilinx 4005e?
35870: 01/10/21: Re: Linux tools
37330: 01/12/06: Re: quartus post simulation setup problem
37374: 01/12/08: Re: ALTERA's Mercury CDR
37375: 01/12/08: Re: Which vendor to choose
37376: 01/12/08: Re: ALTERA's Mercury CDR
37433: 01/12/10: Re: Modelsim
37434: 01/12/10: Re: Modelsim
54655: 03/04/15: Re: Verilog to VHDL or vice-versa converters ??
Asher Martin-CRAY:
23341: 00/06/22: HOW DO YOU MANUALLY CONFIGURE AND READ CLB's ON A RUNNING FPGA???
23344: 00/06/22: Re: HOW DO YOU MANUALLY CONFIGURE AND READ CLB's ON A RUNNING FPGA???
23459: 00/06/26: BOUNDARY-SCAN OF INTERNAL LOGIC INSIDE A VIRTEX FPGA?
23460: 00/06/26: Re: Fpga in tristate?
23733: 00/07/06: Re: HOW DO YOU MANUALLY CONFIGURE AND READ CLB's ON A RUNNING FPGA???
23735: 00/07/06: Where is the documentation on .ll files for Xilinx parts?
24351: 00/08/04: Q: JTAG BOUNDARY SCAN FOR FPGA's?
<ashes.man@gmail.com>:
120075: 07/05/31: Re: weird PACE Error, not one google result
120090: 07/05/31: Re: weird PACE Error, not one google result
Ashish:
72163: 04/08/10: Help wanted for ethernet on xilinx fpga Virtex2 multimedia demonstration board
102053: 06/05/09: Interrupt signal sampling (Level or edge?)
102056: 06/05/09: Re: Interrupt signal sampling (Level or edge?)
102143: 06/05/10: Re: Interrupt signal sampling (Level or edge?)
102222: 06/05/12: clock multiplier in spartan 2
102229: 06/05/12: Re: clock multiplier in spartan 2
103681: 06/06/07: Block Ram vs Distributed Ram
103685: 06/06/07: Re: Block Ram vs Distributed Ram
109466: 06/09/27: PLB-IPIF and user IP interface problem
109689: 06/10/03: Re: PLB-IPIF and user IP interface problem
109747: 06/10/04: Re: PLB-IPIF and user IP interface problem
113095: 06/12/06: Xilinx PLB IPIF
113097: 06/12/06: Clock phase shift
113105: 06/12/06: Re: Clock phase shift
113148: 06/12/06: Re: Clock phase shift
115191: 07/02/02: Re: UNKNOWN Processor Version (0) in XMD
Ashish Kapoor:
52815: 03/02/23: Re: Carry Save Adder
70545: 04/06/19: Re: CPLD mistery. Help.
70662: 04/06/22: Re: Newbie Q
<ashish.dobhal@gmail.com>:
113449: 06/12/13: How does FPGA tools infer FIFO
ashishshuklabs:
122157: 07/07/20: Re: XilinxSystemGenerator and Simulink
Ashley:
38054: 02/01/03: Automatically pipeline combinatorial EDIF
47345: 02/09/24: Re: Handel-C: a bit of a funny 'for loop'
Ashley Stevens:
1611: 95/07/28: Re: VHDL/FPGAs/PLDs help
Ashok:
89484: 05/09/16: ISE 7.1 on Linux, ngdbuild failed without error
89850: 05/09/28: Re: Sythesis software for Virtex-4
Ashok Chotai:
26939: 00/11/03: Re: Fpga vs. ASIC
26937: 00/11/03: Re: ACEX1K vs FLEX10K
28732: 01/01/22: Re: info about FPGA market?
28733: 01/01/22: Re: what placement and route tool?
58003: 03/07/11: Re: Spartan XL Prom Selection
130537: 08/03/26: Places to visit in Amsterdam and Brussells
Ashok Mahadevan:
9013: 98/02/13: Re: Philips P5Z22V10 wanted
11669: 98/08/30: Re: PROM alternative
22477: 00/05/10: Re: Looking for Altera programmer in France
22664: 00/05/17: Q: Creating custom flip-flops in Altera MAX+Plus II
28280: 01/01/05: HELP: Problem with interfacing an Altera MAX7000 device to the ISA bus
28300: 01/01/05: Re: HELP: Problem with interfacing an Altera MAX7000 device to the ISA bus
38126: 02/01/06: Re: Suitability of Atmel for project?
ashtonrsmiller:
152804: 11/10/24: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE
152813: 11/10/25: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE
Ashu:
99768: 06/03/28: Re: Keystroke saving w/ IEEE.Numeric_Std
<ashu_19_1980@yahoo.com>:
110513: 06/10/17: mapping memory to fpga
Ashutosh Singla:
818: 95/03/06: Partitioning and synthesis
<ashutoshkaushik@gmail.com>:
101427: 06/04/30: fpga programming
ashwin:
90946: 05/10/25: ETHERNET MAC
90994: 05/10/26: crc on only data or including the address
91072: 05/10/28: ethernet phy- DP83847
91209: 05/11/01: can ethereal detect an ethernet packet for which crc is wrong
91218: 05/11/01: lenght/type not included
91276: 05/11/02: crc code using vhdl found , few questions on it!!!
91587: 05/11/09: How do i detect ethernet frames of layer 2 using ethereal?
91833: 05/11/14: Having trouble Detecting ethernet packets using ethereal
91868: 05/11/15: Re: Having trouble Detecting ethernet packets using ethereal
118992: 07/05/08: ISE : Linux - coregen, compxlib errors
Ashwini G:
49379: 02/11/11: New to FPGA!
ashwini012:
157800: 15/03/30: Bad condition in wait statement, or only one clock per process.
<ashwinihs@gmail.com>:
130562: 08/03/27: Xilinx ISE 9.2i out of memory
130569: 08/03/27: Sub: Strange problem with Xilinx ISE 8.1 and Chipscope Pro 8.1
130571: 08/03/27: [CORRECTED] Strange problem with Xilinx ISE 8.1 and Chipscope Pro 8.1
ASIC:
150177: 10/12/28: Verilog inout, I2C
ASIC Engineer:
31646: 01/06/01: Help requested in choosing a career
asic1234@gmail.com:
123536: 07/08/29: SDF File basics
123643: 07/08/31: Re: SDF File basics
123646: 07/08/31: what does asynchronous loop mean?
asicbaba:
115619: 07/02/15: Re: Minimum Speed of DDR / DDR2 SDRAM w/o DLL
<asieving@my-dejanews.com>:
11872: 98/09/15: measuring junction temperature
Asif Chowdhury:
15660: 99/04/06: viterbi/trellis decoder
15670: 99/04/07: Re: viterbi/trellis decoder
Asif Siddiq:
46192: 02/08/21: cdma code acquisition problem
asimatta@hotmail.com:
123644: 07/08/31: signal termination in spartan 3e starter kit
asimlink:
148023: 10/06/14: Trouble with Altium Openbus document based UART example using
148030: 10/06/15: Trouble with Altium Openbus document based UART example using TSK3000A
148159: 10/06/23: Please suggest NON Volatile FPGA Devices
ask:
29100: 01/02/06: where FlexGen is?
<asklfdlsjd@>:
6610: 97/06/05: Send thousands of Posting to the Newsgroups at once with Mailloop
aslic:
7490: 97/09/17: Viewsim.var help
7489: 97/09/17: Lucent Orca Fpga
7526: 97/09/19: Lucent ORCA Fpga to ASIC
7527: 97/09/19: Re: Lucent Orca Fpga
ASM:
920: 95/03/30: Neocad merges with Xilinx
<asoc35@dsl.pipex.com>:
84002: 05/05/11: Any Virtex 4 development/prototyping boards out there???
<asp654@gmail.com>:
154076: 12/07/30: 3 to 1 mux with 4 bit inputs
154079: 12/07/30: Re: 3 to 1 mux with 4 bit inputs
Assaf:
141873: 09/07/14: Re: How to implementa an FSM in block ram
Assaf Sarfati:
17811: 99/09/07: Re: QuickLogic FPGAs
18910: 99/11/21: Re: [Q] End-goal: porting ISA design to PCI. Which PLD to learn?
21821: 00/04/02: Re: What's so good about antifuse???
27899: 00/12/14: Re: Dual-ported RAM instantiation in Virtex-E ?
35060: 01/09/19: Re: Synplify BUFG instantiation bug
35345: 01/09/29: Re: Programming flash connected to CPLD via JTAG
35956: 01/10/24: CPLD with built-in oscillator?
36256: 01/11/03: Re: Synplicity, Xilinx, & unwanted BUFGs
36326: 01/11/06: Virtex2 gate-level simulation: SDF and timing errors
36382: 01/11/07: Re: Synplicity, Xilinx, & unwanted BUFGs
36383: 01/11/07: Re: Virtex2 gate-level simulation: SDF and timing errors
36525: 01/11/11: Re: Virtex2 gate-level simulation: SDF and timing errors
36669: 01/11/14: Re: SDRAM Module vs. SDRAM
36792: 01/11/19: Re: Virtex2 gate-level simulation: SDF and timing errors
37271: 01/12/05: Re: Crossing a clock domain
38401: 02/01/13: Re: How can I relate Virtex2 pin names and Slice XY loc?
38657: 02/01/20: Re: bottom up synthesis with synplicity?
39211: 02/02/04: Destroying a CPLD by JTAG
40058: 02/02/25: Re: Comparison between two FPGAs- what is decisive factor?
40364: 02/03/05: Re: exceeding 2GB limits in xilinx
42914: 02/05/06: Re: Opinions on FPGA cores - best for a commercial project?
43532: 02/05/22: Re: xc2v-6000 FF1152 orcad symbol ???
45162: 02/07/14: Re: LogiCore and PLX
45832: 02/08/06: Re: Is it necessary to instantiate IPAD, OPAD, IBUF, OBUF...?
45866: 02/08/07: Re: Is it necessary to instantiate IPAD, OPAD, IBUF, OBUF...?
50124: 02/12/02: Re: CAM tutorial
51542: 03/01/15: Re: SChematic design approach compared to VHDL entry approach
51683: 03/01/18: Re: SChematic design approach compared to VHDL entry approach
51706: 03/01/19: Re: SChematic design approach compared to VHDL entry approach
51793: 03/01/21: Re: VHDL or Verilog?
51832: 03/01/22: Re: VHDL or Verilog?
51919: 03/01/25: Re: VHDL or Verilog?
52621: 03/02/16: Re: About automatically programming my FPGA
53797: 03/03/23: Re: synthesizability question
54080: 03/04/01: Re: parity checking trick for PCI core
54254: 03/04/05: Re: parity checking trick for PCI core
60035: 03/09/03: Re: OT: Block diagramming tools?
61696: 03/10/08: Re: Visualizing VHDL
62094: 03/10/18: Re: 3rd party pci dma engine
64446: 04/01/04: Re: is this a good idea
<assaf_sarfati@yahoo.com>:
89787: 05/09/26: Spartan3E - problem in creating LVDS DDR pads
89816: 05/09/27: Re: Spartan3E - problem in creating LVDS DDR pads
89838: 05/09/27: Re: Version Control Software
89965: 05/09/30: Re: Version Control Software
astonish:
51304: 03/01/10: typedef ram in Handel-C
51402: 03/01/13: Celoxica's White Paper on TripleDES
51905: 03/01/25: Rijndael Implementation using DK1
<astra32@mail.comor35>:
<astra35@pathfinder.gr>:
<astra3@europe.com>:
AstroLad:
141746: 09/07/06: Suzaku SZx30 or similar
141944: 09/07/18: Re: Suzaku SZx30 or similar
142015: 09/07/21: Re: Suzaku SZx30 or similar
AT:
39848: 02/02/21: SRL16E Initialization
40570: 02/03/11: JTAG & CPLD
ata:
127524: 08/01/01: no SystemACE on Xilinx Spartan 3A 1800 DSP in EDK 9.2.02
127574: 08/01/03: Re: no SystemACE on Xilinx Spartan 3A 1800 DSP in EDK 9.2.02
<atarynka@gazeta.pl>:
91086: 05/10/28: Reed Solomon generation / verification
atass:
136420: 08/11/15: Re: Synplicity/Synplify and Systemverilog support?
136457: 08/11/17: Re: Synplicity/Synplify and Systemverilog support?
ATG Technology:
3986: 96/08/29: Re: INDUSTRY GADFLY: EDA Goes OJ
<athar.kaludi@gmail.com>:
158509: 15/12/05: Re: Lattice diamond / MachXO2
Athena:
83846: 05/05/07: Re: how can i add my math library libm.a in my project
83847: 05/05/07: Re: how can i add my math library libm.a in my project
83852: 05/05/08: float computing: how to add libm.a
84963: 05/06/01: how to use GCC compiler
89584: 05/09/20: Re: how to set OPB EMC for flash use?
89619: 05/09/20: Re: how to set OPB EMC for flash use?
90743: 05/10/20: to write the driver for my own ip core
90794: 05/10/21: Re: to write the driver for my own ip core
91520: 05/11/08: how to use registers and fifo in ipif
91564: 05/11/08: Re: how to use registers and fifo in ipif
92331: 05/11/27: boot from flah
92370: 05/11/28: Re: boot from flah
92444: 05/11/29: Re: boot from flah
94273: 06/01/09: how to speed up the program running in ddr sdram
94274: 06/01/09: Re: how to speed up the program running in ddr sdram
athena:
89517: 05/09/16: how to set OPB EMC for flash use?
Atif:
55944: 03/05/23: FPGA Board
56327: 03/06/03: Online courses for FPGA
58419: 03/07/23: inputs and outputs for clb in ISE5
58466: 03/07/23: Re: inputs and outputs for clb in ISE5
59209: 03/08/12: Non volatile implementation of Xc2s100
59255: 03/08/13: Xilinx Platform flash prom price
59768: 03/08/27: Implementing FIFO in Spartan-II
59769: 03/08/27: Is Platform Flash PROM an electrically erasable??
59977: 03/09/02: Generating Asynchronous FIFO in Block Memory of Sparatn-II in CoreGen
62453: 03/10/29: DDFS technique problem in generating a few clocks
62699: 03/11/05: Problem in Implementation Costraints
62984: 03/11/11: About the purchase of XCF01s
atif:
33661: 01/08/01: a few xilinx fpga and hdl questions
Atif Hashmi:
65766: 04/02/05: project navigator fails to detect inputs to the module
Atif Zafar:
15908: 99/04/20: Virtex based PCI cards
16198: 99/05/09: Looking for Altera APEX board
55253: 03/05/01: MJL Stratix Dev Kit
55366: 03/05/05: Re: MJL Stratix Dev Kit
55494: 03/05/09: Re: MJL Stratix Dev Kit
<atifnawaz08@gmail.com>:
161341: 19/04/01: BITSLIP STATE MACHINE
Atilla Filiz:
132954: 08/06/11: Re: FPGA to solve the two most annoying problems on usenet -
Atkins, Kate:
30753: 01/04/27: Re: back annotation
35313: 01/09/28: Active-HDL back annotated simulation and PC memory usage
atlantic_pure:
154929: 13/02/19: Help with .mem and .bmm file generation
154931: 13/02/19: Re: Help with .mem and .bmm file generation
Atlas:
26742: 00/10/26: Excellent Opportunity ASIC Engineers CA International Relocation
atlgpag:
49437: 02/11/12: vhdl inout question
* Atmel FPGA Apps *:
3190: 96/04/22: Serial EEPROMs
3377: 96/05/23: Evolvable HW
3562: 96/06/24: Atmel AT17C65/128/256 Serial EEPROM Memories.
3729: 96/07/22: Atmel AT17Cxxx EEPROMs
** Atmel FPGA Apps. :-):
2901: 96/02/27: Atmel Serial Configuration E2PROMs
Atmel_PLDs_Rock:
102604: 06/05/17: Re: getting good deals on small qty?
102605: 06/05/17: Re: Altera Equiv.
102764: 06/05/19: Re: CPLD (CoolRunner) failures.
119569: 07/05/22: Re: Config PROM for Spartan II
ATOMROB:
4359: 96/10/19: Announcing Workview Office Student Edition
<atsadang@hotmail.com>:
14405: 99/01/29: No. of CLBs in Xilinx nearly 100% can't implement.
Attila Kinali:
116295: 07/03/06: Re: How to implement pipeline in this case?
116356: 07/03/07: Re: How to implement pipeline in this case?
Attila Szabo:
5084: 97/01/22: 16v8,20v8 programming
ATTRACT MORE WOMEN:
7612: 97/09/27: HOW TO ATTRACT GIRLS INSTANTLY....Secrets to instant sex appeal!!!
ATTRACT WOMEN NOW:
7903: 97/10/28: HOW TO ATTRACT GIRLS INSTANTLY....Secrets to instant sex appeal!!
atts:
71766: 04/07/29: Re: How to program a spartan-3
Atukem:
132573: 08/06/01: Re: HWICAP initialization
Atul:
8729: 98/01/22: MAX+II software from Altera.
8740: 98/01/23: Re: MAX+II software from Altera.
8741: 98/01/23: Re: MAX+II software from Altera.
<atul.iagent@gmail.com>:
159439: 16/11/09: Re: xc3sprog
<atulm1@gmail.com>:
136286: 08/11/09: Connect XST board with PC through USB
atus72:
75468: 04/11/06: Programming XCR3064(Xilinx) or ZR3064 (Philips)
atutu:
149669: 10/11/15: Maximum speed SPI on Spartan3a?
Augast15:
97596: 06/02/24: The 95108 cpld is getting heated when connected by CRO
97747: 06/02/27: Re: The 95108 cpld is getting heated when connected by CRO
august22nd:
142838: 09/09/03: Re: Where to find source code for Xilinx ML507 board demos?
auguste.chindji@googlemail.com:
129373: 08/02/22: Software Defined Radio on Xilinx Virtex 4
<auguste.chindji@googlemail.com>:
129336: 08/02/21: Software Defined Radio auf Xilinx Virtex 4
AugustoEinsfeldt:
78716: 05/02/06: ISE6.x/iMPACT, JTAG fails after any completed command
78767: 05/02/07: Re: ISE6.x/iMPACT, JTAG fails after any completed command
78790: 05/02/07: Re: ISE6.x/iMPACT, JTAG fails after any completed command
79286: 05/02/16: clock split approach for 270MHz design in Spartan2E
79323: 05/02/17: Re: clock split approach for 270MHz design in Spartan2E
81884: 05/04/03: how to use both FFs in a CLB's slice using LOC or RLOC
81886: 05/04/03: Re: how to use both FFs in a CLB's slice using LOC or RLOC
81889: 05/04/03: Re: how to use both FFs in a CLB's slice using LOC or RLOC
81903: 05/04/04: Re: how to use both FFs in a CLB's slice using LOC or RLOC
121340: 07/07/02: high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
121364: 07/07/03: Re: high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
121382: 07/07/03: Re: high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
121426: 07/07/03: Re: high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
128773: 08/02/06: Re: Minimum Oscillator Frequency
128774: 08/02/06: Re: Minimum Oscillator Frequency
128841: 08/02/07: Re: Possible CRC error on XC3S400 - now what?
129096: 08/02/14: Re: Virtex-4 input pad failures
130169: 08/03/17: Re: Xilinx impact, boldly going into nightmareland
131131: 08/04/11: Re: Xilinx tech Xclusive
131715: 08/04/29: XCF02S not seen in the JTAG chain
131734: 08/04/30: Re: XCF02S not seen in the JTAG chain
131792: 08/05/02: Re: XCF02S not seen in the JTAG chain
auliya:
30882: 01/05/02: Re: VHDL coding question.
AUM Systems, Inc.:
8869: 98/02/03: Job Posyting -- US-NJ * * * System Testing & Optimization * * *
8868: 98/02/03: Job Posting -- US-NJ * * * System Testing & Optimization * * *
Aurash Lazarut:
50928: 02/12/23: Re: serdes
50965: 02/12/24: Re: FPGA accelerated FPGA/ASIC tools
50968: 02/12/24: Re: Prom Splitting
50969: 02/12/24: Re: Prom Splitting
50970: 02/12/24: Re: Floor Planning DCM
50973: 02/12/24: Re: thermal issues on FPGA
51089: 02/12/31: Re: BP programmer questions, prices, alternatives
51305: 03/01/10: Re: conversions and some assistance please
52300: 03/02/06: Re: Help needed
52304: 03/02/06: Re: Help needed
52355: 03/02/07: Re: USB2 or firewire or 100Mb ethernet link to FPGA design
52356: 03/02/07: Re: blockram initialization
52451: 03/02/10: Re: Signal delays
52514: 03/02/12: Re: USB2 or firewire or 100Mb ethernet link to FPGA design
52697: 03/02/19: Re: Spartan 1 : Help
Aurel Wosylus:
17103: 99/06/30: Re: fast counter in 4013XL?
Aurelian Lazarut:
54921: 03/04/22: Re: help required in ISE 5.1 -----ERROR:NgdBuild:604 - logical block
57909: 03/07/09: Re: clock management on SPARTAN2
58421: 03/07/23: Re: iMPACT batch mode
60052: 03/09/04: Re: MICROBLAZE: user core problem
60414: 03/09/12: Re: Error when downloading with EDK
60425: 03/09/12: Re: Error when downloading with EDK
60685: 03/09/19: Re: Xilinx Parallel Cable 4 (PC4) and Platform Flash JTAG
73550: 04/09/23: Re: equal to zero
75884: 04/11/18: Re: Vccaux on Spartan 3
75890: 04/11/18: Re: Spartan-3 configuring problem
75894: 04/11/18: Re: Spartan-3 configuring problem
76231: 04/11/29: Re: CPLD + CAN bus
77368: 05/01/05: Re: iMPACT 5.1i w/Parallel Cable
78070: 05/01/24: Re: Power Analisys with MicroBlaze
78080: 05/01/24: Re: EPROMs
78407: 05/01/31: Re: Master Serial Programming
81146: 05/03/18: Re: Xilinx ISE and IP cores
82193: 05/04/08: Re: running microblaze from bram through OPB-bus
82988: 05/04/21: Re: Power Estimation without Pad Connection (XPower)
83057: 05/04/22: Re: JTAG and SPROM for Spartan II-e
83888: 05/05/09: Re: Uart16550 can't receive data over 16byte a time
83946: 05/05/10: Re: Configuring an XC3S400 Spartan 3 with JTAG
83965: 05/05/10: Re: Configuring an XC3S400 Spartan 3 with JTAG
84014: 05/05/11: Re: Configuring an XC3S400 Spartan 3 with JTAG
84252: 05/05/16: Re: SPI interface cpol & cpha
84253: 05/05/16: Re: why is it wrong with "sin"?
84327: 05/05/17: Re: Is a gated oscillator using NAND okay within a Cyclone FPGA?
84329: 05/05/17: Re: delays
84339: 05/05/17: Re: Virtex-2 JTAG problem
84341: 05/05/17: Re: Virtex-2 JTAG problem
84617: 05/05/23: Re: Virtex4 Block Ram : ISE6.3 Problem
84658: 05/05/24: Re: Mapping problem due to invalid pins in UCF file
84677: 05/05/24: Re: Mapping problem due to invalid pins in UCF file
84679: 05/05/24: Re: using a SDRAM FIFO
84686: 05/05/24: Re: Mapping problem due to invalid pins in UCF file
84725: 05/05/25: Re: Mapping problem due to invalid pins in UCF file
84762: 05/05/26: Re: State Machines.. and their efficiency.
84923: 05/06/01: Re: Spartan 3 kit FPGA configuration problem
85256: 05/06/07: Re: PowerPC crash down
85500: 05/06/10: Re: Building a MicroBlaze from scratch, unable to run.
88730: 05/08/26: Re: Writing to Spartan 3 SRAM
88904: 05/08/31: Re: Gated clock for FPGA (verilog)???
88958: 05/09/01: Re: CPLD CoolRunner-II - IO current limited to 8mA?
88965: 05/09/01: Re: Discrepancies in area estimation (Precision RTL vs Xilinx ISE
89082: 05/09/05: Re: Logic??
89307: 05/09/12: Re: SDRAM quality
89396: 05/09/14: Re: FFT implementation in Xilinx Spartan 3 started kit
90261: 05/10/07: Re: FPGA behaviour when its used resource is >90% ?
90322: 05/10/10: Re: Library Simprim cannot be found?
90448: 05/10/13: Re: RAMB16 primitive write/read collision differences betweem virtex2
91649: 05/11/10: Re: Can't pack into OLOGIC
91853: 05/11/15: Re: Having trouble Detecting ethernet packets using ethereal
92090: 05/11/22: Re: Uart core for a virtex-4
92175: 05/11/23: Re: Design Implementation in Xilinx XST
92235: 05/11/24: Re: Memory in VHDL
92752: 05/12/06: Re: problem with timing simulation (clear explanation of problem)
92819: 05/12/07: Re: Problem programming CoolRunner II xc2c256_tq144 CPLD using IMPACT
92870: 05/12/08: Re: 2 clocks switching
92912: 05/12/09: Re: How do I find the signature of PROM bitstreams?
93172: 05/12/15: Re: Mission critical & low core voltages
94150: 06/01/06: Re: Clock related questions
94144: 06/01/06: Re: Signal Skew
95420: 06/01/23: Re: Configuration Spartan 3
95965: 06/01/27: Re: Current to sink PROG_B low?
96274: 06/02/01: Re: power up reset question
96971: 06/02/14: Re: XPower report precision
96997: 06/02/14: Re: is there a way to initialize signals to a value
97030: 06/02/15: Re: is there a way to initialize signals to a value
97353: 06/02/21: Re: EDK -running from external sram
97484: 06/02/23: Re: OpenRisc 1200 on Spartan 3 - problems with stability and enabling
97537: 06/02/23: Re: OpenRisc 1200 on Spartan 3 - problems with stability and enabling
97956: 06/03/02: Re: Virtex-4FX Mini Module TEMAC examples
97970: 06/03/02: Re: problem with ISE versions
97976: 06/03/02: Re: Help wanted
98216: 06/03/07: Re: Terminologie/knowledge issu
98238: 06/03/07: Re: Questions about counter in VHDL
98284: 06/03/08: Re: Does xilinx ise 8.1 support linux red hat 4.0??????(with device
98316: 06/03/08: Re: Terminologie/knowledge issu
98320: 06/03/08: Re: speed control ac motor in FPGA
98333: 06/03/08: Re: VHDL
98341: 06/03/08: Re: Parallel readback on Spartan IIE
98404: 06/03/09: Re: speed control ac motor in FPGA
99179: 06/03/21: Re: Simulation tool
99180: 06/03/21: Re: Disk/LCD defect tolerant models for FPGA sales
99687: 06/03/28: Re: OPB monitor error
99849: 06/03/30: Re: PCB Bypass Caps
99931: 06/03/31: Re: no output from BUFGMUX
100463: 06/04/10: Re: xilinx JTAG
100486: 06/04/10: Re: xilinx JTAG
101071: 06/04/25: Re: Max and Argmax across 1,000 unsigned 10-bit numbers
101200: 06/04/27: Re: How are constants stored ?
101258: 06/04/28: Re: How are constants stored ?
101503: 06/05/02: Re: fpga programming
101572: 06/05/03: Re: detailed description on the archetecture of FPGA's/CPLD's
101718: 06/05/05: Re: Xilinx SelectMAP Question
101720: 06/05/05: Re: Xilinx SelectMAP Question
101743: 06/05/05: Re: Xilinx SelectMAP Question
101744: 06/05/05: Re: Xilinx SelectMAP Question
101745: 06/05/05: Re: Xilinx SelectMAP Question
101875: 06/05/08: Re: booting problem ML300 :eth0: Could not read PHY control register;
101897: 06/05/08: Re: Strange power up issue on Virtex4
101912: 06/05/08: Re: Strange power up issue on Virtex4
102169: 06/05/11: Re: ISE 8.1 error, help. Or where is the path?
102322: 06/05/15: Re: Power for Spartan 3
103270: 06/05/30: Re: Personalization of Xilinx ISE
103287: 06/05/30: Re: Personalization of Xilinx ISE
103344: 06/05/31: Re: Configuring Spartan 3
103351: 06/05/31: Re: Configuring Spartan 3
103411: 06/06/01: Re: Configuring Spartan 3
103414: 06/06/01: Re: Ethernet Snooping in the FPGA
103800: 06/06/12: Re: How do I use the DDS core in a verilog flow?
103801: 06/06/12: Re: Xilinx timing viloations
103815: 06/06/12: Re: How do I use the DDS core in a verilog flow?
103816: 06/06/12: Re: Xilinx timing viloations
103846: 06/06/13: Re: Xilinx timing viloations
103856: 06/06/13: Re: IDELAY clock spec. in Xilinx V4
103894: 06/06/14: Re: How do I use the DDS core in a verilog flow?
103898: 06/06/14: Re: boot mode pins on Spartan3
103981: 06/06/16: Re: bga routing
104269: 06/06/22: Re: newbie:my ISE doesn't include old xcs30 spartan how........
104418: 06/06/27: Re: Webpack ISE 8 and Vertex4 XC4VLX60
104420: 06/06/27: Re: Number of bonded IOB's
104438: 06/06/27: Re: Once synthesized RAMs are vanishing in WebPACK 8.1i03
104439: 06/06/27: Re: Once synthesized RAMs are vanishing in WebPACK 8.1i03
104472: 06/06/28: Re: Once synthesized RAMs are vanishing in WebPACK 8.1i03
104532: 06/06/29: Re: RS232 transmitter core--Xilinx xapp223(Chapman's macro)
104648: 06/07/03: Re: can't read device ID xcv200....what about the PROGRAM pin
104652: 06/07/03: Re: can't read device ID xcv200....what about the PROGRAM pin
104657: 06/07/03: Re: can't read device ID xcv200....what about the PROGRAM pin
104695: 06/07/04: Re: stable reset in fpga
104727: 06/07/05: Re: using cores exported from Xilinx plan Ahead with verilg design
104851: 06/07/07: Re: Obtain old ver ISE Foundation?
105140: 06/07/14: Re: OPB or FSL?
105580: 06/07/26: Re: How to phase align a 10MHz clock using V4LX60 DCM
106213: 06/08/09: Re: ISE software bug???
106215: 06/08/09: Re: ISE software bug???
106271: 06/08/10: Re: ISE software bug???
106613: 06/08/16: Re: Large Spartan3 vs. Small V5
106759: 06/08/18: Re: Problem Instantiating a DSP48E or RAMB36 for a Virtex5 in ISE
107574: 06/08/30: Re: Spartan-4 ?
109026: 06/09/20: Re: DDR2 Memory Controller : IOSTANDARD
109236: 06/09/22: Re: DDR2 Memory Controller : IOSTANDARD
109465: 06/09/27: Re: PUBLISHABLE PAPER RELATED TO FPGA!
109541: 06/09/28: Re: Driving a 30 bit wide LVTTL bus at 160MHz
109545: 06/09/28: Re: Virtex-5: small little things.
109656: 06/10/02: Re: Looking for HDL code for sin( a ) and x ** y Functions
109861: 06/10/06: Re: ISE 8.2 and partitions from command line
109872: 06/10/06: Re: ISE 8.2 and partitions from command line
110523: 06/10/17: Re: Virtex-5 LXT launched today !
110530: 06/10/17: Re: Virtex-5 LXT launched today !
110985: 06/10/26: Re: OPB to SPI clock frequency ratio
Aurobindo Dasgupta:
826: 95/03/08: Looking for someone to share room in hotel for ISCAS-95
austin:
66732: 04/02/25: Re: Stratix 2 ALUT architecture patented ?
67264: 04/03/09: Re: HOW to Increase jitter in ALTERA PLL ?
73827: 04/09/29: Re: DISCLOSURE : NV on-chip memory?
74013: 04/10/02: Re: FPGA vs ASIC area
74015: 04/10/02: Re: FPGA vs ASIC area
74017: 04/10/02: Re: FPGA vs ASIC area
74020: 04/10/02: Re: XPower help.
74999: 04/10/23: Re: Hello Xilinx folks -- please answer
75005: 04/10/24: Re: VCXO Emulation, or using a DLL to shift phase infinitely, or
75006: 04/10/24: Re: Hello Xilinx folks -- please answer
75015: 04/10/24: Re: Hello Xilinx folks -- please answer
74076: 04/10/03: Re: FPGA vs ASIC area
74077: 04/10/03: Re: FPGA vs ASIC area
74078: 04/10/03: Re: FPGA vs ASIC area
74095: 04/10/03: Re: FPGA vs ASIC area
75983: 04/11/21: Re: Xilinx and Altera -- maximum total bitrate for high-speed serial
76136: 04/11/25: Re: Choice of FPGA device -- my view on benchmarks
76137: 04/11/25: Re: Xilinx and Altera -- maximum total bitrate for high-speed serial
76163: 04/11/26: Re: Choice of FPGA device -- my view on benchmarks
76202: 04/11/28: Re: Xilinx and Altera -- maximum total bitrate for high-speed serial
76203: 04/11/28: Re: When JTAG programming Xilinx FPGA, should other pins be constrained?
77502: 05/01/08: Re: Tracking down HardWired History
77508: 05/01/08: Re: a general question
78171: 05/01/25: Re: Xilinx Engineering Samples [JTAG issues]
78215: 05/01/26: Re: Impact errors programing V4LX25
78216: 05/01/26: Re: Xilinx Engineering Samples [JTAG issues]
78778: 05/02/07: Re: See Peter's High-Wire Act next Tuesday
79122: 05/02/14: Re: Updated Stratix II Power Specs & Explanation
79123: 05/02/14: Re: See the next high-wire act, this time on power consumption
79138: 05/02/14: Re: Updated Stratix II Power Specs & Explanation
79139: 05/02/14: Re: Cyclone clock
79237: 05/02/15: Re: See the next high-wire act, this time on power consumption
79245: 05/02/15: Re: Updated Stratix II Power Specs & Explanation
79246: 05/02/15: Re: Updated Stratix II Power Specs & Explanation
79467: 05/02/19: Re: Issues with a batch of Virtex-II chips
79469: 05/02/19: Re: Updated Stratix II Power Specs & Explanation
79476: 05/02/19: Re: why to use FIFO on FPGA?
79481: 05/02/19: Re: why to use FIFO on FPGA?
79510: 05/02/20: Re: hdl:lament
79522: 05/02/20: Re: hdl:lament
80428: 05/03/05: Re: V4 SI: The package is thrilling Explanation of Cin
80809: 05/03/11: Re: Xilinx vs Altera high-end solutions
81215: 05/03/19: Re: XC3S50 or EPM1270?
81217: 05/03/19: Re: Stratix II vs Virtex 4
81224: 05/03/19: Re: rocketio
81233: 05/03/19: Re: Spartan 3E vs. Cyclone2
81234: 05/03/19: Re: rocketio
81260: 05/03/20: Re: Spartan 3E vs. Cyclone2
81261: 05/03/20: Mickey on Mars?
82281: 05/04/10: Re: clk_div illigal connection
82616: 05/04/14: Re: LVDS PCI card is needed
82726: 05/04/16: Re: The DLP from Texas Instruments...
82727: 05/04/16: Re: salary ballpark please guys
82735: 05/04/17: Re: salary ballpark please guys
82736: 05/04/17: Re: Spartan 3E slower that Spartan 3?
82743: 05/04/17: Re: Spartan 3E slower that Spartan 3?
82770: 05/04/17: Re: Spartan 3E slower that Spartan 3?
82856: 05/04/18: Re: Spartan 3E slower that Spartan 3?
82888: 05/04/19: GPD+APD=FPG? TLA's run amok.....
82982: 05/04/20: Re: Soft CPU vs Hard CPU's
83279: 05/04/26: Re: XC4k parts obsolete ?
83349: 05/04/27: Re: DCM Cycle-to-Cycle Jitter
83616: 05/05/03: Re: Decoupling V2P
83674: 05/05/04: Re: Speed acceleration !!!
83794: 05/05/06: Re: 40% less SEU's! in V4: another good reason to choose Xilinx
83796: 05/05/06: Re: 40% less SEU's! in V4: another good reason to choose Xilinx
83805: 05/05/06: Re: 40% less SEU's! in V4: another good reason to choose Xilinx
83831: 05/05/07: Re: 40% less SEU's! in V4: another good reason to choose Xilinx
83838: 05/05/07: Re: 40% less SEU's! in V4: another good reason to choose Xilinx
83988: 05/05/10: Re: Virtex4 running at 360Mhz DDR
84135: 05/05/12: Re: V4 vs. Stratix-II...
84602: 05/05/22: Re: spartan 3 designing board
84698: 05/05/24: Re: Altera Apex20KE PLL output jitter problem
84843: 05/05/30: Re: Xilinx Spartan 3 SSO Guidelines for 3.3V LVCMOS when using "series
86306: 05/06/24: Re: FPGA vs. ASIC vs. Processor
86483: 05/06/28: Re: Xilinx Virtex 4 device technology
87179: 05/07/18: Re: Virtex-4 breaking the 1GHz clocking barrier in general purpose FPGA fabric (e.g non dedicated circuits)
87184: 05/07/18: Re: Virtex-4 5V tolerance
87247: 05/07/20: Re: Virtex-4 hot-swappable?
87320: 05/07/21: Re: Creating Variable Delay for output signals in an XCV1000
87341: 05/07/21: Re: Xilinx software update?
87425: 05/07/23: Re: July 20th Altera Net Seminar: Stratix II Logic Density
87467: 05/07/24: Re: July 20th Altera Net Seminar: Stratix II Logic Density
87505: 05/07/25: Re: DCM.
87528: 05/07/25: Re: Free 8 bit micro for fpga
87529: 05/07/25: Re: Exact time-to-Failure data for FPGA devices
87653: 05/07/27: Re: Reset and Power-On Reset Activation XCFxxP PROMs
87692: 05/07/28: Re: Delay Generators in FPGAs
87852: 05/08/02: Re: Programmable frequency synthesizer with Xilinx DCM
87976: 05/08/04: Re: Xilinx Impact order
88020: 05/08/05: Re: Xilinx XC4VFX140 Availability ?
88035: 05/08/07: Re: Xilinx V4 & DDR2 Memory Interface
88121: 05/08/09: Re: Virtex-4 hot-swappable?
88157: 05/08/10: Re: XBERT module.
88202: 05/08/11: Re: creating HARD MACROs broken in ISE 7.1 SP3 ?
88236: 05/08/12: Re: creating HARD MACROs broken in ISE 7.1 SP3 ?
88281: 05/08/14: Re: creating HARD MACROs broken in ISE 7.1 SP3 ?
88508: 05/08/20: Re: Best FPGA for floating point performance
88664: 05/08/24: Re: Antti's last comp.arch.fpga posting
88689: 05/08/25: Re: what is the difference between "configuring" and "programming"?
88703: 05/08/25: Re: what is the difference between "configuring" and "programming"?
88772: 05/08/27: Re: Best FPGA for floating point performance
88779: 05/08/28: Re: mails from Aman Mediratta
88854: 05/08/30: Re: Array of slope A/Ds in FPGA?
89211: 05/09/07: Re: Fastest input IOB on a Spartan-3?
89284: 05/09/10: Re: Fastest input IOB on a Spartan-3?
89285: 05/09/10: Re: future of antifuse fpgas?
89531: 05/09/18: Re: future of antifuse fpgas?
89802: 05/09/26: Re: Spartan3E - problem in creating LVDS DDR pads
90053: 05/10/03: Re: Altera why so QUIET !?
90162: 05/10/05: Re: Avoiding meta stability? No where in this thread...
90163: 05/10/05: Re: Avoiding meta stability?
90551: 05/10/16: Re: Anyone remember the really early Xilinx FPGAs?
92012: 05/11/19: Re: hi everyone, tell me something about Cyclone II.
94278: 06/01/09: Re: Xilinx DCM
94219: 06/01/08: Re: PCI compliance ?
94601: 06/01/13: Re: how do I minimize the logic in this function?
95913: 06/01/26: Re: So what happened to JHDLBits?
95765: 06/01/25: Re: Xilinx padding LC numbers, how do you reeeeellly feel about it?
96315: 06/02/01: Re: BGA central ground matrix
96380: 06/02/02: Re: BGA central ground matrix
96381: 06/02/02: Re: BGA central ground matrix
96382: 06/02/02: Re: BGA central ground matrix
96385: 06/02/02: Re: BGA central ground matrix
96388: 06/02/02: Re: BGA central ground matrix
96484: 06/02/04: Re: BGA central ground matrix
96489: 06/02/04: Re: BGA central ground matrix
96667: 06/02/08: Re: Virtex4 Powerdown, Vcco questions
96766: 06/02/09: Re: Spartan3 embedded synchronous multipliers
97110: 06/02/16: Re: Implementing a two-modulus PLL divider in Altera Stratix II
98096: 06/03/04: Re: Simple ADS5273 -> Xilinx Interconnect Model
98105: 06/03/04: Re: why use an FPGA when a CPLD will do ??
98259: 06/03/07: Re: for all those who believe in ASICs....
98486: 06/03/10: Re: for all those who believe in ASICs....
98510: 06/03/11: Re: for all those who believe in ASICs....
98537: 06/03/12: Re: Combinatorial Division?
98830: 06/03/16: Re: Where are FPGA heading?
98963: 06/03/17: Re: for all those who believe
98995: 06/03/18: Re: Spartan 3 Power Supply Design
98997: 06/03/18: Re: Historical Fpga Resources
98999: 06/03/18: Re: question regarding maximum frequency on virte-e-2000
99007: 06/03/18: Re: Spartan 3 Power Supply Design
99008: 06/03/18: Re: Where are you heading?
99043: 06/03/19: Re: Historical Fpga Resources
99046: 06/03/19: Re: Where are we heading?
118628: 07/05/01: Re: Problem cascading 2 DCMs
118637: 07/05/01: Re: Where can I find the pass transistor's working curve under 1.2V?
118642: 07/05/01: Re: Problem cascading 2 DCMs
118647: 07/05/01: Re: Problem cascading 2 DCMs
118661: 07/05/01: Re: Where can I find the pass transistor's working curve under 1.2V?
118710: 07/05/02: Re: Where can I find the pass transistor's working curve under 1.2V?
118711: 07/05/02: Re: Xilinx tools concern
118712: 07/05/02: Re: DCIRESET in Virtex-4
118798: 07/05/03: Re: Select pullup, pulldown or none via embedded S/W
118808: 07/05/03: Re: Select pullup, pulldown or none via embedded S/W
118842: 07/05/04: Re: Select pullup, pulldown or none via embedded S/W
118845: 07/05/04: Re: Select pullup, pulldown or none via embedded S/W
118850: 07/05/04: Re: Select pullup, pulldown or none via embedded S/W
118851: 07/05/04: Re: Select pullup, pulldown or none via embedded S/W
118861: 07/05/04: Re: Select pullup, pulldown or none via embedded S/W
118863: 07/05/04: Re: Select pullup, pulldown or none via embedded S/W
118935: 07/05/07: Re: Xilinx software quality - how low can it go ?!
119103: 07/05/11: =?windows-1252?Q?Re=3A_power_consumption_of_integrated_?=
119113: 07/05/11: Re: how to choose the perfect fpga support
119127: 07/05/12: Re: Power Consumption Estimation for PCI card, any advice?
119144: 07/05/13: Re: Power Consumption Estimation for PCI card, any advice?
119173: 07/05/14: Re: does SRL exist in non-xilinx FPGAs?
119191: 07/05/14: Re: Power Consumption Estimation for PCI card, any advice?
119235: 07/05/15: Re: Power Consumption Estimation for PCI card, any advice?
119262: 07/05/15: Re: Power Consumption near Timing Failure Point
119300: 07/05/16: Re: Video scaler for Spartan 3E?
119303: 07/05/16: Re: seeking insights for potential reconfigurable computing application
119324: 07/05/16: Re: Video scaler for Spartan 3E?
119374: 07/05/17: Re: Video scaler for Spartan 3E?
119565: 07/05/22: Re: System-synchronous interface clocking between FPGA's
119596: 07/05/23: Re: LVCMOSS33 I/O sink current
119611: 07/05/23: Re: clarification: clock doubling in Spartan 3
119613: 07/05/23: Re: clarification: clock doubling in Spartan 3
119614: 07/05/23: Re: clarification: clock doubling in Spartan 3
119666: 07/05/24: Re: LVDS termination scheme to nonstandard ribbon cable
119671: 07/05/24: Re: LVDS termination scheme to nonstandard ribbon cable
119676: 07/05/24: Re: LVDS termination scheme to nonstandard ribbon cable
119678: 07/05/24: Re: LVDS termination scheme to nonstandard ribbon cable
119686: 07/05/24: Re: LVDS termination scheme to nonstandard ribbon cable
119688: 07/05/24: Re: LVDS termination scheme to nonstandard ribbon cable
119689: 07/05/24: Re: LVDS termination scheme to nonstandard ribbon cable
119700: 07/05/24: Re: LVDS termination scheme to nonstandard ribbon cable
119755: 07/05/25: Re: LVDS termination scheme to nonstandard ribbon cable
119772: 07/05/25: Re: low speed communication
119805: 07/05/26: Re: Spartan3 LVCMOS33 Slew rate
119806: 07/05/26: Re: 6502 and CPU licences in general
119809: 07/05/26: Re: Spartan3 LVCMOS33 Slew rate
119812: 07/05/26: Re: 6502 and CPU licences in general
119813: 07/05/26: Re: Spartan3 LVCMOS33 Slew rate
119912: 07/05/29: Re: LVDS termination scheme to nonstandard ribbon cable
119916: 07/05/29: Re: Spartan3 LVCMOS33 Slew rate
119925: 07/05/29: Re: Spartan3 LVCMOS33 Slew rate
119933: 07/05/29: Re: Spartan3 LVCMOS33 Slew rate
119977: 07/05/30: Re: Spartan3 LVCMOS33 Slew rate
119989: 07/05/30: Re: Nexys by Digilen xbd file
119994: 07/05/30: Re: Xilinx Seminars in Wiesbaden, Berlin, Hannover
120033: 07/05/31: Re: LVDS termination scheme to nonstandard ribbon cable
120044: 07/05/31: Re: Xilinx Seminars in Wiesbaden, Berlin, Hannover
120054: 07/05/31: Can we move on, please?
120179: 07/06/02: Re: 180 differential inputs each 800Mbps using V5
120187: 07/06/02: Re: 180 differential inputs each 800Mbps using V5
120192: 07/06/02: Re: 180 differential inputs each 800Mbps using V5
120265: 07/06/04: Re: ISE and total equivalent gate count
120278: 07/06/04: Re: Lattice XP2 finally announced
120281: 07/06/04: Re: Lattice XP2 finally announced
120284: 07/06/04: Power on Spartan 90nm process node
120288: 07/06/04: Re: Power on Spartan 90nm process node
120305: 07/06/05: Re: Power on Spartan 90nm process node
120306: 07/06/05: V4 FX Apologia: (again)
120307: 07/06/05: Re: Lattice XP2 finally announced
120311: 07/06/05: Re: ISE and total equivalent gate count
120314: 07/06/05: Re: Topics and Ideas for BS Project
120315: 07/06/05: Re: Choosing a clock
120319: 07/06/05: ARM in FPGA's?
120324: 07/06/05: Re: ARM in FPGA's?
120349: 07/06/05: Re: Virtex4 CLKX2 DCM Jitter
120355: 07/06/05: Re: Virtex4 CLKX2 DCM Jitter
120393: 07/06/06: Re: Virtex4 CLKX2 DCM Jitter
120401: 07/06/06: Re: Virtex4 CLKX2 DCM Jitter, comments on DAC
120403: 07/06/06: Re: asynchronous circuit design
120408: 07/06/06: Re: What should be taken care of when two FPGA broad connected together?
120458: 07/06/07: Re: Lattce SC Purspeed I/O
120459: 07/06/07: Re: Virtex4 CLKX2 DCM Jitter, comments on DAC
120473: 07/06/07: Re: Virtex4 CLKX2 DCM Jitter
120475: 07/06/07: Re: Lattce SC Purspeed I/O
120483: 07/06/07: Re: LVPECL output skew
120490: 07/06/07: Re: LVPECL output skew
120517: 07/06/08: Re: LVPECL output skew
120537: 07/06/08: Re: LVPECL output skew
120785: 07/06/16: Re: Virtex-4 pre-configuration pull-ups
120810: 07/06/17: Re: Graduate/Junior FPGA Designer concerns
120811: 07/06/17: Re: Xpower complains about Vccint for Spartan 3A
120830: 07/06/18: Re: Xpower complains about Vccint for Spartan 3A
120831: 07/06/18: Re: help on clock fowarding between 2 FPGAs
120898: 07/06/19: Re: noisy rising edge clock - non-monotonic clock
120940: 07/06/20: Re: Suggestions for Xilinx based evaluation board for image processing
121001: 07/06/21: Re: Virtex 5 Rocketio
121006: 07/06/21: Re: Virtex 5 Rocketio
121147: 07/06/26: Re: Can FPGAs inputs detect low currents?
121326: 07/07/02: Re: s3a kit - Use sma as signal output ?
121336: 07/07/02: Re: Can I use chipscoe to look at V5 GTPoutputs
121386: 07/07/03: Re: Xilinx DCM Reset
121393: 07/07/03: Re: Why PLL and not DCM for V5?
121398: 07/07/03: Re: Spartan-3e JTAG no device id
121399: 07/07/03: Re: Spartan-3e JTAG no device id
121408: 07/07/03: Re: Xilinx DCM Reset
121409: 07/07/03: Re: Spartan-3e JTAG no device id
121410: 07/07/03: Re: Spartan-3e JTAG no device id
121411: 07/07/03: Re: Spartan-3e JTAG no device id
121417: 07/07/03: Re: Spartan-3e JTAG no device id
121418: 07/07/03: Re: Xilinx DCM Reset
121422: 07/07/03: Re: Xilinx DCM Reset
121423: 07/07/03: Re: Xilinx DCM Reset
121450: 07/07/04: Re: Rocket IO clocking
121460: 07/07/04: Re: Spartan-3e JTAG no device id
121482: 07/07/05: Re: ICAP in V4 FX20 only working after Reset
121483: 07/07/05: Re: Xilinx V4/V5 FPGA SATA GTP
121485: 07/07/05: Re: Xilinx DCM Reset
121486: 07/07/05: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121490: 07/07/05: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121491: 07/07/05: Re: SOLVED: Spartan-3e JTAG no device id
121532: 07/07/06: Re: ML555 SATA GTP dosen't work
121533: 07/07/06: Re: ML555 SATA GTP dosen't work
121600: 07/07/09: Re: A Way for a DSP to tell an FPGA to load itself from Flash
121609: 07/07/09: Re: A Way for a DSP to tell an FPGA to load itself from Flash
121646: 07/07/10: Re: EDK and ecncrpted .bit, .nky, .mcs files
121672: 07/07/11: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
121673: 07/07/11: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
121676: 07/07/11: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
121677: 07/07/11: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
121679: 07/07/11: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
121681: 07/07/11: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
121687: 07/07/11: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
121703: 07/07/11: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
121736: 07/07/12: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
121737: 07/07/12: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
121738: 07/07/12: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
121750: 07/07/12: Re: Designing the right clock tree for a multi-FPGA setup
121752: 07/07/12: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
121761: 07/07/12: Re: Convert Schematic Files (.sch) to Verilog Files (.v) for simulation
121763: 07/07/12: Re: CML output swing for V5
121768: 07/07/12: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
121770: 07/07/12: Re: Convert Schematic Files (.sch) to Verilog Files (.v) for simulation
121777: 07/07/12: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,Leon)?
121818: 07/07/13: Re: Convert Schematic Files (.sch) to Verilog Files (.v) for simulation
121819: 07/07/13: Re: Designing the right clock tree for a multi-FPGA setup
121831: 07/07/13: Re: Designing the right clock tree for a multi-FPGA setup
121833: 07/07/13: Re: Newbie's first FPGA board !
121870: 07/07/13: Re: What is the resistance of a big FPGA for VCCINT (unpowered)
121890: 07/07/14: Re: What is the resistance of a big FPGA for VCCINT (unpowered)
121921: 07/07/15: Re: spartan-3e idcode
121923: 07/07/15: Re: QDR II SRAM Interface
121939: 07/07/15: Re: spartan-3e idcode
121987: 07/07/16: Re: spartan-3e idcode
122055: 07/07/18: Re: Can multiple Ferrite Beads be used to connect ...?
122061: 07/07/18: Re: Bypass caps for Spartan 3, PQ208, 4-layer board... Educational
122064: 07/07/18: Re: Xilinx S3 Starterkit, how hot it is supposed to be?
122112: 07/07/19: Re: Xilinx S3 Starterkit, how hot it is supposed to be?
122144: 07/07/20: Re: Xilinx fpgas...
122207: 07/07/23: Re: Bizarre Xilinx configuration problem
122236: 07/07/24: Re: Bizarre Xilinx configuration problem -- oops never mind
122238: 07/07/24: Re: hard_temac : mdio conflict
122304: 07/07/25: Re: hard_temac : mdio conflict
122305: 07/07/25: Re: Virtex-5 and powerpc...its alive....
122316: 07/07/25: Re: Virtex-5 and powerpc...its alive....
122439: 07/07/27: Re: V5 Differential Select I/O
122450: 07/07/27: Re: Question about GSR?
122456: 07/07/27: Re: Question about GSR?
122457: 07/07/27: Re: Can Altera and Xilinx Done signals be tied together? Has anyone
122465: 07/07/27: Re: Question about GSR?
122467: 07/07/27: Re: Question about GSR?
122468: 07/07/27: Re: Question about GSR?
122471: 07/07/27: Re: Question about GSR?
122487: 07/07/28: Re: dual port ram
122523: 07/07/30: Re: Website
122528: 07/07/30: Re: Question on using RLOC_RANGE
122531: 07/07/30: Re: Website
122534: 07/07/30: Re: Question on using RLOC_RANGE
122535: 07/07/30: Re: Question on using RLOC_RANGE
122540: 07/07/30: Re: Question on using RLOC_RANGE
122629: 07/08/01: Re: V5 compared to V2P
122704: 07/08/03: Re: V4FX PPC suspend/resume
122707: 07/08/03: Re: V4FX PPC suspend/resume
122765: 07/08/06: Re: Need suggestion for my project
122779: 07/08/06: Re: FPGA board connected to CMOS chip: ESD hazards?
122810: 07/08/07: Re: FPGA board connected to CMOS chip: ESD hazards?
122826: 07/08/07: Re: New Xilinx forum.
122846: 07/08/08: Re: New Xilinx forum.
122847: 07/08/08: Re: New Xilinx forum.
122848: 07/08/08: Re: New Xilinx forum.
122849: 07/08/08: Re: New Xilinx forum.
122852: 07/08/08: Re: New Xilinx forum.
122890: 07/08/09: Re: Reset and DCM
122897: 07/08/09: Re: New Xilinx forum.
122921: 07/08/10: Re: Amount of wire and logic
122922: 07/08/10: Re: embedded tips
122986: 07/08/13: Re: New Xilinx forum.
122990: 07/08/13: Re: LUT distributed memory in FPGA devices
123076: 07/08/15: Re: Virtex 4 IBUFG to DCM routing question
123077: 07/08/15: Re: Virtex 4 IBUFG to DCM routing question
123252: 07/08/21: Re: Spartan-3A DSP vs. Cyclone III Power-wise
123317: 07/08/23: Re: Spartan-3A DSP vs. Cyclone III Power-wise
123417: 07/08/27: Re: PLL Power and m/n ratio
123709: 07/09/02: Re: V5 Configuration via SPI
123743: 07/09/03: Re: V5 Configuration via SPI
123744: 07/09/03: Re: Low-level FPGA programming?
124022: 07/09/10: Re: Question about Virtex-4 DCM
124234: 07/09/15: Re: Virtex5 PLL for DDR2 interface
124272: 07/09/17: Re: Altera / Lattice / Xilinx CPLDs ?
124635: 07/09/28: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
124831: 07/10/05: Re: Virtex 13?
124876: 07/10/09: Re: Need suggestion on FPGA kit
124877: 07/10/09: Re: Starting FPGA
124882: 07/10/09: Re: Need suggestion on FPGA kit
124919: 07/10/10: Re: Cyclone II SSTL-2 on-chip resistors
125204: 07/10/17: Re: difference between XC5VLX50-1FFG676C and XC5VLX50-1FFG676CES
125245: 07/10/18: Re: difference between XC5VLX50-1FFG676C and XC5VLX50-1FFG676CES
125297: 07/10/19: Re: FPGA input level conversion
125298: 07/10/19: Re: FPGA input level conversion
125308: 07/10/19: Re: FPGA input level conversion
125313: 07/10/20: Re: virtex-4 power consumption
125539: 07/10/27: Re: total equivalent gate count
125711: 07/11/01: Re: Another way to handle floating inputs.
125721: 07/11/01: Re: Another way to handle floating inputs.
125775: 07/11/04: Re: APU (xilinx PPC) is it a soft core ?
125778: 07/11/04: Re: DDR2 Interface
125799: 07/11/05: Re: FPGA I/O Selection in UCF
125803: 07/11/05: Re: FPGA I/O Selection in UCF
125827: 07/11/06: Re: not totally repulsive
125878: 07/11/07: Re: Custom processor developement issues
125902: 07/11/08: Re: Maximum current drive according to datasheet ?!
125903: 07/11/08: Re: Maximum current drive according to datasheet ?!
126010: 07/11/12: Students: where to go for help
126019: 07/11/12: Re: Students: where to go for help
126078: 07/11/14: Re: Xilinx Encrypted bit file
126093: 07/11/14: Re: Xilinx Encrypted bit file
126104: 07/11/14: Re: Xilinx Encrypted bit file
126182: 07/11/16: Low cost FPGA w/serdes
126207: 07/11/16: Re: TI DSP soft core in Xilinx?
126230: 07/11/17: Re: Low cost FPGA w/serdes
126255: 07/11/18: Re: Low cost FPGA w/serdes
126266: 07/11/18: Re: Low cost FPGA w/serdes
126301: 07/11/19: Re: Low cost FPGA w/serdes
126308: 07/11/19: Re: Low cost FPGA w/serdes
126312: 07/11/19: Re: Parallel to Serial ASI ...
126369: 07/11/20: Re: Low cost FPGA w/serdes
126371: 07/11/20: Re: Virtex5 Evaluation Board
126414: 07/11/21: Re: partial dynamic reconfiguration on Virtex-4 SX35
126515: 07/11/26: Re: DCM with instable clock
126546: 07/11/27: Re: Global Reset using Global Buffer
126563: 07/11/27: Re: Global Reset using Global Buffer
126611: 07/11/28: Re: DCM with instable clock
126612: 07/11/28: Re: Global Reset using Global Buffer
126613: 07/11/28: Re: Xilinx IO leakage when not powered
126615: 07/11/28: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
126681: 07/11/29: Re: Cascaded DCMs with variable phase shift (Xilinx)
126745: 07/11/30: Re: Cascaded DCMs with variable phase shift (Xilinx)
126911: 07/12/05: Re: reconfigurable, modular design and clock signals - Question
126940: 07/12/06: Re: reconfigurable, modular design and clock signals - Question
127130: 07/12/12: Re: Poor quality Xilinx boards ? Your experience ?
127133: 07/12/12: Re: Poor quality Xilinx boards ? Your experience ?
127140: 07/12/12: Re: Poor quality Xilinx boards ? Your experience ?
127245: 07/12/15: Re: Using LVDS_25 with 3.3V Vcco.
127246: 07/12/15: Re: Getting started guide for Digilent Spartan 3E Starter Board?
127266: 07/12/16: Re: Why the core dynamic power isn't 0 when the toggle =?ISO-8859-1?Q?_rate_is_0??=
127294: 07/12/17: Re: Why the core dynamic power isn't 0 when the toggle rate is 0
127327: 07/12/18: Re: VCCIO issue on Xilinx Spartan3E !
127330: 07/12/18: Re: MGT Transciever
127377: 07/12/19: Re: ASIC verification job info request
127416: 07/12/21: Re: PowerPC & Spartan-3E Embedded Processing Development Kit - SP3E1600E
127418: 07/12/21: Re: PowerPC & Spartan-3E Embedded Processing Development Kit - SP3E1600E
127563: 08/01/02: Re: spartan 3e JTAG programming
127613: 08/01/03: Re: Differential output drive-strength in spartan-3
127615: 08/01/03: Re: Differential output drive-strength in spartan-3
127617: 08/01/03: Re: Differential output drive-strength in spartan-3
127641: 08/01/04: Re: Vendors of FPGA's
127642: 08/01/04: Re: XPS MPMC
127644: 08/01/04: Re: XPS MPMC
127803: 08/01/08: Re: Bad micro blaze behaviour during power off
127814: 08/01/08: Re: Bad micro blaze behaviour during power off
127878: 08/01/09: Re: How to program FPGA permanently?
127970: 08/01/11: Re: Power up Behavior of Virtex5 IOs
127971: 08/01/11: Re: FPGA evaluation board with > 32K slices
128020: 08/01/13: Re: Virtex4 burn-in failure
128042: 08/01/14: Re: Virtex4 burn-in failure
128044: 08/01/14: Re: Virtex4 burn-in failure
128059: 08/01/14: Re: FPGA's as DSP's
128109: 08/01/15: Re: Question on FPGA
128135: 08/01/16: Re: Basic FPGA question about Reset
128146: 08/01/16: Re: Basic FPGA question about Reset
128166: 08/01/17: Re: Basic FPGA question about Reset
128167: 08/01/17: Re: Basic FPGA question about Reset
128168: 08/01/17: Re: effect of xray on fpga electronic circuits
128169: 08/01/17: Re: effect of xray on fpga electronic circuits
128182: 08/01/17: Re: Basic FPGA question about Reset
128233: 08/01/18: Re: Fuzzy Fixed Point Calculating
128235: 08/01/18: Re: Fuzzy Fixed Point Calculating
128299: 08/01/20: Re: How FPGA downconvert Giga SPS ADC data?
128302: 08/01/20: Re: How FPGA downconvert Giga SPS ADC data?
128647: 08/02/01: Re: Xilinx timming analysis
128652: 08/02/01: Re: Keeping Xilinx tool from Optimizing out Debugging signals
128666: 08/02/02: Re: spartan3a support DVI ?
128684: 08/02/03: Re: Bitstream verification through readback
128789: 08/02/06: Re: Partial Reconfiguration of Virtex-5: ISE and EAPR?
128794: 08/02/06: Re: Virtex5 not for SONET or SDH
128836: 08/02/07: Re: Partial Reconfiguration of Virtex-5: ISE and EAPR?
128837: 08/02/07: Re: Partial Reconfiguration of Virtex-5: ISE and EAPR?
128839: 08/02/07: Virtex 5 and SONET/SDH
128852: 08/02/07: Re: I/O mode to use for USB ..?
128997: 08/02/12: Re: Virtex4FX over-voltage
129048: 08/02/13: Re: HELP on PLL and DCM
129111: 08/02/14: Re: Microblaze 7.0 on V2pro?
129117: 08/02/14: Re: Microblaze 7.0 on V2pro?
129137: 08/02/15: Re: Microblaze 7.0 on V2pro?
129138: 08/02/15: Re: Virtex 4 package layout
129142: 08/02/15: Re: Microblaze 7.0 on V2pro?
129153: 08/02/15: Re: Virtex 4 package layout
129249: 08/02/19: Re: Virtex 4 package layout
129252: 08/02/19: Re: Virtex 4 package layout
129260: 08/02/19: Re: Virtex5 BUFR min frequency
129327: 08/02/20: Re: V4FX: LVCMOS25 vs LVCMOS33 output buffer
129339: 08/02/21: Re: which IOSTANDARD to use for IO-bank in Spartan-3
129341: 08/02/21: Re: Software Defined Radio auf Xilinx Virtex 4
129345: 08/02/21: Re: Reconfiguration (on the fly) using SPARTAN 3A
129349: 08/02/21: Re: Reconfiguration (on the fly) using SPARTAN 3A
129352: 08/02/21: Re: Reconfiguration (on the fly) using SPARTAN 3A
129382: 08/02/22: Re: V4FX: LVCMOS25 vs LVCMOS33 output buffer
129383: 08/02/22: Re: Reconfiguration (on the fly) using SPARTAN 3A
129387: 08/02/22: Re: ICAP in SPARTAN 3A
129388: 08/02/22: Re: Software Defined Radio on Xilinx Virtex 4
129393: 08/02/22: Re: ICAP in SPARTAN 3A
129409: 08/02/22: Re: V4FX: LVCMOS25 vs LVCMOS33 output buffer
129411: 08/02/22: Re: V4FX: LVCMOS25 vs LVCMOS33 output buffer
129412: 08/02/22: Re: V4FX: LVCMOS25 vs LVCMOS33 output buffer
129495: 08/02/26: Re: Typical jitter of high frequency oscillators?
129509: 08/02/26: Re: Typical jitter of high frequency oscillators?
129566: 08/02/27: Re: Why must a V4 be configured within 10 minutes of power up?
129598: 08/02/28: Re: Why must a V4 be configured within 10 minutes of power up?
129706: 08/03/03: Re: clock distribution accross boards
129752: 08/03/04: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
129780: 08/03/05: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
129785: 08/03/05: Removal of a feature, moving SCD to production
129788: 08/03/05: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
129796: 08/03/05: Re: Removal of a feature, moving SCD to production
129798: 08/03/05: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
129799: 08/03/05: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
129808: 08/03/05: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
129836: 08/03/06: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
129844: 08/03/06: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
129845: 08/03/06: Re: AES Bitstream Encryption in Virtex-4. How safe it is?
129868: 08/03/07: Re: ML523 power module schematics
129869: 08/03/07: Re: SiliconBlue enters the FPGA fray
129870: 08/03/07: Re: SiliconBlue enters the FPGA fray
129873: 08/03/07: Re: SiliconBlue enters the FPGA fray
129877: 08/03/07: Re: Danger of having JTAG TAP controller always enabled in Xilinx
129883: 08/03/07: Re: Danger of having JTAG TAP controller always enabled in Xilinx
129919: 08/03/10: Re: ML523 power module schematics
129920: 08/03/10: Re: Virtex-4 VLX25 DCM problem
129921: 08/03/10: Re: SiliconBlue enters the FPGA fray
129925: 08/03/10: Re: SiliconBlue enters the FPGA fray
129931: 08/03/10: Re: Virtex-4 VLX25 DCM problem
129948: 08/03/11: Re: Virtex-4 VLX25 DCM problem
130067: 08/03/14: Re: DDR3 speed, Altera vs Xilinx
130088: 08/03/14: Re: DDR3 speed, Altera vs Xilinx
130093: 08/03/14: Re: DDR3 speed, Altera vs Xilinx
130172: 08/03/17: Altera vs Xilinx
130174: 08/03/17: Re: total cost for virtex II pro FPGA
130180: 08/03/17: Re: Xilinx Webcase Workflow
130196: 08/03/17: Re: Chipscope
130228: 08/03/18: Re: Xilinx Webcase Workflow
130229: 08/03/18: Re: Xilinx interview questions
130233: 08/03/18: Re: Xilinx Webcase Workflow
130379: 08/03/21: Re: Power Estimation of Microblaze (Power PC) based architectures
130413: 08/03/22: Re: High speed memory read and transfer via rocket IO..
130496: 08/03/25: Re: Timing constraints in ucf
130519: 08/03/26: Re: Timing constraints in ucf
130671: 08/03/29: Re: ISE 10.1 - Initial experience
130686: 08/03/30: Re: ISE 10.1 - Initial experience
130732: 08/03/31: Welcome to our world - Blog
130776: 08/04/01: now I can talk about it...
130780: 08/04/01: Re: now I can talk about it...
130781: 08/04/01: Re: now I can talk about it...
130791: 08/04/01: Re: now I can talk about it...
130809: 08/04/02: Re: now I can talk about it...
130839: 08/04/03: Re: Protecting design from being downloaded on other (similar) FPGA
130844: 08/04/03: Re: Beginner's silly question about ICAP
130899: 08/04/04: Re: Xilinx FPGA + SMPS
130917: 08/04/04: Re: Xilinx FPGA + SMPS
130918: 08/04/04: Re: Xilinx FPGA + SMPS
130919: 08/04/04: Re: Xilinx inferred FIFOs
130948: 08/04/06: Re: Xilinx inferred FIFOs
131013: 08/04/08: Re: Intel plans to tackle cosmic ray threat (actually they have been
131018: 08/04/08: Re: Intel plans to tackle cosmic ray threat (actually they have been
131019: 08/04/08: Re: Intel plans to tackle cosmic ray threat (actually they have been
131020: 08/04/08: Re: Intel plans to tackle cosmic ray threat (actually they have been
131023: 08/04/08: Re: Intel plans to tackle cosmic ray threat (actually they have been
131038: 08/04/08: Re: Intel plans to tackle cosmic ray threat (actually they have been
131069: 08/04/09: Re: Intel plans to tackle cosmic ray threat
131099: 08/04/10: Re: Intel plans to tackle cosmic ray threat (actually they have been
131100: 08/04/10: Re: Intel plans to tackle cosmic ray threat (actually they have been
131124: 08/04/11: Re: Xilinx tech Xclusive
131126: 08/04/11: Space - Xilinx Frontier?
131483: 08/04/22: Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860
131486: 08/04/22: Re: DCM configuration in Virtex-4 FPGA
131506: 08/04/23: Re: FPGA comeback
131512: 08/04/23: Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860
131563: 08/04/25: Re: -. . ..- ... --. .-. --- ..- --- .--.
131567: 08/04/25: Re: -. . ..- ... --. .-. --- ..- --- .--.
131581: 08/04/25: Re: -. . ..- ... --. .-. --- ..- --- .--.
131589: 08/04/25: Re: -. . ..- ... --. .-. ..- --- .--.
131591: 08/04/25: Re: Virtex-4 inrush power-on current
131593: 08/04/25: Re: Spartan3 "commercial" temperature range
131604: 08/04/25: Re: (won't even attempt to try again .. .. ..)
131605: 08/04/25: Re: Spartan3 "commercial" temperature range
131612: 08/04/25: Re: Virtex-4 inrush power-on current
131643: 08/04/27: Re: how can i recover my unencrypted bitstream starting from encrypted
131649: 08/04/27: Re: how can i recover my unencrypted bitstream starting from encrypted
131657: 08/04/28: Aldiss Lamps, etc.
131658: 08/04/28: Re: how can i recover my unencrypted bitstream starting from encrypted
131668: 08/04/28: Re: Virtex-4 power-on current
131671: 08/04/28: Re: how can i recover my unencrypted bitstream starting from encrypted
131692: 08/04/29: Re: Virtex-4 power-on current
131712: 08/04/29: Re: how can i recover my unencrypted bitstream starting from encrypted
131714: 08/04/29: Re: understanding xilinx silicon revisions (does ES come before CES4,
131716: 08/04/29: Re: understanding xilinx silicon revisions (does ES come before CES4,
131717: 08/04/29: Re: understanding xilinx silicon revisions (does ES come before CES4,
131718: 08/04/29: Re: XCF02S not seen in the JTAG chain
131739: 08/04/30: Re: XCF02S not seen in the JTAG chain
131741: 08/04/30: Re: how can i recover my unencrypted bitstream starting from encrypted
131742: 08/04/30: Re: Virtex4 DCM doesn't work unless freezing cold
131743: 08/04/30: Re: Virtex4 DCM doesn't work unless freezing cold
131746: 08/04/30: Re: how can i recover my unencrypted bitstream starting from encrypted
131799: 08/05/02: Re: Virtex4 Output Pins during Configuration
131804: 08/05/02: Re: quick question
131805: 08/05/02: Re: Virtex4 Output Pins during Configuration
131810: 08/05/02: Re: quick question
131815: 08/05/02: Re: quick question
131816: 08/05/02: Re: quick question
131826: 08/05/02: Re: quick question
131840: 08/05/03: Re: Using SRL16
131852: 08/05/04: Re: Using SRL16 with reset
131888: 08/05/06: Re: BRAM initialization / bitstream configuration
131894: 08/05/06: Re: Getting started with VHDL and Verilog
131906: 08/05/06: Re: FPGA dev kit with 4-8 Cyclones or Spartans
131964: 08/05/08: Re: Virtex XCV1000E-6FG860C
131992: 08/05/09: Re: Vritex2PRO: LVDCI for inputs?
131999: 08/05/09: Re: Anyway to secure a Xilinx NGC file ?
132002: 08/05/09: Re: Virtex XCV1000E-6FG860C
132065: 08/05/12: Re: Anyway to secure a Xilinx NGC file ?
132066: 08/05/12: Re: RLC package parasitics
132067: 08/05/12: Re: Is Virtex 4 supported by Jbits ?
132068: 08/05/12: Re: value of the weak pull up resistor on IOBs of Virtex5
132107: 08/05/13: Re: power supply noise margin
132142: 08/05/15: Re: Cyclone 3 on chip termination
132146: 08/05/15: Re: question about high speed serial links with clock forwarding
132180: 08/05/16: Re: Cyclone 3 margins: none at all at 3.3v
132184: 08/05/16: Re: Resetting FPGA Without watch dog timer
132189: 08/05/16: Re: frame format virtex 5
132196: 08/05/16: Re: Cyclone 3 margins: none at all at 3.3v
132242: 08/05/19: Re: Resetting FPGA Without watch dog timer
132243: 08/05/19: Re: frame format virtex 5
132253: 08/05/19: Announcing Virtex 57!
132280: 08/05/20: Re: Stratix IV Announced
132316: 08/05/21: Re: Every newbie's favorite project: the Quadrature Rotary Encoder
132343: 08/05/22: Re: 1250gbps input on virtex-5
132452: 08/05/27: 'Nother one bites the dust
132453: 08/05/27: Re: 'Nother one bites the dust
132694: 08/06/05: Re: Xilinx cuts 250 jobs.
132695: 08/06/05: Re: A new FPGA company comes out of Stealth mode - SiliconBlue
132720: 08/06/05: Re: A new FPGA company comes out of Stealth mode - SiliconBlue
132953: 08/06/11: Re: Cheating the FPGA clock speed
132959: 08/06/11: New Home
132964: 08/06/11: Re: New Home
132965: 08/06/11: Re: DISABLING POWERPC IN VIRTEXII PRO
132967: 08/06/11: Re: Cheating the FPGA clock speed
133001: 08/06/12: Re: Automotive Temperature +100 deg C+ FPGA's -- who's parts are
133107: 08/06/18: Re: Xilinx Webpack
133127: 08/06/18: Re: Xilinx Webpack
133134: 08/06/18: Re: Xilinx Webpack
133166: 08/06/19: Re: Xilinx Webpack
133289: 08/06/23: Re: XAUI - INTERNAL LOOPBACK SETUP - DRP (DYNAMIC RECONFIGURATION
133317: 08/06/24: Re: Linked Group for FPGAs & CPLDs
133320: 08/06/24: Re: XAUI - INTERNAL LOOPBACK SETUP - DRP (DYNAMIC RECONFIGURATION
133345: 08/06/25: Re: RAM and shift register constraints
133348: 08/06/25: Re: RAM and shift register constraints
133465: 08/06/30: Re: on FRAME_ECC_VIRTEX4 functionality
133466: 08/06/30: Re: on FRAME_ECC_VIRTEX4 functionality
133468: 08/06/30: Re: on FRAME_ECC_VIRTEX4 functionality
133471: 08/06/30: Re: What is TIEOFF_X0Y31
133484: 08/07/01: Re: on FRAME_ECC_VIRTEX4 functionality
133487: 08/07/01: Re: What is TIEOFF_X0Y31
133497: 08/07/01: Re: Nintendo DS Screenshots / Video Capture
133527: 08/07/02: Re: Timing Analyzer report for IOBs -- 1GSPS DAC interface
133530: 08/07/02: Re: Timing Analyzer report for IOBs -- 1GSPS DAC interface
133531: 08/07/02: Re: Nintendo DS Screenshots / Video Capture
133705: 08/07/10: Re: Low cost solution to program Spartan 3AN DSP development board
133833: 08/07/16: Re: Xilinx/Altera gate equivalence
134184: 08/07/29: Re: HWICAP in virtex-5
134185: 08/07/29: Re: Die sizes of FPGAs (approx)
134306: 08/08/05: Re: Altera sues Zilog - signs of desperation from Programmable Vendor
134453: 08/08/11: Re: spartan sa dcm maximal frequency
134508: 08/08/14: Re: Question on V4 HSPICE model
134558: 08/08/18: More work, less posts
135964: 08/10/24: Re: Design security
138706: 09/03/05: Re: Spartan 6 3.3V (was Re: Virtex6 Virtex4 FPGA compatibility)
139337: 09/03/26: Re: Dynamic reconfiguration in Spartan 3
139352: 09/03/27: Re: Dynamic reconfiguration in Spartan 3
139501: 09/04/01: Re: DCM vs PLL
139616: 09/04/07: Re: Virtex6 software
139824: 09/04/15: Re: What is the minimum acceptable slack on a signal
140672: 09/05/21: Re: DCM Jitter
141217: 09/06/11: Re: Latest Xilinx Discontinuations
141231: 09/06/11: Re: Latest Xilinx Discontinuations
141232: 09/06/11: Re: Safe margin in FPGA static timing analysis
141343: 09/06/19: Re: Virtex 2 Pro IO Banks Vcco
141344: 09/06/19: Re: Virtex 2 Pro IO Banks Vcco
141906: 09/07/16: Re: Using DCMs in a spartan 3 FPGA
142038: 09/07/22: Re: Is it possible to encrypt an existing bit file with BitGen?
142322: 09/08/04: Re: AES encryption of bitstream - is my design secure?
142339: 09/08/05: Re: AES encryption of bitstream - is my design secure?
142349: 09/08/05: Re: AES encryption of bitstream - is my design secure?
142363: 09/08/06: Peter Alfke
142498: 09/08/13: Re: V5 GTX and V4 MGT interoperability
142819: 09/09/02: Re: Virtex-5 clock input is excessively loading SERDES recovered
143177: 09/09/24: Re: Virtex 4 configruation frame internal details
143382: 09/10/07: Re: Spartan-6 SERDES Speed
143476: 09/10/12: Re: integrating chipscope pro in EDK
143479: 09/10/12: Re: FPGA ruined (?)
143499: 09/10/13: Re: FPGA on-die LVDS termination issues
143519: 09/10/14: Re: FPGA on-die LVDS termination issues
143540: 09/10/15: Re: FSM-states after reconf.
143544: 09/10/15: Re: What is the basis on flip-flop replaced by a latch
143548: 09/10/15: Re: What is the basis on flip-flop replaced by a latch
143644: 09/10/19: Re: xilinx edge trigger interrupt
143714: 09/10/22: Re: Time stability of clock on FPGA board
143722: 09/10/22: Re: Time stability of clock on FPGA board
143725: 09/10/22: Re: CPLD/FPGA with Linux
143793: 09/10/26: Re: Time stability of clock on FPGA board
143800: 09/10/26: Re: V5 GTX Receiver Detect
143811: 09/10/27: Re: V5 GTX Receiver Detect
143870: 09/10/30: Re: save data from adc in text file
143898: 09/11/02: Re: Need some help creating a ring oscillator on a Spartan-3AN
143946: 09/11/04: Re: Cyclone IV announced
143968: 09/11/05: Re: Cyclone IV announced
144133: 09/11/12: Re: max. sinking current of XC95144xl cpld
144148: 09/11/13: New blog post on alphas in packagin
144150: 09/11/13: Re: New blog post on alphas in packagin
144166: 09/11/16: Re: Interconnecting 3v3 LVDS transmitter to 2V5 Receiver
144205: 09/11/19: Re: Shannon limit
144226: 09/11/20: Re: EDK11 under 64-bit OS
144265: 09/11/23: Re: Microblaze interconnection
144282: 09/11/24: Re: Deskew Reginal clock input
144283: 09/11/24: Re: Help needed with Quicklogic QL8X12B-1PL68M tools and programmer
144394: 09/12/03: Re: Does Xilinx sync FIFO use dual port memory? Does this affect
144398: 09/12/03: Re: Where to go when Spartan-3A DSP 3400 is full?
144413: 09/12/04: Re: fpga clock resolution
144558: 09/12/14: Re: Best clock output pin in Spartan-3
144572: 09/12/15: Re: Best "bang for buck" Student Starter board for image/video
144647: 09/12/21: Re: Configuring the ML402
144649: 09/12/21: Re: H.264 on Spartan3A DSP
144656: 09/12/21: Re: H.264 on Spartan3A DSP
144685: 09/12/22: Re: Configuring the ML402
144894: 10/01/12: Re: Xilinx ISE 10.1.03
144910: 10/01/14: Re: Which WebPack for old Spartan and Spartan-2?
145140: 10/01/29: Re: In system memory editor of Altera for Xilinx
145142: 10/01/29: Re: Xilinx DCM: Is CLKIN_PERIOD really required
145146: 10/01/29: Re: In system memory editor of Altera for Xilinx
145162: 10/01/29: Re: DPA vs FPGA Security?
145288: 10/02/04: Re: DONE_cycle:6 setting neccessary in bitgen
145315: 10/02/05: Re: Simulating Spartan 3A pins in ltspice
145678: 10/02/18: Re: BRAM16 error
145683: 10/02/18: Re: What is the basis on flip-flops replaced by a latch
145687: 10/02/18: Re: BRAM16 error
145750: 10/02/22: Re: Triming timing constraints from pin ...
145847: 10/02/25: Re: EDK spi ip core
145889: 10/02/26: Re: Frustration with Vendors!
145910: 10/02/27: Re: Frustration with Vendors!
145979: 10/03/02: Re: Tabula. (FPGA start up)
146037: 10/03/04: Re: Ethernet development kit
146263: 10/03/10: Re: Tier Logic introduces the world's first 3D FPGA
146308: 10/03/11: Re: Tier Logic introduces the world's first 3D FPGA
146409: 10/03/16: Re: Xilinx Spartan6 Virtex6 Rollout
146424: 10/03/17: Re: Spartan 3 LVDS - current mode outputs?
146428: 10/03/17: Re: Xilinx Spartan6 Virtex6 Rollout
146449: 10/03/18: Re: Xilinx Spartan6 Virtex6 Rollout
146458: 10/03/18: Re: Xilinx Spartan6 Virtex6 Rollout
146467: 10/03/19: Re: Xilinx Spartan6 Virtex6 Rollout
146531: 10/03/22: Re: Xilinx Spartan6 Virtex6 Rollout
146652: 10/03/25: Re: EMC discussion
146828: 10/03/29: Re: Spartan 3E: MAX_STEPS as a function of CLKIN frequency
146829: 10/03/29: Re: Spartan 3E: MAX_STEPS as a function of CLKIN frequency
146865: 10/03/30: Re: Spartan 6 PLL - Why such a strict input jitter requirement?
146869: 10/03/30: Re: Spartan 6 PLL - Why such a strict input jitter requirement?
146871: 10/03/30: Re: Spartan 6 PLL - Why such a strict input jitter requirement?
146902: 10/04/01: Re: Spartan 3E: MAX_STEPS as a function of CLKIN frequency
146903: 10/04/01: Re: Spartan 6 PLL - Why such a strict input jitter requirement?
146911: 10/04/01: Re: Spartan 3E: MAX_STEPS as a function of CLKIN frequency
147009: 10/04/09: Re: ISE Timing Constraints
147011: 10/04/09: Re: Can Spartan-6 Support M-LVDS ?
147480: 10/04/28: Re: xilinx arm finally announced
147491: 10/04/28: Re: xilinx arm finally announced
152816: 11/10/25: Re: Peter Alfke has passed away
Austin:
113367: 06/12/11: Re: Virtex4 : cleaner signals?
113579: 06/12/17: Re: electrical level conversion
113587: 06/12/17: Re: electrical level conversion
113590: 06/12/17: Re: electrical level conversion
113795: 06/12/21: Re: DCM start up
113803: 06/12/22: Re: Virtex-5 Webpack?
113807: 06/12/22: Re: Simple questions on IDELAYCTRL vs DCM
113808: 06/12/22: Re: Virtex-5 Webpack?
113810: 06/12/22: Re: Virtex-5 Webpack?
113826: 06/12/23: Re: Simple questions on IDELAYCTRL vs DCM
113831: 06/12/23: Re: Simple questions on IDELAYCTRL vs DCM
113930: 06/12/29: Re: assigned a special pins in ISE
113931: 06/12/29: Re: remove logic redundancy
113936: 06/12/29: Re: remove logic redundancy
113964: 06/12/31: Re: hi......
113983: 07/01/01: Re: xilinx xc9536?
114375: 07/01/13: Re: Will FPGAs suit my need?
114616: 07/01/20: Re: suggest me the right fpga
114617: 07/01/20: Re: frequency-Phase Detector?
115646: 07/02/15: Re: Do you like Virtex-5 ?
115721: 07/02/17: Re: Do you like Virtex-5 ?
115843: 07/02/21: Re: Using Xilinx DCM FX output without DLL
115879: 07/02/22: Re: Structured ASIC players
115902: 07/02/24: Re: Interfacing to 10Gig ethernet with Xilinx FPGAs
116193: 07/03/04: Re: Large power planes vs. power islands vs. slits for decoupling
116204: 07/03/04: Re: Large power planes vs. power islands vs. slits for decoupling
116205: 07/03/04: Re: Large power planes vs. power islands vs. slits for decoupling
116856: 07/03/19: Re: Altera introduces Cyclone III devices, ships 65nm
116920: 07/03/20: Re: Why is Xilinx's WebPACK so inferior?
116921: 07/03/20: Re: Why is Xilinx's WebPACK so inferior?
116929: 07/03/20: Off topic: what is the purpoe of XST?
116930: 07/03/20: Re: Why is Xilinx's WebPACK so inferior?
117471: 07/04/01: Re: DCM_STANDBY macro in Virtex-4
Austin Cassidy:
5593: 97/02/27: Instatiation of Xilinx Primitives in VHDL?
Austin Clarkson:
Austin Franklin:
4332: 96/10/17: Re: PCI compliant ?
4333: 96/10/17: Re: Info/opinions wanted for PCI interface in an FPGA
4349: 96/10/18: Re: What are I/O's doing prior to configuration?
4350: 96/10/18: Re: (no subject)
4353: 96/10/18: Re: VHDL for Xilinx designs?
4366: 96/10/20: Re: VHDL for Xilinx designs?
4367: 96/10/21: Has anyone ever used a C -> Xilinx netlister?
4371: 96/10/21: Re: VHDL for Xilinx designs?
4380: 96/10/22: Re: VHDL for Xilinx designs?
4381: 96/10/22: Re: VHDL for Xilinx designs?
4390: 96/10/23: Re: VHDL for Xilinx designs?
4395: 96/10/23: Re: VHDL for Xilinx designs?
4413: 96/10/25: Re: Synplicity vs. FPGA Express
4419: 96/10/26: Re: New user
4427: 96/10/28: Re: Info/opinions wanted for PCI interface in an FPGA
4436: 96/10/29: Re: VHDL for Xilinx designs?
4456: 96/10/31: Re: VHDL for Xilinx designs?
4459: 96/11/01: Re: Info/opinions wanted for PCI interface in an FPGA
4468: 96/11/01: Re: What is the fastest fpga for ...
4477: 96/11/03: Re: XACT under WinNT is very slow
4504: 96/11/06: Re: XACT under WinNT is very slow
4580: 96/11/18: Re: VHDL adder: how do I get at the carry bit?
4884: 96/12/24: Re: XLNX M-1
4885: 96/12/24: Re: PCI Bus Based designs using FPGA's
4931: 97/01/01: NT 4.0, ViewOffice 7.2 and Xilinx tools...96->97 problem...
4941: 97/01/02: Re: NT 4.0, ViewOffice 7.2 and Xilinx tools...96->97 problem...
5083: 97/01/22: Re: Able to reverse a .JED back to logic?
5115: 97/01/24: Re: Altera PCI experience anyone?
5117: 97/01/24: Re: Altera support better than Xilinx
5134: 97/01/25: Re: Altera support better than Xilinx
5161: 97/01/28: Re: Altera support better than Xilinx
5167: 97/01/28: Re: FPGAs with internal Tri-state busses ?
5361: 97/02/11: Re: Using FPGA for PCI interface
5381: 97/02/12: Re: PCI Prototyping board with a XC4013E or XC4013EX
5495: 97/02/20: Re: Xilinx or Altera?
5515: 97/02/21: Re: Xilinx or Altera?
5544: 97/02/24: Re: Reverse Engineering FPGAs
5561: 97/02/25: Re: Xilinx or Altera?
5562: 97/02/25: Re: Xilinx PPR Strategy Tips?
5595: 97/02/27: Opinions on SMT Assembly.Rework soldering tools.... (a bit off topic...)
5673: 97/03/05: Re: Reverse Engineering FPGAs
5663: 97/03/05: Re: viewlogic ...
5772: 97/03/13: Re: Reverse Engineering FPGAs
5910: 97/03/25: Re: Viewlogic Licensing delays?? Anyone?
5967: 97/04/01: Re: XC2018
6011: 97/04/04: Re: PCI Bus Problems
6012: 97/04/04: Re: New Technology
6017: 97/04/05: Re: Pentium Pro Worth it for Altera Max Plus?
6032: 97/04/06: Re: Pentium Pro Worth it for Altera Max Plus?
6037: 97/04/07: Re: PCI Bus Problems
6068: 97/04/09: Re: PCI and DRAM control - Xilinx 4000 -Verilog
6136: 97/04/15: PCI Reset Spec...
6150: 97/04/18: Re: PCI Reset Spec...
6156: 97/04/19: Re: PCI Reset Spec...
6159: 97/04/19: Re: PCI Reset Spec...
6393: 97/05/21: Re: universal PCI-Interface with FPGA?
6394: 97/05/21: Re: VHDL PCI FPGA Implementation
6415: 97/05/22: Re: VHDL PCI FPGA Implementation
6582: 97/06/04: Re: VHDL PCI FPGA Implementation
6602: 97/06/05: Re: VHDL PCI FPGA Implementation
6619: 97/06/06: Re: VHDL PCI FPGA Implementation
6634: 97/06/07: Re: PCI how to
6636: 97/06/08: Re: PCI how to
6664: 97/06/11: Re: PCI how to
6696: 97/06/16: PCMCIA CardBus controller...
6700: 97/06/17: PC Keyboard Controller in a Xilinx...
6825: 97/07/01: Re: Xilinx XACT question
6824: 97/07/01: Xilinx CPLD Tool Flow....
6828: 97/07/01: Does the Xilinx Xchecker work with NT 4.0?
6839: 97/07/01: Re: Does the Xilinx Xchecker work with NT 4.0?
6852: 97/07/02: Re: Xilinx CPLD Tool Flow....
6868: 97/07/04: Re: Does FAQ for this group exist? (empty)
7009: 97/07/22: Re: PCI burst transfers
7010: 97/07/22: Re: PCI burst transfers
7026: 97/07/24: Re: Why fast message delete in this group?
7073: 97/07/29: Re: MEM_CS16 timing on ISA BUS
7087: 97/07/30: Re: PCI burst transfers
7145: 97/08/06: Re: PCI burst transfers
7136: 97/08/05: Re: PCI Interface
7146: 97/08/06: Re: Are 2 PCs better than One?
7153: 97/08/07: Re: Are 2 PCs better than One?
7186: 97/08/12: Re: PCI Interface
7264: 97/08/19: Re: Help!!!!
7265: 97/08/19: Xilinx PCI simulation problem...
7296: 97/08/22: Re: Xilinx PCI simulation problem...
7316: 97/08/25: Re: Xilinx PCI simulation problem...
7352: 97/08/29: Re: Xilinx PCI simulation problem...
7358: 97/08/31: Re: fpga configuration over PCI
7340: 97/08/28: Re: Xilinx PCI simulation problem...
7365: 97/09/02: Re: fpga configuration over PCI
7600: 97/09/25: Another XABEL bug.....
7641: 97/09/30: Problem using FAST config mode with X4kE part?
7672: 97/10/02: Re: Xilinx 5200 I/O Performance
7766: 97/10/13: I looked up Altera in an Italian dictionary.....
7861: 97/10/24: Anyone know of an I2C Controller design for an FPGA?
7936: 97/10/31: Re: Questions about FPGA hardware design
7987: 97/11/05: Re: Help with 64 bit, 33MHz PCI bridge in FPGA...
7989: 97/11/05: Re: Help with 64 bit, 33MHz PCI bridge in FPGA?
8011: 97/11/07: Re: ABEL HDL state machine question
8024: 97/11/08: Re: scsi host adapter
8067: 97/11/13: Re: scsi host adapter
8068: 97/11/13: Re: xilinx xc4kE and PCI LogiCORE
8330: 97/12/09: Re: Xilinx P&R - how does M1 compare to XACT6?
8331: 97/12/09: Re: Xilinx P&R - how does M1 compare to XACT6?
8438: 97/12/15: Re: PCs vs. workstations
8475: 97/12/19: Re: xc4000e tms/tck/tdi/tdo pins
8576: 98/01/10: Re: Xilinx Stock
8587: 98/01/11: Re: Xilinx Stock
8601: 98/01/12: Re: Xilinx Stock
8613: 98/01/13: Re: hdl, schematic, simulation, graphical front ends: (was xilinx stock)
8623: 98/01/14: Re: hdl, schematic, simulation, graphical front ends: (was xilinx stock)
8653: 98/01/16: Re: hdl, schematic, simulation, graphical front ends: (was xilinx stock)
8658: 98/01/17: Re: hdl, schematic, simulation, graphical front ends: (was xilinx stock)
8660: 98/01/17: Re: hdl, schematic, simulation, graphical front ends: (was xilinx stock)
8671: 98/01/19: Re: hdl, schematic, simulation, graphical front ends: (was xilinx stock)
8680: 98/01/19: Re: hdl, schematic, simulation, graphical front ends: (was xilinx stock)
8685: 98/01/20: Re: hdl, schematic, simulation, graphical front ends: (was xilinx stock)
8711: 98/01/21: Re: hdl, schematic, simulation, graphical front ends: (was xilinx stock)
8762: 98/01/24: Re: hdl, schematic, simulation, graphical front ends: (was xilinx stock)
8585: 98/01/11: Re: PCI question
8586: 98/01/11: Re: Xilinx PCI cores
8712: 98/01/21: Re: PCI question
8713: 98/01/21: Re: SDRAM Interface from an FPGA
8881: 98/02/04: Re: VHDL vs schematics
8882: 98/02/04: Re: VHDL vs schematics
8883: 98/02/04: Re: VHDL vs schematics, I vote for VHDL and this is why...
8896: 98/02/05: Off topic...Netiquite and Emoticons WAS Re: VHDL vs schematics, I vote for VHDL and this is why...
9012: 98/02/13: Re: Development Board for ARM/FPGA
9542: 98/03/22: Re: "CORE Competency" ???
9571: 98/03/24: Re: USB bus interface (12 mbit/sec) in an FPGA - how difficult?
9633: 98/03/27: Re: XactStep6 - The cure for a dongle
9733: 98/04/02: Re: XactStep6 - The cure for a dongle
9734: 98/04/02: Re: XactStep6 - The cure for a dongle
9744: 98/04/03: Re: XactStep6 - The cure for a dongle
9763: 98/04/03: Re: XactStep6 - The cure for a dongle
9773: 98/04/04: Re: XactStep6 - The cure for a dongle
9806: 98/04/07: Re: XactStep6 - The cure for a dongle
9807: 98/04/07: Re: XactStep6 - The cure for a dongle
9817: 98/04/07: Re: XactStep6 - The cure for a dongle
9823: 98/04/08: Re: XactStep6 - The cure for a dongle
9829: 98/04/08: Re: XactStep6 - The cure for a dongle
9844: 98/04/09: Re: XactStep6 - The cure for a dongle
9845: 98/04/09: Re: XactStep6 - The cure for a dongle
9851: 98/04/09: Re: XactStep6 - The cure for a dongle
9852: 98/04/09: Re: XactStep6 - The cure for a dongle
9860: 98/04/09: Re: XactStep6 - The cure for a dongle
9861: 98/04/09: Re: XactStep6 - The cure for a dongle
9862: 98/04/09: Re: XactStep6 - The cure for a dongle
9875: 98/04/10: Re: XactStep6 - The cure for a dongle
9885: 98/04/11: Re: XactStep6 - The cure for a dongle
9939: 98/04/15: Re: XactStep6 - The cure for a dongle
9762: 98/04/03: Re: Choosing the right tools and company....
9771: 98/04/04: Re: Xilinx routing optimization?
10044: 98/04/24: Re: Xilinx Serial Proms
10091: 98/04/27: Re: Make a delay in Xilinx FPGAs (Help)?
10221: 98/05/05: Re: 3.3V design conversion
10224: 98/05/05: Re: 3.3V design conversion
10225: 98/05/05: Re: 3.3V design conversion
10344: 98/05/13: Re: Chicken & egg problem in PCI/CardBus designs using FPGA
10345: 98/05/13: Re: Chicken & egg problem in PCI/CardBus designs using FPGA
10348: 98/05/14: Re: Chicken & egg problem in PCI/CardBus designs using FPGA
10349: 98/05/14: Re: Chicken & egg problem in PCI/CardBus designs using FPGA
10350: 98/05/14: Re: Chicken & egg problem in PCI/CardBus designs using FPGA
10358: 98/05/14: Re: Chicken & egg problem in PCI/CardBus designs using FPGA
10359: 98/05/14: Re: Chicken & egg problem in PCI/CardBus designs using FPGA
10361: 98/05/14: Re: Chicken & egg problem in PCI/CardBus designs using FPGA
10362: 98/05/14: Re: Chicken & egg problem in PCI/CardBus designs using FPGA
10636: 98/06/08: Re: ViewDraw Info
10750: 98/06/16: Re: AHDL vs. VHDL vs. Verilog HDl
10751: 98/06/16: Re: floorplanning in xilinx
10759: 98/06/17: Re: AHDL vs. VHDL vs. Verilog HDl
10896: 98/06/29: Re: I squared C on an FPGA
10897: 98/06/29: Re: I squared C on an FPGA
10919: 98/07/01: Re: I squared C on an FPGA
11021: 98/07/11: Re: Consultants
11088: 98/07/18: Re: Floorplanning Intro?....seems to be HDL v schematics sort of ;-)
11089: 98/07/18: Too much advertising in this news group?
11096: 98/07/18: Re: Too much advertising in this news group?
11193: 98/07/24: Re: Too much advertising in this news group?
11194: 98/07/24: Re: Schematic Symbol Generation
11195: 98/07/24: Re: Silicore VHDL 8-bit RISC uC core for FPGA
11206: 98/07/25: Re: Schematic Symbol Generation
11258: 98/07/31: Re: Schematic Symbol Generation
11286: 98/08/02: Re: PCI Core In FPGA
11287: 98/08/02: Re: Symbols, design changes, pin changes
11288: 98/08/02: Re: how much ? prices of Xilinx chips
11312: 98/08/04: Re: PCI Core In FPGA
11341: 98/08/05: Re: PCI Core In FPGA
11342: 98/08/05: Re: Symbols, design changes, pin changes
11353: 98/08/06: Re: PCI Core In FPGA
11365: 98/08/06: Re: PCI Core In FPGA
11375: 98/08/07: Re: Silicore VHDL 8-bit RISC uC core for FPGA
11379: 98/08/07: Re: PCI Core In FPGA
11462: 98/08/17: Re: PCI BUS Master's Performance
11465: 98/08/17: Re: entry level ASIC salary question
11478: 98/08/18: Re: BIG MONEY !!!!!!
11854: 98/09/14: Re: ASIC -> FPGA async issues
11864: 98/09/15: Re: ASIC -> FPGA async issues
11865: 98/09/15: Re: PCI Initiator/Target questions
11873: 98/09/15: Re: ASIC -> FPGA async issues
11988: 98/09/23: Re: How to reduce ringing/ground bounce from FPGA output pin?
12008: 98/09/24: Re: easier testing for PCI cards??
12012: 98/09/24: Re: easier testing for PCI cards??
12042: 98/09/25: Re: CardBus CIS useless?
12058: 98/09/26: Re: CardBus CIS useless?
12129: 98/10/01: Re: Announcement: 200.000 Gates FPGA Prototyping Board
12362: 98/10/10: Re: Xilinx may not support schematics for Virtex?????
12372: 98/10/10: Re: Xilinx may not support schematics for Virtex?????
12376: 98/10/10: Re: Xilinx may not support schematics for Virtex?????
12401: 98/10/11: Re: Xilinx may not support schematics for Virtex?????
12412: 98/10/11: Re: Xilinx may not support schematics for Virtex?????
12471: 98/10/13: Re: Xilinx may not support schematics for Virtex?????
12490: 98/10/13: Re: gray code counter in a Xilinx fpga???
12493: 98/10/13: Re: gray code counter in a Xilinx fpga???
12499: 98/10/14: Re: Viewsim bashing 101
12508: 98/10/14: Re: Viewsim bashing 101
12518: 98/10/14: Re: Viewsim bashing 101
12524: 98/10/14: Re: FOCUS FOCUS FOCUS
12525: 98/10/15: Re: Viewsim bashing 101
12541: 98/10/15: Re: Library of boards
12567: 98/10/16: Re: gray code counter in a Xilinx fpga???
12569: 98/10/16: Re: Xilinx may not support schematics for Virtex?????
12574: 98/10/16: Re: PCI target code
12575: 98/10/17: Re: PCI target code
12602: 98/10/20: Re: optimized fpga
12638: 98/10/21: Re: Xilinx may not support schematics for Virtex?????
12650: 98/10/21: Re: Xilinx may not support schematics for Virtex?????
12712: 98/10/24: Re: Xilinx F1.5/FPGA Express wackiness (& Floorplanner)
13081: 98/11/15: Re: WorkView office Library files need
13082: 98/11/15: Re: WorkView office Library files need
13119: 98/11/16: Re: Modifying Disk serial number in boot sector....anyone have any problems with it?
13205: 98/11/19: Xilinx 5.2/6 tools v M1.5 tools for an XC4013E part.....
13207: 98/11/19: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13229: 98/11/20: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13236: 98/11/20: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13239: 98/11/21: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13249: 98/11/21: Digital Millennium Copyright Act of 1998 (S.2037)
13273: 98/11/23: Anyone use XChecker cable with 3.3V Xilinx parts?
13283: 98/11/24: Re: Anyone use XChecker cable with 3.3V Xilinx parts?
13360: 98/11/30: Re: Xilinx 5.2/6 tools v M1.5 tools for an XC4013E part.....
13371: 98/11/30: Re: Will XILINX survive?
13372: 98/11/30: Re: Will XILINX survive?
13379: 98/11/30: Re: Will XILINX survive?
13380: 98/11/30: Re: Will XILINX survive?
13388: 98/11/30: Re: Will XILINX survive?
13459: 98/12/03: Re: Will XILINX survive?
13496: 98/12/06: Re: A short digression...
13511: 98/12/07: Re: Will XILINX survive?
13512: 98/12/07: Re: Will XILINX survive?
13513: 98/12/07: Re: A short digression...
13415: 98/12/01: Re: Is it normal to have to edit the xnf file???
13430: 98/12/02: Re: Will XILINX survive?
13571: 98/12/10: Re: A short digression...
13582: 98/12/10: Re: A short digression...
13560: 98/12/09: Abel 5 and Windows NT
13570: 98/12/10: Re: Abel 5 and Windows NT
13679: 98/12/18: Anyone simulate a JEDEC PAL file in Viewsim???
13682: 98/12/18: Re: Anyone simulate a JEDEC PAL file in Viewsim???
13721: 98/12/21: Re: Fast *Industrial* 22V10?
13722: 98/12/21: Re: Async Fifo Core or Macro for Xilinx FPGA
13727: 98/12/21: Re: Fast *Industrial* 22V10?
14146: 99/01/15: Re: FPGA/core PCI interface system
14165: 99/01/16: Re: Hard porting to FPGA Express
14177: 99/01/17: Re: FPGA/core PCI interface system
14401: 99/01/28: Off topic DRAM/SIMM question....
14402: 99/01/28: Re: Off topic DRAM/SIMM question....
14403: 99/01/29: Re: Off topic DRAM/SIMM question....
14411: 99/01/29: Re: Off topic DRAM/SIMM question....
14422: 99/01/29: Re: Off topic DRAM/SIMM question....
14445: 99/01/30: Re: Off topic....
14450: 99/01/30: Re: No. of CLBs in Xilinx nearly 100% can't implement.
14451: 99/01/30: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
14467: 99/01/31: Re: Off topic DRAM/SIMM question....
14474: 99/01/31: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
14478: 99/02/01: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
14485: 99/02/01: Re: Off topic DRAM/SIMM question....
14486: 99/02/01: Re: Off topic DRAM/SIMM question....
14498: 99/02/01: Re: Off topic DRAM/SIMM question....
14518: 99/02/03: Re: Off topic DRAM/SIMM question....
14532: 99/02/03: Re: Off topic DRAM/SIMM question....
14533: 99/02/03: Re: Off topic DRAM/SIMM question....
14553: 99/02/04: Re: Off topic DRAM/SIMM question....
14611: 99/02/06: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
14654: 99/02/08: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
14627: 99/02/07: Re: dual port RAM on XC4000
14638: 99/02/08: Re: dual port RAM on XC4000
14759: 99/02/15: Re: Xilinx Spartan and pin-locking
14792: 99/02/17: Re: Xilinx Spartan and pin-locking
14928: 99/02/25: Re: Xilinx ABEL?
14954: 99/02/26: Re: Xilinx ABEL?
15021: 99/03/03: Re: experience with Xilinx 4K series I/Os
15128: 99/03/08: Re: Current State of FPGA-based PCI Interfaces?
15214: 99/03/14: FYI: XC4013EPQ240C and XCS30PQ240C bit stream identical....
15294: 99/03/17: Re: Xilinx Spartan configuration troubles
15310: 99/03/18: Re: Xilinx Spartan configuration troubles
15316: 99/03/18: Re: Xilinx Spartan configuration troubles
15364: 99/03/20: Re: From VHDL to FPGA?
15714: 99/04/09: Anyone using FPGA Express 'Time Tracker' option?
15762: 99/04/12: Viewlogic FPGA Express vs Xilinx FPGA Express....any difference?
15771: 99/04/13: Re: Viewlogic FPGA Express vs Xilinx FPGA Express....any difference?
15857: 99/04/17: Re: Some FPGA questions
15981: 99/04/24: Re: Timing Constraint
16403: 99/05/20: Re: Virtex based PCI cards
16465: 99/05/24: Re: Virtex based PCI cards
16494: 99/05/25: Re: Virtex based PCI cards
16524: 99/05/26: Re: Virtex based PCI cards
16331: 99/05/17: Re: How synthesize tools concern with size of the design?
16724: 99/06/04: Re: Xilinx symbols, Viewlogic
16943: 99/06/18: Re: vhdl and viewlogic problem
16972: 99/06/21: Re: Simple PCI card prototyping.
16986: 99/06/22: Re: Simple PCI card prototyping.
17008: 99/06/23: Re: Simple PCI card prototyping.
17063: 99/06/28: Re: 100 Billion operations per sec.!
17151: 99/07/04: Re: Simple PCI card prototyping.
17192: 99/07/08: Re: 100 Billion operations per sec.!
17193: 99/07/08: Re: Simple PCI card prototyping.
17191: 99/07/07: Re: PCI interface
17216: 99/07/09: Re: PCI interface
17226: 99/07/12: Re: PCI interface
17390: 99/07/23: Re: Solaris vs. NT
17894: 99/09/16: Re: xilinx v2.1i
17910: 99/09/16: Re: simple VHDL?
17915: 99/09/16: Re: Xilinx XC4005E
17969: 99/09/20: Re: xilinx v2.1i
17983: 99/09/21: Re: Back engineer xc3000
18052: 99/09/26: Re: Looking for substitute for XC17*** Xilinx Prom
18128: 99/10/02: Re: Evaluation/Development Board with SA-11XX Processor
18164: 99/10/04: Re: ABEL for CPLD Design
18186: 99/10/06: Re: Xilinx post route simulation
18197: 99/10/07: Re: Xilinx post route simulation
18410: 99/10/23: Re: Xilinx Orientation Question
18446: 99/10/25: Re: Synplify / LPM?
18463: 99/10/26: Xilinx BGA pinout issue.....
18481: 99/10/27: Re: Xilinx BGA pinout issue.....
18502: 99/10/27: Re: schematics ==> www
18511: 99/10/28: Re: schematics ==> www
18548: 99/10/30: Re: StateCAD versus Viewdraw
18689: 99/11/08: Downloading Xilinx FPGA with just .bit file???
18697: 99/11/08: Re: Downloading Xilinx FPGA with just .bit file???
18809: 99/11/17: Re: implementing TCP/IP on PLD
18810: 99/11/17: Re: implementing TCP/IP on PLD
18826: 99/11/18: Re: How to use GSR-net in Virtex?
18854: 99/11/19: Re: How to use GSR-net in Virtex?
18863: 99/11/19: Re: How to use GSR-net in Virtex?
18867: 99/11/19: Re: How to use GSR-net in Virtex?
18868: 99/11/19: Re: How to use multiple resets?
18869: 99/11/19: Re: How to use GSR-net in Virtex?
18888: 99/11/20: Xilinx FPGA Editor...does it really work?
18900: 99/11/20: Re: Xilinx FPGA Editor...does it really work
18901: 99/11/20: Re: Xilinx FPGA Editor...does it really work?
18902: 99/11/20: Re: Xilinx FPGA Editor...does it really work?
18953: 99/11/22: Xilinx changed the pinout of the download cable?
18970: 99/11/23: Re: VHDL vs. schematic entry
19071: 99/11/26: Xilinx FPGA Editor guessing games solved!
19074: 99/11/27: Re: Xilinx FPGA Editor guessing games solved!
19082: 99/11/28: Re: Xilinx FPGA Editor guessing games solved!
19167: 99/12/03: Re: Command line for FPGA Express
19191: 99/12/04: Re: Command line for FPGA Express
19340: 99/12/15: Re: State machine ok with binary encoding but unstable with one hot encoding
19341: 99/12/15: Re: State machine ok with binary encoding but unstable with one hot encoding
19350: 99/12/15: Re: State machine ok with binary encoding but unstable with one hot encoding
19355: 99/12/15: Re: State machine ok with binary encoding but unstable with one hot encoding
19545: 99/12/30: Re: PCI slot 3.3V pins.
19556: 99/12/30: Re: PCI slot 3.3V pins.
19865: 00/01/14: Re: PCI Bus Problems with Burst Transfers
19942: 00/01/19: Re: Patent licenses for circuits in FPGA
19943: 00/01/19: looping FIFO?
19947: 00/01/20: Re: looping FIFO?
19948: 00/01/20: Re: looping FIFO?
19974: 00/01/20: Re: looping FIFO?
20290: 00/02/04: Re: Anyone changed an NT disk serial number?
20356: 00/02/07: How to get Synplicity to NOT use Global Clock for Virtex...
20357: 00/02/07: Re: How to get Synplicity to NOT use Global Clock for Virtex...
20779: 00/02/22: Re: Viewlogic 4 and XACT6.1 - any good for XC4k ??
20780: 00/02/22: Re: Viewlogic 4 and XACT6.1 - any good for XC4k ??
20913: 00/02/27: Xilinx 1802/4 SPROMs....anyone get them to actually work?
20914: 00/02/27: Re: Xilinx 1802/4 SPROMs....anyone get them to actually work?
20931: 00/02/29: Re: Xilinx 1802/4 SPROMs....anyone get them to actually work? - FIXED!!!
21025: 00/03/03: Re: Xilinx 1802/4 SPROMs....anyone get them to actually work? - FIXED!!!
21345: 00/03/17: Re: Virtex DLL inoperability
22606: 00/05/13: Re: virtex configuration with synplify
22946: 00/06/05: Re: PLA to ABEL converter?
23042: 00/06/10: Re: XILINX RAM Useless
23102: 00/06/14: Re: PCI for a fpga board
23114: 00/06/14: Re: PCI for a fpga board
23142: 00/06/15: Re: PCI for a fpga board
23208: 00/06/17: Re: PCI for a fpga board
23432: 00/06/25: Re: Defining a reset concept for VirtexE
23449: 00/06/26: Re: Defining a reset concept for VirtexE
23476: 00/06/27: Re: Defining a reset concept for VirtexE
23507: 00/06/28: Re: Defining a reset concept for VirtexE
24210: 00/07/30: Re: Viewlogic Licencing
24242: 00/07/31: QuickLogic PCI/FPGA chip (QL5064)...experiences?
24262: 00/08/02: Re: QuickLogic PCI/FPGA chip (QL5064)...experiences?
24310: 00/08/03: Re: QuickLogic PCI/FPGA chip (QL5064)...experiences?
24329: 00/08/04: Re: Viewlogic Licensing
24330: 00/08/04: Verilog multiplier in Xilinx...
24350: 00/08/04: Re: Verilog multiplier in Xilinx...
24377: 00/08/05: Re: Verilog multiplier in Xilinx...
24389: 00/08/06: Re: Help! Troubles using async FIFO cores in Virtex
24397: 00/08/06: Re: Help! Troubles using async FIFO cores in Virtex
24398: 00/08/06: Re: Circuit Drawing
24399: 00/08/06: Re: Circuit Drawing
24513: 00/08/11: Re: Xilinx, XVC300, 18V02
24535: 00/08/12: Re: XC2S200 / Master Serial / PCI system
24536: 00/08/12: Re: Verilog multiplier in Xilinx...
24771: 00/08/18: Re: Xilinx design flow with Mentor
24803: 00/08/18: Re: Fully constrained designs...
24904: 00/08/21: Re: Verilog multiplier in Xilinx...
24908: 00/08/22: Re: Verilog multiplier in Xilinx...
24934: 00/08/22: Re: Fully constrained designs...
24942: 00/08/22: Re: Fully constrained designs...
25201: 00/08/30: Re: Xilinx and CD databooks (rant)
25256: 00/09/02: Re: Xilinx block Ram Verilog model
25261: 00/09/03: Re: Xilinx block Ram Verilog model
25558: 00/09/14: Re: hardware compatibility and patent infringement
26201: 00/10/08: Re: program Xilinx FPGAs via JTAG
26202: 00/10/08: Re: multi-input adders in virtex ?
26203: 00/10/08: Re: multi-input adders in virtex ?
26226: 00/10/09: Re: multi-input adders in virtex ?
26419: 00/10/15: Re: PCI host
26548: 00/10/20: Re: Very Lucrative FPGA Jobs
26635: 00/10/23: Re: Very Lucrative FPGA Jobs
26650: 00/10/23: Re: Very Lucrative FPGA Jobs
26807: 00/10/30: Re: Undergraduate PLD Studies
26993: 00/11/07: Re: ViewLogic ViewDraw questions
26995: 00/11/07: Re: level shifting buffers ??
27031: 00/11/08: Re: ViewLogic ViewDraw questions
27347: 00/11/19: Re: Using FPGA as PCI target
27348: 00/11/19: Real size of the Virtex-E parts...
27527: 00/11/27: Re: Fifo design problem
27626: 00/11/30: Re: Synplify Benchmarks
27637: 00/11/30: Re: Synplify Benchmarks
27738: 00/12/05: Re: Issues with Spartan II
28129: 00/12/22: Synplicity and multiple input IOB flops...how to specify which one goes in the IOB?
28160: 00/12/23: Re: Synplicity and multiple input IOB flops...how to specify which one goes in the IOB?
28161: 00/12/23: Re: Synplicity and multiple input IOB flops...how to specify which one goes in the IOB?
28162: 00/12/23: Re: Synplicity and multiple input IOB flops...how to specify which one goes in the IOB?
28184: 00/12/25: Re: Synplicity and multiple input IOB flops...how to specify which one goes in the IOB?
28689: 01/01/21: Is the Xilinx XCV200 in the FG456 package cavity UP or DOWN?
28701: 01/01/21: Re: CMOS or TTL
28713: 01/01/22: Re: CMOS or TTL
28735: 01/01/22: Re: Is the Xilinx XCV200 in the FG456 package cavity UP or DOWN?
29246: 01/02/11: Re: Virtex XCV2000E-6 BG560C - Orcad capture symbol
29332: 01/02/14: Re: Virtex XCV2000E-6 BG560C - Orcad capture symbol
29756: 01/03/07: Re: How to get Xilinx FPGA demo board?
29948: 01/03/19: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
30002: 01/03/20: Re: Book on FPGA-Design with Xilinx chips
30058: 01/03/22: Is the carry logic for Virtex included in PAR timing report/check?
30069: 01/03/22: Re: Is the carry logic for Virtex included in PAR timing report/check?
30089: 01/03/22: Re: Is the carry logic for Virtex included in PAR timing report/check?
30097: 01/03/22: Re: Is the carry logic for Virtex included in PAR timing report/check?
30125: 01/03/23: Re: Software Pundits ASIC/FPGA
30235: 01/03/28: Re: PCI-X core
30242: 01/03/29: Re: Programmble Logic Sequencer
30257: 01/03/29: Re: Programmble Logic Sequencer
30273: 01/03/30: Re: Programmble Logic Sequencer
30741: 01/04/26: Re: Configuration via PCI JTAG
30780: 01/04/28: Re: C++ To Gates
30787: 01/04/28: Re: C++ To Gates
30798: 01/04/29: Re: C++ To Gates
30799: 01/04/29: Re: C++ To Gates
30801: 01/04/29: Re: C++ To Gates
30845: 01/05/01: Gates to Hardware...
30865: 01/05/01: Re: C++ To Gates
30909: 01/05/03: Re: ccd imaging with fpga
31270: 01/05/16: Re: PCI The Real Hardware
31437: 01/05/23: Re: FPGA consultant needed
31510: 01/05/28: Re: FPGA consultant needed
31590: 01/05/30: Re: FPGA consultant needed
31609: 01/05/31: Re: Xilinx XC4010E Problem
31612: 01/05/31: Re: Spartan2 PCI-IP Core @ power-up
31628: 01/05/31: Re: Xilinx XC4010E Problem
31632: 01/05/31: Re: Xilinx webpack and modelsim
31650: 01/06/01: Re: Xilinx webpack and modelsim
31670: 01/06/02: Re: Spartan2 PCI-IP Core @ power-up
31671: 01/06/02: Re: Help in FIFO design
31679: 01/06/02: Re: Xilinx webpack and modelsim
31693: 01/06/03: Re: Spartan2 PCI-IP Core @ power-up
31772: 01/06/05: Re: Xilinx Configuration Bitstream
31775: 01/06/05: Re: Help in FIFO design
31778: 01/06/05: Re: one state machine
31780: 01/06/05: Re: Help in FIFO design
31781: 01/06/05: Re: one state machine
31782: 01/06/05: Re: one state machine
31787: 01/06/05: Re: Help in FIFO design
31788: 01/06/05: Re: Help in FIFO design
31806: 01/06/06: Re: one state machine
31807: 01/06/06: Re: Help in FIFO design
31823: 01/06/06: Re: one state machine
31826: 01/06/06: Re: one state machine
31827: 01/06/06: Re: one state machine
31838: 01/06/06: Re: one state machine
31844: 01/06/06: Re: Help in FIFO design
31855: 01/06/06: Re: Help in FIFO design
31856: 01/06/06: Re: Help in FIFO design
31858: 01/06/06: Re: one state machine
31872: 01/06/07: Re: one state machine
31873: 01/06/07: Re: Xilinx Configuration Bitstream
31886: 01/06/07: Re: Help in FIFO design
31997: 01/06/10: Re: one state machine
32008: 01/06/10: Re: one state machine
32009: 01/06/10: Re: one state machine
32010: 01/06/10: Re: one state machine
32012: 01/06/10: Re: XC4005XL is it a modern chip?
32039: 01/06/11: Re: one state machine
32434: 01/06/26: Re: Stupid Xilinx Patent
32442: 01/06/26: Re: Stupid Xilinx Patent
32444: 01/06/26: Re: IOB FF in Synplicity
32476: 01/06/27: Re: Stupid Xilinx Patent
32477: 01/06/27: Re: Stupid Xilinx Patent
33730: 01/08/02: Re: finite defect statistics
33731: 01/08/03: Re: finite defect statistics
33794: 01/08/05: Re: finite defect statistics
33927: 01/08/08: Re: LUT as Buffer?
33928: 01/08/08: Re: PCI Postcode Display
33939: 01/08/09: Re: LUT as Buffer?
33964: 01/08/09: Re: LUT as Buffer?
33965: 01/08/09: Re: PCI Postcode Display
33968: 01/08/09: Re: PCI Postcode Display
34216: 01/08/16: Re: Slowing PCI for FPGA
34217: 01/08/16: Re: Slowing PCI for FPGA
34218: 01/08/16: Re: Slowing PCI for FPGA
34238: 01/08/16: Re: PCI Postcode Display
34296: 01/08/19: Re: PCI Postcode Display
34340: 01/08/21: Re: Slowing PCI for FPGA
34386: 01/08/23: Re: Slowing PCI for FPGA
34423: 01/08/24: Re: Slowing PCI for FPGA
34436: 01/08/24: Re: Slowing PCI for FPGA
34456: 01/08/25: Re: Slowing PCI for FPGA
34460: 01/08/25: Re: Slowing PCI for FPGA
34472: 01/08/27: Re: Slowing PCI for FPGA
34534: 01/08/28: Re: Defending Austin Franklin
34548: 01/08/29: Re: Defending Austin Franklin
34549: 01/08/29: Re: Version Control
34573: 01/08/29: Re: Version Control
34596: 01/08/30: Re: Version Control
34610: 01/08/30: Re: Defending Austin Franklin
34647: 01/08/31: Re: Defending Austin Franklin
35138: 01/09/23: Re: problem with location constraints in Verilog
35353: 01/09/30: Xchecker and NT???
35518: 01/10/09: Re: FPGA reset
35534: 01/10/09: Re: Synplicity/Leonardo License Agreement Information
36469: 01/11/09: Virtex 2 parts availability???
36496: 01/11/09: Re: Virtex 2 parts availability???
36497: 01/11/09: Re: Virtex 2 parts availability???
36571: 01/11/12: Re: Virtex 2 parts shipping = receiving
36588: 01/11/12: Re: Virtex 2 parts shipping = receiving
36663: 01/11/14: Re: 'Timing' simulation in ModelSIM
36737: 01/11/18: Xilinx Fpga Editor support for Virtex 2...does it exist in 3.x? How about 4.x?
36741: 01/11/18: Re: Xilinx Fpga Editor support for Virtex 2...does it exist in 3.x? How about 4.x?
36806: 01/11/20: Re: Xilinx Fpga Editor support for Virtex 2...does it exist in 3.x? How about 4.x?
37176: 01/12/03: Re: PCI card - 2 layers versus four layers
37194: 01/12/03: Re: PCI card - 2 layers versus four layers
37241: 01/12/04: Re: Crossing a clock domain
37661: 01/12/18: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37666: 01/12/18: Re: Spartan-IIE schematic symbol?
37667: 01/12/18: Re: Kindergarten Stuff
37672: 01/12/18: Re: Kindergarten Stuff
37680: 01/12/18: Re: You take the low road and I'll ......
37732: 01/12/19: Re: Default Should Be "Inputs and Outputs" For IOBs
37733: 01/12/19: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37734: 01/12/19: Re: You take the low road and I'll ......
37743: 01/12/19: Re: Default Should Be "Inputs and Outputs" For IOBs
37745: 01/12/19: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu < 7 ns requirement?
37746: 01/12/19: Re: FPGA-Conversion. IP Cores
37761: 01/12/19: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37762: 01/12/19: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37788: 01/12/20: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37851: 01/12/21: Re: You take the low road and I'll ......
37852: 01/12/21: Re: Defauolt Should Be "Inputs and Outputs" For IOBs - please respond???
37880: 01/12/22: Re: Defauolt Should Be "Inputs and Outputs" For IOBs - please respond???
37882: 01/12/22: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu < 7 ns requirement?
37892: 01/12/23: Re: Default Should Be "Inputs and Outputs" For IOBs - please respond???
38068: 02/01/03: Re: PCI Solution: LogiCore?
38084: 02/01/04: Re: PCI Solution: LogiCore?
40618: 02/03/11: Article in March Embedded Systems - "The Death of Hardware Engineering"...
40851: 02/03/16: Re: just bought...
40862: 02/03/16: Re: just bought...
40886: 02/03/17: Re: just bought...
40903: 02/03/17: VERY OT - Re: just bought...
41090: 02/03/20: Re: virtex 2 orcad symbols?
41521: 02/04/01: Re: PCI Compliance..
42698: 02/05/01: Spartan outputs to 3.3V DRAMs...
42699: 02/05/01: Re: Spartan outputs to 3.3V DRAMs...
42700: 02/05/01: Re: Spartan outputs to 3.3V DRAMs...
42719: 02/05/01: Re: Spartan outputs to 3.3V DRAMs...
42729: 02/05/01: Re: Spartan outputs to 3.3V DRAMs...
43189: 02/05/15: Re: PCI Board Project
43259: 02/05/17: Re: PCI Board Project
43260: 02/05/17: Re: PCI target with FPGA question
43276: 02/05/17: Re: PCI Board Project
43342: 02/05/19: Re: PCI Board Project
43445: 02/05/21: Re: PCI Board Project
43454: 02/05/21: Re: Synchronous Single Clock Designs
43757: 02/05/31: Re: Director of FPGA Design - New York City
44452: 02/06/20: Re: 5V tolerance
45681: 02/08/01: Re: VirtexE : OrCAD capture part symbol
45750: 02/08/03: Re: PCI Interrupt latency
46044: 02/08/15: Re: Xilinx tools: which one? Esp. schematic
46053: 02/08/15: Re: 2 questions using Synplify Pro.
46062: 02/08/15: Re: Problem with Xilinx mapper
46120: 02/08/19: Re: xilinx pci troubles with flakey host initiator
46121: 02/08/19: Re: Xilinx tools: which one? Esp. schematic
46126: 02/08/20: Re: I2C License
46149: 02/08/20: Re: I2C License
46193: 02/08/21: Re: Xilinx tools: which one? Esp. schematic
46218: 02/08/21: Re: Xilinx tools: which one? Esp. schematic
46238: 02/08/22: Re: I2C License
46570: 02/09/03: Re: Hardware Code Morphing?
46572: 02/09/03: Re: Hardware Code Morphing?
46585: 02/09/03: Re: C/C++ to Verilog/VHDL ?!
46781: 02/09/08: Re: OrCAD 9.2 Capture Part Library For SpartanXL&18VXX
46912: 02/09/11: Re: Clocking an FPGA with the PCI clock
46921: 02/09/11: Re: Clocking an FPGA with the PCI clock
47714: 02/10/02: Re: C\C++ to VHDL Converter
47716: 02/10/02: Re: xilinx free logic analyzer?
47930: 02/10/07: Re: C\C++ to VHDL Converter
48277: 02/10/15: Re: FPGA breadboard with a SmartMedia Card to store the bit file.
48528: 02/10/19: Re: FPGA breadboard with a SmartMedia Card to store the bit file.
48534: 02/10/19: Re: FPGA breadboard with a SmartMedia Card to store the bit file.
48876: 02/10/25: Re: PCI burst reads w/ Spartan
48931: 02/10/27: Re: A PCI Data Aqcuisition Card Design
49014: 02/10/29: Re: PCI ARBITER
49180: 02/11/04: Re: C\C++ to VHDL Converter
49188: 02/11/04: Re: tips for cutting down on slice usage in a VirtexII
49206: 02/11/05: Re: C\C++ to VHDL Converter
49229: 02/11/05: Re: C\C++ to VHDL Converter
49458: 02/11/12: Re: C\C++ to VHDL Converter
49566: 02/11/15: Re: C\C++ to VHDL Converter
49579: 02/11/15: Re: C\C++ to VHDL Converter
49586: 02/11/15: Re: DLL again :-)
49594: 02/11/16: Re: DLL again :-)
49599: 02/11/16: Re: DLL again :-)
49774: 02/11/20: Re: C\C++ to VHDL Converter
49802: 02/11/21: Re: C\C++ to VHDL Converter
49875: 02/11/23: Re: C\C++ to VHDL Converter
50059: 02/11/29: Re: Spartan-II 2S200 PCI Board
50072: 02/11/30: Re: Spartan-II 2S200 PCI Board
50073: 02/11/30: Re: Spartan-II 2S200 PCI Board
50345: 02/12/09: Re: FPGA/PCI on low budget
50472: 02/12/11: Re: FPGA/PCI on low budget
50494: 02/12/11: Re: FPGA/PCI on low budget
50496: 02/12/11: Re: FPGA/PCI on low budget
50525: 02/12/11: Re: FPGA/PCI on low budget
50643: 02/12/15: Re: what makes an implementation a patent?
50644: 02/12/15: Re: what makes an implementation a patent?
50646: 02/12/15: Re: what makes an implementation a patent?
50664: 02/12/16: Re: what makes an implementation a patent?
50665: 02/12/16: Re: Virtex2Pro question
50670: 02/12/16: Re: what makes an implementation a patent?
50695: 02/12/17: Re: what makes an implementation a patent?
50875: 02/12/21: Re: FPGA Supercomputing opportunity
50926: 02/12/23: Re: serdes
50934: 02/12/23: Re: serdes
50935: 02/12/23: Re: serdes
51050: 02/12/28: Re: FPGA accelerated FPGA/ASIC tools
51074: 02/12/30: Re: BP programmer questions, prices, alternatives
51075: 02/12/30: Re: BP programmer questions, prices, alternatives
51082: 02/12/30: Re: BP programmer questions, prices, alternatives
51193: 03/01/06: Re: BP programmer questions, prices, alternatives
51196: 03/01/06: Re: BP programmer questions, prices, alternatives
51295: 03/01/09: Re: FPGA accelerated FPGA/ASIC tools
51398: 03/01/13: Re: SChematic design approach compared to VHDL entry approach
51464: 03/01/14: Re: SChematic design approach compared to VHDL entry approach
51465: 03/01/14: Re: SChematic design approach compared to VHDL entry approach
51476: 03/01/14: Re: SChematic design approach compared to VHDL entry approach
51501: 03/01/14: Re: SChematic design approach compared to VHDL entry approach
51506: 03/01/15: Re: SChematic design approach compared to VHDL entry approach
51507: 03/01/15: Re: Spartan II found on Ebay
51535: 03/01/15: Re: Schematic design approach compared to VHDL entry approach
51539: 03/01/16: Re: Schematic design approach compared to VHDL entry approach
51568: 03/01/16: Re: Schematic design approach compared to VHDL entry approach
51572: 03/01/16: Re: SChematic design approach compared to VHDL entry approach
51618: 03/01/17: PCI Device/Vendor resource off line now...
51619: 03/01/17: Re: Schematic design approach compared to VHDL entry approach
51620: 03/01/17: Re: Schematic design approach compared to VHDL entry approach
51651: 03/01/17: Re: XST vs Synplify observations
51652: 03/01/17: Re: Schematic design approach compared to VHDL entry approach
51670: 03/01/18: Re: Schematic design approach compared to VHDL entry approach
51671: 03/01/18: Re: Schematic design approach compared to VHDL entry approach
51691: 03/01/19: Re: Schematic design approach compared to VHDL entry approach
51693: 03/01/19: Re: PLX PCI DMA address
51696: 03/01/19: Re: PLX PCI DMA address
51697: 03/01/19: Re: Schematic design approach compared to VHDL entry approach
51698: 03/01/19: Re: SChematic design approach compared to VHDL entry approach
51718: 03/01/20: Re: Schematic design approach compared to VHDL entry approach
51720: 03/01/20: Re: Schematic design approach compared to VHDL entry approach
51748: 03/01/20: Re: Schematic design approach compared to VHDL entry approach
51750: 03/01/21: Re: Schematic design approach compared to VHDL entry approach
51751: 03/01/21: Re: Schematic design approach compared to VHDL entry approach
51869: 03/01/24: Re: SChematic design approach compared to VHDL entry approach
51871: 03/01/24: Re: FLEXlm
52079: 03/01/30: Re: SChematic design approach compared to VHDL entry approach
52080: 03/01/30: Re: Schematic design approach compared to VHDL entry approach
52114: 03/01/31: Re: PCI protocol - assigning an address to my device
52270: 03/02/05: Re: PCI protocol - assigning an address to my device
52346: 03/02/07: Re: Contract Rates?
53693: 03/03/20: Using DDR placed on the PCB with a Virted II...
53729: 03/03/20: Re: Using DDR placed on the PCB with a Virted II...
73036: 04/09/11: Need some help with some technical claims...
73048: 04/09/12: Re: Need some help with some technical claims...
73049: 04/09/12: Re: Need some help with some technical claims...
73063: 04/09/13: Re: Need some help with some technical claims...
73064: 04/09/13: Re: Need some help with some technical claims...
73162: 04/09/14: Re: Need some help with some technical claims...
73192: 04/09/15: Re: Need some help with some technical claims...
84708: 05/05/24: Re: VHDL vs. Schematic Capture
84731: 05/05/25: Re: VHDL vs. Schematic Capture
84747: 05/05/25: Re: VHDL vs. Schematic Capture
84777: 05/05/26: Re: VHDL vs. Schematic Capture
85334: 05/06/07: Re: VHDL vs. Schematic Capture
85565: 05/06/10: Re: computer upgrade time.
85596: 05/06/11: Synplify vs XST...
85606: 05/06/11: Re: OrCAD Symbol For Xilinx V2PRO
85609: 05/06/12: Re: OrCAD Symbol For Xilinx V2PRO
85622: 05/06/12: Re: OrCAD Symbol For Xilinx V2PRO
85625: 05/06/12: Re: Synplify vs XST...
85628: 05/06/12: Re: Synplify vs XST...
85630: 05/06/12: Re: Gated clock question
85672: 05/06/13: Re: Synplify vs XST...
86103: 05/06/21: Re: Ideal CPU for FPGA?
86153: 05/06/22: Re: Ideal CPU for FPGA?
89611: 05/09/20: XST equivelent for Synplify "synthesis syn_preserve = 1"
89617: 05/09/20: Re: XST equivelent for Synplify "synthesis syn_preserve = 1"
89642: 05/09/21: Re: XST equivelent for Synplify "synthesis syn_preserve = 1"
89689: 05/09/22: Re: Reprogramming FPGA over PCI???
90941: 05/10/25: Anyone have experience with Linux in V2Pro?
Austin Lesea:
21708: 00/03/29: Re: FPGA & single point failure
21835: 00/04/03: Re: Virtex DLL Spread-spectrum clock sensitivity
21873: 00/04/04: Re: Virtex DLL Spread-spectrum clock sensitivity
22078: 00/04/19: Re: Virtex E Pads Output Impedance
23323: 00/06/22: Re: 500 million transistor FPGA's
23339: 00/06/22: Re: 500 million transistor FPGA's
23457: 00/06/26: Re: 500 million transistor FPGA's
23527: 00/06/28: Re: Virtex power estimation
23734: 00/07/06: Re: IBIS model for the XCV400E
23988: 00/07/19: Re: FPGAs in AC Magnetic Field
23808: 00/07/10: Re: XC2018 development system xact5 or xact6 sale?
24804: 00/08/18: Re: multiplying DLL in Virtex
25085: 00/08/25: Re: largest fpga in the industry
25167: 00/08/29: Re: largest fpga in the industry
25228: 00/08/31: Re: Large amout of Interconnect between FPGAs
25164: 00/08/29: Re: availability of Spartan II
25375: 00/09/08: Re: 3.3/2.5 voltage regulators
25421: 00/09/11: Re: 3.3/2.5 voltage regulators
25423: 00/09/11: Re: Numerically-Controlled Crystal Oscillator (NCXO) or
25422: 00/09/11: Re: 3.3/2.5 voltage regulators
25443: 00/09/11: Re: Numerically-Controlled Crystal Oscillator (NCXO) or
25483: 00/09/12: Re: Numerically-Controlled Crystal Oscillator (NCXO) or
25617: 00/09/15: Re: 3.3/2.5 voltage regulators
25618: 00/09/15: Re: Numerically-Controlled Crystal Oscillator (NCXO) or
25715: 00/09/18: Re: 3.3/2.5 voltage regulators
25716: 00/09/18: Re: Simon,Floating Inputs
25738: 00/09/18: Re: Safe voltage regulator for Xilinx XC2S150 part?
25343: 00/09/07: Re: 3.3/2.5 voltage regulators
25356: 00/09/07: Re: 3.3/2.5 voltage regulators
25368: 00/09/08: Re: 3.3/2.5 voltage regulators
25952: 00/09/27: Re: Simon , decoupling caps
26147: 00/10/05: Re: DLL unlocking
26233: 00/10/09: Re: Simon , decoupling caps
26338: 00/10/12: Re: Xilinx and CD databooks (rant) re: startup I
26452: 00/10/16: Re: Xilinx and CD databooks (rant)
27042: 00/11/08: Re: PLL vs DLL
27053: 00/11/08: Re: PLL vs DLL
27420: 00/11/21: Re: Spartan 3.3V Driving 5v input tristate + pull up problem...
27523: 00/11/27: Re: What is the fundamental limitation factor for FPGA clock rate
27525: 00/11/27: Re: Power consumption FPGA...
27550: 00/11/28: Re: hard or soft core for FPGA?
27561: 00/11/28: Re: PLL vs DLL
27571: 00/11/28: Re: Virtex II DLL at 311MHz on XCV300e-8ES
27594: 00/11/29: Re: PLL vs DLL
27799: 00/12/08: Re: Altera MAX+PlusII v.s. Xilinx Foundation
27810: 00/12/09: Re: Linear Regulator troubles
27820: 00/12/10: Re: Linear Regulator troubles
27821: 00/12/10: Re: Linear Regulator troubles
28074: 00/12/20: Re: Reverse-engineering FPGA's
28266: 01/01/04: Re: Spartan-II DLL Usage
28307: 01/01/05: Re: Spartan-II DLL Usage
28308: 01/01/05: Re: Spartan-II DLL Usage
28348: 01/01/08: Re: Spartan-II DLL Usage
28439: 01/01/12: Re: Spartan-II DLL Usage
28492: 01/01/15: Re: Virtex-II officially launched
28511: 01/01/15: Re: Virtex-II officially launched
28577: 01/01/17: Re: Virtex-II officially launched
28578: 01/01/17: Re: Virtex-II officially launched
28595: 01/01/17: Re: Virtex-II officially launched
28649: 01/01/19: Re: Virtex-II officially launched
28651: 01/01/19: Re: FPGAs with a partial reconfiguration
28703: 01/01/21: Re: Virtex-II officially launched
28704: 01/01/21: Re: Is the Xilinx XCV200 in the FG456 package cavity UP or DOWN?
28715: 01/01/22: Re: Virtex-II officially launched
28718: 01/01/22: Re: Is the Xilinx XCV200 in the FG456 package cavity UP or DOWN?
28720: 01/01/22: Re: Is the Xilinx XCV200 in the FG456 package cavity UP or DOWN?
28729: 01/01/22: Re: Virtex-II officially launched
28756: 01/01/23: Re: Xilinx XCell is not on-line?
28766: 01/01/23: Re: Virtex-II officially launched
28811: 01/01/24: Re: Encryption is supported in new Virtex II but.....
28823: 01/01/25: Re: Can Virtex-II be programmed with MultiLINX?
28824: 01/01/25: Re: Encryption is supported in new Virtex II but.....
28948: 01/01/30: Re: Can Virtex-II be programmed with MultiLINX?
28985: 01/01/31: Re: Can Virtex-II be programmed with MultiLINX?
28998: 01/02/01: Re: Spartan 2 DLL
29076: 01/02/05: Re: Spartan 2 DLL
29207: 01/02/09: DLL jitter "bake-off" vs. PLL
29521: 01/02/24: Re: Spartan II power
29547: 01/02/26: Re: Spartan II power
29548: 01/02/26: Re: Spartan II power
29549: 01/02/26: Re: Spartan II power
29565: 01/02/26: Re: Virtex USB solution
29595: 01/02/27: Re: Spartan II power
29604: 01/02/28: Re: Spartan II power
29631: 01/03/02: Re: What about speed-grade?
29741: 01/03/06: Re: Bad Xilinx bitstream=big bang?
29742: 01/03/06: Re: Again Spartan II power
29743: 01/03/06: Re: Is there any Virtex-II Evaluation Board?
29754: 01/03/07: Re: SRAM fpga cell
29767: 01/03/08: Re: SRAM fpga cell
29778: 01/03/08: Re: Fanout
29828: 01/03/12: Re: Again Spartan II power
29950: 01/03/19: Re: Spartan-II VREF and VCCO
29970: 01/03/19: Re: Spartan-II VREF and VCCO
30007: 01/03/20: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
30021: 01/03/20: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
30071: 01/03/22: Globals are plenty fast
30072: 01/03/22: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
30073: 01/03/22: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
30190: 01/03/27: Re: Powerup problems with XC9500XL
30245: 01/03/29: Re: Recommended Oscillators for DLL's at 25 MHz
30283: 01/03/30: Re: FPGA V CPLD
30346: 01/04/03: Re: pseudo random numbers
30349: 01/04/03: Re: pseudo random numbers
30371: 01/04/04: Re: pseudo random numbers
30488: 01/04/10: Re: Why FPGA/CPLDs draw a lot current?
30539: 01/04/12: Re: Thank you very much.
30598: 01/04/18: Re: looking for comment on implementation
30622: 01/04/19: Re: Voltage supply reduction for low power in FPGAs.
30679: 01/04/23: Re: Virtex-E & 5V tolerance
30698: 01/04/24: Re: Any good sources for digital rf processing ?
30738: 01/04/26: Re: clock to pad timing
30823: 01/04/30: Re: Shannon Capacity
30828: 01/04/30: Re: High resolution time measurement?
30855: 01/05/01: Re: Shannon Capacity
30861: 01/05/01: Re: High resolution time measurement?
30892: 01/05/02: Re: Shannon Capacity
30893: 01/05/02: Re: Shannon Capacity
30894: 01/05/02: Re: Shannon Capacity
30902: 01/05/02: Re: Shannon Capacity
30906: 01/05/02: Re: Shannon Capacity
30930: 01/05/03: Re: Shannon Capacity
31019: 01/05/09: Re: Virtex-2 - experiences ?
31026: 01/05/09: Re: Shannon Capacity - An Apology
31033: 01/05/09: Re: Virtex-2 - experiences ?
31034: 01/05/09: Re: Shannon Capacity - An Apology
31044: 01/05/09: Re: Virtex-2 - experiences ?
31046: 01/05/09: Re: Virtex-2 - experiences ?
31047: 01/05/09: Re: Virtex-2 - experiences ?
31063: 01/05/10: Shannon Capacity, a quote from the paper
31163: 01/05/13: Re: Virtex-2 - experiences ?
31164: 01/05/13: Re: Fine phase shift in Virtex2
31184: 01/05/14: Re: Fine phase shift in Virtex2
31185: 01/05/14: Re: Fine phase shift in Virtex2
31186: 01/05/14: Re: Fine phase shift in Virtex2
31268: 01/05/16: Re: Ideas for Faster XILINX compilations ?
31457: 01/05/25: Re: spartan xl rise/fall time ?
31514: 01/05/28: Re: Fun with DLLs.
31570: 01/05/30: Re: Fun with DLLs.
31610: 01/05/31: Re: Fun with DLLs.
31719: 01/06/04: Re: XtremeDSP - the dawn of a new age
31789: 01/06/05: Re: Help in FIFO design
31880: 01/06/07: Re: Help in FIFO design
31897: 01/06/07: Re: Help in FIFO design
31925: 01/06/08: Re: Help in FIFO design
32446: 01/06/26: Re: Xilinx Spartan - Power Rail Related Timing Problem
32447: 01/06/26: Re: Alpha Particle
32475: 01/06/27: Re: Stupid Xilinx Patent
32506: 01/06/28: Re: how to DONE after DCM locked(VirtexII)?
32507: 01/06/28: Re: Alpha Particle
32877: 01/07/10: Re: Large Power up Current on Spartan2
32909: 01/07/11: Re: emergency consumption reduction for Spartan II
32948: 01/07/12: Re: DLL Phase Locking in Division Mode
33112: 01/07/17: Re: DLL Phase Locking in Division Mode
33113: 01/07/17: Re: Drive strength of Xilinx DONE pin
33114: 01/07/17: Re: Fibre Channel info?
33156: 01/07/18: Re: Spartan2XC2S30 vs ACEXEP1K30
33157: 01/07/18: Re: FPGAs in Safety Involved Applications
33326: 01/07/23: Re: Measuring power consumption
33440: 01/07/26: He is back from vacation, and he has a tan, too!
33469: 01/07/27: Re: SRL16
33807: 01/08/05: Re: Duty cycle problem with Virtex-II
33839: 01/08/06: revisting Claude Shannon
34000: 01/08/10: Re: how do i LOC Virtex-II BUFGMUX and DCM?
34067: 01/08/13: Re: Virtex-II and LVDS clocks.
34077: 01/08/13: Re: virtex2 Block Ram: dual port ram with different da
34082: 01/08/13: Re: virtex2 Block Ram: dual port ram with different da
34104: 01/08/14: Re: virtex2 Block Ram: dual port ram with different da
34167: 01/08/15: Re: fpga with the smallest i/o setup and hold requirement
34208: 01/08/16: Re: fpga with the smallest i/o setup and hold requirement
34209: 01/08/16: Re: Virtex-II and 5V devices
34215: 01/08/16: Re: Internal clock skew when using DLL
34227: 01/08/16: Re: Virtex-II and 5V devices
34251: 01/08/17: Re: Virtex-II and 5V devices
34252: 01/08/17: Re: fpga with the smallest i/o setup and hold requirement
34268: 01/08/17: Re: Virtex-II and 5V devices
34306: 01/08/20: Re: hardware damage to a Virtex or Spartan-II?
34307: 01/08/20: Re: Virtex-II and 5V devices
34364: 01/08/22: Re: hardware damage to a Virtex or Spartan-II?
34440: 01/08/24: Re: hardware damage to a Virtex or Spartan-II?
34450: 01/08/24: Re: Some questions about Spartan2 (& a bug report for XST sp8)
34476: 01/08/27: Re: Some questions about Spartan2 (& a bug report for XST sp8)
34559: 01/08/29: Re: Gate Count Definition
34740: 01/09/05: Re: Virtex-2 engineering samples
34757: 01/09/06: Re: Virtex-2 engineering samples
34759: 01/09/06: Re: HOW LONG WOULD LAST LONG
34833: 01/09/10: Re: Powering up a multi virtex fpga board
34938: 01/09/14: Re: configuration latency for PCI bridge in FPGA
34940: 01/09/14: Re: A vs. X
34943: 01/09/14: Re: A vs. X
34946: 01/09/14: Re: A vs. X
34975: 01/09/17: Re: Xilinx Virtex II Embedded Multiplier - Pipeline Register?
34976: 01/09/17: Re: Virtex-2 availability
34977: 01/09/17: Re: INIT attribute of SRL16E
34997: 01/09/17: Re: Virtex-2 availability
34998: 01/09/17: Re: Virtex-2 variable DPS availability
34999: 01/09/17: Re: INIT attribute of SRL16E
35002: 01/09/17: Re: Virtex-2 availability
35008: 01/09/17: Re: Virtex-2 availability
35084: 01/09/20: Re: virtex II (2v3000) configuration problem
35110: 01/09/21: Re: Virtex-2 availability
35111: 01/09/21: Re: Stopping a DLL
35113: 01/09/21: Re: Stopping a DLL
35123: 01/09/21: Re: Stopping a DLL
35232: 01/09/26: Re: Spartan-IIE?
35239: 01/09/26: Re: Spartan-IIE?
35246: 01/09/26: Re: Spartan-IIE?
35310: 01/09/28: Re: Spartan-IIE?
35311: 01/09/28: Re: Meta-stability
35324: 01/09/28: Re: Meta-stability
35369: 01/10/01: Re: Hitop Warning hi434
35371: 01/10/01: Re: CTL Register in Virtex-E Configuration
35407: 01/10/03: Re: Virtex II DCM: Phase Shifting
35553: 01/10/10: Re: Virtex-2 maximum clock speed
35574: 01/10/10: Re: Virtex-2 maximum clock speed
35597: 01/10/11: Re: Virtex2 DCM: frequenqy synthesis
35729: 01/10/15: Re: PLLs & DLLs
35811: 01/10/18: Re: VirtexII ES
35816: 01/10/18: Re: Phase noise of Xilinx/Altera DLL/PLL
35843: 01/10/19: Re: Glitch Hunting, a true story ;-)
35995: 01/10/25: Re: transferring data between related clocks
36025: 01/10/26: Re: Xilinx XST vs FPGA Express?
36117: 01/10/30: Re: Phase noise of Xilinx/Altera DLL/PLL
36226: 01/11/02: Re: Open configuration bitstreams
36468: 01/11/09: Re: Xilinx unconnected logic - always connected!
36481: 01/11/09: Re: Decoupling capacitors on Virtex II
36489: 01/11/09: Re: Virtex 2 parts availability???
36563: 01/11/12: Re: Decoupling capacitors on Virtex II
36564: 01/11/12: Re: Virtex 2 parts shipping = receiving
36565: 01/11/12: Re: PLL in Altera's Apex20K
36617: 01/11/13: Place your orders....
36639: 01/11/13: Re: Place your orders....
36685: 01/11/15: Re: Decoupling capacitors on Virtex II
36758: 01/11/19: Re: Decoupling capacitors on Virtex II
36764: 01/11/19: Re: DLL cycle-to-cycle jitter
36836: 01/11/21: Re: slew rate of virtex output buffers figures
36843: 01/11/21: Re: slew rate of virtex output buffers figures
36926: 01/11/26: Re: slew rate of virtex output buffers figures
36932: 01/11/26: Re: ALTERA's Mercury CDR -- whoops, misplaced comments
36969: 01/11/27: Re: Creating a jitter free clock
36970: 01/11/27: Re: Creating a jitter free clock
36974: 01/11/27: Re: Creating a jitter free clock
36981: 01/11/27: Re: Creating a jitter free clock
37004: 01/11/28: Re: maximum output current on Spartan2
37005: 01/11/28: Re: DLL cycle-to-cycle jitter
37008: 01/11/28: Kibibytes?
37009: 01/11/28: Re: FPGA startup current
37012: 01/11/28: Re: Creating a jitter free clock
37020: 01/11/28: Re: Creating a jitter free clock
37030: 01/11/28: Re: FPGA startup current
37036: 01/11/28: Re: FPGA startup current
37037: 01/11/28: Re: FPGA startup current
37058: 01/11/29: Re: maximum output current on Spartan2
37061: 01/11/29: Re: DLL cycle-to-cycle jitter
37062: 01/11/29: Re: FPGA startup current
37070: 01/11/29: Re: Spartan2 problems with 5V periphery
37071: 01/11/29: Re: FPGA startup current
37087: 01/11/29: Re: DLL cycle-to-cycle jitter
37092: 01/11/29: Re: FPGA startup current
37118: 01/11/30: Re: FPGA startup current
37119: 01/11/30: Re: FPGA startup current
37187: 01/12/03: Re: Phase noise (jitter) of XILINX logic elements - ?
37230: 01/12/04: Re: Phase noise (jitter) of XILINX logic elements - ?
37258: 01/12/05: Re: Phase noise (jitter) of XILINX logic elements - ?
37266: 01/12/05: Re: Phase noise (jitter) of XILINX logic elements - ?
37311: 01/12/06: Re: where is designed FPGA for apple II computer...?
37525: 01/12/13: Re: referencing Spartan2 DLL to 24.576 Mhz?
37673: 01/12/18: You take the low road and I'll ......
37715: 01/12/19: Re: You take the low road and I'll ......
37717: 01/12/19: Re: DCM stability in Virtex2 -ES
37742: 01/12/19: Re: Best-case timing?
37804: 01/12/20: Re: You take the low road and I'll ......
37814: 01/12/20: Re: You take the low road and I'll ......
38038: 02/01/02: Re: Virtex-2 maximum clock speed
38058: 02/01/03: Re: Q: Cable for multiple LVDS signals - ?
38088: 02/01/04: Re: Spartan-IIE interfacing issues
38152: 02/01/07: Re: Article FPGA + Reliable Systems
38189: 02/01/08: Re: Virtex-II parallel LVDS demo board (FAO Austin Lesea?)
38229: 02/01/09: Re: ADPCM?
38312: 02/01/11: Re: Xilinx High speed I/O
38314: 02/01/11: Re: ASIC faster than VirtexII FPGA?
38316: 02/01/11: Re: Spartan-IIE interfacing issues
38330: 02/01/11: Re: Picking an FPGA
38432: 02/01/14: Re: Radiation Resistance
38472: 02/01/15: Re: CLKDLL cascade questions
38473: 02/01/15: Re: Virtex-2 Frequency Synhtesis
38486: 02/01/15: Re: Virtex-2 Frequency Synhtesis
38535: 02/01/16: Re: Signal processing using FPGAs
38541: 02/01/16: Re: Virtex-2 Frequency Synhtesis
38556: 02/01/17: Re: Signal processing using FPGAs
38557: 02/01/17: Re: Virtex2 ICAP
38586: 02/01/18: Re: DDR-Interface
38604: 02/01/18: Re: VirtexII ES configuration
38664: 02/01/21: Re: SPARTAN 2-DLL USAGE
38926: 02/01/28: Re: XC2V10000 still on the Xilinx roadmap?
38944: 02/01/28: Re: Spartan-2E data sheet (ds077_x.pdf)
38953: 02/01/28: Re: Spartan II power-up current - again
39002: 02/01/29: Re: Soft errors climb in 0,13u SRAM
39034: 02/01/30: Re: Spartan II power-up current - again
39050: 02/01/30: Re: Spartan II power-up current - again and again, and again, and .....
39092: 02/01/31: {72,64} extended hamming ECC
39104: 02/01/31: Re: FPGA or Micro-controller in Lowpower designs?
39109: 02/01/31: Re: skew between gated clks in Virtex2?
39141: 02/02/01: Re: Virtex2-3000 (XC2V3000) engineering samples and chipscope
39210: 02/02/04: Re: Virtex-II and SDRAM Controller at 133MHz
39225: 02/02/04: Re: Destroying a CPLD by JTAG
39265: 02/02/05: Re: Destroying a CPLD by JTAG
39266: 02/02/05: Re: When is Xilinx going to have multi-gigabit serial PHY?
39269: 02/02/05: Re: When is Xilinx going to have multi-gigabit serial PHY?
39271: 02/02/05: Re: Destroying a CPLD by JTAG
39275: 02/02/05: Re: DCM relationship question
39286: 02/02/05: Re: FPGA vs GAL : Lattice
39296: 02/02/05: Re: FPGA --> SDRAM & Groundbounce: Latchup Possible?
39335: 02/02/06: Re: RE Xilinx 3.3SP8, Beware!
39336: 02/02/06: Re: FPGA --> SDRAM & Groundbounce: Latchup Possible?
39413: 02/02/08: Re: Xilinx DCM question anyone? (or Peter if he is there?)
39414: 02/02/08: Re: Xilinx DCM question anyone? (or Peter if he is there?)
39476: 02/02/11: Re: Altera's new family Stratix
39512: 02/02/12: Re: Altera's new family Stratix
39536: 02/02/12: Re: Altera's new family Stratix
39537: 02/02/12: Re: Altera's new family Stratix
39568: 02/02/13: Re: Altera's new family Stratix
39569: 02/02/13: Re: CLKDLL doesn't work without BUFG ?
39606: 02/02/14: Re: Altera's new family Stratix
39609: 02/02/14: Re: Altera's new family Stratix
39685: 02/02/15: Re: SpartanXL & VHDL -- free software?
40115: 02/02/27: Re: APEX-II vs VIRTEX-II
40148: 02/02/28: Re: FPGAs with differential LVDS terminations?
40186: 02/03/01: Re: high-speed clock distribution/divider in a FPGA?
40188: 02/03/01: Re: high-speed clock distribution/divider in a FPGA?
40274: 02/03/04: Re: Xilinx Virtex Family die photos...
40322: 02/03/05: Re: exceeding 2GB limits in xilinx
40331: 02/03/05: Re: digital video PLL
40335: 02/03/05: Re: exceeding 2GB limits in xilinx
40347: 02/03/05: Re: digital video PLL
40350: 02/03/05: Re: digital video PLL
40396: 02/03/06: Re: Xilinx announces Virtex-II Pro is shipping
40397: 02/03/06: Re: V-II DCM options
40455: 02/03/07: Re: max frequency of obuf_lvdci_dv2_18
40456: 02/03/07: Re: Virtex-II : Temperature Sensing Diodes
40474: 02/03/07: Re: Virtex-II : Temperature Sensing Diodes
40485: 02/03/07: Re: Clamping Diode in the I/O !!!
40579: 02/03/11: Re: Spartan II E output voltage characteristics
40581: 02/03/11: Re: FPGA which supports LVDS
40601: 02/03/11: Re: FPGA wich supports LVDS
40604: 02/03/11: Re: Spartan II E output voltage characteristics
40621: 02/03/11: Re: FPGA wich supports LVDS
40709: 02/03/13: Re: IBIS simulation (was Re: max frequency of obuf_lvdci_dv2_18)
40710: 02/03/13: Re: IBIS simulation (was Re: max frequency of obuf_lvdci_dv2_18)
40741: 02/03/14: Re: Difference between Virtex-II(E) und Virtex-E
40742: 02/03/14: Re: use virtex2 DCM as delay line
40767: 02/03/14: Re: Virtex-II : Temperature Sensing Diodes
40784: 02/03/15: Re: Xilinix FPGA with 5V IO
40786: 02/03/15: 18X18, oh the possibilities!
40804: 02/03/15: Re: High speed clock routing
40809: 02/03/15: Re: High speed clock routing
40810: 02/03/15: Re: High speed clock routing
40811: 02/03/15: Re: Xilinix FPGA with 5V IO
40928: 02/03/18: Re: [Virtex 2] DCM: "Factory_JF" option box in FPGA editor question
40943: 02/03/18: Re: High speed clock routing
40987: 02/03/19: Re: High speed clock routing
40988: 02/03/19: Re: [Virtex 2] DCM: "Factory_JF" option box in FPGA editor question
40994: 02/03/19: Re: Unused I/Os + External Clock on Virtex II
41005: 02/03/19: Re: Unused I/Os + External Clock on Virtex II
41009: 02/03/19: Re: Unused I/Os + External Clock on Virtex II
41016: 02/03/19: Re: High speed clock routing
41055: 02/03/20: Re: Unused I/Os + External Clock on Virtex II + P-P Jitter
41062: 02/03/20: Re: spartan 2e, 5V i/o
41089: 02/03/20: Re: Unused I/Os + External Clock on Virtex II + P-P Jitter
41138: 02/03/21: Re: spartan 2e, 5V i/o
41141: 02/03/21: Re: High speed clock routing
41222: 02/03/22: Re: Poor availability problems on Coolrunner
41233: 02/03/22: Got Parts?
41300: 02/03/25: Re: Missing Timing by 30,000 ns
41307: 02/03/25: Re: question on LFSR
41523: 02/04/01: Re: VirtexII : Any limitation on using LVDS?
41583: 02/04/02: Re: powerpc in virtex2pro
41628: 02/04/03: Re: powerpc in virtex2pro
41645: 02/04/04: Re: powerpc in virtex2pro
41666: 02/04/04: Re: powerpc in virtex2pro
41798: 02/04/08: Re: Variable phase-shift
41820: 02/04/08: Re: bad experience with Xilinx ISE 4.1i and Xilinx hotline suppot
41824: 02/04/08: Re: bad experience with Xilinx ISE 4.1i and Xilinx hotline suppot
42112: 02/04/16: Re: Using SRL16E Xilinx primitive.
42162: 02/04/17: Re: FPGA Timing Problem
42168: 02/04/17: Re: GND Outputs being optimized out using FPGA Express 3.6.1 in
42209: 02/04/18: Re: GND Outputs being optimized out using FPGA Express 3.6.1 in
42238: 02/04/18: Re: 1000 I/O Pins -- What is cheapest FPGA?
42240: 02/04/18: Re: fpga limitation
42257: 02/04/18: Re: fpga limitation
42279: 02/04/19: Re: 1000 I/O Pins -- What is cheapest FPGA?
42281: 02/04/19: Re: Using Virtex-II DCM to determine clock activity
42282: 02/04/19: Re: Virtex-II core power supply
42287: 02/04/19: Re: Xilinx Programmable World 2002 - Review
42300: 02/04/19: Re: Xilinx Easypath- Selling parts with known defects
42375: 02/04/22: Re: virtex-e DLL and clock skew
42376: 02/04/22: Re: Using Virtex-II DCM to determine clock activity
42377: 02/04/22: Re: fpga limitation
42378: 02/04/22: Re: Xilinx Programmable World 2002 - Review
42379: 02/04/22: Re: Xilinx Programmable World 2002 - Review
42380: 02/04/22: Re: Xilinx Easypath- Selling parts with known defects
42381: 02/04/22: Re: Xilinx Easypath- Selling parts with known defects
42397: 02/04/22: Re: Xilinx Programmable World 2002 - Review
42412: 02/04/23: Re: Xilinx Easypath- Selling parts with known defects
42431: 02/04/23: Re: Xilinx Easypath- Selling parts with known defects
42451: 02/04/24: Re: Virtex 2: Partial Bitstream Generation
42455: 02/04/24: Re: Frequency synthesiser
42472: 02/04/24: Re: SpartanII design considerations...
42475: 02/04/24: Re: Xilinx Easypath- Selling parts with known defects
42489: 02/04/25: Re: Using 74HCT245N between Spartan-II and ISA
42492: 02/04/25: Re: Frequency synthesiser
42499: 02/04/25: Re: SpartanII design considerations...
42529: 02/04/26: Re: Does Virtex II PRO Really work? You damn betcha!
42531: 02/04/26: Re: SpartanII design considerations...
42532: 02/04/26: Re: Frequency synthesiser
42656: 02/04/30: Re: Xilinx Easypath- Selling parts with known defects
42658: 02/04/30: Re: power supply sequencer for Virtex II
42667: 02/04/30: Re: simultaneous switching of LVPECL outputs
42668: 02/04/30: Re: Power-up reset of Xilinx Spartan-II
42678: 02/04/30: Re: simultaneous switching of LVPECL outputs
42679: 02/04/30: Re: power supply sequencer for Virtex II
42680: 02/04/30: Re: Xilinx Easypath- Selling parts with known defects
42686: 02/04/30: Re: power supply sequencer for Virtex II
42688: 02/04/30: Re: Xilinx Easypath- is it a fake?
42713: 02/05/01: Re: simultaneous switching of LVPECL outputs
42714: 02/05/01: Re: Spartan outputs to 3.3V DRAMs...
42720: 02/05/01: Re: Spartan outputs to 3.3V DRAMs...
42731: 02/05/01: Re: simultaneous switching of LVPECL outputs
42763: 02/05/02: Re: simultaneous switching of LVPECL outputs
42764: 02/05/02: Re: Delivery problems..
42790: 02/05/02: Re: simultaneous switching of LVPECL outputs
42796: 02/05/02: Re: simultaneous switching of LVPECL outputs
42818: 02/05/03: Re: simultaneous switching of LVPECL outputs
42896: 02/05/06: Re: Xilinx 2GB limit... something has to be done
42902: 02/05/06: Re: clock multiplication in xilinx
42931: 02/05/07: Re: clock multiplication in xilinx
42935: 02/05/07: Re: clock multiplication in xilinx
42959: 02/05/08: Re: Opinions on FPGA cores - best for a commercial project?
42961: 02/05/08: Re: JTAG 5V tollerance...?
42986: 02/05/08: Re: Transistor Counts for Xilinx FPGAs
43016: 02/05/09: Re: Timing of XC2S200E-6FG456C compared to XC2S200E-6FG456I
43017: 02/05/09: Re: JTAG 5V tollerance...?
43018: 02/05/09: Re: clock multiplication in xilinx
43021: 02/05/09: Re: JTAG 5V tollerance...?
43050: 02/05/10: Re: power supply sequencer for Virtex II
43087: 02/05/13: Re: Virtex-II DCM Frequency Synthesis
43148: 02/05/14: Re: Architecture for high-level reconfigurable computing
43167: 02/05/15: Re: Architecture for high-level reconfigurable computing
43168: 02/05/15: Re: Architecture for high-level reconfigurable computing
43174: 02/05/15: Re: Architecture for high-level reconfigurable computing
43207: 02/05/16: Got to get those decimals in the right place on the slide rule .....
43209: 02/05/16: Re: output rise and fall time for Spartan2E, but don't talk about IBIS??
43213: 02/05/16: Re: Bidirectional DONE?
43224: 02/05/16: Re: output rise and fall time for Spartan2E, but don't talk about IBIS??
43252: 02/05/17: Re: HardPath
43253: 02/05/17: Re: LOCKED signal of a DLL in a Virtex device questions
43358: 02/05/20: Re: HardPath
43360: 02/05/20: Re: How to generate fractional-N clock ?
43367: 02/05/20: Re: How to generate fractional-N clock ?
43369: 02/05/20: Re: Driving high speed external devices from an FPGA
43388: 02/05/20: Re: Power Consumption scaling factor
43427: 02/05/21: Re: Synchronous Single Clock Designs
43439: 02/05/21: Re: Synchronous Single Clock Designs
43440: 02/05/21: Re: virtex II : DCM phases
43446: 02/05/21: Re: 5V differential -> Virtex 2
43453: 02/05/21: Re: 5V differential -> Virtex 2
43455: 02/05/21: Re: Driving high speed external devices from an FPGA
43499: 02/05/22: Re: Testing Philosophy
43500: 02/05/22: Re: Xilinx Serial IO Data rates
43504: 02/05/22: Re: Xilinx configuration times
43638: 02/05/28: Re: IO simulations
43643: 02/05/28: Re: Frequency synthesiser
43647: 02/05/28: Re: Frequency synthesiser
43651: 02/05/28: Re: Frequency synthesiser
43654: 02/05/28: Re: Frequency synthesiser
43658: 02/05/28: Re: Frequency synthesiser
43678: 02/05/29: Re: Frequency synthesiser
43691: 02/05/29: Re: DCM partial reconfiguration
43703: 02/05/30: Re: virtex 2 : DCM divided clock
43705: 02/05/30: Re: Frequency synthesiser
43732: 02/05/31: Re: IO simulations
43744: 02/05/31: Re: IO simulations
43807: 02/06/03: Re: divide by 5
43853: 02/06/04: FPGA destruction vs power management
43889: 02/06/05: Re: virtex 2 : IOBUF tristate plarity
43927: 02/06/06: Re: FPGA destruction vs power management
43965: 02/06/07: Thresholds
43984: 02/06/07: Re: Do I have metastability issues?
43987: 02/06/07: Re: Do I have metastability issues?
44029: 02/06/10: Re: Virtex 2 Pro Board
44094: 02/06/11: Re: IBIS to Spice Translation (part1)
44128: 02/06/12: Re: IBIS to Spice Translation (part1)
44130: 02/06/12: Re: Digital FM demodulator in FPGA-continue
44353: 02/06/18: Re: 5V tolerance
44354: 02/06/18: Re: Seeking CPLD/FPGA recomendation
44357: 02/06/18: Re: Seeking CPLD/FPGA recomendation
44377: 02/06/18: Re: 5V tolerance
44469: 02/06/20: Re: 5V tolerance
44599: 02/06/24: Parts are almost never bad ....
44673: 02/06/26: Re: IBIS simulator
44799: 02/07/01: Re: Xpower accuracy (is there anybody from Xilinx out there ?)
44803: 02/07/01: Re: No damage to Virtex-E from 2.5V vs 3.3 V IOB standard
44872: 02/07/03: Re: Power consumtion simulation for FPGA?
45001: 02/07/09: Re: DCM - LOCKED output stays high when it shouldn't?
45033: 02/07/10: Re: DCM - LOCKED output stays high when it shouldn't?
45101: 02/07/12: Re: Security features
45102: 02/07/12: Re: Security features
45194: 02/07/15: Re: Virtex-2 configuration: Device check ?
45195: 02/07/15: Re: Spartan clock mirroring
45196: 02/07/15: Re: Xilinx (spartan 2) - SI even applies to the config pins
45315: 02/07/18: Re: Virtex-II variable vs fixed DCM phase-shift ?
45350: 02/07/19: Re: Virtex-II variable vs fixed DCM phase-shift ?
45539: 02/07/25: Re: Wind River Diab Xilinx Edition
45542: 02/07/25: Re: logic elements v/s logic cells
45804: 02/08/06: Re: Xilinx hiring practises
45828: 02/08/06: Re: Programming bits reverse engineering
45847: 02/08/07: Re: Programming bits reverse engineering
45890: 02/08/09: Re: Xilinx XC2VP4 price/availability ?
45905: 02/08/09: Re: Xilinx XC2VP4 price/availability ?
46078: 02/08/16: Re: Phase shift in high frequency mode in VirtexII's DCM
46099: 02/08/19: Re: Phase shift in high frequency mode in VirtexII's DCM
46152: 02/08/20: Re: Poor man's DSP/FPGA instructional tool?
46186: 02/08/21: Re: Virtex-II LVPECL Inputs
46188: 02/08/21: Re: Academics vs 'real' FPGA use
46205: 02/08/21: Re: Academics vs 'real' FPGA use
46213: 02/08/21: Re: Logic Analyzers not required with Xilinx Boards....
46252: 02/08/22: Re: Downloading bit streams in Xilinx
46270: 02/08/23: Re: Virtex-2Pro CPU to memory performance
46343: 02/08/26: Re: VirtexII: HSWAP_EN
46344: 02/08/26: Re: VirtexII: HSWAP_EN
46349: 02/08/26: Re: VirtexII: HSWAP_EN
46353: 02/08/26: Re: VirtexII: HSWAP_EN
46372: 02/08/27: Re: Spartan-II inrush and other power suppy isues (was Re: need cheap
46433: 02/08/29: Re: Use SSTL2_I or SSTL2_II for bidir?
46568: 02/09/03: Re: C/C++ to Verilog/VHDL ?!
46612: 02/09/04: Re: PPC blocks in XC2VP50
46623: 02/09/04: Re: xilinx contact with regard to qpro
46731: 02/09/06: Re: XCR3384XL availability
46736: 02/09/06: Re: XCR3384XL availability
46799: 02/09/09: Re: Can FPGA implements ADC?
46803: 02/09/09: Re: XCR3384XL availability
46878: 02/09/10: Re: XCR3384XL availability
46886: 02/09/10: Re: XCR3384XL availability
46973: 02/09/13: Re: exploiting metastability
46975: 02/09/13: Re: exploiting metastability
47054: 02/09/16: Re: Question about Virtex-II DCM's jitter
47064: 02/09/16: Re: Question about Virtex-II DCM's jitter
47066: 02/09/16: Re: Virtex II packaging, why no QFP?
47077: 02/09/16: Re: Question about Virtex-II DCM's jitter
47078: 02/09/16: Re: Question about Virtex-II DCM's jitter
47079: 02/09/16: Re: Virtex II packaging, why no QFP?
47080: 02/09/16: Re: Virtex II packaging, why no QFP?
47082: 02/09/16: Re: 1.8V regulator needed for Spartan IIE
47100: 02/09/17: Re: Question about Virtex-II DCM's jitter
47308: 02/09/23: Re: MTBF
47354: 02/09/24: Re: Altera Cyclone low-cost FPGA chips?
47371: 02/09/24: Re: Altera Cyclone low-cost FPGA chips?
47374: 02/09/24: Re: MTBF
47425: 02/09/25: Re: Altera Cyclone low-cost FPGA chips?
47433: 02/09/25: ESD Undressing Story
47472: 02/09/26: Re: Can a fpga replace external inverters in a crystal osc ?
47523: 02/09/27: Re: Is it possible to build a Ring Oscillator in an FPGA chip?
47668: 02/10/01: Re: xilinx free logic analyzer?
47703: 02/10/02: Re: Help for Altera's FPGAs' pinout
47717: 02/10/02: Re: virtex 2 -5i vs -6
48295: 02/10/15: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
48305: 02/10/15: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
48387: 02/10/16: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
48434: 02/10/17: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
48657: 02/10/22: Re: slow slew rate signal...
48727: 02/10/23: Re: How full is too full?
48786: 02/10/24: Re: Silly Virtex 2 Pro question...
48792: 02/10/24: Re: Silly Virtex 2 Pro question...
48797: 02/10/24: Re: Silly Virtex 2 Pro question...
48811: 02/10/24: Re: Xilinx POS Power On Surge Current
48812: 02/10/24: Re: Silly Virtex 2 Pro question...
48818: 02/10/24: Re: Silly Virtex 2 Pro question...
49225: 02/11/05: Re: Decoupling requirements on VREF pins (Xilinx)
49226: 02/11/05: Re: LVDS I/Os on Virtex-II Devices: Short circuit safety?
49237: 02/11/05: Re: Decoupling requirements on VREF pins (Xilinx)
49383: 02/11/11: Re: Xilinx Virtex SelectMAP question
49384: 02/11/11: Re: Partial Reconfiguration, Modular Design
50144: 02/12/03: Re: question about PCB traces for FPGA board... ?
50248: 02/12/06: Re: *Exactly* How and when does attribute DESKEW_ADJUST affect the DCM
50343: 02/12/09: Re: virtex output pin voltage
50354: 02/12/09: Re: virtex output pin voltage
50489: 02/12/11: Re: partial Bitstream Size in Virtex-II
50502: 02/12/11: Re: Power consumption question
50663: 02/12/16: Re: Virtex2Pro question
50668: 02/12/16: Re: Virtex2Pro question
50787: 02/12/19: Re: Multi cycle Paths..
50796: 02/12/19: Re: Multi cycle Paths..
50932: 02/12/23: Re: serdes
50977: 02/12/24: Re: HSTL standards
50980: 02/12/24: Re: FPGA accelerated FPGA/ASIC tools
51231: 03/01/07: Re: Spartan II:Bidirectional IO interfacing 5V CMOS ?
51250: 03/01/08: Re: Bug in Quartus2 Web 2.2
51254: 03/01/08: Re: Bug in Quartus2 Web 2.2
51309: 03/01/10: Re: Power usage of CLOCK in FPGA
51310: 03/01/10: Re: DLL/PLL with global clock net
51318: 03/01/10: Re: Student development board
51320: 03/01/10: Re: Virtex-II Pro misfire?
51521: 03/01/15: Re: How can I use DCM to 1/24 freq-division?
51522: 03/01/15: Re: Student development board
51643: 03/01/17: Re: How can I use DCM to 1/24 freq-division?
51729: 03/01/20: Re: frequency matching of ring oscillators
51739: 03/01/20: Re: frequency matching of ring oscillators
51781: 03/01/21: Re: Virtex II: noise on Vcco causing loss of DCM lock
51815: 03/01/22: Re: Virtex II: noise on Vcco causing loss of DCM lock
51822: 03/01/22: Re: Xilinx Spartan2 with more than 4 clocks
52159: 03/02/03: Re: Spartan-II OBUF Driver Impedance
52166: 03/02/03: Re: 3.3 Volt tolerance in Virtex II Pro...
52170: 03/02/03: Re: Altera Stratix terminator technology
52521: 03/02/12: Re: Multicontext FPGA
52555: 03/02/13: Re: Coolrunner II I/O speeds?
52559: 03/02/13: Re: Multicontext FPGA
52569: 03/02/13: Re: Coolrunner II I/O speeds?
52570: 03/02/13: Re: Altera Stratix terminator technology
52591: 03/02/14: Re: Implementing BIG state machhine
52784: 03/02/21: Re: Gate boosting
52854: 03/02/24: Re: Looking for Virtex2Pro and Linux (PPC)
52981: 03/02/27: Re: Spartan II PCB, I/O pins consederations
52982: 03/02/27: Re: several fpga high bandwidth questions
52992: 03/02/27: Re: Spartan II PCB, I/O pins consederations
53096: 03/03/03: Re: Avnet Cilicon Xilinx Virtex-E development kit
53133: 03/03/04: Re: Xilinx support...
53135: 03/03/04: Using Xilinx DCMs out of specifications is not recommended!!!!
53343: 03/03/11: Re: Cyclone power up problem
53361: 03/03/11: Re: Cyclone power up problem
53378: 03/03/12: Re: Cyclone power up problem
53394: 03/03/12: Re: Cyclone power up problem
53440: 03/03/13: Re: Help understanding 7408 and gate chip
53828: 03/03/24: triple des
53862: 03/03/25: How failures happen, and how they don't
53889: 03/03/26: Re: Virtex II pro board design question
53928: 03/03/27: Re: How failures happen, and how they don't
53931: 03/03/27: Re: Differential LVPECL Inteface of Spartan IIE
53939: 03/03/27: Re: Differential LVPECL Inteface of Spartan IIE
53940: 03/03/27: Re: Tristate pins + Inputs => External Pullup ?
53961: 03/03/28: Re: Tristate pins + Inputs => External Pullup ?
54019: 03/03/31: Xilinx announces 90nm sampling today!
54022: 03/03/31: Re: Xilinx announces 90nm sampling today!
54027: 03/03/31: Re: Xilinx announces 90nm sampling today!
54038: 03/03/31: Re: Xilinx announces 90nm sampling today!
54106: 03/04/02: Re: odd virtex-ii bufgmux behavior??
54150: 03/04/03: Re: uP interface question
54190: 03/04/04: Re: Cyclone power up problem - 'Engineerus Emptor'
54215: 03/04/04: Re: Xilinx announces 90nm sampling today!
54305: 03/04/07: Re: Spartan-3 in docsan Webpack release notes... a joke???
54374: 03/04/09: Re: OK, where does an FPGA newbie start?
54378: 03/04/09: Re: OK, where does an FPGA newbie start?
54411: 03/04/10: Balanced Presentation
54615: 03/04/14: Re: Xilinx has released SpartanIII
54616: 03/04/14: Re: Spartan 3, Vccaux?
54652: 03/04/15: Re: Xilinx has released SpartanIII
54654: 03/04/15: Re: fpga fault tolerence.
54663: 03/04/15: Re: Spartan 3, Vccaux?
54718: 03/04/16: Re: 2.5V switching regulator for Spartan 2
54725: 03/04/16: Re: Xilinx has released SpartanIII
54732: 03/04/16: Re: 2.5V switching regulator for Spartan 2
54871: 03/04/21: Re: Cyclone power up problem - Summery
54973: 03/04/23: Re: Xilinx has released SpartanIII
55052: 03/04/25: Re: Xilinx has released SpartanIII
55077: 03/04/25: Re: Cyclone power up problem - Summery
55130: 03/04/28: Re: DDR SDRAM controlled by fpga?
55285: 03/05/02: Re: SPI-4.2 dynamic alignment - how'd they do that?
55351: 03/05/05: Re: PLL in fpga
55357: 03/05/05: Re: Virtex2 BUFGMUX problem ?
55362: 03/05/05: Re: Output switching time
55384: 03/05/06: Re: Output switching time
55385: 03/05/06: Re: Output switching time
55418: 03/05/07: Re: Using Cyclone's PLL
55419: 03/05/07: Re: How failures happen, and how they don't
55432: 03/05/07: Re: How failures happen, and how they don't
55489: 03/05/09: Re: Encrypted bitstream - battery lifetime solved
55516: 03/05/11: Re: Encrypted bitstream - battery lifetime problem
55517: 03/05/11: Re: Encrypted bitstream - battery lifetime problem
55550: 03/05/12: Re: PLL in fpga
55551: 03/05/12: Re: OK I am pissed off with Xilinx webpack.
55561: 03/05/12: Re: OK I am pissed off with Xilinx webpack.
55586: 03/05/13: Re: Spartan 3 Power requirements
55633: 03/05/14: Re: Can XST takes place of Synplify or FPGA Compiler? "No" FAQ #3.
55709: 03/05/16: Re: Eng. samples -- differences from production?
55712: 03/05/16: Re: smallest embedded cpu....and the most pain?
55765: 03/05/19: Re: Output switching time
55812: 03/05/20: Re: smallest embedded cpu.
55854: 03/05/21: Re: FPGA design: firmware or hardware?
55878: 03/05/22: Re: FPGA design: firmware or hardware?
55879: 03/05/22: Re: How to verify timing parameters of clock
55880: 03/05/22: Re: Xilinx announces 90nm sampling today!
55933: 03/05/23: Re: DCM Trouble
56019: 03/05/27: Re: Multiply 19.44MHz with Virtex-II DCM
56034: 03/05/27: Re: Multiply 19.44MHz with Virtex-II DCM
56079: 03/05/28: Re: Multiply 19.44MHz with Virtex-II DCM
56148: 03/05/29: Re: Multiply 19.44MHz with Virtex-II DCM
56165: 03/05/29: Re: FPGA's an Flash
56202: 03/05/30: Antifuse and CCC FPGA
56211: 03/05/30: Re: FPGA's an Flash
56277: 03/06/02: Re: FPGA's an Flash
56278: 03/06/02: Re: MicroBlaze and Spartan3
56280: 03/06/02: Re: power consumption in CMOS..
56339: 03/06/03: Re: FPGA's an Flash
56398: 03/06/04: Re: FPGA's an Flash
56408: 03/06/04: Re: DES-encrypt, Spartan3, was Re: FPGA's an Flash
56447: 03/06/05: Re: An FPGA is flying to Mars
56451: 03/06/05: Re: DES-encrypt, Spartan3, was Re: FPGA's an Flash
56496: 03/06/06: Re: Xilinx Block RAM
56501: 03/06/06: Re: Xilinx Block RAM
56550: 03/06/09: Re: Xilinx Block RAM
56686: 03/06/11: Re: Drive Capabilities of the FPGA
56731: 03/06/12: Re: Analog signals connected to xilinx spartan2
56754: 03/06/13: Re: Analog signals connected to xilinx spartan2
56848: 03/06/17: Re: Xilinx Block RAM
56897: 03/06/18: Re: FPGA to Custom ASIC ??
56900: 03/06/18: Re: Cyclone vs. Acex consumption?
56906: 03/06/18: Re: Cyclone vs. Acex consumption?
56912: 03/06/18: Re: Cyclone vs. Acex consumption?
56949: 03/06/19: No longer talking about power consumption....
56950: 03/06/19: Re: Dr. Leaky responds
56957: 03/06/19: Re: How one specifies Icco, Iccint quiescent...
56958: 03/06/19: 0.13u leakage
56963: 03/06/19: Re: Cyclone vs. Acex consumption?
57080: 03/06/23: Re: Virtex-II's IO Level?
57188: 03/06/25: Re: Interfacing IDE
57191: 03/06/25: Re: Interfacing IDE
57193: 03/06/25: Re: Interfacing IDE
57195: 03/06/25: Re: Interfacing IDE
57252: 03/06/26: Re: Low-power FPGA
57270: 03/06/26: Re: Low-power FPGA
57271: 03/06/26: Re: why so many problems Xilinx ?
58019: 03/07/11: Re: Cyclone vs Spartan-3
58125: 03/07/15: Virtex-II Pro family is a hands-down winner for DSP
58138: 03/07/15: Re: PROM size for spartan
58145: 03/07/15: Re: PROM size for spartan
58269: 03/07/18: Re: Level translators on PCI
58342: 03/07/21: Use ICAp iwth a soft IP core to decompress!!!!
58353: 03/07/21: Re: Use ICAp iwth a soft IP core to decompress!!!!
58471: 03/07/24: Re: Pricing question....
58472: 03/07/24: Re: Use ICAp iwth a soft IP core to decompress!!!!
58535: 03/07/25: Re: Use ICAp iwth a soft IP core to decompress!!!!
58536: 03/07/25: Re: Use ICAp iwth a soft IP core to decompress!!!!
58618: 03/07/29: Re: Spartan IIE max pin switching
58622: 03/07/29: Re: FPGA research
58629: 03/07/29: Re: Spartan IIE max pin switching
58658: 03/07/30: Re: Spartan IIE max pin switching
58680: 03/07/30: Re: Altera-to-Xilinx IO 3.3V -> 1.8V
58685: 03/07/30: Re: Altera-to-Xilinx IO 3.3V -> 1.8V
58686: 03/07/30: Re: Mentor Hyperlynx IBIS simulator (was Re: Spartan IIE max pin
58714: 03/07/31: Re: DDS question. How to generate a square from a sine wave?
58715: 03/07/31: Re: DDS question. How to generate a square from a sine wave?
58723: 03/07/31: Level shifting using NMOS pass gate devices
58735: 03/07/31: Re: Mentor Hyperlynx IBIS simulator (was Re: Spartan IIE max pin
58743: 03/07/31: Re: Spartan 3 Overshoot limit
58778: 03/08/01: Re: 5 volt tolerant Xilinx parts
58801: 03/08/01: Re: 5 volt tolerant Xilinx parts
58912: 03/08/04: Re: 'Virtual Grounds'
58914: 03/08/04: Re: 5 volt tolerant Xilinx parts
58915: 03/08/04: Re: 5 volt tolerant Xilinx parts
58916: 03/08/04: Re: DDS question. How to generate a square from a sine wave?
58923: 03/08/04: Re: 5 volt tolerant Xilinx parts
58934: 03/08/04: Re: 5 volt tolerant Xilinx parts
58935: 03/08/04: Re: 5 volt tolerant Xilinx parts
58960: 03/08/05: Re: Patent granted for "system on a chip" framework?
58961: 03/08/05: Re: JTAG programmers
58962: 03/08/05: Re: 'Virtual Grounds'
59278: 03/08/13: Re: Skew on a clock tree on a virtex II : what is the good figure ?
59304: 03/08/14: Re: Skew on a clock tree on a virtex II : what is the good figure ?
59305: 03/08/14: Re: Old Xilinx FPGAs
59309: 03/08/14: Re: Virtex II Output Impedance
59310: 03/08/14: Re: Skew on a clock tree on a virtex II : what is the good figure ?
59313: 03/08/14: Re: Virtex II Output Impedance
59390: 03/08/18: Re: Virtex II Output Impedance
59391: 03/08/18: Re: Skew on a clock tree on a virtex II : what is the good figure ?
59412: 03/08/18: Re: DDFS question
59478: 03/08/20: Re: Legacy 4005 series and current Xilinx ISE offerings?
59479: 03/08/20: Re: Skew on a clock tree on a virtex II : what is the good figure ?
59488: 03/08/20: Re: Legacy 4005 series and current Xilinx ISE offerings?
59496: 03/08/20: Re: Legacy 4005 series and current Xilinx ISE offerings?
59512: 03/08/20: Re: DCM vs state machine
59514: 03/08/20: Re: Legacy 4005 series and current Xilinx ISE offerings?
59516: 03/08/20: Re: DCM vs state machine
59542: 03/08/21: Re: DCM vs state machine
59543: 03/08/21: Re: DCM vs state machine
59544: 03/08/21: Re: DCM vs state machine
59547: 03/08/21: Re: DCM vs state machine
59548: 03/08/21: Re: Skew on a clock tree on a virtex II : what is the good figure ?
59553: 03/08/21: Re: DCM vs state machine
59563: 03/08/21: Re: DCM vs state machine
59585: 03/08/22: Re: Why can't Xilinx DCM's regain lock without a RESET??
59631: 03/08/25: Re: Why can't Xilinx DCM's regain lock without a RESET??
59632: 03/08/25: Re: Reusing CCLK line after configuration for Spartan-II
59633: 03/08/25: Re: Lithium cell on Virtex2 Pro
59701: 03/08/26: Re: FPGA minimum operating frequencies
59702: 03/08/26: Re: Why can't Xilinx DCM's regain lock without a RESET??
59707: 03/08/26: Re: Free FPGA samples anywhere?
59497: 03/08/20: Re: where to find interfacing on support.xilinx.com
59946: 03/09/02: Re: Input comparator
59947: 03/09/02: Re: Selecting between two clock signals
59948: 03/09/02: Re: Selecting between two clock signals
59949: 03/09/02: Re: Why can't Xilinx DCM's regain lock without a RESET??
59950: 03/09/02: Re: A student's question
59951: 03/09/02: Re: DDR capabilities of a Virtex II device
59966: 03/09/02: Re: Measuring metastability.
60004: 03/09/03: Re: Measuring metastability.
60005: 03/09/03: Re: Measuring metastability.
60006: 03/09/03: Re: Input comparator
60007: 03/09/03: Re: Input comparator
60017: 03/09/03: Re: Selecting between two clock signals
60019: 03/09/03: Re: Measuring metastability.
60053: 03/09/04: Re: Input comparator
60054: 03/09/04: Re: Clock Recovery from 8B10B encoded Data Stream
60055: 03/09/04: Re: More about metastability
60063: 03/09/04: Re: How to contact the writer of Xilinx FPGA application notes?
60067: 03/09/04: Re: New to FPGA, seeking advice
60076: 03/09/04: Re: New to FPGA, seeking advice
60077: 03/09/04: Re: New to FPGA, seeking advice
60080: 03/09/04: Re: Input comparator
60082: 03/09/04: Re: New to FPGA, seeking advice, off topic again....
60085: 03/09/04: Re: More about metastability
60146: 03/09/05: still off topic again....
60150: 03/09/05: Re: Suitable FPGA architecture for Robots..
60152: 03/09/05: Re: Original (5V) Xilinx Spartan ?
60227: 03/09/08: Re: Original (5V) Xilinx Spartan ?
60236: 03/09/08: Re: microblaze on XSV800
60261: 03/09/09: Re: Xilinx S3 I/O robustness question
60273: 03/09/09: opinions are OK
60312: 03/09/10: Re: Power on problems
60712: 03/09/19: Re: Xilinx
60769: 03/09/22: Re: Transistor count
60771: 03/09/22: Re: Xilinx S3 I/O robustness question
60784: 03/09/22: Re: Transistor count
60791: 03/09/22: Re: Xilinx S3 I/O robustness question
60825: 03/09/23: Re: Xilinx S3 I/O robustness question
60826: 03/09/23: Re: Xilinx S3 I/O robustness question
60827: 03/09/23: Re: Xilinx S3 I/O robustness question
60828: 03/09/23: Re: DCM virtex 2 doesn't lose lock
60838: 03/09/23: Re: Xilinx S3 I/O robustness question
60844: 03/09/23: Re: Xilinx S3 I/O robustness question
60883: 03/09/24: Re: Xilinx S3 I/O robustness question
60884: 03/09/24: Re: Regulator for Spartan 2
60898: 03/09/24: Re: Xilinx S3 I/O robustness question
60942: 03/09/25: Re: Xilinx S3 I/O robustness question
60944: 03/09/25: Re: Xilinx S3 I/O robustness: is that your final answer?
61007: 03/09/26: Re: Xilinx S3 I/O robustness question
61217: 03/09/30: Re: Bit error rate
61225: 03/09/30: Re: doubling clock rate does what to power consumption?
61243: 03/09/30: Ask the hotline, you may be surprised and pleased
61285: 03/10/01: Re: Ask the hotline, you may be surprised and pleased
61296: 03/10/01: Re: Ask the hotline, you may be surprised and pleased
61322: 03/10/01: Re: Ask the hotline, you may be surprised and pleased
61359: 03/10/02: Re: LVDS_25_DCI : Top Ten List
61427: 03/10/03: Re: LVDS_25_DCI : Top Ten List
61432: 03/10/03: Re: Xilinx courses
61524: 03/10/06: Re: Xilinx courses
61525: 03/10/06: Re: Interesting article about FPGAs
61528: 03/10/06: Re: LVDS_25_DCI : Top Ten List
61550: 03/10/06: Re: Xilinx courses
61552: 03/10/06: Re: Should I worry about metastability
61556: 03/10/06: Re: Xilinx courses
61558: 03/10/06: Re: Should I worry about metastability
61587: 03/10/07: Re: Xilinx courses
61589: 03/10/07: Re: LVDS_25_DCI : Top Ten List
61660: 03/10/08: ....and he left with his marbles.....
61670: 03/10/08: Re: 5V Tolerant Spartan 2
61677: 03/10/08: Re: syncing the CLK0 outputs of two DCMs if they use CLKIN_DIVIDE_BY_2
61714: 03/10/09: Re: Input capacitance
61718: 03/10/09: Re: syncing the CLK0 outputs of two DCMs if they use CLKIN_DIVIDE_BY_2
61721: 03/10/09: Re: Input capacitance: "L" vs "X"
61783: 03/10/10: Re: Virtex-II Pro Core Voltage on ML300
61858: 03/10/14: Re: Xilinx S3 I/O robustness question
61877: 03/10/14: Re: DCM driving multiple OBUF's ... skew in between ...
61937: 03/10/15: Re: SpartanXL
61939: 03/10/15: Re: SpartanXL
61940: 03/10/15: Re: Powersupply virtex 2 and spartan 3
61942: 03/10/15: Re: DCM driving multiple OBUF's ... skew in between ...
61943: 03/10/15: Re: Xilinx XAPP265 and 800Mb/sec data input....
61962: 03/10/15: Re: SpartanXL
61972: 03/10/15: Re: SpartanXL
62004: 03/10/16: Re: SpartanXL
62353: 03/10/27: Re: Are clock and divided clock synchronous?
62390: 03/10/28: Re: Are clock and divided clock synchronous?
62425: 03/10/29: Re: Are clock and divided clock synchronous?
62427: 03/10/29: Re: Are clock and divided clock synchronous?
62428: 03/10/29: Re: Virtex-II DCM frequency synthesizer
62429: 03/10/29: Re: Power calculation using Xpower
62436: 03/10/29: Electronic News Article on 90 nm soft error FUD
62443: 03/10/29: Re: Xilinx Spartan3: Price
62479: 03/10/30: Re: CLKFX problem with a Virtex II
62512: 03/10/31: Re: How to protect fpga based design against cloning?
62521: 03/10/31: Re: How to protect fpga based design against cloning?
62537: 03/10/31: Re: Electronic News Article on 90 nm soft error FUD
62542: 03/10/31: Re: Shannon Entropy for Black Holes
62625: 03/11/03: Re: Electronic News Article on 90 nm soft error FUD
62631: 03/11/03: Re: Shannon Entropy for Black Holes
62667: 03/11/04: Re: DCM recover after interruption of input clock
62668: 03/11/04: Re: Shannon Entropy for Black Holes
62681: 03/11/04: Re: help with 120MHz comparator
62746: 03/11/06: Re: Crossing/muxing clocks thru TBUF mux (w/DLL "stunts")
62793: 03/11/07: Re: Crossing/muxing clocks thru TBUF mux (w/DLL "stunts")
62794: 03/11/07: Re: Altera "my support" :-(
62795: 03/11/07: Re: ASIC speed
62858: 03/11/10: Re: VirtexII-Pro: Why is ICAP slower than SelectMAP?
62883: 03/11/10: Re: Home grown CPU core legal?
62934: 03/11/11: Re: DCM input clock
62937: 03/11/11: Re: Xilinx S3 I/O robustness question
63063: 03/11/13: Re: Transforming vector position to binary value
63166: 03/11/17: Re: Do I need to connect all Vref in a bank together?
63167: 03/11/17: Re: Power on problems
63190: 03/11/17: Re: Do I need to connect all Vref in a bank together?
63256: 03/11/18: Re: Xilinx DCM LOCKED signal valid after input clock returns?
63462: 03/11/21: Re: Differential terminations in Virtex2 Pro.
63467: 03/11/21: Re: Differential terminations in Virtex2 Pro.
63509: 03/11/24: Re: Differential terminations in Virtex2 Pro.Attempt II!
63555: 03/11/25: Re: 5V I/O with 1.8V Core
63557: 03/11/25: Re: Differential terminations in Virtex2 Pro.
63577: 03/11/25: Re: 5V I/O with 1.8V Core
63579: 03/11/25: Re: 5V I/O with 1.8V Core
63605: 03/11/26: Re: 5V I/O with 1.8V Core
63606: 03/11/26: Re: Input pins without Vcco supply-- Virtex-II
63708: 03/12/01: Re: 5V I/O with 1.8V Core
63709: 03/12/01: Re: jitter in Virtex2 DCM
63767: 03/12/03: Re: jitter in Virtex2 DCM
63837: 03/12/05: Re: XILINX FPGA: DCM locked Signal
63851: 03/12/05: Re: XILINX FPGA: DCM locked Signal
63944: 03/12/09: Re: ASMBL - hmmm ---- hmmmm -- Wow?
63959: 03/12/10: Re: ASMBL - hmmm ---- hmmmm -- Wow? -- "Hard-tocopy" rant -- skip
63973: 03/12/10: Re: Easypath question (was "Hard-tocopy" rant)
63983: 03/12/10: Re: ASMBL - hmmm ---- hmmmm -- Wow?
64084: 03/12/15: Re: Rocket IO testing
64164: 03/12/18: Re: powering spartan IIe
64462: 04/01/05: Re: Do all the Vertex DCM outs use same global clock tree?
64522: 04/01/06: Re: VirtexE DLL locked range
64612: 04/01/08: Re: Anybody know what the REAL story is? Play it again? Sam? Oh
64623: 04/01/09: Re: Anybody know what the REAL story is? Jim figured it out.
64624: 04/01/09: Re: Spartan3 IOB without supply
64804: 04/01/14: Re: ASMBL - hmmm ---- hmmmm -- Wow? -- "Hard-tocopy" rant -- skip
64822: 04/01/14: Re: ASMBL - hmmm ---- hmmmm -- Wow? -- "Hard-tocopy" rant -- skip
64873: 04/01/15: Re: yo, Mr. FPGA Engineer
64889: 04/01/15: Re: yo, Mr. FPGA Engineer
64934: 04/01/16: Re: Spartan-3 VCCINT
64947: 04/01/16: Re: Impact of voltage variations on timings for an FPGA
65245: 04/01/22: Spirit on Mars
65260: 04/01/22: Re: Xilinx LVDS_25_DT termination issues????
65284: 04/01/23: Re: Spirit on Mars
65285: 04/01/23: Re: Spirit on Mars
65289: 04/01/23: Re: Spirit on Mars, upsets on Earth -- does your vendor know? How?
65304: 04/01/23: Re: Spirit on Mars, upsets on Earth -- does your vendor know? How?
65363: 04/01/26: Re: Spirit on Mars, upsets on Earth -- does your vendor know? How?
65364: 04/01/26: Re: Spirit on Mars, upsets on Earth -- does your vendor know? How?
65374: 04/01/26: Re: Spirit on Mars, upsets on Earth -- does your vendor know? How?
65376: 04/01/26: Re: Spirit on Mars, upsets on Earth -- does your vendor know? How?
65395: 04/01/27: Re: Spirit on Mars, upsets on Earth -- does your vendor know? How?
65409: 04/01/27: Re: Spirit on Mars, upsets on Earth -- does your vendor know? How?
65425: 04/01/28: Re: Flip-Chip Package Substrate Solder Issue
65443: 04/01/29: Re: Flip-Chip Package Substrate Solder Issue
65465: 04/01/29: Re: PowerPC and JTAG
65481: 04/01/30: Re: V2Pro & PCI Problem?
65491: 04/01/30: Re: PowerPC and JTAG
65559: 04/02/02: Re: ASMBL
65574: 04/02/02: Re: Is it possible that a Virtex II device performs below its spec?
65580: 04/02/02: Re: ASMBL anxiety
65609: 04/02/03: Re: ASMBL anxiety
65610: 04/02/03: Re: Xilinx Virtex II Pro: LVDS_25 vs. BLVDS_25
65733: 04/02/05: Re: Do Xilinx Fix Their Prices?
65784: 04/02/06: Pricing, 101
65785: 04/02/06: Re: Rocket I/O receiver
65790: 04/02/06: Re: Help with BUFGMUX in Xilinx Virtex2 and Timing constraints ?
65807: 04/02/06: Re: Connecting FPU core on Virtex II Pro
65812: 04/02/06: Who do we serve?
65873: 04/02/09: Re: Pricing, 101
65948: 04/02/10: Re: Xilinx training
65960: 04/02/10: Re: Pricing, 101
66037: 04/02/11: Re: Spartan-3 shipping, or perhaps not!
66042: 04/02/11: Everything is not only shipping, but a lot of it shipped.....
66043: 04/02/11: Re: Spartan-3 shipping, or perhaps not!
66052: 04/02/11: Re: Spartan-3 shipping, or perhaps not!
66099: 04/02/12: Re: Pricing, 101
66133: 04/02/12: Re: Sensible starter FPGA board
66135: 04/02/12: Re: Peter's 1Hz-640MHz Synth project
66181: 04/02/13: Re: Using DLL "locked" output as a global reset signal ?
66432: 04/02/19: Re: Virtex-II Speed grade -6 exist?
66493: 04/02/20: Re: Virtex-II Speed grade -6 exist?
66494: 04/02/20: Re: altera, xilinx susceptible to power transients?
66591: 04/02/23: Re: FPGA vendors and their patents
66641: 04/02/24: Re: DCM Simulation Error
66661: 04/02/24: Re: Stratix 2 ALUT architecture patented ?
66695: 04/02/25: Re: Warning on DCM min frequency...
66696: 04/02/25: Re: Basic jitter from a CPLD (XC7500XL)
66698: 04/02/25: Re: Basic jitter from a CPLD (XC7500XL)
66768: 04/02/26: Re: Stratix 2 ALUT architecture patented ?
66787: 04/02/26: Re: Stratix 2 ALUT architecture patented ?
66805: 04/02/26: Re: Stratix 2 ALUT architecture patented ?
66850: 04/02/27: Re: Stratix 2 ALUT architecture patented ?
66936: 04/03/01: Re: Stratix 2 ALUT architecture patented ?
67049: 04/03/04: Re: Jitter in DLLs vs PLLs
67063: 04/03/04: Re: Jitter in DLLs vs PLLs
67120: 04/03/05: Re: Jitter in DLLs vs PLLs
67198: 04/03/08: Re: HOW to Increase jitter in ALTERA PLL ?
67206: 04/03/08: Re: NEWS: Xilinx announces acquisition of Triscend
67208: 04/03/08: Re: NEWS: Xilinx announces acquisition of Triscend
67351: 04/03/10: Re: Basic jitter from a CPLD (XC7500XL)
67358: 04/03/10: Re: copy protection on FPGA using embedded serial number
67363: 04/03/10: Re: Xilinx differential output voltage is adjustable.
67414: 04/03/11: Re: Xilinx differential output voltage is adjustable.
67818: 04/03/19: Re: LVTTL Spartan-3 pin input current...but if you give him a centimeter,
67897: 04/03/22: Re: Virtex2
67898: 04/03/22: Re: XCV2000E survived 3.3V core voltage!
67918: 04/03/22: Re: Xilinx and PCI
68010: 04/03/24: Re: Fried a XC2S200!
68012: 04/03/24: Re: How many times can I burn an FPGA?
68052: 04/03/25: Re: How many times can I burn an FPGA?
68053: 04/03/25: Re: Virtex-Fore
68081: 04/03/25: Re: Xilinx Virtex2Pro DDR output glitch free?
68110: 04/03/26: Homework Questions: where to find the best answers the fastest
68197: 04/03/29: Re: Spartan3 hot-swap configuration issue
68273: 04/03/31: Re: Metastablility
68328: 04/04/01: Re: The mapper is getting rid of all my logic!!
68372: 04/04/02: Re: Best price per I/O
68374: 04/04/02: Re: ML300 and GigE Experiences
68381: 04/04/02: Re: ML300 and GigE Experiences
68389: 04/04/02: Re: ML300 and GigE Experiences
68390: 04/04/02: Re: vertex II vs Stratix
68537: 04/04/07: Apples to Apples? Starrix Two <> Virtex II Pro
68550: 04/04/07: Re: Apples to Apples? Stratrix Two <> Virtex II Pro
68589: 04/04/08: Re: Apples to Apples? Stratrix Two <> Virtex II Pro
68590: 04/04/08: Re: Apples to Apples? Stratrix Two <> Virtex II Pro
68665: 04/04/13: Re: Apples to Apples? Stratrix Two <> Virtex II Pro
68694: 04/04/14: Re: Apples to Apples? Stratix II <> Virtex-II Pro
68723: 04/04/15: Re: Apples to Apples? Stratix II <> Virtex-II Pro
68761: 04/04/16: Re: Osborne [Was: Apples to Apples? Stratix II <> Virtex-II Pro]
68804: 04/04/19: Re: FPGA power supply circuits
68805: 04/04/19: Re: dumb question CPLD or FPGA
68942: 04/04/22: Re: PLL and DLL
68974: 04/04/23: Re: transport applications
69056: 04/04/26: Re: CPLD input
69158: 04/04/28: Re: Clock frequency converter from 1.544MHz to 2.048MHz (or multiples)
69179: 04/04/29: Re: I think I fried my I/O bank... (virtex-E question)
69188: 04/04/29: Re: package choice, temperature and obsolesence issues with a xilinx
69218: 04/04/30: Re: package choice, temperature and obsolesence issues with a xilinx
69345: 04/05/07: Re: Virtex2 (500) DCM Frequency Synthesize
69398: 04/05/10: Easypath
69417: 04/05/10: Re: unused IO on SPARTAN-IIE
69444: 04/05/11: Re: Effects of moisture on CPLD
69455: 04/05/11: EasyPath
69457: 04/05/11: Re: Effects of moisture on CPLD
69466: 04/05/11: Re: EasyPath
69500: 04/05/12: Re: Easypath question (was "Hard-tocopy" rant)
69501: 04/05/12: Re: Easypath
69514: 04/05/12: Re: Easypath -- Inspiration from Warner Brothers Anamainiacs?
69585: 04/05/14: Re: virtex dev board?
69752: 04/05/19: Re: Xilinx V2P: DCM and changing input clock
69754: 04/05/19: Re: Nios II Going Live...
69782: 04/05/19: S3 cheap shot
69804: 04/05/20: Never right, always room for improvement
69809: 04/05/20: Re: Xilinx V2P: DCM and changing input clock
69817: 04/05/20: Re: Never right, always room for improvement
69835: 04/05/21: Re: Never right, always room for improvement
69836: 04/05/21: Re: XIlinx V2P7: DCM won't lock
69904: 04/05/24: Re: Never right, always room for improvement
69905: 04/05/24: Re: Xilinx V2P: DCM and changing input clock
69910: 04/05/24: Re: Xilinx V2P: DCM and changing input clock
69911: 04/05/24: Re: XIlinx V2P7: DCM won't lock
69968: 04/05/25: Re: VHDL simple question: is 2-D array synthesizable
70093: 04/06/02: Re: tri-state in altera
70116: 04/06/03: Re: tri-state in altera and xilinx
70128: 04/06/03: Re: tri-state in altera and xilinx
70225: 04/06/09: Re: Digital Clock Manager (DCM) Question
70230: 04/06/09: Re: Digital Clock Manager (DCM) Question
70232: 04/06/09: Re: Digital Clock Manager (DCM) Question
70256: 04/06/10: Re: Virtex4: I don't understand their thinking....
70258: 04/06/10: Re: Virtex4: I don't understand their thinking....
70490: 04/06/17: Re: compressing Xilinx bitstreams
70636: 04/06/22: Family Photo Album
70644: 04/06/22: Re: Family Photo Album
70657: 04/06/22: Re: Family Photo Album
70685: 04/06/23: Re: Family Photo Album
70788: 04/06/28: Re: Family Photo Album
70797: 04/06/28: Re: Family Photo Album
70800: 04/06/28: Re: Family Photo Album
70820: 04/06/29: Re: Family Photo Album
70821: 04/06/29: Re: Family Photo Album
70822: 04/06/29: Re: Battle of the Vapours
70831: 04/06/29: Re: Family Photo Album
71144: 04/07/09: Re: Spartan 3 termination question (DCI)
71213: 04/07/12: Re: Spartan 3 termination question (DCI)
71214: 04/07/12: Re: Is the Xilinix XC3020 atill supported?
71242: 04/07/12: Re: speed in FPGA
71270: 04/07/13: Re: Xilinx Virtex 4
71319: 04/07/14: Re: Spartan 3 termination question (DCI)
71351: 04/07/15: Re: Spartan 3 termination question (DCI)
71386: 04/07/16: Re: Spartan 3 termination question (DCI)
71389: 04/07/16: Re: Spartan 3 termination question (DCI)
71395: 04/07/16: Re: ChipScope Pro : Stimulation
71496: 04/07/20: Re: Spartan 3 termination question (DCI)
71508: 04/07/20: Low Power Applications - enumerate
71592: 04/07/23: Re: XILINX RocketIO / MGT signal quality problems
71644: 04/07/26: Re: VHDL model of Xilinx's Rocket I/O MGT
71684: 04/07/27: Re: ramdon noise generation
71689: 04/07/27: Re: ramdon noise generation
71705: 04/07/28: Re: ramdon noise generation
71706: 04/07/28: Re: configuration SRAM cells in Xilinx/Altera FPGAs
71713: 04/07/28: XUP Support
71715: 04/07/28: Re: configuration SRAM cells in Xilinx/Altera FPGAs
71719: 04/07/28: Re: XILINX RocketIO / MGT signal quality problems
71720: 04/07/28: Re: XUP Support
71724: 04/07/28: Re: configuration SRAM cells in Xilinx/Altera FPGAs
71786: 04/07/30: Re: XILINX RocketIO / MGT signal quality problems
71910: 04/08/03: Re: 1GHz FPGA counters
71944: 04/08/04: Re: Can I use RocketIO to generate pulse edge with very high precision?
71957: 04/08/04: ES vs production
71964: 04/08/04: Re: practical Virtex2 output buffer speeds
72047: 04/08/06: Re: Comparing Quality of Results of FPGA CAD Tools
72048: 04/08/06: Re: Comparing Quality of Results of FPGA CAD Tools
72054: 04/08/06: Re: Comparing Quality of Results of FPGA CAD Tools
72392: 04/08/17: Re: Q: DCI used as current limiters?
72423: 04/08/18: Re: Regarding BIST in FPGA
72464: 04/08/19: Re: Spartan III I/O robustness
72488: 04/08/20: Re: Spartan III I/O robustness
72550: 04/08/24: Re: SSO and decoupling relationship
72551: 04/08/24: Re: Maximum allowable ground bounce for xilinx fpgas
72619: 04/08/26: Re: 6.1 vs. 6.2
72647: 04/08/27: Re: Xilinx DCM Spread Spectrum feature
72728: 04/08/30: Re: Xilinx Spartan II and 5V PCI
72729: 04/08/30: Re: Xilinx Spartan II and 5V PCI
72744: 04/08/31: Re: Xilinx DCM Spread Spectrum feature
72765: 04/08/31: Re: Xilinx Spartan II and 5V PCI
72766: 04/08/31: Re: Xilinx Spartan II and 5V PCI
72767: 04/08/31: Re: Xilinx Spartan II and 5V PCI
73723: 04/09/28: Re: Spartan-3 VCCIO ramp up time
73795: 04/09/29: Re: Read back FPGA configuration
73810: 04/09/29: Re: NV on-chip memory?
73812: 04/09/29: Re: NV on-chip memory?
73816: 04/09/29: Re: DISCLOSURE : NV on-chip memory?
73862: 04/09/30: Re: Read back FPGA configuration
73863: 04/09/30: Re: NV on-chip memory?
73864: 04/09/30: Re: ELABORATED DISCLOSURE and continued discussion : NV on-chip
73872: 04/09/30: Re: Read back FPGA configuration
73878: 04/09/30: Re: Spartan-3 VCCIO ramp up time
73895: 04/09/30: Re: Spartan-3 VCCIO ramp up time
73903: 04/09/30: Re: ASIC vs FPGA and In-Circuit Reconfigurability (ICR)?
73906: 04/09/30: Re: MicroBlaze is no available as Open-Source!! (from independant
73939: 04/10/01: Re: ASIC vs FPGA and In-Circuit Reconfigurability (ICR)?
73941: 04/10/01: Re: FPGA vs ASIC area
73943: 04/10/01: Re: FPGA vs ASIC area
73966: 04/10/01: Re: FPGA vs ASIC area
73968: 04/10/01: Re: FPGA vs ASIC area
72970: 04/09/09: Re: ISE 6.2 - Bug or folly?
72971: 04/09/09: Re: Xilinx Virtex2: Erroneous DCM "Tap" Position after Reset
73018: 04/09/10: Re: Xilinx Virtex2: Erroneous DCM "Tap" Position after Reset
73031: 04/09/10: Re: Xilinx Virtex2: Erroneous DCM "Tap" Position after Reset
73071: 04/09/13: Virtex 4 released today
73080: 04/09/13: Re: Virtex 4 released today
73114: 04/09/14: Re: Virtex 4 released today
73115: 04/09/14: Re: Would flash/antifuse-based vendors be more likely to disclose
73125: 04/09/14: Re: Virtex 4 released today
73142: 04/09/14: Re: Virtex 4 released today
73179: 04/09/15: Re: Virtex 4 released today
73180: 04/09/15: Re: Virtex 4 released today
73181: 04/09/15: Re: Virtex 4 released today
73182: 04/09/15: Re: Virtex 4 released today
73183: 04/09/15: Re: CLK2X
73248: 04/09/16: Re: Virtex 4 released today
73253: 04/09/16: Re: Virtex 4 released Monday, and we are still learning about it......
73277: 04/09/17: Re: Virtex 4 released Monday, and we are still learning about it......
73278: 04/09/17: Re: Would flash/antifuse-based vendors be more likely to disclose
73289: 04/09/17: Re: Statix II vs. Virtex 4
73356: 04/09/20: Re: Would flash/antifuse-based vendors be more likely to disclose
73357: 04/09/20: Re: Statix II vs. Virtex 4
73370: 04/09/20: Re: Virtex 4 integrated A/Ds? Yes it does.
73404: 04/09/21: Re: Virtex 4 integrated A/Ds? Yes it does.
73405: 04/09/21: Re: Ring Oscillator Redux
73406: 04/09/21: Re: Stratix II vs. Virtex 4 - power
73407: 04/09/21: Re: Stratix II vs. Virtex 4 - power
73519: 04/09/22: Re: Stratix II vs. Virtex 4 - power
73547: 04/09/23: Re: Stratix II vs. Virtex 4 - features and performance
73647: 04/09/27: Re: xilinx spice models
74981: 04/10/22: Re: VCXO Emulation, or using a DLL to shift phase infinitely, or
75035: 04/10/25: Re: Low-power FPGAs?
75041: 04/10/25: Re: Low-power FPGAs?
75042: 04/10/25: Re: Low-power FPGAs?
75046: 04/10/25: Re: Low-power FPGAs?
75062: 04/10/25: Re: Low-power FPGAs?
75105: 04/10/26: Re: Low-power FPGAs?
75106: 04/10/26: Re: Low-power FPGAs?
75109: 04/10/26: Re: PCBs for modern FPGAs.
75111: 04/10/26: Re: JTAG Configuration
75113: 04/10/26: Re: JTAG Configuration
75115: 04/10/26: Re: JTAG Configuration
75130: 04/10/26: Re: JTAG Configuration
75138: 04/10/26: Re: Low-power FPGAs?
75150: 04/10/27: Re: JTAG Configuration
75330: 04/11/02: Re: Question on Xilinx VirtexProII PCMCIA support (FPGA boards)....
74132: 04/10/04: Re: Is it possible to Reverse-Engineer an FPGA Output file?
74186: 04/10/05: Re: Xilinx Multiple Clock Domains
74245: 04/10/06: Re: Xilinx Multiple Clock Domains
74246: 04/10/06: Re: FPGA vs ASIC area
74254: 04/10/06: Re: DCM and CLKFX - is this allowed?
74265: 04/10/06: Re: IBM Paper with answer to FPGA vs ASIC comparisons
74299: 04/10/07: Re: DCM and CLKFX - is this allowed?
74308: 04/10/07: Re: FPGA vs ASIC area
74310: 04/10/07: Re: IBM Paper with answer to FPGA vs ASIC comparisons
74348: 04/10/08: Re: FPGA vs ASIC area
74442: 04/10/11: Re: Xilinx DCMs
74478: 04/10/12: Re: DCM for generating higher frequencies.
74483: 04/10/12: Re: DCM for generating higher frequencies.
74486: 04/10/12: Re: DCM for generating higher frequencies.
74531: 04/10/13: Re: multiplexing clocks
74532: 04/10/13: Re: spartan 3 on 4 layers
74537: 04/10/13: Re: Problem in Xilinx Rocket IO Simulation using HyperLynx SI tool
74629: 04/10/15: Re: spartan 3 on 4 layers
74646: 04/10/15: Re: spartan 3 on 4 layers
74647: 04/10/15: Re: Metastability pipeline causes bad juju
74662: 04/10/15: Re: spartan 3 on 4 layers
74760: 04/10/18: Re: Virtex 4 released today
74796: 04/10/19: Re: spartan 3 on 4 layers
74810: 04/10/19: Re: spartan 3 on 4 layers
74844: 04/10/20: Re: bufgmux
74857: 04/10/20: Re: bufgmux
74880: 04/10/20: Re: spartan 3 on 4 layers
75396: 04/11/04: Re: CPLDs and Safety? Re: ASICs Vs. FPGA in Safety Critical Apps.
75398: 04/11/04: Re: Spartan3 Engineering Sample Performance?
75432: 04/11/05: Re: CPLDs and Safety? Re: ASICs Vs. FPGA in Safety Critical Apps.
75433: 04/11/05: Re: Number of FPGA users?
75434: 04/11/05: Re: Low-power FPGAs?
75445: 04/11/05: Re: Number of FPGA users?
75530: 04/11/08: Re: diode recovery time for Spartan 3
75553: 04/11/09: Re: FPGA as "Differential SSTL_2" clock driver
75584: 04/11/10: Re: FPGA as "Differential SSTL_2" clock driver
75585: 04/11/10: Re: Overshoot/undershoot towards 2V4000
75652: 04/11/11: Re: Overshoot/undershoot towards 2V4000
75653: 04/11/11: Re: Xilinx and Altera -- maximum total bitrate for high-speed serial
75699: 04/11/12: Re: Xilinx and Altera -- maximum total bitrate for high-speed serial
75788: 04/11/15: Re: Xilinx and Altera -- maximum total bitrate for high-speed serial
75789: 04/11/15: Re: Driving towards 2V4000 during Power up
75790: 04/11/15: Re: IO pins : short circuit protection ?
75802: 04/11/15: Re: Help with Virtex II and 5v TTL
75814: 04/11/15: Re: IO pins : short circuit protection ?
75830: 04/11/16: Re: Help with Virtex II and 5v TTL
75866: 04/11/17: Re: 5V inputs with series resistor on Spartan-3
75897: 04/11/18: Re: Vccaux on Spartan 3
75904: 04/11/18: Re: 5V inputs with series resistor on Spartan-3
75933: 04/11/19: Re: RocketIO success?
75938: 04/11/19: Re: RocketIO success?
76014: 04/11/22: Re: Xilinx S3 IO during programming latches Cypress FX2 Reset
76074: 04/11/23: Re: Spartan 3L - read the offering and see if it is what you want?
76089: 04/11/24: Re: Spartan 3L - read the offering and see if it is what you want?
76090: 04/11/24: Re: Choice of FPGA device -- my view on benchmarks
76279: 04/11/29: Re: Xilinx and Altera -- maximum total bitrate for high-speed serial
76280: 04/11/29: Re: lowest-cost FPGA
76306: 04/11/30: Re: lowest-cost FPGA
76307: 04/11/30: Re: Pin connection doubts
76308: 04/11/30: Re: RocketIO success? Shame on you....
76310: 04/11/30: Re: Xilinx Virtex 4 question
76328: 04/11/30: Re: CMOS capacitive loads, transition probabilities and FPGAs
76350: 04/11/30: Re: Pin connection doubts
76388: 04/12/01: Re: Xilinx Virtex 4 question
76389: 04/12/01: Re: CMOS capacitive loads, transition probabilities and FPGAs
76396: 04/12/01: Re: Xilinx Virtex 4 question
76397: 04/12/01: Re: Xilinx Virtex 4 question
76421: 04/12/01: Re: Xilinx Virtex 4 question
76440: 04/12/02: Re: Does Easypath make sense for a XC2S15 @ 20K units?
76458: 04/12/02: Re: FPGA Floating Point core IPs
76477: 04/12/03: Re: Searching for rad tolerant, non-volatile (once programmable)
76478: 04/12/03: Re: making an fpga hot
76562: 04/12/06: Re: Virtex II : 3V3 to 1,8V IOB VCC
76614: 04/12/07: Performance claims
76625: 04/12/07: Re: Performance claims
76629: 04/12/07: Re: Performance claims
76825: 04/12/13: Re: Xilinx S3 late arriving DCM clkin
76890: 04/12/15: Re: Xilinx speed grading
76891: 04/12/15: Re: Virtex2 I/O standards
76901: 04/12/15: Re: Virtex2 I/O standards
76903: 04/12/15: Re: Xilinx speed grading
76920: 04/12/15: Re: Xilinx speed grading
76950: 04/12/16: Re: Xilinx speed grading
76951: 04/12/16: Re: Xilinx speed grading
77045: 04/12/20: Re: Using low-core-voltage devices in industrial applications
77061: 04/12/21: Re: Using low-core-voltage devices in industrial applications
77068: 04/12/21: Re: Using low-core-voltage devices in industrial applications
77079: 04/12/21: Re: Using low-core-voltage devices in industrial applications
77080: 04/12/21: Re: Using low-core-voltage devices in industrial applications
77099: 04/12/22: Re: Using low-core-voltage devices in industrial applications
77103: 04/12/22: Re: Using low-core-voltage devices in industrial applications
77116: 04/12/23: Re: Using low-core-voltage devices in industrial applications
77120: 04/12/23: Re: Using low-core-voltage devices in industrial applications
77167: 04/12/27: Noise Margins of low voltage core FPGAs translates into Jitter Issues
77373: 05/01/05: Re: Spartan-3 PQ/TQ/VQ SSO guidelines
77374: 05/01/05: Re: Tracking down HardWired History
77383: 05/01/05: Re: Spartan-3 PQ/TQ/VQ SSO guidelines
77389: 05/01/05: Re: Spartan-3 PQ/TQ/VQ SSO guidelines
77414: 05/01/06: Re: Tracking down HardWired History
77435: 05/01/06: Re: Tracking down HardWired History
77569: 05/01/11: Re: How protection diodes 'wear out'.
77570: 05/01/11: Re: Editting spartan-3 bitstream to change dcm values
77576: 05/01/11: Re: Beware of Vref pins becoming "unused" (Xilinx)
77578: 05/01/11: Re: Beware of Vref pins becoming "unused" (Xilinx)
77586: 05/01/11: Re: Beware of Vref pins becoming "unused" (Xilinx)
77704: 05/01/14: Re: Programming and copyright
77787: 05/01/17: Re: HardCopy costs- the hidden ones
77802: 05/01/17: Re: Tracking down HardWired History
77917: 05/01/20: Hardened Logic and SEUs
77946: 05/01/20: Re: Hardened Logic and SEUs
78820: 05/02/08: Re: See Peter's High-Wire Act next Tuesday
78823: 05/02/08: Re: See Peter's High-Wire Act next Tuesday
78995: 05/02/10: Re: Variable phase shift on Spartan3 DCMs. Does it work?
79039: 05/02/11: Re: Variable phase shift on Spartan3 DCMs. Does it work?
79199: 05/02/15: Re: See the next high-wire act, this time on power consumption
79201: 05/02/15: Re: Updated Stratix II Power Specs & Explanation [And a Junction
79226: 05/02/15: Re: See the next high-wire act, this time on power consumption
79228: 05/02/15: Re: Updated Stratix II Power Specs & Explanation
79273: 05/02/16: Re: See the next high-wire act, this time on power consumption
79274: 05/02/16: Re: Updated Stratix II Power Specs & Explanation
79275: 05/02/16: Re: Updated Stratix II Power Specs & Explanation
79328: 05/02/17: Re: Updated Stratix II Power Specs & Explanation
79401: 05/02/18: Re: Updated Stratix II Power Specs & Explanation
79402: 05/02/18: Re: Updated Stratix II Power Specs & Explanation
79403: 05/02/18: Re: Is Altera Cyclone a good choice ?
79416: 05/02/18: Re: Xilinx: Pitfalls of chaining DLLs
79424: 05/02/18: Re: Issues with a batch of Virtex-II chips
79637: 05/02/22: Re: Issues with a batch of Virtex-II chips
79649: 05/02/22: Re: Xilinx: Pitfalls of chaining DLLs
79655: 05/02/22: Re: Hardcopy Vs ASIC
79704: 05/02/23: Re: Hardcopy Vs ASIC
79717: 05/02/23: Signal Integrity break-through: V4 packaging
79718: 05/02/23: The real performance leader: V4
79748: 05/02/23: Re: Hardcopy Vs ASIC
79749: 05/02/23: Re: Hardcopy Vs ASIC
79750: 05/02/23: Re: Signal Integrity break-through: V4 packaging
79752: 05/02/23: Re: The real performance leader: V4
79802: 05/02/24: Re: The real performance leader: V4
79803: 05/02/24: Re: Signal Integrity break-through: V4 packaging
79810: 05/02/24: Re: The real performance leader: V4
79874: 05/02/25: Re: IP unnecessarily using Spartan-3 DCM?
79877: 05/02/25: Re: Virtex4 : speed improvement
79890: 05/02/25: Re: IP unnecessarily using Spartan-3 DCM?
79892: 05/02/25: Re: Virtex-4 performance, where is it?
79901: 05/02/25: Re: Virtex-4 performance, where is it?
79902: 05/02/25: Re: Virtex-4 performance, where is it?
79912: 05/02/25: Re: Maximum Current utilized by Spartan-3
80086: 05/03/01: Why We Post*
80186: 05/03/02: Re: RocketIO, where to start?
80187: 05/03/02: Re: Xilinx ISE7.1
80199: 05/03/02: Re: Signal Integrity, ground bounce, crosstalk, SSOs, BGA pin-outs,
80224: 05/03/02: Re: Signal Integrity, ground bounce, crosstalk, SSOs, BGA pin-outs,
80225: 05/03/02: Re: Signal Integrity, ground bounce, crosstalk, SSOs, BGA pin-outs,
80242: 05/03/02: Re: Fault Tolerant FPGA design
80305: 05/03/03: Re: V4 SI: The package is thrilling Explanation of Cin
80320: 05/03/03: Re: V4 SI: The package is thrilling, but the Cin is bleak
80365: 05/03/04: Re: V4 SI: The package is thrilling, but the Cin is bleak
80376: 05/03/04: Re: Xilinx/Howard Johnson's crosstalk web seminar
80381: 05/03/04: Re: Xilinx/Howard Johnson's crosstalk web seminar
80505: 05/03/07: Surge in S2? ~3 amperes at cold for a millisecond
80506: 05/03/07: Re: Surge in S2? ~3 amperes at cold for a millisecond
80513: 05/03/07: Re: Surge in S2? ~3 amperes at cold for a millisecond
80525: 05/03/07: Re: Surge in S2? ~3 amperes at cold for a millisecond-- on ES material,
80565: 05/03/08: Re: Surge in S2? ~3 amperes at cold for a millisecond
80566: 05/03/08: Re: Surge in S2? ~3 amperes at cold for a millisecond
80567: 05/03/08: Re: Surge in S2? ~3 amperes at cold for a millisecond-- on ES material,
80651: 05/03/09: Re: Xilinx vs Altera high-end solutions
80666: 05/03/09: Re: Xilinx vs Altera high-end solutions
80669: 05/03/09: Re: Xilinx vs Altera high-end solutions
80712: 05/03/10: Re: Xilinx vs Altera high-end solutions
80713: 05/03/10: Re: Xilinx vs Altera high-end solutions
80714: 05/03/10: Iccint(max)
80718: 05/03/10: Re: Xilinx vs Altera high-end solutions
80727: 05/03/10: Re: Xilinx vs Altera high-end solutions
80729: 05/03/10: Re: Xilinx vs Altera high-end solutions
80796: 05/03/11: Re: Xilinx vs Altera high-end solutions
80938: 05/03/14: Re: XC3000 non-recoverable lockup problem
81043: 05/03/16: Re: spartan3E price
81183: 05/03/18: Re: Spartan 3E vs. Cyclone2
81315: 05/03/21: Re: Spartan 3E vs. Cyclone2
81369: 05/03/22: Re: XC3000 non-recoverable lockup problem
81382: 05/03/22: Re: XC3000 non-recoverable lockup problem
81431: 05/03/23: Re: XC3000 non-recoverable lockup problem
81432: 05/03/23: Re: XC3000 non-recoverable lockup problem
81439: 05/03/23: Re: XC3000 non-recoverable lockup problem
81448: 05/03/23: Re: XC3000 non-recoverable lockup problem
81648: 05/03/29: Re: XC3000 non-recoverable lockup problem
81659: 05/03/29: Re: XC3000 non-recoverable lockup problem
81726: 05/03/30: Re: Software Defined Radio
81821: 05/04/01: 4/1
81985: 05/04/05: Re: Reverse engineering ASIC into FPGA
82088: 05/04/06: Re: Single Event Functional Interrupts (SEFI) in Virtex
82089: 05/04/06: Re: Single Event Functional Interrupts (SEFI) in Virtex
82100: 05/04/06: Re: Single Event Functional Interrupts (SEFI) in Virtex
82102: 05/04/06: Re: LVDS PCI card is needed
82152: 05/04/07: Re: Single Event Functional Interrupts (SEFI) in Virtex
82162: 05/04/07: Re: Single Event Functional Interrupts (SEFI) in Virtex
82421: 05/04/12: Re: 5V PCI interface
82491: 05/04/13: Re: 5V PCI interface
82520: 05/04/13: Re: "The ISE 7.1 Experience"
82530: 05/04/13: Re: 5V PCI interface
82605: 05/04/14: Re: 5V PCI interface
82652: 05/04/15: Re: DCI question
82904: 05/04/19: Charge-pumps in FPGAs? Not Since 1998
82961: 05/04/20: Re: Charge-pumps in FPGAs? Not Since 1998
82962: 05/04/20: Re: Virtex II Scrubbing, Readback and Reconfiguration time durations
82976: 05/04/20: subjects should reflect the subject
82977: 05/04/20: Re: LVDS pin assignment
82979: 05/04/20: Re: Charge-pumps in FPGAs? Not Since 1998
83006: 05/04/21: Re: Soft CPU vs Hard CPU's
83063: 05/04/22: Re: Virtex-4 Routing
83178: 05/04/25: Re: Virtex 4 Power consumption
83190: 05/04/25: Re: Virtex 4 Power consumption
83191: 05/04/25: Re: Experience with Hitech Global & Xilinx
83239: 05/04/26: Re: Virtex 4 Power consumption
83242: 05/04/26: Re: Experience with Hitech Global & Xilinx
83244: 05/04/26: Re: Experience with Hitech Global & Xilinx
83273: 05/04/26: Re: Virtex 4 Power consumption
83573: 05/05/03: Re: Xilinx V4 Power Calculations
83593: 05/05/03: Re: Xilinx V4 Power Calculations
83605: 05/05/03: Re: Xilinx V4 Power Calculations
83606: 05/05/03: Re: 5V PCI interface
83629: 05/05/04: Re: Virtex 4 Power consumption
83639: 05/05/04: Re: Xilinx V4 Power Calculations
83706: 05/05/05: Re: Xilinx V4 Power Calculations
83719: 05/05/05: Re: System Ace: How many FPGA's in the JTAG chain before require
83761: 05/05/06: Re: Xilinx V4 Power Calculations
83764: 05/05/06: Re: Using capacitor to slow the rise time.
83783: 05/05/06: 40% less SEU's! in V4: another good reason to choose Xilinx
84029: 05/05/11: Re: Virtex4 running at 360Mhz DDR
84044: 05/05/11: Re: Virtex4 running at 360Mhz DDR
84047: 05/05/11: Re: Virtex4 running at 360Mhz DDR
84053: 05/05/11: Re: Virtex4 running at 360Mhz DDR
84090: 05/05/12: Re: Virtex4 running at 360Mhz DDR
84093: 05/05/12: Re: Virtex4 running at 360Mhz DDR
84118: 05/05/12: Re: Virtex4 running at 360Mhz DDR
84131: 05/05/12: Re: V4 vs. Stratix-II...
84155: 05/05/13: Re: V4 vs. Stratix-II...fabric only thread...LUT details...
84174: 05/05/13: Re: V4 vs. Stratix-II...fabric only thread...LUT details...
84330: 05/05/17: Re: Virtex4 running at 360Mhz DDR
84333: 05/05/17: Re: 40% less SEU's! in V4: another good reason to choose Xilinx
84335: 05/05/17: Re: V4 vs. Stratix-II...
84347: 05/05/17: Re: V4 vs. Stratix-II...
84355: 05/05/17: Re: V4 vs. Stratix-II...
84404: 05/05/18: Re: DDR2 based Xilinx Development boards ?
84802: 05/05/27: Re: Altera Apex20KE PLL output jitter problem
85161: 05/06/06: Re: Spartan 3 Starter kit group formed
85198: 05/06/06: Re: not clear about doing power estimation using xpower
85200: 05/06/06: Re: Clock doubler to double an input 13.5 Mhz
85277: 05/06/07: Re: not clear about doing power estimation using xpower
85278: 05/06/07: Re: VirtexII:DCM:CLKFX phase delay
85368: 05/06/08: General gripe session ....
85375: 05/06/08: Re: VirtexII:DCM:CLKFX phase delay
85381: 05/06/08: Re: Available under the terms of the SignOnce IP License
85385: 05/06/08: Re: General gripe session ....
85390: 05/06/08: Re: Great Tutorial on Signal Integrity, SSOs, Ground Bounce etc
85391: 05/06/08: Re: General gripe session ....
85425: 05/06/09: Re: Available under the terms of the SignOnce IP License
85444: 05/06/09: Re: pcb layers on BGAs Spartan-3
85461: 05/06/09: Re: General gripe session ....
85513: 05/06/10: Re: General gripe session ....
85516: 05/06/10: Re: not clear about doing power estimation using xpower
86064: 05/06/21: Re: : Parts Back on Xilinx Online Store (www.xilinx.com/store)
86088: 05/06/21: Re: FPGAs: Where will they go?
86235: 05/06/23: Re: Xilinx Power Requirements V2PRO complaint
86236: 05/06/23: Re: Virtex-4 FX20 device availablity issue
86265: 05/06/23: Re: Xilinx webshop
86266: 05/06/23: Re: XILINX DCMs and synthesis results
86455: 05/06/28: Re: Good FPGA for an encryptor
86458: 05/06/28: Re: Good FPGA for an encryptor
86469: 05/06/28: V4 and NBTI answer
86520: 05/06/29: Re: Good FPGA for an encryptor
86521: 05/06/29: Re: Good FPGA for an encryptor
86522: 05/06/29: Re: V4 and NBTI question, again..
86541: 05/06/29: Re: Good FPGA for an encryptor
86544: 05/06/29: Re: V4 and NBTI question, again..
86592: 05/06/30: Re: Good FPGA for an encryptor
86593: 05/06/30: Re: V4 and NBTI question, again..
86594: 05/06/30: Re: Xilinx Virtex 4 device technology
86606: 05/06/30: Re: Good FPGA for an encryptor
86607: 05/06/30: Re: Good FPGA for an encryptor
86637: 05/07/01: Re: V4 and DDR2 666
86776: 05/07/06: Re: fastest FPGA speed grade? Not the only measure, but ...
86851: 05/07/07: Re: fastest FPGA speed grade? Not the only measure, but ...
86852: 05/07/07: Re: Has anybody run Virtex-4 FPGAs at 300MHz+ interface speed?
86854: 05/07/07: Re: Xilinx Virtex 4 device technology
86855: 05/07/07: Re: aurora reliability
88249: 05/08/12: Re: ASIC suggestions
88318: 05/08/15: Re: Delay implementation and logic optimization.
88329: 05/08/15: Re: Clock generation
88332: 05/08/15: Re: Peter Alfke's SPDT Switch Debouncer
88367: 05/08/16: Re: XC5200 tool help needed
88368: 05/08/16: Re: Peter Alfke's SPDT Switch Debouncer
88458: 05/08/18: Re: super fast divide-by-N
88472: 05/08/18: Re: Antti's last comp.arch.fpga posting
88485: 05/08/19: Re: looking for OLD OLD software
88490: 05/08/19: Re: Best FPGA for floating point performance
88494: 05/08/19: Re: Best FPGA for floating point performance
88498: 05/08/19: Re: Best FPGA for floating point performance
88545: 05/08/22: Re: Peter Alfke's SPDT Switch Debouncer
88927: 05/08/31: Re: Hello A newbie to FPGA
89001: 05/09/02: Re: Spartan3 PCI SSO(Simultaneously Switching Output) problem
89016: 05/09/02: Re: Spartan3 PCI SSO(Simultaneously Switching Output) problem
89192: 05/09/07: Re: Fastest input IOB on a Spartan-3?
89207: 05/09/07: Re: Fastest input IOB on a Spartan-3?
89373: 05/09/13: Re: place and route
89409: 05/09/14: Re: Spartan-3 1000 -5 availability
89651: 05/09/21: Re: Xilinx Spartan-3
89660: 05/09/21: Re: Xilinx Spartan-3
89667: 05/09/21: Re: Xilinx Spartan-3
89780: 05/09/26: Re: jbits & reverse engineering
89790: 05/09/26: Re: jbits & reverse engineering
90085: 05/10/04: Re: Radiation + CoolRunner2 CPLD?
90093: 05/10/04: EasyPath, demystified
90094: 05/10/04: Re: Radiation + CoolRunner2 CPLD?
90102: 05/10/04: Re: EasyPath, demystified
90103: 05/10/04: Re: EasyPath, demystified
90145: 05/10/05: Re: EasyPath, demystified
90146: 05/10/05: Re: Where to get informations about Virtex 4 FX Engineering Samples
90155: 05/10/05: Re: Avoiding meta stability?
90193: 05/10/06: Re: Avoiding meta stability? No where in this thread...
90218: 05/10/06: Avoiding meta stability? Finally...? Don't use SRL16 as a synchronizer
90281: 05/10/07: Re: Question about metastability that's been on my mind for a while
90323: 05/10/10: Re: Power on reset generation in FPGA
90327: 05/10/10: Re: How many decoupling capacitors need on one device?
90462: 05/10/13: Re: Anyone remember the really early Xilinx FPGAs?
90488: 05/10/14: Re: Anyone remember the really early Xilinx FPGAs?
90584: 05/10/17: Rosetta Results
90650: 05/10/18: Re: Rosetta Results
90681: 05/10/18: Re: Newbie question: XC3S400 Gate Count
90714: 05/10/19: Re: Rosetta Results
90721: 05/10/19: Re: MAC Architectures
90751: 05/10/20: Re: Rosetta Results
90816: 05/10/21: Re: Rosetta Results
91023: 05/10/27: Re: Cost to go from FPGA to ASIC
91024: 05/10/27: Re: Cost to go from FPGA to ASIC
91027: 05/10/27: Re: Single Event Upset
91045: 05/10/27: Re: Cost to go from FPGA to ASIC
91069: 05/10/28: Re: Cost to go from FPGA to ASIC
91826: 05/11/14: Re: Xilinx flip-chip PCB processing
91938: 05/11/17: Re: Suggestions on good books
91951: 05/11/17: Re: DCM corner issue
91981: 05/11/18: Re: DCM corner issue
91983: 05/11/18: Re: FPGA Reconfiguration : Virtex-4 Frames
91984: 05/11/18: Re: hi everyone, tell me something about Cyclone II.
91992: 05/11/18: Re: FPGA Reconfiguration : Virtex-4 Frames
92121: 05/11/22: Re: Stupid reset question
92555: 05/12/01: Re: Virtex 4 FIFO16 blocks - Corruption ?
92569: 05/12/01: Re: Virtex 4 FIFO16 blocks - Corruption ?
92573: 05/12/01: Re: Virtex 4 FIFO16 blocks - Corruption ?
92577: 05/12/01: Re: Virtex 4 FIFO16 blocks - Corruption ?
92581: 05/12/01: Re: Xilinx LUT behavior question
92627: 05/12/02: Re: Virtex 4 FIFO16 blocks - Corruption ?
92628: 05/12/02: Re: Xilinx LUT behavior question
92629: 05/12/02: What if....
92641: 05/12/02: Re: What if....
92648: 05/12/02: Re: Virtex 4 FIFO16 blocks - Corruption ?
92712: 05/12/05: What's wrong with the document?
92720: 05/12/05: Re: What's wrong with the document?
92727: 05/12/05: Re: What's wrong with the document?
92760: 05/12/06: Re: xilinx research labs
92775: 05/12/06: Re: xilinx research labs
92776: 05/12/06: Re: Virtex 4 FIFO16 blocks - Corruption ?
92844: 05/12/07: Re: Embedded ppc405 w/o RAM?
92874: 05/12/08: Re: Embedded ppc405 w/o RAM?
92931: 05/12/09: Re: XC4VFX12 -- availability?
93025: 05/12/12: Re: Hello PPl, is there a way of locking a design (NGC) to a particular
93035: 05/12/12: Re: FPGA in industrial environment
93039: 05/12/12: Re: 3/2 with virtex 300
93041: 05/12/12: Re: 3/2 with virtex 300
93195: 05/12/15: Re: Mission critical & low core voltages
93197: 05/12/15: Re: Mission critical & low core voltages
93198: 05/12/15: Re: Xilinx DCM Shuts down at 75degree centigrade
93200: 05/12/15: Re: Xilinx' encrypted HPICE models in PSPICE
93291: 05/12/19: Re: Powering unused MGTs in XC4VFX20CES2
93343: 05/12/20: Re: Virtex-4 clocking
93419: 05/12/21: Re: Place and Route Algorithms: where's the fat?
93459: 05/12/22: Re: Place and Route Algorithms: where's the fat?
93460: 05/12/22: Re: Place and Route Algorithms: where's the fat?
93477: 05/12/22: Re: Place and Route Algorithms: where's the fat? here's some beef?
93643: 05/12/27: Re: Xilinx Stepping Methodology
93652: 05/12/27: Re: Virtex-4 CCLK termination
93682: 05/12/28: Re: Xilinx Stepping Methodology
93694: 05/12/28: Re: Xilinx LVDS termination resistor
93699: 05/12/28: Power Optimization: can the routing and placement really save power?
93701: 05/12/28: Re: What is 'drive strength' for? (Spartan 3)
93708: 05/12/28: Re: What is 'drive strength' for? (Spartan 3)
93709: 05/12/28: Re: Power Optimization: can the routing and placement really save
93711: 05/12/28: Re: Virtex-4 CCLK termination
93741: 05/12/29: Re: Virtex-4 CCLK termination
93742: 05/12/29: Re: System Monitor in Virtex-4: alive? or dead? or just forgotten?
93921: 06/01/03: Re: basic DSP with FPGA
93910: 06/01/03: Re: optimization tips (badly) needed
93917: 06/01/03: Re: optimization tips (badly) needed
93909: 06/01/03: Re: Clock generation
93920: 06/01/03: Re: Xilinx Spartan3E Sample Pack: Real fun for all Ages!
93942: 06/01/03: Re: Xilinx upgrade issues
93945: 06/01/03: Re: Xilinx upgrade issues
93946: 06/01/03: Re: Xilinx upgrade issues
93996: 06/01/04: Re: DCM spartan 3 variable frequency divider
94005: 06/01/04: Re: DCM spartan 3 variable frequency divider
94027: 06/01/04: Re: Schematic Entry, Xilinx or Altera?
94080: 06/01/05: Re: Xilinx DCM
94092: 06/01/05: Re: Do you name your FPGA?
94100: 06/01/05: Re: Do you name your FPGA?
94345: 06/01/10: Re: PCI compliance ?
94361: 06/01/10: Re: PCI compliance ?
94310: 06/01/09: Re: Stepping vs. ES
94359: 06/01/10: Re: FPGA configuration time for PCI identification ?
94424: 06/01/11: Back to Power?
94443: 06/01/11: Re: DCI power variations
94449: 06/01/11: Re: More Vehemence and mis-direction aimed at me, personally?
94506: 06/01/12: Re: FPGA Journal Article
94872: 06/01/18: Re: FPGA Journal Article
94883: 06/01/18: Re: FPGA Journal Article
94508: 06/01/12: Re: OT: RoHS and Lead?
94559: 06/01/13: Don't even get me started on lead, and alphas
94565: 06/01/13: Re: Xilinx Virtex-4 BRAM-16 Simulation
94567: 06/01/13: Re: Don't even get me started on lead,
94576: 06/01/13: Re: how do I minimize the logic in this function?
94585: 06/01/13: Re: how do I minimize the logic in this function?
94574: 06/01/13: A Better Way?
94575: 06/01/13: Re: Attack of the clones
94751: 06/01/17: Re: S3e slower than S3
94768: 06/01/17: Re: S3e slower than S3
94773: 06/01/17: Re: S3e slower than S3
94769: 06/01/17: Re: How to set Xilinx compiling parameters to get PCI setup time
94767: 06/01/17: Standards in the real world: UWB
94856: 06/01/18: Re: Selling Microblaze based Machines
94882: 06/01/18: Re: Selling Microblaze based Machines
95029: 06/01/20: Re: Security of Xilinx Virtex2 Pro
95511: 06/01/23: Re: Creating Multiple Configuration PROM File
95423: 06/01/23: Re: SSOs and Vcco on Spartan3
95434: 06/01/23: Re: SSOs and Vcco on Spartan3
95428: 06/01/23: Re: Xilinx padding LC numbers, how do you really feel about it?
95443: 06/01/23: Re: Xilinx padding LC numbers, how do you really feel about it?
95473: 06/01/23: Re: Xilinx padding LC numbers, how do you really feel about it?
95486: 06/01/23: Re: Xilinx padding LC numbers, how do you really feel about it?
95515: 06/01/23: Re: Xilinx padding LC numbers, how do you really feel about it?
95530: 06/01/23: Re: Xilinx padding LC numbers, how do you really feel about it?
95591: 06/01/24: Re: Xilinx padding LC numbers, how do you really feel about it?
95605: 06/01/24: Re: Xilinx package/PDS
95606: 06/01/24: Re: Xilinx package/PDS
95721: 06/01/25: Re: XO for Xilinx V2Pro MGTs
95827: 06/01/26: Re: XO for Xilinx V2Pro MGTs
95841: 06/01/26: Re: Xilinx ....
95859: 06/01/26: Re: Xilinx ....
95879: 06/01/26: Re: Xilinx ....
95889: 06/01/26: Re: Xilinx ....
95904: 06/01/26: Spartan 3, V4 and reconfig, both static and dynamic
95967: 06/01/27: This is ended - there is no excuse for the false and sometimes malicious
96114: 06/01/30: Re: XDL Tools wiki site
96126: 06/01/30: Re: XDL Tools wiki site
96139: 06/01/30: Re: XDL Tools wiki site
96103: 06/01/30: Xilinx Legal
96107: 06/01/30: Re: Xilinx Legal
96112: 06/01/30: Re: Xilinx Legal
96129: 06/01/30: Re: Xilinx Legal
96113: 06/01/30: Re: Xilinx Legal
96115: 06/01/30: Re: Xilinx Legal
96289: 06/02/01: Re: Back to max thermal and power for XC4VLX200's
96301: 06/02/01: Re: Back to max thermal and power for XC4VLX200's
96308: 06/02/01: Re: Back to max thermal and power for XC4VLX200's
96363: 06/02/02: Re: BGA central ground matrix
96430: 06/02/03: Re: BGA central ground matrix
96431: 06/02/03: Re: BGA central ground matrix
96432: 06/02/03: Re: Back to max thermal and power for XC4VLX200's
96451: 06/02/03: Re: BGA central ground matrix
96453: 06/02/03: Re: FPGA growth vs. ASIC growth
96464: 06/02/03: Re: FPGA growth vs. ASIC growth
97452: 06/02/22: Re: FPGA to ASIC migrate
97519: 06/02/23: Re: Truth about Spartan-3E DCM speed
97618: 06/02/24: Re: FPGA Selection Question
97620: 06/02/24: Re: FPGA Selection Question
97974: 06/03/02: Re: Help wanted
98025: 06/03/03: Re: Help wanted
98027: 06/03/03: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
98028: 06/03/03: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
98038: 06/03/03: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
98039: 06/03/03: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
98043: 06/03/03: Re: Simple ADS5273 -> Xilinx Interconnect Model
98045: 06/03/03: Re: VirtexII routing data widths (further query)
98050: 06/03/03: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
98051: 06/03/03: Re: VirtexII routing data widths (further query)
98052: 06/03/03: Re: why use an FPGA when a CPLD will do ??
98059: 06/03/03: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
98060: 06/03/03: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
98061: 06/03/03: Re: VirtexII routing data widths (further query)
98062: 06/03/03: Re: VirtexII routing data widths (further query)
98154: 06/03/06: Re: why use an FPGA when a CPLD will do ??
98243: 06/03/07: Re: Asynchronous FIFO design question
98246: 06/03/07: for all those who believe in ASICs....
98321: 06/03/08: Re: Asynchronous FIFO design question
98326: 06/03/08: Re: for all those who believe in ASICs....
98327: 06/03/08: Re: Crosstalk Analysis on a FPGA
98358: 06/03/08: Re: for all those who believe in ASICs....
98359: 06/03/08: Re: for all those who believe in ASICs....
98360: 06/03/08: Re: for all those who believe in ASICs....
98408: 06/03/09: Re: Virtex-4 DCM CLKFX jitter
98452: 06/03/10: Re: for all those who believe in ASICs....
98460: 06/03/10: Re: for all those who believe in ASICs....
98467: 06/03/10: Re: for all those who believe in ASICs....
98473: 06/03/10: Re: for all those who believe in ASICs....
98480: 06/03/10: Re: for all those who believe in ASICs....
98691: 06/03/14: Re: for all those who believe in ASICs....
98777: 06/03/16: Re: Purchasing Virtex-4 FPGAs
98778: 06/03/16: Re: for all those who believe in ASICs....
98779: 06/03/16: Re: for all those who believe in ASICs....
98783: 06/03/16: Re: Where are FPGA heading?
98790: 06/03/16: Re: Where are FPGA heading?
98792: 06/03/16: Re: for all those who believe in ASICs....
98799: 06/03/16: Re: Where are FPGA heading?
98801: 06/03/16: Re: for all those who believe in ASICs....
98816: 06/03/16: Re: Where are FPGA heading?
98817: 06/03/16: Re: for all those who believe in ASICs....
98871: 06/03/17: Re: Where are you heading?
98875: 06/03/17: Re: for all those who have stopped listening, and are ranting now...
98899: 06/03/17: Re: Where are FPGAs heading?
98900: 06/03/17: Re: for all those who believe in ASICs....and can't stop ranting
98908: 06/03/17: Re: for all those who believe in ASICs....and can't stop ranting
98911: 06/03/17: Re: Where am I heading?
98936: 06/03/17: Re: for all those who believe in ASICs....and can't stop ranting
99116: 06/03/20: ignore thread
99325: 06/03/22: Re: OpenSPARC released
99357: 06/03/23: Re: Going from CLK1X to CLK2X.. really safe?
99358: 06/03/23: Re: this JTAG thing is a joke
99360: 06/03/23: Re: Lattice FPGA
99370: 06/03/23: Re: this JTAG thing is a joke
99378: 06/03/23: Re: Lattice FPGA
99391: 06/03/23: Re: Lattice FPGA
99394: 06/03/23: Re: for all those who believe in (structured) ASICs....
99396: 06/03/23: Re: Xilinx hi-speed interconnect/routing question
99404: 06/03/23: Re: this JTAG thing is a joke
99413: 06/03/23: Re: Going from CLK1X to CLK2X.. really safe?
99415: 06/03/23: Re: for all those who believe in (structured) ASICs....
99442: 06/03/24: Re: Xilinx - was Lattice FPGA
99443: 06/03/24: Re: Lattice FPGA
99445: 06/03/24: Re: Memory leaks with ISE 8.1
99448: 06/03/24: Re: for all those who believe in (structured) ASICs....
99471: 06/03/24: Re: Lattice FPGA
99476: 06/03/24: Re: Lattice FPGA
99496: 06/03/25: Re: Lattice FPGA
99498: 06/03/25: Re: Spartan-3E 500 and PCI 33/66 design
99504: 06/03/25: Re: OpenSPARC released
99506: 06/03/25: Re: OpenSPARC released
99618: 06/03/27: Re: Lattice FPGA
99798: 06/03/29: Re: Stratum4E holdover
99810: 06/03/29: Re: Stratum4E holdover
99812: 06/03/29: Re: Stratum4E holdover
99815: 06/03/29: Re: Stratum4E holdover
100150: 06/04/04: Re: PCB Bypass Caps
100170: 06/04/04: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan
100182: 06/04/04: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan
100183: 06/04/04: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan
100220: 06/04/05: Re: Virtex-4 readback via ICAP
100222: 06/04/05: Re: max lvds IO speed on V2Pro
100232: 06/04/05: Re: Virtex-4 readback via ICAP
100257: 06/04/05: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan
100299: 06/04/06: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan3
100324: 06/04/06: Re: USB Interface to Virtex-4
100377: 06/04/07: Re: USB Interface to Virtex-4
100594: 06/04/12: Re: vertex II and powerpc core
100632: 06/04/13: Re: Did National cheat with the Virtex 4? Or are they just smart
100732: 06/04/17: Re: Did National cheat with the Virtex 4? Or are they just smart
100739: 06/04/17: Re: Did National cheat with the Virtex 4? Doesn't look like it....
100950: 06/04/21: Re: fpga space estimate
100952: 06/04/21: Re: CAM, TCAM in Stratix
100964: 06/04/21: Re: Xilinx DCI resistor placement guidelines
100968: 06/04/21: Re: EDK : FSL macros defined by Xilinx are wrong
100969: 06/04/21: Re: EDK : FSL macros defined by Xilinx are wrong
100980: 06/04/22: Re: Microblaze & Linux tools. (repost)
100985: 06/04/22: Re: Microblaze & Linux tools. (repost)
101015: 06/04/24: Re: Xilinx DCI resistor placement guidelines
101021: 06/04/24: Re: Spartan 3 documentation confusing...
101029: 06/04/24: Re: Heating problem of the CPLD
101034: 06/04/24: Re: Heating problem of the CPLD
101046: 06/04/24: Re: Spartan 3 documentation confusing...
101057: 06/04/24: Re: Spartan 3 documentation confusing...
101085: 06/04/25: Re: Spartan 3 documentation confusing...
101088: 06/04/25: Re: Virtex 2 Config Times
101134: 06/04/26: Re: Async FPGA ~2GHz
101155: 06/04/26: Re: Async FPGA ~2GHz
101156: 06/04/26: Re: Async FPGA ~2GHz
101160: 06/04/26: Re: Async FPGA ~2GHz
101328: 06/04/28: Re: DRC has announced its newest FPGA that drops into AMD's Socket
101352: 06/04/29: Re: Spartan 3 documentation confusing...
101402: 06/04/30: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
101449: 06/05/01: Spartan 3 documentation confusing...no more
101456: 06/05/01: Re: Async FPGA ~2GHz
101661: 06/05/04: Re: Xilinx 3s8000?
101681: 06/05/04: Re: Xilinx 3s8000?
101683: 06/05/04: Re: Xilinx 3s8000?
101691: 06/05/04: Re: LVDS inputs on Cyclone II
101693: 06/05/04: Re: Xilinx 3s8000?
101700: 06/05/04: Re: LVDS inputs on Cyclone II
101742: 06/05/05: Re: LVDS inputs on Cyclone II
101759: 06/05/05: <ignore thread>
101771: 06/05/05: Re: Xilinx 3s8000?
101781: 06/05/06: Re: Xilinx 3s8000?
101926: 06/05/08: Re: Can an FPGA be operated reliably in a car wheel?
101994: 06/05/09: Re: Can an FPGA be operated reliably in a car wheel?
102022: 06/05/09: Re: Funky experiment on a Spartan II FPGA
102030: 06/05/09: Re: Funky experiment on a Spartan II FPGA
102103: 06/05/10: Re: CoolRunner XPLA3 getting axed?
102178: 06/05/11: Re: Xilinx warning for DCM
102180: 06/05/11: Re: reverse engineering ?
102192: 06/05/11: Re: reverse engineering ?
102200: 06/05/11: Re: reverse engineering ?
102256: 06/05/12: Re: Synchronous Scrambler
102300: 06/05/14: Re: How to decide Fanout limit?
102301: 06/05/14: Re: Spartan 3E
102345: 06/05/15: Re: Virtex 5 announced
102349: 06/05/15: Re: Virtex 5 announced
102356: 06/05/15: Re: Virtex 5 announced
102357: 06/05/15: Re: Virtex 5 announced
102361: 06/05/15: Re: Virtex 5 announced and sampling
102362: 06/05/15: Re: Virtex 5 announced
102365: 06/05/15: Re: Virtex 5 announced and sampling ... and real!
102368: 06/05/15: Re: Virtex 5 announced
102380: 06/05/15: Re: Virtex 5 announced and sampling
102392: 06/05/15: Re: Virtex 5 announced and sampling ... and real!
102394: 06/05/15: Re: Virtex 5 announced and sampling ... and real!
102401: 06/05/15: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
102402: 06/05/15: Re: Virtex 5 announced and sampling
102411: 06/05/15: Re: Virtex 5 announced and sampling ... and real!
102464: 06/05/16: Re: Virtex 5 announced and sampling
102538: 06/05/17: Re: "disappointing" performance
102596: 06/05/17: Reality of V5 as ES
102597: 06/05/17: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
102637: 06/05/18: Re: Reality of V5 as ES
102641: 06/05/18: Re: "disappointing" performance
102642: 06/05/18: Re: "disappointing" performance
102653: 06/05/18: Re: ADC implementation on FPGA ?
102654: 06/05/18: Re: Virtex 5 announced and sampling: now we just wait?
102661: 06/05/18: Re: DCM and Clock
102663: 06/05/18: Re: DCM and Clock
102668: 06/05/18: Re: DCM and Clock
102754: 06/05/19: Re: "disappointing" performance
102928: 06/05/23: Re: Xilinx -- please help with Virtex-4 datasheet
103033: 06/05/24: Re: Superscalar Out-of-Order Processor on an FPGA
103113: 06/05/25: Re: DSP48E, What are the internal implementations used?
103116: 06/05/25: Re: DSP48E, What are the internal implementations used?
103150: 06/05/26: Re: DCM lock - require clarification
103154: 06/05/26: Re: ISE sends sensitive information to Xilinx site!------ Only if
103161: 06/05/26: Re: ISE sends sensitive information to Xilinx site!------ Only if
103190: 06/05/27: Re: ISE sends sensitive information to Xilinx site!------ Only if
103309: 06/05/30: Re: Virtex 5 announced and sampling ... and real!
103310: 06/05/30: Re: Virtex 5 announced and sampling ... and real!
103317: 06/05/30: Re: Need help reattaching top to FPGA
103357: 06/05/31: Re: Using part of CPLD to Invert Own Clock
103478: 06/06/03: Re: Difference Logic Cells <=> Slices
103588: 06/06/06: Re: FlipChip BGA Conformal Coating
103600: 06/06/06: Re: Propagation delay sensitivity to temperature, voltage, and manufacturing
103611: 06/06/06: Who's dying?
103614: 06/06/06: Re: Who's dying?
103644: 06/06/07: Re: FlipChip BGA Conformal Coating
103645: 06/06/07: Re: FlipChip BGA Conformal Coating
103647: 06/06/07: Re: Who's dying?
103663: 06/06/07: Re: Who's dying?
103671: 06/06/07: Re: STOP IT :)
103739: 06/06/09: Re: Anyone with Xilinx SP305-board ?
103762: 06/06/10: Re: Anyone with Xilinx SP305-board ?
103763: 06/06/10: Re: Anyone with Xilinx SP305-board ?
103772: 06/06/10: Re: Anyone with Xilinx SP305-board ?
103829: 06/06/12: Re: Looking for patent attorney specialized in programmable logic
103836: 06/06/12: Re: Looking for patent attorney specialized in programmable logic
103859: 06/06/13: Re: IDELAY clock spec. in Xilinx V4
103863: 06/06/13: Re: IDELAY clock spec. in Xilinx V4
103910: 06/06/14: Re: Time for a new "Largest FPGA with free tool support"?
103988: 06/06/16: Re: bga routing
104021: 06/06/16: Re: Time for a new "Largest FPGA with free tool support"?
104054: 06/06/17: Re: Temperature sensing diode on Vertex 4
104224: 06/06/21: Re: Locks for the peasants :-)
104226: 06/06/21: Re: Locks for the peasants :-) Let them eat cake! Off with their
104227: 06/06/21: Re: Locks for the peasants :-)
104276: 06/06/22: Re: Locks for the peasants :-)
104277: 06/06/22: Re: keys to the Kingdom
104280: 06/06/22: Re: keys to the Kingdom
104294: 06/06/22: Re: keys to the Kingdom
104308: 06/06/23: Re: keys to the Kingdom
104309: 06/06/23: Re: keys to the Kingdom
104440: 06/06/27: Re: dcm clkin_divide_by_2
104458: 06/06/27: Re: keys to the Kingdom
104460: 06/06/27: Re: keys to the Kingdom
104477: 06/06/28: Re: keys to the Kingdom
104481: 06/06/28: Re: keys to the Kingdom
104507: 06/06/28: Re: Virtex5 Availability
104508: 06/06/28: Re: Reverse engineering has the protection of law in the U.S.
104509: 06/06/28: Re: keys to the Kingdom
104587: 06/06/30: Re: Xilinx BUFGMUX Setup Time requirement clarification needed
104169: 06/06/20: keys to the Kingdom
104898: 06/07/08: Re: Chaos in FF metastability
104913: 06/07/09: Re: Weird JTAG lockup issue, where is the BUG?
104983: 06/07/11: Re: DIFFICULT MULTICYCLE PATH WITH QUARTUS II, or any other tool
104994: 06/07/11: Re: Virtex-4 Vicm for LVDS with Vcco = 3.3V.
105035: 06/07/12: Re: DIFFICULT MULTICYCLE PATH WITH QUARTUS II, or any other tool
105036: 06/07/12: Re: Diffenrential I/Os in Virtex-4
105149: 06/07/14: Re: Where are you heading?
105444: 06/07/23: Re: Virtex 4, LVDS I/O: Sanity check please
105445: 06/07/23: Re: Why 8 clock trees in Xilinx Spartan-3 device?
105453: 06/07/23: Re: Virtex 4, LVDS I/O: Sanity check please
105455: 06/07/23: Re: Why 8 clock trees in Xilinx Spartan-3 device?
105626: 06/07/27: Re: Rocket IO as a high speed sampler
105627: 06/07/27: Re: Rocket IO as a high speed sampler
105635: 06/07/27: Re: Rocket IO as a high speed sampler
105645: 06/07/27: Re: OT (2nd try): do you get paid for your travel time?
105692: 06/07/28: Re: Xilinx Corgen & Synplicity... Anyone? Help?
105848: 06/08/01: Re: 100m JTAG cable
105992: 06/08/04: Re: 100m JTAG cable
106037: 06/08/06: Re: 100m JTAG cable
106079: 06/08/07: Re: 3.3V configuration of Spartan-3?
106161: 06/08/08: Re: 100 Mbit manchester coded signal in FPGA
106173: 06/08/08: Re: 100 Mbit manchester coded signal in FPGA
106193: 06/08/08: Re: Question about SSTL
106280: 06/08/10: Re: Switching two (synchronous) clocks with variable phase difference,
106445: 06/08/13: Re: Maximum Current Draw of FPGA
106446: 06/08/13: Re: Virtex 4 could not work correct,is it damaged?
106497: 06/08/14: Re: synthesis intelligence of quartus regarding range of values
106501: 06/08/14: Re: synthesis intelligence of quartus regarding range of values
106522: 06/08/14: Re: Crystal input for FPGA
106564: 06/08/15: Re: Maximum Current Draw of FPGA
106573: 06/08/15: Re: Maximum Current Draw of FPGA
106583: 06/08/15: Re: Maximum Current Draw of FPGA
106585: 06/08/15: Re: Large Spartan3 vs. Small V5
106622: 06/08/16: Re: Maximum Current Draw of FPGA
106632: 06/08/16: Re: Power Supply Sequencing to V4 MGTs
106694: 06/08/17: Re: Power Supply Sequencing to V4 MGTs
106802: 06/08/19: Re: S3 starter kit, command-line
106982: 06/08/23: Re: DCM vs. PLL
106987: 06/08/23: Re: DCM vs. PLL
106988: 06/08/23: Re: DCM vs. PLL
107013: 06/08/23: Re: fastest FPGA
107081: 06/08/24: Re: DCM vs. PLL
107083: 06/08/24: Re: Why No Process Shrink On Prior FPGA Devices ?
107118: 06/08/24: Re: Why isn't there a thermal diode on large FPGAs?
107130: 06/08/24: Re: fastest FPGA
107201: 06/08/25: Re: fastest FPGA
107251: 06/08/25: Re: FPGA -> SATA?
107261: 06/08/25: Re: FPGA -> SATA?
107317: 06/08/26: Re: Why isn't there a thermal diode on large FPGAs?
107334: 06/08/26: Re: Why isn't there a thermal diode on large FPGAs?
107343: 06/08/26: Re: What is the truth about the Virtex5 ?
107362: 06/08/27: Re: Why isn't there a thermal diode on large FPGAs?
107363: 06/08/27: Re: Why isn't there a thermal diode on large FPGAs?
107364: 06/08/27: Re: What is the truth about the Virtex5 ?
107373: 06/08/27: placing addiional caps across existing caps to reduce noise
107378: 06/08/27: RLC, extraction, and file formats
107428: 06/08/28: Re: placing addiional caps across existing caps to reduce noise
107429: 06/08/28: Re: placing addiional caps across existing caps to reduce noise
107430: 06/08/28: Re: placing addiional caps across existing caps to reduce noise
107443: 06/08/28: Re: Question on Virtex-4 CLB
107449: 06/08/28: Re: RocketIO over cable
107454: 06/08/28: Re: Question on Virtex-4 CLB
107459: 06/08/28: Re: FPGA -> SATA?
107460: 06/08/28: Re: Question on Virtex-4 CLB
107493: 06/08/29: Re: What is the truth about the Virtex5 ?
107533: 06/08/29: Re: Question on Virtex-4 CLB
107598: 06/08/30: Re: Xilinx - no secret, you are not to use the PMV primitive
107600: 06/08/30: Re: Virtex-4FX DCM autoshutdown failure, any suggestions
107614: 06/08/30: Re: Virtex-4FX DCM autoshutdown failure, any suggestions
107615: 06/08/30: Re: Xilinx - no secret, you are not to use the PMV primitive
107616: 06/08/30: Re: Aurora implementation
107623: 06/08/30: Re: Virtex-4FX DCM autoshutdown failure, any suggestions
107636: 06/08/30: Re: Virtex-4FX DCM autoshutdown failure, any suggestions
107642: 06/08/30: Re: Questions
107661: 06/08/30: Re: Questions
107842: 06/09/01: Re: 5V FPGAs & CPLDs in 2006?
108116: 06/09/05: Re: FPGA multiplier
108129: 06/09/05: Re: FPGA multiplier
108133: 06/09/05: Re: Virtex4 FPGA minimum power
108312: 06/09/07: Re: Synchronous Clocks
108338: 06/09/08: Re: Why No Process Shrink On Prior FPGA Devices ?
108346: 06/09/08: Re: Virtex4FX12 and Spartan3 lead time
108352: 06/09/08: Re: Why No Process Shrink On Prior FPGA Devices ?
108354: 06/09/08: Re: Virtex4FX12 and Spartan3 lead time
108370: 06/09/09: Re: Can a FPGA work like a microprocessor ?
108373: 06/09/09: Re: FPGA Devices' stability and process parameters
108515: 06/09/12: Re: Spartan-3: 5V -> 2.5V level shifting
108537: 06/09/12: Re: Spartan-3: 5V -> 2.5V level shifting
108541: 06/09/12: Re: Spartan-3: 5V -> 2.5V level shifting
108582: 06/09/13: Re: Spartan-3: 5V -> 2.5V level shifting
108583: 06/09/13: Re: X4000 bad configuration
108608: 06/09/13: Re: X4000 bad configuration
108647: 06/09/14: Digilent 3S200 pcb + webpack ISE 8.2 + service pack
108656: 06/09/14: Re: Linear Interploation Algorithms
108665: 06/09/14: Re: Linear Interploation Algorithms
108706: 06/09/15: Re: XIlinx Spartan 2E stuck in configuration mode
108707: 06/09/15: S3 - alive and doing very well, thank you
108709: 06/09/15: Re: Digilent 3S200 pcb + webpack ISE 8.2 + service pack
108754: 06/09/15: Re: XIlinx Spartan 2E stuck in configuration mode
108755: 06/09/15: Re: XIlinx Spartan 2E stuck in configuration mode
108777: 06/09/16: Re: XIlinx Spartan 2E stuck in configuration mode
108788: 06/09/16: Re: XIlinx Spartan 2E stuck in configuration mode
108795: 06/09/16: Re: XIlinx Spartan 2E stuck in configuration mode
108796: 06/09/16: Re: XIlinx Spartan 2E stuck in configuration mode
108812: 06/09/17: Re: XIlinx Spartan 2E stuck in configuration mode
108813: 06/09/17: Re: XIlinx Spartan 2E stuck in configuration mode
108873: 06/09/18: Re: Spartan3: Multiplier Madness
108878: 06/09/18: Re: Spartan3: Multiplier Madness
108880: 06/09/18: Re: Virtex4 Configuration ROM?
108930: 06/09/19: Re: Virtex4 Configuration ROM?
108931: 06/09/19: Re: Are you ready for Virtex-5? We are...
108938: 06/09/19: Re: BUF component
108941: 06/09/19: Re: VHDL oddity
108944: 06/09/19: Re: VHDL oddity
108963: 06/09/19: Hilbert Transform in verilog or VHDL -- it has got to be out there
108973: 06/09/19: Re: xilinx or altera?
108978: 06/09/19: Re: Spartan3: Multiplier Madness
108983: 06/09/19: Re: Hilbert Transform in verilog or VHDL -- it has got to be out
108988: 06/09/19: Re: Metastability resolution
109051: 06/09/20: Re: xilinx or altera?
109052: 06/09/20: Re: maximum life of FPGA based products ????
109089: 06/09/20: Re: xilinx or altera?
109150: 06/09/21: Re: ddr clock issues
109151: 06/09/21: Re: maximum life of FPGA based products ????
109152: 06/09/21: Re: Are you ready for Virtex-5? We are...
109618: 06/10/01: Re: Are you ready for Virtex-5? We are...
109631: 06/10/02: Re: Are you ready for Virtex-5? We are...
109901: 06/10/07: Re: An implementation of a clean reset signal
109905: 06/10/07: Re: Spartan 3 Starter Kit I/O ports
109910: 06/10/07: Re: Spartan 3 Starter Kit I/O ports
109911: 06/10/07: Re: Spartan 3 DCI
109927: 06/10/08: Re: Spartan 3 DCI
109930: 06/10/08: Re: Spartan 3 DCI
109991: 06/10/09: Re: a clueless bloke tells Xilinx to get a move on
110001: 06/10/09: Re: a clueless bloke tells Xilinx to get a move on
110057: 06/10/10: Re: longest webcase record
110135: 06/10/11: Re: longest webcase record -- perhaps it is explained?
110136: 06/10/11: Re: Spartan 3 DCI
110146: 06/10/11: Re: longest webcase record -- perhaps it is explained?
110163: 06/10/11: Re: longest webcase record -- understandably so
110236: 06/10/12: Re: How much function of FPGA Editor is open in webpack?
110313: 06/10/13: Re: Xilinx FPGAs in battery-powered scenarios
110314: 06/10/13: Re: Xilinx FPGAs in battery-powered scenarios
110326: 06/10/13: Re: Xilinx FPGAs in battery-powered scenarios
110368: 06/10/14: Re: Xilinx FPGAs in battery-powered scenarios
110384: 06/10/14: Re: Xilinx FPGAs in battery-powered scenarios
110388: 06/10/14: Re: Xilinx FPGAs in battery-powered scenarios
110398: 06/10/14: Re: Xilinx FPGAs in battery-powered scenarios
110424: 06/10/15: Re: Xilinx FPGAs in battery-powered scenarios
110440: 06/10/15: boundary scan, JTAG
110480: 06/10/16: Re: longest webcase record -- understandably so
110496: 06/10/16: Re: Virtex-5 LXT launched today !
110500: 06/10/16: Re: longest webcase record -- understandably so
110539: 06/10/17: Re: Virtex-5 LXT launched today !
111116: 06/10/29: Re: Safe Routing
111171: 06/10/30: Re: On the Futility of Documentation Webcases ( Was: Xilinx documentation
111173: 06/10/30: Re: On the Futility of Documentation Webcases ( Was: Xilinx documentation
111263: 06/10/31: Re: Question about bandwidth of scope?
111339: 06/11/01: Re: Rad-hard (neutron/SEU and space) tutorial?
111397: 06/11/02: Re: How to avoid negative slack?
111414: 06/11/02: Re: How to avoid negative slack?
111417: 06/11/02: Re: OT. Warning bad jokes. was :- How to avoid negative slack?
112006: 06/11/14: Re: Influence of temperature and manufacturing to propagation delay
112010: 06/11/14: Re: Influence of temperature and manufacturing to propagation delay
112049: 06/11/15: Re: Influence of temperature and manufacturing to propagation delay
112105: 06/11/16: Re: Old Spartan-II, worth prototyping?
112106: 06/11/16: System Jitter calculation by hand
112121: 06/11/16: Re: V-5 power saving ...how?
112182: 06/11/17: Re: pulse jitter due to clock
112192: 06/11/17: Re: pulse jitter due to clock
112242: 06/11/18: Re: pulse jitter due to clock
112378: 06/11/21: Re: pulse jitter due to clock
112456: 06/11/22: Re: Protecting netlist for Xilinx
112476: 06/11/22: Re: Protecting netlist for Xilinx
112504: 06/11/23: Re: DCM Jitter
112544: 06/11/24: Re: DCM Jitter
112545: 06/11/24: Re: Are FPGAs available with ADCs onchip ?
112825: 06/11/29: Re: DVI clock generation
112845: 06/11/29: Re: FPGA application field
112885: 06/11/30: Re: DVI clock generation
112891: 06/11/30: Re: FPGA application field
112903: 06/11/30: Re: DCM jitter (again)
112933: 06/12/01: Re: DCM jitter (again)
113175: 06/12/07: Re: Spartan-3A launched
113217: 06/12/08: Re: About partial reconfiguration in Virtex 4
113433: 06/12/13: Re: BLVDS_25 @ SPARTAN3
113530: 06/12/15: Re: electrical level conversion
113536: 06/12/15: Re: electrical level conversion
113544: 06/12/15: Re: 3.3V LVPECL into a LVPECL_25, VCCO-2.5V on a Virtex-4
113547: 06/12/15: Re: Xilinx PMCD+DCM reset question...
113629: 06/12/18: Re: electrical level conversion
113633: 06/12/18: Re: Simple questions on IDELAYCTRL vs DCM
113637: 06/12/18: Re: Simple questions on IDELAYCTRL vs DCM
113743: 06/12/20: Re: CCLK Virtex4 IBIS model.
113750: 06/12/20: Re: CCLK Virtex4 IBIS model.
113769: 06/12/20: Re: Soft processor Microblaze vs embedded core PowerPC
114161: 07/01/05: Re: Anyone seen eASIC?
114244: 07/01/08: Re: Variable clock using Virtex 4?
114283: 07/01/10: Re: Can I use 3.3V clock into the MGTCLK? MGT RocketIO
114457: 07/01/16: Re: interesting article FPGA routing field programmable nanowire
114489: 07/01/17: Re: Can I use 3.3V clock into the MGTCLK? MGT RocketIO
114540: 07/01/18: "Gate" = ???
114584: 07/01/19: Re: "Gate" = ???
114668: 07/01/22: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
114672: 07/01/22: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
114726: 07/01/23: Re: FPGA power supply design
114729: 07/01/23: Re: Xilinx ISE 8.2
114732: 07/01/23: Re: FPGA damage from bad bitstream
114750: 07/01/23: Re: FPGA damage from bad bitstream
114803: 07/01/24: Re: FPGA damage from bad bitstream
114814: 07/01/24: Re: Xilinx ISE 8.2
114864: 07/01/25: Re: On-chip randomness (V4FX)
115078: 07/01/30: Re: 1 Gbps - state of the art?: PCIe is 2.5Gb/s, and PCIe V2.x will
115115: 07/01/31: Re: 1 Gbps - state of the art?: PCIe is 2.5Gb/s, and PCIe V2.x will
115334: 07/02/07: Re: Impact of only one bank powered?
115500: 07/02/12: Re: Building Coaxial transmission line on PCB?
115548: 07/02/13: Re: Typical clock frequencies of FPGA designs
115692: 07/02/16: Re: Where to start???
115694: 07/02/16: Re: Where to start???
115783: 07/02/20: Re: Managing input clock of 20MHz at input of DCM
115784: 07/02/20: Business is not "as usual"
115814: 07/02/21: Re: Business is not "as usual"
115820: 07/02/21: Re: up down lfsr
115826: 07/02/21: Re: Can someone give me some pointers on using ibis models?
115827: 07/02/21: Re: Can someone give me some pointers on using ibis models?
115938: 07/02/26: Re: Virtex 4, how do I generate 100khz clock
115946: 07/02/26: Re: Virtex 4
115947: 07/02/26: Re: Spartan-3AN
115951: 07/02/26: Re: Spartan-3AN
115956: 07/02/26: Re: Spartan-3AN
116008: 07/02/27: Re: Spartan-3AN
116014: 07/02/27: Re: Spartan-3AN
116056: 07/02/28: Re: Xilinx USB flatform cable length mistery ?
116092: 07/03/01: Re: Bypass caps, X2Y and 'puddles'.
116111: 07/03/01: apologia
116150: 07/03/02: Re: apologia
116231: 07/03/05: Re: Large power planes vs. power islands vs. slits for decoupling
116242: 07/03/05: Re: Large power planes vs. power islands vs. slits for decoupling
116288: 07/03/06: Re: Xilinx Ise 6.3i
116334: 07/03/07: Re: Query regarding Project.Plz help very urgent
116339: 07/03/07: Re: Query regarding Project.Plz help very urgent
116361: 07/03/07: Re: Spartan3AN - Roadmap - bigger questions may prevail...
116362: 07/03/07: Re: Introducing picosecond delay between two output signals
116369: 07/03/07: Re: Spartan3AN - Roadmap - bigger questions may prevail...
116403: 07/03/08: Re: Spartan3AN - Roadmap - bigger questions may prevail...
116404: 07/03/08: Re: Introducing picosecond delay between two output signals
116434: 07/03/08: Re: Xilinx Spartan DCM jitter spectrum
116561: 07/03/12: Re: 3.3V tolerant Virtex-4 JTAG Configuration
116592: 07/03/13: Re: Xilinx SRL's and sync flip flops
116645: 07/03/14: Re: Xilin X-Fest Lunacy
116881: 07/03/20: Re: Altera introduces Cyclone III devices, 'ships' 65nm
116882: 07/03/20: Re: timing in xilinx fpga
116888: 07/03/20: Re: Altera introduces Cyclone III devices, 'ships' 65nm
116906: 07/03/20: Re: softcore CPU tools
116963: 07/03/21: Re: Why is Xilinx's WebPACK so inferior?
116979: 07/03/21: Re: Off topic: what is the purpoe of XST?
116989: 07/03/21: Re: Why is Xilinx's WebPACK so inferior?
117012: 07/03/21: XST coverage
117058: 07/03/22: Re: Austin the Altera Mole
117060: 07/03/22: Re: Altera introduces Cyclone III devices, 'ships' 65nm
117061: 07/03/22: Re: Altera introduces Cyclone III devices, 'ships' 65nm
117071: 07/03/22: Re: Altera introduces Cyclone III devices, 'ships' 65nm
117074: 07/03/22: Re: Altera introduces Cyclone III devices, 'ships' 65nm
117079: 07/03/22: Re: Altera introduces Cyclone III devices, 'ships' 65nm
117130: 07/03/23: Re: XST coverage
117140: 07/03/23: Re: Altera introduces Cyclone III devices, 'ships' 65nm
117197: 07/03/26: Re: Software Management
117209: 07/03/26: Re: Minimal pins for JTAG configuration
117254: 07/03/27: Re: Minimal pins for JTAG configuration
117261: 07/03/27: Re: Minimal pins for JTAG configuration
117328: 07/03/28: Re: Minimal pins for JTAG configuration
117336: 07/03/28: Re: suggestion for choosing the right FPGA for gigabit transciever
117386: 07/03/29: Re: RISC implementation questions
117413: 07/03/30: Re: RISC implementation questions
117425: 07/03/30: Re: Another simple DCM question
117489: 07/04/02: Re: DCM_STANDBY macro in Virtex-4
117581: 07/04/04: Re: high number of multipliers / low cost
117666: 07/04/06: Re: Transition from ASIC to FPGA
117680: 07/04/06: Re: Transition from ASIC to FPGA
117795: 07/04/10: Re: Ross Freeman - inventor of the FPGA
117804: 07/04/10: Re: Flip Flop problem (asynchronous or synchronous???? )
117838: 07/04/11: Re: Xilinx WebCase support
117844: 07/04/11: Re: Xilinx WebCase support
117852: 07/04/11: Re: Xilinx WebCase support
117897: 07/04/12: Re: spartan 3e availability
117921: 07/04/13: Re: spartan 3e availability
117943: 07/04/13: Re: Distributor stock (was Re: spartan 3e availability)
118193: 07/04/19: Re: Summer with fpgas
118208: 07/04/19: Re: Summer with fpgas
118209: 07/04/19: Re: Spartan 3 IOSTANDARD vs VCCO
118213: 07/04/19: Re: Question about reset signal for several DCMs in EDK design.
118215: 07/04/19: Re: Summer with fpgas
118303: 07/04/23: Re: Non-intrusive readback on FPGA configuration data
118304: 07/04/23: Re: Non-intrusive readback on FPGA configuration data
118316: 07/04/23: Re: V5 GTP question
118320: 07/04/23: Re: I/O-Standards: HSTL vs. SSTL and others...
118321: 07/04/23: Re: Ouputs during startup and Programming
118345: 07/04/24: Re: V5 GTP question
118482: 07/04/27: Re: Problem cascading 2 DCMs
124904: 07/10/10: Re: Need suggestion on FPGA kit
Austin O'Hara:
3685: 96/07/13: PCI Information Disk.
3918: 96/08/19: How to build a PCI Expansion Board
Austin Tempany:
24567: 00/08/14: Re: ASIC SCAN TEST
24630: 00/08/15: Re: what does 0.35 micron mean
24631: 00/08/15: Re: ASIC SCAN TEST
24475: 00/08/10: ASIC SCAN TEST
<austin@darkroom.com>:
16835: 99/06/12: Re: PCI + I2O in a FPGA.... has anyone done it?
Autofuzz:
45409: 02/07/22: Cheap licenses..
45670: 02/07/31: FPGA performance matrix..
<autogenerate@hotmail.com>:
79171: 05/02/15: Re: ATM Cell Payload Scrambler / Descrambler Process Explaination Required
79189: 05/02/15: Re: ATM Cell Payload Scrambler / Descrambler Process Explaination Required
<autumn@osearch.com>:
26862: 00/11/01: Hardware Engineer position in Pittsburgh
avalanche effect:
64111: 03/12/16: From ASIC to FPGA these days
64122: 03/12/17: From FPGA to ASIC these days
Avanish:
48306: 02/10/15: Re: VHDL & OBUFE8
48308: 02/10/15: Re: Spartan II: CLKDLL
48991: 02/10/28: Re: Leonardo and lpm (Altera)
49018: 02/10/29: Re: Leonardo and lpm (Altera)
AvdL:
29497: 01/02/23: Searching for FPGA designer (PCI interface,DES, IDE)
AVG:
84081: 05/05/12: Re: 8051 IP core
84103: 05/05/12: Re: 8051 IP core
84146: 05/05/13: Re: Q)BRAM VHDL simulation in modelsim
84315: 05/05/17: Re: 8051 IP core
84320: 05/05/17: Re: 8051 IP core
84716: 05/05/25: Re: ethernet
84720: 05/05/25: Re: ethernet
84724: 05/05/25: Re: ethernet
Avi Halfon:
65142: 04/01/20: spartan3 power supply
avider:
1542: 95/07/12: info
Avin:
73544: 04/09/23: Why are there 2 clock supplies in Nios Apex board proto-connectors
74824: 04/10/19: How To Provide External Input & Output To Startix 1S40..?
Avinash Maddy:
21257: 00/03/14: Can we read bits from a file in PCc using Altera or Xilinx ?
Avinash Sharma:
66737: 04/02/26: FSM in fpga's
Avion:
110321: 06/10/13: Re: LatticeMico32 extremly poor performance without caches
110357: 06/10/14: EDIF Design Entry tools
110371: 06/10/14: Re: EDIF Design Entry tools
110389: 06/10/14: Re: EDIF Design Entry tools
110415: 06/10/15: Re: EDIF Design Entry tools
110434: 06/10/15: Re: EDIF Design Entry tools
110702: 06/10/20: Re: Cheapest FPGA board to study VHDL on
<avionion@gmail.com>:
108828: 06/09/17: Re: SSFP16 GPL licensed 16 Fpga processor released
109882: 06/10/06: Re: BSD indi processor IP compiles at 283 LEs
110176: 06/10/11: Re: Xilinx MicroBlaze 4.00.a source codes released by Xilinx !?
110179: 06/10/11: Re: LatticeMico32 extremly poor performance without caches
110266: 06/10/12: Re: LatticeMico32 extremly poor performance without caches
110293: 06/10/13: Re: Last ISE version that supports XC95xxXL ?
110294: 06/10/13: Re: LatticeMico32 extremly poor performance without caches
110316: 06/10/13: Re: Last ISE version that supports XC95xxXL ?
<aviralmittal@gmail.com>:
160324: 17/11/14: Re: grey code counters
avishay:
82359: 05/04/11: Re: Altera and VHDL library
93093: 05/12/13: Frequency dependent SOPC builder components
93111: 05/12/13: Re: Frequency dependent SOPC builder components
93627: 05/12/26: Re: Xilinx V4 LVDS
96592: 06/02/07: Re: nios II stratix II handling interrrupts from uController
96828: 06/02/11: Creating low freq. clock on Altera FPGA
101355: 06/04/29: Quartus and source control
101431: 06/04/30: Re: Quartus and source control
101651: 06/05/04: Re: Quartus and source control
108308: 06/09/07: Managing small IP library
111624: 06/11/06: Should I use an external synthesis tool?
113138: 06/12/06: FPGA to Camera (Channel) link
113157: 06/12/06: Re: FPGA to Camera (Channel) link
113158: 06/12/07: Re: Quartus II: Back-annotating bidir's gives two entries per pin...
avl:
104352: 06/06/25: Test:PRBS
<avms@my-deja.com>:
17721: 99/08/27: Re: Feasibility of 200 MHz, 12K design on FPGA
18344: 99/10/16: Re: SRAM FPGA with hardwired 40 MHz AVR RISC processor, memory and peripherals
avrbasic:
77135: 04/12/25: Re: EDK Bug ?
77136: 04/12/25: Re: mb-gcc bug ?
77138: 04/12/25: Re: Xilinx Christmas present: EDK 6.3 !
77142: 04/12/25: Re: Using EDK libraries in ISE
77143: 04/12/25: Re: edk-chipscope 6.2 to 6.3 update
77153: 04/12/26: Re: SATA/SAS designs with FPGA
77197: 04/12/29: Re: Google is turning usenet into crap - was Primers for Handel-C
77209: 04/12/30: Re: SATA/SAS designs with FPGA
77241: 05/01/01: Free IP-Core for FPGA Config from MMC-Cards
77249: 05/01/01: Re: Getting started with Xilinx CPLD
<avrbasic@hotmail.com>:
125068: 07/10/16: Re: FPGA quiz2: spartan3A return Virtex JTAGID. Also prizes for quiz1 and quiz2
125069: 07/10/16: Re: FPGA quiz: what can be wrong
125070: 07/10/16: Re: FPGA quiz: what can be wrong
125072: 07/10/16: Re: FPGA quiz: what can be wrong
125073: 07/10/16: Re: FPGA quiz: what can be wrong
125074: 07/10/16: Re: FPGA quiz: what can be wrong
125076: 07/10/16: Re: FPGA quiz: what can be wrong
125079: 07/10/16: Re: FPGA quiz: what can be wrong
125080: 07/10/16: Re: FPGA quiz: what can be wrong
125082: 07/10/16: Re: FPGA quiz: what can be wrong
125084: 07/10/16: Re: FPGA quiz: what can be wrong
125118: 07/10/16: Re: FPGA quiz2: spartan3A return Virtex JTAGID. Also prizes for quiz1 and quiz2
125120: 07/10/16: Re: FPGA quiz: what can be wrong
125123: 07/10/16: Re: FPGA quiz2: spartan3A return Virtex JTAGID. Also prizes for quiz1 and quiz2
125131: 07/10/16: Re: FPGA quiz: what can be wrong
Avrum:
53817: 03/03/24: Re: CLKDLL synthesized with synplify pro
53852: 03/03/25: Re: CLKDLL synthesized with synplify pro
54837: 03/04/20: Re: Distributing clock to external devices
54906: 03/04/21: Re: Virtex-II IOB setup/hold and clock-to-out timing
54924: 03/04/22: Re: Distributing clock to external devices
54938: 03/04/22: Re: Virtex-II IOB setup/hold and clock-to-out timing
54992: 03/04/23: Re: Challenge: (n mod 3) in hardware???
54996: 03/04/23: Re: Challenge: (n mod 3) in hardware???
54997: 03/04/23: Re: Challenge: (n mod 3) in hardware???
55002: 03/04/23: Re: Challenge: (n mod 3) in hardware???
55506: 03/05/10: Re: global buffer and the dll
55554: 03/05/12: Re: Exploting the DDR input registers in Virtex2
55581: 03/05/13: Re: Exploting the DDR input registers in Virtex2
56811: 03/06/16: Re: Implementaion of Mux-DFF with Virtex ..
57722: 03/07/04: Re: information required
57852: 03/07/08: Re: About BRAM in VirtexII
57854: 03/07/08: Re: [DLL usage Virtex/Spartan-II] HowTo drive CLKDV Div 2 off Chip
57897: 03/07/09: Re: memory
58079: 03/07/14: Re: Combinational logic and gate delays - Help
58315: 03/07/20: Re: CRC questions
58339: 03/07/21: Re: Xilinx GCLK voltages
58372: 03/07/21: Re: Xilinx GCLK voltages
58432: 03/07/23: Re: inputs and outputs for clb in ISE5
58603: 03/07/28: Re: help neede-----Error Pack 1107 -Unable to combine the following .........
58640: 03/07/29: Re: DCM delays in the TRCE report.
58669: 03/07/30: Re: DCM delays in the TRCE report.
59181: 03/08/11: Re: async flip-flop reset by a signal from a different clock domain
59185: 03/08/11: Re: async flip-flop reset by a signal from a different clock domain
83078: 05/04/22: Re: How do I convert binary data from Agilent logic analyzer 16702 into plain text?
83079: 05/04/22: Re: What is the cause of a "can not see clock" problem in logic analyser?
84362: 05/05/17: Re: Registers replication on Xilinx IOBs
86401: 05/06/27: Re: Poor PCI performance during read accesses (in master mode)
91870: 05/11/15: Re: Best Case Timing Parameters
91888: 05/11/15: Re: Multiple Waits 2 Xilinx WebPack???
92196: 05/11/23: Re: Xilinx DCM_ADV 280MHz no lock
92198: 05/11/23: Re: FPGA and metastability once again
92232: 05/11/24: Re: FPGA and metastability once again
awa:
112023: 06/11/14: Programming model on FPGA
112037: 06/11/15: Re: Programming model on FPGA
112878: 06/11/30: Thesis
112914: 06/11/30: Re: Thesis
122287: 07/07/25: PC104+ communication with FPGA using Xilinx IPCore
122350: 07/07/25: Re: PC104+ communication with FPGA using Xilinx IPCore
<awaish2011@namal.edu.pk>:
157104: 14/10/13: Need ideas for FYP
157105: 14/10/13: Re: Need ideas for FYP
157146: 14/10/18: Re: Need ideas for FYP
157147: 14/10/18: Re: Need ideas for FYP
157344: 14/11/25: FYP Selection!
aweas:
14125: 99/01/14: AHDL VS. VHDL
14126: 99/01/14: AHDL VS. VHDL
14127: 99/01/14: AHDL VS. VHDL
14174: 99/01/17: Re: AHDL VS. VHDL
<awelker@students.uni-mainz.de>:
154923: 13/02/15: OSERDES as delay regulator e.g. Artix 7
awellfriend4u@gmail.com:
126872: 07/12/05: Re: ISE WARNING Xst:647
<awynne@controlsystems.com.au>:
52865: 03/02/25: XC9500 JTAG programming problems
axalay:
111456: 06/11/03: maximum distanse beetwin SFP-module and FPGA (RocketIO) ???
111508: 06/11/04: Re: maximum distanse beetwin SFP-module and FPGA (RocketIO) ???
111509: 06/11/04: Re: maximum distanse beetwin SFP-module and FPGA (RocketIO) ???
111511: 06/11/04: PCI
113872: 06/12/27: assigned a special pins in ISE
113914: 06/12/28: Re: assigned a special pins in ISE
114435: 07/01/16: Digital Filter and external PLL (VCO)
114440: 07/01/16: about XAPP028
114447: 07/01/16: Re: Digital Filter and external PLL (VCO)
114469: 07/01/17: Re: Digital Filter and external PLL (VCO)
114472: 07/01/17: Re: Clock Frequency
114558: 07/01/19: Phasse Detector
114597: 07/01/20: Re: Phasse Detector
114641: 07/01/21: Re: frequency-Phase Detector?
124867: 07/10/09: CY22393
126961: 07/12/06: Help! I want give MGTREFCLK LVDS clock to GTP_DUAL (FPGA-Virtex5)
126962: 07/12/07: Re: Help! I want give MGTREFCLK LVDS clock to GTP_DUAL (FPGA-Virtex5)
127038: 07/12/09: Re: Help! I want give MGTREFCLK LVDS clock to GTP_DUAL (FPGA-Virtex5)
127079: 07/12/11: Re: Help! I want give MGTREFCLK LVDS clock to GTP_DUAL (FPGA-Virtex5)
128049: 08/01/14: Help! Micriblase + plbv46_pci in Virtex5
128092: 08/01/15: Re: Help! Micriblase + plbv46_pci in Virtex5
128100: 08/01/15: Re: Help! Micriblase + plbv46_pci in Virtex5
128533: 08/01/30: Can I connect PLB and OPB to mlcroblase v7 (use EDK 9.2 and Virtex 5)
128535: 08/01/30: Re: Can I connect PLB and OPB to mlcroblase v7 (use EDK 9.2 and
131417: 08/04/21: opb_intc + PowerPC
131492: 08/04/22: Re: opb_intc + PowerPC
131944: 08/05/08: Quartus 7.2 and PCI Express
131951: 08/05/08: Re: Quartus 7.2 and PCI Express
131954: 08/05/08: Re: Quartus 7.2 and PCI Express
131958: 08/05/08: Re: Quartus 7.2 and PCI Express
131989: 08/05/09: Re: Quartus 7.2 and PCI Express
131991: 08/05/09: Re: Quartus 7.2 and PCI Express
132402: 08/05/26: Problem when for program and data memory use SDRAM
132404: 08/05/26: Re: Problem when for program and data memory use SDRAM
134296: 08/08/05: I whant connected one port of dual port BRAM from NIOS. help....
134298: 08/08/05: Re: I whant connected one port of dual port BRAM from NIOS. help....
136391: 08/11/13: Number of GCLKs: 9 out of 8 112% (OVERMAPPED)
136438: 08/11/17: Re: Number of GCLKs: 9 out of 8 112% (OVERMAPPED)
136439: 08/11/17: Re: Number of GCLKs: 9 out of 8 112% (OVERMAPPED)
149180: 10/10/06: StratixII GX development board
<axalay@gmail.com>:
106906: 06/08/22: ModelSim SE PLUS 6.1B. Problem to simulate RocketIO in GT_CUSTOM mode
106958: 06/08/22: Re: ModelSim SE PLUS 6.1B. Problem to simulate RocketIO in GT_CUSTOM mode
106960: 06/08/22: Re: ModelSim SE PLUS 6.1B. Problem to simulate RocketIO in GT_CUSTOM mode
107784: 06/09/01: problem generate PCI-32/66MHz with Coregen
107786: 06/09/01: Re: problem generate PCI-32/66MHz with Coregen
107788: 06/09/01: Re: problem generate PCI-32/66MHz with Coregen
108010: 06/09/04: Virtex2Pro: Xilinx PCI core mapping error
108011: 06/09/04: Re: Virtex2Pro: Xilinx PCI core mapping error
108015: 06/09/04: Re: Virtex2Pro: Xilinx PCI core mapping error
108267: 06/09/07: Xilinx LogiCORE PCI32
108276: 06/09/07: Re: Xilinx LogiCORE PCI32
110187: 06/10/12: rocketIO in custom mode
110190: 06/10/12: Re: rocketIO in custom mode
111029: 06/10/27: connecting SFP-module to Virtex2PRO
axel:
39094: 02/01/31: Re: Xilinx XC3020-70
Axel:
52780: 03/02/21: FPGA : best case delay timings
Axel Dietrich:
13311: 98/11/25: Xilinx6216 cal->edn conversion?
Axel Jantsch:
27954: 00/12/17: 4 associate professor/professor positions in System-on-Chip design
Axel Mammes:
150649: 11/01/31: Looking for contractor for FPGA-based multiUART
Axel Sautter:
33607: 01/07/31: Altera MPLD
Axil Frawley:
88048: 05/08/08: Re: Good intro books on OFDM?
axilon:
38213: 02/01/09: How can I relate Virtex2 pin names and Slice XY loc?
axr0284:
113887: 06/12/28: Re: ethernet checksum nightmare
113888: 06/12/28: Re: ethernet checksum nightmare
113938: 06/12/29: Re: ethernet checksum nightmare
114100: 07/01/04: measure setup and hold time
114140: 07/01/05: Re: measure setup and hold time
114157: 07/01/05: timing constraints properly setup
114288: 07/01/10: Re: measure setup and hold time
114314: 07/01/11: picoblaze RS-232 using 62.5 MHz
114319: 07/01/11: Re: picoblaze RS-232 using 62.5 MHz
114321: 07/01/11: Re: picoblaze RS-232 using 62.5 MHz
115831: 07/02/21: Determine error in asynchronous signal
115854: 07/02/22: Re: Determine error in asynchronous signal
115876: 07/02/22: Re: Determine error in asynchronous signal
116359: 07/03/07: Introducing picosecond delay between two output signals
116396: 07/03/08: Re: Introducing picosecond delay between two output signals
117733: 07/04/09: Measuring the period of a signal
117792: 07/04/10: Re: Measuring the period of a signal
118590: 07/04/30: synthesis tools
118624: 07/05/01: Re: synthesis tools
120027: 07/05/31: Chain of LUTs is being removed during par
120038: 07/05/31: Re: Chain of LUTs is being removed during par
121599: 07/07/09: A Way for a DSP to tell an FPGA to load itself from Flash
121608: 07/07/09: Re: A Way for a DSP to tell an FPGA to load itself from Flash
121633: 07/07/10: Re: A Way for a DSP to tell an FPGA to load itself from Flash
123894: 07/09/06: Clock boundary crossing
126859: 07/12/04: clock lines
126905: 07/12/05: Re: clock lines
127605: 08/01/03: Area group constraint
127876: 08/01/09: Creation of BUGMUX from non clock signals
133671: 08/07/09: Xilinx ISE impact outputs bad idcode when in batch mode but works in
136093: 08/10/31: FPGA implementation of a PCI module
136136: 08/11/03: Re: FPGA implementation of a PCI module
137424: 09/01/15: Creating a core from my VHDL code
138126: 09/02/06: clk synchronization of reset signal
138132: 09/02/06: Re: clk synchronization of reset signal
138453: 09/02/23: Quantitive value for slew rate
139008: 09/03/18: false path assignment for clock boundary crossing.
139611: 09/04/07: xilinx edk issues
139729: 09/04/10: Avnet spartan 3A design issue
139772: 09/04/13: microblaze and flash access
139775: 09/04/13: Re: microblaze and flash access
139797: 09/04/14: Re: Xilinx ISE bug, or?
139800: 09/04/14: microblaze and data bus matching access to external memory
139850: 09/04/16: microblaze and interrupt question
139854: 09/04/16: Re: How to constraint the In&Outputs of an ADC in XILINX ISE 9.2
139857: 09/04/16: xilinx SDK issues
145015: 10/01/19: IEEE fixed_pkg not recognized in ISE 11.1
<axr0284@yahoo.com>:
113880: 06/12/27: ethernet checksum nightmare
Ayaz Gul al-Sheikh:
<aydin3w@gmail.com>:
91522: 05/11/08: Internal signal to drive clock resources
Aylons Hazzud:
156808: 14/07/03: Re: What use of Python, Perl in FPGA development?
156810: 14/07/03: Re: What use of Python, Perl in FPGA development?
156820: 14/07/04: Re: What use of Python, Perl in FPGA development?
156821: 14/07/04: Re: What use of Python, Perl in FPGA development?
156894: 14/07/22: Re: Generating a desired synthesizable binary pulse train on FPGA
<aymanmimomimomimo@gmail.com>:
158865: 16/05/13: FPGA boards in egypt
aymmmm@gmail.com:
100924: 06/04/21: Bluetooth with FPGA?????
azam:
86802: 05/07/06: Has anybody run Virtex-4 FPGAs at 300MHz+ interface speed?
87267: 05/07/20: All of the design is being optimized away and logic removed
87279: 05/07/20: Re: All of the design is being optimized away and logic removed
87398: 05/07/22: Re: All of the design is being optimized away and logic removed
azcycle:
69519: 04/05/12: Decompiler for GAL JEDEC fusemap
69521: 04/05/12: Re: Decompiler for GAL JEDEC fusemap
Azeddien Sllame:
9489: 98/03/18: Test
9628: 98/03/27: Request..
10033: 98/04/23: Ask
<aziemer50@gmail.com>:
160581: 18/04/24: Re: Philips LA PM3585 disassembler software wanted
azim premji:
52188: 03/02/03: Difference between : CPLD , FPGA , ASICS
<azimalimoll@gmail.com>:
156749: 14/06/16: Re: PLA? PAL? PLD? GAL?
Aziz:
122170: 07/07/21: watchdog timer: interrupt handler: microblaze
Aziz AhmedSaid:
57408: 03/06/30: Does anyone know about hardware implementaions of the SVD ?
57630: 03/07/03: RE:can you please post a summary of your findings to the group?
<azzhang2007@hotmail.com>:
121468: 07/07/05: Does synplify 8.8 can support xilinx virtex5?
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