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> I was actually referring to rerunning a process (PAR or MAP are the >obvious big ones, but bitgen and translate are also one) rather than >just a result file or tool. This happened to me just yesterday in >6.2.1i Someone was working on a different part of the design than I >was (he was actually doing iterative floorplanning runs) and I changed >the names of some CONSTANTs in the .vhd source files to be more >descriptive. Project Nav insisted the he re-run synthesis and >translate, wasting nearly and hour of his time while he waited. >Said another way, just because the source has changed doesn't mean >that we want the tool to automatically recompile everything (there are >ways to graphically show that the eariler files are not in sync if >that is your worry). If you know of a way around this, please do let >us know! You won't get a lot of sympathy on that case from any of the people I have worked with. You need to talk to software people. This is the standard (and hard) source control/revision problem. The bigger the project the harder it gets. Basically, your edits shouldn't polute your friend's working area. It's hard enough getting/keeping things compiled correctly that it isn't worth any hacks to cover the case you described. (You can probably do it from the command line.) The general approach is usually something like this: You have a working copy of the files. After testing and such, you merge your edits into the master copy which is usually stored on a file server. Then, when it's convienent/appropriate, other people working on the same project should update their local copies from the master copy. Good systems have a mechanism for keeping track of who is editing which file, making sure that only one person at a time is editing a file, and/or merging edits from several people into the master copy. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 68126
The numbers are real. They greatly improved the BRAM outputs in V2 pro and
later parts. As for built in registers, yes that would have been nice provided
they could also be bypassed if not needed. The average user still is not
pushing the BRAM or any of the rest of the fabric anywhere near its capability.
Kevin Neilson wrote:
> I'm still mad at Xilinx for not putting built-in registers on the BRAMs.
> You don't have time to do anything with the BRAM output before registering
> it, so why burn up CLBs for that? Such registers are needed for the
> multipliers too.
>
> I did notice that the Tbcko of the slowest V2Pro part is listed as 1.68ns in
> the datasheet, so that does leave a lot of time to get to the registers if
> you are operating at, say 200MHz, and makes placement less critical. I
> don't know if the numbers are real though.
> -Kevin
>
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
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Article: 68127Synplify has a feature we call a compile point. A level of hierarchy can be designated a compile point with its own constraints. Instead of using file date checks to determine when to re-optimize and map we do a more sophisticated check that the result of the language front end produced the same starting point. This means that if you change constant names or add comments to a file, or add a function to a VHDL package that is not called inside the hierarcy, it will generally not result in a full re-compile. Compile points also automatically create a timing model which is used for compiling the level above. Compile points also work really well with the incremental mode of PAR. - Ken McElvain Marc Randolph wrote: > > I was actually referring to rerunning a process (PAR or MAP are the > obvious big ones, but bitgen and translate are also one) rather than > just a result file or tool. This happened to me just yesterday in > 6.2.1i Someone was working on a different part of the design than I > was (he was actually doing iterative floorplanning runs) and I changed > the names of some CONSTANTs in the .vhd source files to be more > descriptive. Project Nav insisted the he re-run synthesis and > translate, wasting nearly and hour of his time while he waited. > > Said another way, just because the source has changed doesn't mean > that we want the tool to automatically recompile everything (there are > ways to graphically show that the eariler files are not in sync if > that is your worry). If you know of a way around this, please do let > us know! > > Best regards, > > MarcArticle: 68128
Hello, I plan to use the RAM_B4 of the SPARTAN IIE FPGA in my design. Does anyone know how fast it is? In particular I was wandering whats the fastest I can run the clock of the RAM? Thanks,Article: 68129
In article <smt9609qub8etdrak9ajkvij0nukmljheg@4ax.com>, Phil Hays wrote:
> (tbiggs) wrote:
>
>> If you already are familiar with C, then learning Verilog will
>> go much faster.
>
> It's easier to write bugs in Verilog. Mastering VHDL will come
> sooner.
Speaking as someone who has watched an FPGA project shift from
2000 lines of VHDL, to 1100 lines of Verilog, to 3000 lines of
VHDL, and back to 1600 lines of Verilog (scope creep), I'll
stick with Verilog. My ability to find bugs scales poorly
with code size. VHDL is simply too complex for me.
I am also enamored with Icarus Verilog for system simulation,
and I know of no comparable quality libre tool for VHDL.
- Larry
Article: 68130Brian Philofsky wrote: > > Rudolf Usselmann wrote: > <snip> > >> Now, the simulation models I use are the once that came with ISE 6.2i. >> I double checked my Makefile and it is using: >> XIL_LIB = +libext+.v -y /tools/ise/verilog/src/simprims >> >> where ise is the root installation directory for ise 6.2i. > > I almost forgot you said you were using NC-Verilog. If you are using > the Project Navigator GUI to create the netlist, there is a bug in that > when you select NC-Verilog, it enables the switch to add a `uselib to > the netlist. That was not intended and is scheduled to be changed in > the next major version of the software. Really it does no big harm but > would likely yield your -y switch useless. If you want, you could > simply turn that off. It just turns it on when you change the simulator > to NC-Verilog but you can turn it back off yourself if you prefer not to > have the `uselib in there. Personally, I just pre-compile the library > using compxlib and do not use `uselib or the -y switch. If the > library Damn ! I knew about uselib but didn't check the verilog simulation model. Turns out somebody (probably me) forgot to update a link on the compute server ! We keep several generations of ise around, installed under ise_m.n and create a symbolic link "ise" pointing to the latest one. Well, the compute server was still pointing to 6.1 ... OK, I recompiled everything now and rerun the simulations. Now I correctly see no error messages after the normal startup complaints. And the test suite passes too. Why do you say that the "uselib" is not intended ? I find it actually quite useful - if I remember that it is there ! Saves me the trouble to look up the path for the library and specifying it ... <snip> > > -- Brian Again, thanks alot for your help ! Appreciate the fast turn around time ! :*) Regards, rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> http://www.asics.ws/ <- FREE EDA ToolsArticle: 68131
> Best results come when you do the PCB and PLD designs in parallel, >and swap the PCB pins as needed for best layout, and then >track that within the PLD design. I think that's worth repeating. Of course, it's a lot easier to do if you are the only person working on the project so you have/get to do everything. Sometimes, the CPLD/FPGA is the limiting factor and you are willing to work harder on the PCB layout. Sometimes it's the other way around. My usual recipe is to sketch out the one that seems harder, do the other, then go back and do the first to see if it works. Iterate until happy. (or it stops smoking) Many times, the big picture is pretty obvious. For example, consider what would happen if you had to do a bus swap between your chip and a PCI connector. In the ideal world, the pin to signal mapping would live in one file, and there would be programs/scripts/whatever to convert that file format into something that both the CPLD/FPGA tools could use and also the PCB layout chip library could process. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 68132
Hal Murray wrote: >> Best results come when you do the PCB and PLD designs in parallel, >>and swap the PCB pins as needed for best layout, and then >>track that within the PLD design. > > > I think that's worth repeating. Of course, it's a lot easier to do > if you are the only person working on the project so you have/get > to do everything. > > Sometimes, the CPLD/FPGA is the limiting factor and you are willing > to work harder on the PCB layout. Sometimes it's the other way around. > > My usual recipe is to sketch out the one that seems harder, do the other, > then go back and do the first to see if it works. Iterate until happy. > (or it stops smoking) > > Many times, the big picture is pretty obvious. For example, consider > what would happen if you had to do a bus swap between your chip and > a PCI connector. > > In the ideal world, the pin to signal mapping would live in one > file, and there would be programs/scripts/whatever to convert that > file format into something that both the CPLD/FPGA tools could use > and also the PCB layout chip library could process. On this very subject, a DOC from mentor states this : "..a vendor-neutral pin-out file called FPGA Xchange™. In the near future, all major FPGA vendors plan to support this format." Has anyone seen info/examples of this format ? -jgArticle: 68133
"tbiggs" <tnbiggs@yahoo.com> escribió en el mensaje news:39b51bc5.0403261857.3342fbc4@posting.google.com... > A few notes: snip > Verilog has a lot in common with C. If you already are > familiar with C, then learning Verilog will go much faster. after reading about this, it seems that the "good" (or at least the most promoted one) thing about Verilog is that is similar to C, that is faster and that is has more code density. as for VHDL, well, it has strong typing (or what i call it's more structured), it's slower (compared to Verilog) and it's more bulky and not so compact (the exact opposite...) But are those real comparison points?, i'd go for something more like "the X language is more bug proof, when you write something in X it'll synthetize for sure the way you wrote it". If not, then well we should just use what we've got best for each use; if matlab is good for simulating signal processing algorithms, then lets use it. If then we have to build hardware for it, well lets use an HDL; for verification there's another language, well lets use that one who was conceived with verification in mind; lets *not* try to use the same language for everything cause then it wont be as good as an specialized one, of course using the same language has the advantage that one person can do the whole work, from simulation to implementation. But is that optimal? i dont think it is, cause we need a lot of time to master each subject. After all usually you have different people for each part of the design, right?. what i dont understand is why does "Verilog has a lot in common with C" is so important? if you want programmets to write Verilog, then i'd understand, but i would have thought that people doing hardware, would be hardware people, electrical engineering people. I just dont understand this "common with C" thing. I would understand it if we were talking about real languages like french and spanish have some common things, and then it's easier to learn the other when you know the one, but here i think we're talking about the subjacent idea of the language, that is the hardware. maybe Im missing something obvious here (i just woke up and read this whole thread) if you know how to infer hardware, how does it works, etc, then using Verilog or VHDL should be the same, after all going from a language to another should be a matter of syntax when you know how to write the "algorithm" (the hardware in this case). I learned about VHDL sometime, and i didnt like the syntax in the beginning, but i didnt mind because i dont like any syntax. I admit that i even wished that it had a more C like syntax, but at the end of the lectures (30hours) i was already feeling comfortable with it. Some time ago, for some job interview i was required to know Verilog (well no required but it was a plus), so i tried to learn it, but either the book wasnt that clear either i couldnt focus on it cause i dont think i learnt anything. It seemed to me that Verilog was too "not structured", you could write something too many different ways and not knowing if it'd synthetize, how would it work, and this "non structured" thing made the code look messy. This "reg" keyword is weird, it's not a register, but something else, etc. In VHDL sometimes i've felt the same though i cant think in any example right now. But if it was that easy then why i had so much trouble?, maybe i just suck Anyway, both languages are good and bad at the sametime, they have their advantages and disadvantages and these are not even absolute, but relative, after all everything seems to be relative :) Maybe the best would be like an open language, where all the good things about both (and even other languages) are put together. Or maybe even XML :) where you describe your own language!! i'll apreciate any comments as im still thinking into learning also Verilog, though not so sure what use could i have for it since i know VHDL already (except for working for companies where verilog may be required...but then it'd be like the requirements of "military contract requeriments" you're talking about, dont you think?)Article: 68134
jeff_n_moz wrote: > we have been trying to get this done using VHDL, but have run into > multiple driver problem etc. we are unfamiliar with verilog but are > now learning it. Post your code here and let's see what is the problem. > if any of you could spare some time for us, please mail us at the > above address with any sugestions or code(either VHDL or verilog). Are you expecting someone to write the VHDL / Verilog for you? That way you won't learn anything. Post your code and let the group help you fix the bugs. Learning by doing is the way to go... You might also try comp.lang.vhdl or comp.lang.verilog as this problem is not specific to FPGA... JSArticle: 68135
On Thu, 25 Mar 2004 10:22:15 -0500, "Josh Model" <model@ll.mit.edu> wrote: >Hi all, > >Just going through the RocketIO documentation and was wondering if anyone >had 2 cents to add to my understanding-- > >I'm using the RocketIO in receive only mode for a custom app, no 8/10b >coding (transitions are guaranteed, though). Hopefully generating the >RXUSRCLK from the RXRECCLK. > >I'd like to use the 20 or 40-bit wide data path. The User's guide only >gives an example for the 10 bit wide path -- does anyone know where the >extra bits are kept for the wider paths? > >e.g. the 10-bit path is as follows (earliest... latest) > >RXCHARISK[0] & RXUNDISP[0] & RXDATA[7 downto 0] > >I'm guessing that this sequence is repeated for the wider paths, that is the >20-bit path is >RXCHARISK[1] & RXUNDISP[1] & RXDATA[15 downto 8] & RXCHARISK[0] & >RXUNDISP[0] & RXDATA[7 downto 0] Yes, that is correct. >but it's never spelled out anywhere. >Any advice/experience is much appreciated. See http://www.xilinx.com/bvdocs/userguides/ug024.pdf page 64, third paragraph: "In the bypassed configuration, TXCHARDISPMODE [0] becomes bit 9 of the 10 bits of encoded data. TXCHARDISPMODE [1:3] are bits 19, 29, and 39 in the 20- and 40-bit wide buses. TXCHARDISPVAL becomes bits 8, 18, 28, and 38 of the transmit data." and on page 65 "In the bypassed configuration, RXCHARISK and RXRUNDISP are additional data bits for the 10- , 20-, or 40-bit buses, similar to the configuration on the transmit side. RXCHARISK [0:3] relates to bits 9, 19, 29, and 39, while RXRUNDISP pertains to bits 8, 18, 28, and 38 of the data bus." >Thanks, > >--Josh Model You are welcome. Philip Philip Freidin FliptronicsArticle: 68136
How does AHDL (Altera's own HDL language) compared with Verilog or VHDL? What are the advantages (and the differences) between AHDL and the others? Thanks in advance tedArticle: 68137
If you look at the port definition it will tell you. For a 20 bit path you would follow the same rule. -------------- word lane one-----------------------------------------||||| -----------------Word lane zero ---------------------------------- RXCHARISK[1] & RXUNDISP[1] & RXDATA[15 downto 8] & RXCHARISK[0] & RXUNDISP[0] & RXDATA[7 downto 0] lwd Josh Model wrote: > Hi all, > > Just going through the RocketIO documentation and was wondering if anyone > had 2 cents to add to my understanding-- > > I'm using the RocketIO in receive only mode for a custom app, no 8/10b > coding (transitions are guaranteed, though). Hopefully generating the > RXUSRCLK from the RXRECCLK. > > I'd like to use the 20 or 40-bit wide data path. The User's guide only > gives an example for the 10 bit wide path -- does anyone know where the > extra bits are kept for the wider paths? > > e.g. the 10-bit path is as follows (earliest... latest) > > RXCHARISK[0] & RXUNDISP[0] & RXDATA[7 downto 0] > > I'm guessing that this sequence is repeated for the wider paths, that is the > 20-bit path is > RXCHARISK[1] & RXUNDISP[1] & RXDATA[15 downto 8] & RXCHARISK[0] & > RXUNDISP[0] & RXDATA[7 downto 0] > > but it's never spelled out anywhere. > Any advice/experience is much appreciated. > > Thanks, > > --Josh ModelArticle: 68138
Anyone had experiance similar to this? JTAG Chain of an xcv04s, an xc2v1000, a plx9030 and an idt dual port ram. iMPACT detects the chain and after loading the BSD files recognises it correctly every time. The JTAG chain seems very reliable - never have problems programming the devices. If I try the same from ChipScope it detects four devices, but says the first is an XCV00 and does not recognise the others. It lets me set the register lengths but still does not recognise the chips properly - let alone the ChipScope cores. I am using all the latest 6.2i versions of both ISE and Chipscope. Anyone know how to fix this? AndyArticle: 68139
Larry Doolittle <ldoolitt@recycle.lbl.gov> wrote in message news:<slrnc6aa0m.7c9.ldoolitt@recycle.lbl.gov>... > In article <smt9609qub8etdrak9ajkvij0nukmljheg@4ax.com>, Phil Hays wrote: > > (tbiggs) wrote: > > > >> If you already are familiar with C, then learning Verilog will > >> go much faster. > > > > It's easier to write bugs in Verilog. Mastering VHDL will come > > sooner. > > Speaking as someone who has watched an FPGA project shift from > 2000 lines of VHDL, to 1100 lines of Verilog, to 3000 lines of > VHDL, and back to 1600 lines of Verilog (scope creep), I'll > stick with Verilog. My ability to find bugs scales poorly > with code size. VHDL is simply too complex for me. > > I am also enamored with Icarus Verilog for system simulation, > and I know of no comparable quality libre tool for VHDL. > > - Larry I notice the VHDL fans have alot to say about how easy it is to write bugs in Verilog, I am sure its easy for newbies to write bugs in any language period. And who would ever want to buy a product written by a newbie either, newbies should always be under the wing of an oldtimer. The lint issue is a canard too. If I am editing code within the ISE editer when I make edits, I redo synthesis almost every few line to find any syntax errors, and when done I still know if speed is roughly same or just halved. Thats what counts for me, knowing if the performance is on track. If VHDL is large, truth is Verilog is also a large language (and getting much larger with SystemVerilog) with at least 5 ways to write code. But I suspect for most projects, pros only use one tiny subset of the language that synthesizes for RTL, I usually only use hierarchies of modules with assigns and always blocks, and almost nothing else. This is why I suggest looking at the Douglas Smith book and compare the code with schematic and V, v V. The always defines the FF nodes with possible logic behind the input. The assigns does the hook up with other wires or logic. Doesn't get any simpler than that. Other parts of the language for non synthesis can be used for testbenches but I use C instead for that until I need to do timing sims. The issue of unsigned only logic has never been an issue for me when describing detailed math blocks, if you know how to do bit wise arithmetic. It would be more of a pain in the nonsynth part. If I am reading someones elses code, I want to grasp in 1ns if possible what their code will synthesize to, IE I want to see what the chip/fpga size and design is going to be. I am sure the assign/always has an exact equiv in VHDL but I think the code would be 2x bigger and less easy to copy to C for C sims. I notice that comp.lang.vhdl conversation has always been at a newbie level, little point in going there except to help do homework. Now comp.lang.verilog seems to be going the same way, it used to have more input from working EEs. Its the logic that counts. regards johnjakson_usa_comArticle: 68140
On a sunny day (Sat, 27 Mar 2004 07:07:03 +0000 (UTC)) it happened Larry Doolittle <ldoolitt@recycle.lbl.gov> wrote in <slrnc6aa0m.7c9.ldoolitt@recycle.lbl.gov>: >In article <smt9609qub8etdrak9ajkvij0nukmljheg@4ax.com>, Phil Hays wrote: >> (tbiggs) wrote: > >I am also enamored with Icarus Verilog for system simulation, >and I know of no comparable quality libre tool for VHDL. Yes I use Iverilog too, it is fast, clean, and Linux command line. JPArticle: 68141
Hi all, I am new guy in this field and I am looking for a pieces of synthesizable VHDL code that implement 32-Word Single port RAM with latch at its output ports.The latches are transparent when the clock input CP is HIGH and latched when the clock input CP is LOW. Data is written into the RAM when CP input port is LOW with ENW (Enable write) input is also LOW. And one more things :-), How can I force synthesis tool to implement this RAM in EABs? I am using Maxplus II. Any ideas are welcome. best regards, NDQArticle: 68142
ted wrote: > How does AHDL (Altera's own HDL language) compared with Verilog or VHDL? I would guess that AHDL works only with Altera tools, Verilog & VHDL are tool independent and work with any tool. (simulators, synthesis,...) > What are the advantages (and the differences) between AHDL and the others? Don't know any advantages of using AHDL, but a major disadvantage: you're restricted to the Altera tools. What if you need to port your design to Xilinx, for example? Altera tools support VHDL and Verilog, so choose one of these. See the "study verilog or vhdl" thread in this group, started just a few days ago! BTW, does anyone use AHDL? If you do, why? JSArticle: 68143
tbiggs wrote:
> A few notes:
> Systemverilog is getting adopted very fast (not 'in 6 years'). Most of
> it is already in Synopsys's simulator, and will be in the next release
> of Mentor's. Cadence has also anounced support (I'm not sure of the
> schedule). Systemverilog has built in Vera--a nice assertion based
> test language. More is coming.
SV is being released in a multi-phase effort, as a result,
which version with which features are you talking about?
Will Accellera assertions of SV flavor and PSL align and
change the SV assertions?
> Why is everyone saying that VHDL is used more by FPGA designers?
Because according to marketing statistics it is.
> Everyone I know (and I know a LOT of FPGA designers) is doing Verilog,
> with the exception of the aerospace industry (because of military
> contract requirements).
All prior measures of Verilog vs VHDL were done with
marketing statistics which relate to $$$ of EDA tools
sold and nothing to do with actual user base. First,
ASIC tools $$$ >>> FPGA tools $, hence, the EDA
market statistics really only show what the ASIC market
was doing. Furthermore, for the period that is
often quoted, a Verilog simulator cost more than VHDL
simulator.
What is the user base really at? Based on newsgroup
traffic (comp.lang.vhdl vs. comp.lang.verilog),
VHDL usage is 2X that of Verilog.
It would be interesting to see some current market
statistics that some how measure user base with
tool cost and number of tools factored out (a lint
tool is nice to have for VHDL, but a must have for
Verilog).
> Synopsys's CEO all but admitted that because of Systemverilog, they
> will not be doing add-on work with VHDL in the future. This is HUGE.
At DesignCon this year, Aart back peddled alot.
He projected that Synopsys will be supporting VHDL for at
least another 10 years. This gives us lots of time
to forget about what he said when he learns he was
wrong.
What was Aart's motivation? He bought the company that
originated SystemVerilog. He needs to justify the purchase.
He has good market share in Verilog and neglible market
share in VHDL, so little supprise that he is trying to convince
the market to move to SV.
Besides, Aart's prediction may be the doom of SV. After all
just a short while ago, he was promoting SystemC.
Since you bought Aart's marketing statement, I have a nice
bridge to sell you to go with it. :)
> Verilog has a lot in common with C. If you already are
> familiar with C, then learning Verilog will go much faster.
Well lets be honest.
Verilog and C are similar WRT C's operators and C's if statement.
For all other parts there are significant differences (no switch
statement in Verilog, no "{" and "}" instead they are replaced
with "begin" and "end" - talk about verbosity).
As one who did a significant amount of programming in C in
college, the one big thing I hated about C was the operators -
it is much easier to understand VHDL's and, or, xor operators.
VHDL does have some needed improvements WRT to code compactness,
however, the VHDL-200X effort is targeting these and some are
being fixed in the VHDL-200X fast track effort.
Note comparing code compactness by trying to apply
Verilog coding techniques in VHDL will always lead to
larger code. You need to learn enough of VHDL to understand
the syntax for things Verilog does not have to produce
code that is more effective than Verilog.
For example, in VHDL, significant amounts of datapath
code is written as concurrent signal assignments rather
than using a process/always. The following is a shift
register that is parameterizable for both depth and bit
width:
entity ShiftMxN is
generic (
depth : integer := 4 ;
width : integer := 8
) ;
port (
Clk : In std_logic ;
ShiftIn : In std_logic_vector ( width-1 downto 0) ;
ShiftOut : Out std_logic_vector ( width-1 downto 0)
) ;
end ShiftMxN ;
architecture RTL of ShiftMxN is
type RegBankType is array(Depth - 1 downto 0) of
std_logic_vector(Width-1 downto 0) ;
signal ShiftReg : RegBankType ;
begin
ShiftReg <= ShiftReg( (Depth - 2) downto 0) & ShiftIn when rising_edge(Clk) ;
ShiftOut <= ShiftReg( Depth - 1) ;
end RTL ;
We can do this now in VHDL. There are simplifications that
are being introduced in VHDL-200X that will further reduce
the code above. One proposal creates unconstrained arrays of arrays.
Hence, in one of the standard packages we can create arrays of
arrays. Another proposal suggests that we allow active code
in the entity. For simple code such as the above, this allows
all of the code to be written in the entity statement and removes
the necessity for an architecture statement.
While Verilog-2001 and SV are adding VHDL like features to the
languge, you need to look at the details before you buy in.
For example, Verilog now has a library concept, however, as far
as I can tell, separate Verilog libraries do not give you a
separate name space like in VHDL. In Verilog, this means if
separate FPGAs have identically named blocks, the names must be
changed. In VHDL, you only need to compile them in separate
libraries.
Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Article: 68144Hi I have pic (12f675) which is conected to a sensor. PIC will digitise the signal from sensor and sends it over one of the on of IO pins. This pin is connected to Rx wire of the rs232 cable. the other end of rs232(male) is connected to console port of Altera nios board. the PIC continuously sends 8 bit data over the Rx line of the console. My problem is, when I am trying to read a byte from console using the default function provided ie nr_uart_rxchar(). Its always returning -1. I have tested the my program on PIC by connecting it to serial line of a pc and reading the serial line using a program. It just works fine. I did not change any parameters on nios board as I am using the default nios values with PIC also. Please ignore my ignorance as I am just begingin to work with rs232. I am sure I am missing something here. I would appreciate any pointers or help regarding this. Thank you SrikanthArticle: 68145
Hi, I was wondering if there is a way to "copy" a serial prom device (EPC 1441 to be specific). Is the programmer able to read, and later replicate the design, if the source file is lost for example.. any help (and directions) is appreicated.. Yehia.. someone2003@gawab.com http://www.beconvinced.comArticle: 68146
"ted" <edaudio2000@yahoo.co.uk> wrote in message news:c54bf83f.0403270552.266bbebb@posting.google.com... > How does AHDL (Altera's own HDL language) compared with Verilog or VHDL? AHDL only works for Altera hardware. I will avoid using proprietary language like that. It makes your design not portable. You can't migrate your design to Xilinx or ASIC. Why not join the masses by using either Verilog or VHDL? HendraArticle: 68147
"paris" <malaka@email.it> wrote in message news:c43le0$20va$1@avanie.enst.fr... > what i dont understand is why does "Verilog has a lot in common with C" is > so important? > if you want programmets to write Verilog, then i'd understand, but i would > have thought that people doing hardware, would be hardware people, > electrical engineering people. I just dont understand this "common with C" > thing. I agree with you! In fact, I will avoid thinking like C while designing in Verilog. Verilog is not C, or any other programming languages for that matter. We use Verilog to describe a hardware, not to program a computer. So, thinking like C while writing Verilog code will most likely get one in trouble, as I have experienced myself! HendraArticle: 68148
Hi Ted, Our company used to use it. It's often cleaner code, and easier to write vs. VHDL. When I first started writing VHDL, I hated it, because it so unnecessarily verbose and redundant. Besides, what other language out there uses different "if" keywords depending on whether the condition is synchronous or asynchronous! Unfortunately the AHDL stuff could not be testbenched though, and AHDL is being abandoned even by Altera's newer tools, so you should definitely go with VHDL, Verilog, etc. If you want to check out a really cool language, take a look at Confluence from Launchbird Systems. I wish a language like that became standard. -- Pete edaudio2000@yahoo.co.uk (ted) wrote in message news:<c54bf83f.0403270552.266bbebb@posting.google.com>... > How does AHDL (Altera's own HDL language) compared with Verilog or VHDL? > > What are the advantages (and the differences) between AHDL and the others? > > Thanks in advance > > tedArticle: 68149
> What is the user base really at? Based on newsgroup > traffic (comp.lang.vhdl vs. comp.lang.verilog), > VHDL usage is 2X that of Verilog. Twice the traffic at comp.lang.vhdl is not a meaningful statistic. It could be that VHDL users require twice as much help sythesizing their designs. -- Pete
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