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someone2003@gawab.com (someone2003@gawab.com) writes: > I was wondering if there is a way to "copy" a serial prom device Yes.Article: 68201
Jim Lewis <Jim@SynthWorks.com> wrote in message news:<106gm8h2p2vf8a5@corp.supernews.com>... > Jim Lewis wrote: > >>What is the user base really at? Based on newsgroup > >>traffic (comp.lang.vhdl vs. comp.lang.verilog), > >>VHDL usage is 2X that of Verilog. > >> > > john jakson wrote: > > Aha, about as useless as counting the no of HDL textbooks in the local > > EE store. But the book writing industry is remote from HW design, they > > write what the Universities request. Infact its a wonder Verilog > > survived the almost 100% teaching of VHDL in most schools. I rarely > > hear of Verilog being tought in any school. > > How can you question this measure and not realize that > what Cooley has published is nothing more than twisting > EDA sales numbers trying to make the user base look like > it is mostly Verilog. In Cooley's numbers, I did not > see any normalization for tool prices. > > So why do you let Cooley pull the wool over your eyes. > You jest surely! Going back a few yrs long before Virtex and any interest in FPGAs I was immersed only in ASIC design, where ever I worked, and everyone I knew was using Verilog. I had no contact with edu, dod, eec, fpga EEs so I never saw VHDL. I did see a dearth of Verilog books in the stores. I very much got the impression that the professors or whoever were out to save the ASIC industry from itself, I could be mistaken. Imagine if all the C++ books got replaced with ADA or Java both of which have avid users that claim them to be better than C++. Would that force people to switch, nope don't think so (I respect all languages, but I don't have time to use them all). I am also sure the VHDL books were not aimed at FPGA users either (FPGAs were too puny back then), they were aimed at any HW engineers, but I felt they were mostly replicating each other. I only like or use the Douglas Smith book for V to V comparison. The ASIC industry is a very low level detail place where lack of libs for VHDL harmed it, that didn't get better till too late. The VHDL users are obviously working at higher levels than the typical Verilog user since the language allows so much more abstraction. Sometimes better features turn off potential users as some HW EEs are less familiar with CS and more powerfull langs. The improvements to Verilog ie SV are almost entirely aimed at the testbench crowd who often come from CS and not so much EE backgrounds. I would say that most of the Verilog people I know are also averse to programming and anti C if it should suggest any usefulness to HW design. As for Cooley, I think he's ok, he has his pulse on the industry, mostly ASICs though, and lots of people write him with inside info. As for the EDA industry and Cooley, it is Cooley who is left to straighten out the sales figures from EDA by measuring tapeouts, info that these companies are very secretive about. He gets his reports from credible sources with the plusses and lots of minusses. The usual thing is to do with layout SW, Magma v Cadence v Avanti etc. The lang issue was not top of list. If you don't believe the ASIC industry stats, go ask him yourself or see his site or visit DAC. I don't know how tool prices can be normalized, I do see high end FPGA tools going up in price, just look at all the Symplicity goodies, far out of my reach for sure. I suspect the ASIC EDA companies will come to FPGAs for future growth, if FPGAs really could handle 1M gates equiv, they are going to need far better tools than we have now. The layout SW is a prime example. Since there never was a comp.arch.asic (or vlsi or cmos whatever), Cooley site serves a similar purpose to this NG. One should expect a huge influx of new ASIC guys into FPGAs, some may even show up here. regards johnjakson_usa_comArticle: 68202
Try another synthesis tool. Synplify can usually get a substantial area reduction which could give you the room for your new functions. John Braun wrote: > I have a design that come very close to filling a Xilinx XCS20 - it > has 400 > complex logic blocks, and I'm using 388 (97% usage). Under Foundation > 3.1, > the design needs multiple reentrant routes to work properly, and > sometimes > bringing out debug information to a spare pin causes the whole thing > to fail to route. > > Yes, I know this is cutting it close, but I'm trying to make a new set > of functions fit on an old card. We're stuck with this design for now > (we could go to the larger XCS40, but > that would require getting new parts and replacing the existing ones - > time > consuming). My questions are: what is a good rule of thumb for CLB > usage %, > and are there particular issues with Foundation 3.1 that I should be > aware > of? > > (reply in thread so others can benefit from your expertise too...) > > Thanks in advance, > > JohnArticle: 68203
kellydingee@adelphia.net (Kelly) wrote in message news:<62b176ec.0403291155.425d4272@posting.google.com>... > I'm trying to find an experienced FPGA Engineer (currently holding a > clearance) - where do people like this look for jobs typically? The > clearance is critical to this opening. > > Thank you for your help - > > Kelly > kellydingee@adelphia.net How about careerbuilder or monster, they both have lots of "clearance only" positions. Somebody must be looking.Article: 68204
You can have multiple installations of ISE on your pc (choose a seperate directory for each installation). Just make sure the %XILINX% environment variable is pointing to the desired installation for that moment. Frank "George" <george_mercury@hotmail.com> wrote in message news:6d167a0a.0403290615.3e97ec3f@posting.google.com... > Hello, > Here In our company we have just installed the new ISE 6.2 plus the > SP1. Previoudsly we have been using the ISE 6.1 SP3 and the EDK 6.1 > SP2. Now that we have installed the ISE6.2 the EDK ( Xilinx Platform > Studio ) won't start. We get the following error: $XILINX does not > point to and iSE 6.1 installation. So does this mean that we have to > install the ISE6.1 back? > > Best Regards > George MercuryArticle: 68205
>PLAIN TEXT IS GOOD. I'm happy with binary files as long as there is enough info available to parse and manipulate them. One good way to do that is to provide programs to convert between binary and text format. Extra credit if they provide the source code so I can use their .h files rather than inventing my own and look at the way the process things for some hints when getting started. The vendors probably need that sort of program anyway for their own internal use. I remembered another thing for the list... You need to be able to figure all of the library files that are needed to compile/build a design. And which tools are used and what files that includes. The basic idea is that when you are happy with a design, you want to archive a copy of "everything" needed to reconstruct your working environment so you can put it back together again if you ever need to make a simple change. A note with the version of the tools might be enough if you have the CDs handy, but then you have to keep track of patches and such. If you are slightly paranoid, you need to know the version of the OS and such. Setting the hard disk aside might be a reasonable approach. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 68206
>Now, the people who try to use C as a hardware description language >are the ones I really don't understand. Two that I know about >(though not much about) are Handel C and Transmogrifier C. What's wrong with c for "describing" hardware? You just need a good library. The actual code is just subroutine calls and argument shuffeling. Using c might be slightly less dense than better approaches, but it works fine. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 68207
Learn the architecture and use schematic design entry. This gives you almost full control over FPGA resources. Think how to make the design denser (for example converting FFs to RAM and working in time multiplex - for example recently I have made this way 16 UART receivers with almost equal FPGA resources as the single one) - human brain is still much better than any expert system.Article: 68208
You may wonder but we make almost all our designs in OrCAD SDT 386+. For us (no flame, please! ;-) it is the best design entry tool ever. We drawn compact libraries for Spartan2+ and Virtex FPGAs, we modified the EDIF 2 0 0 netlister and we created an interface for embedding VHDL blocks into the schematics. Although this old program has some disadvantages in today's Windows envirinment, it allows for almost direct "brain-to-PC" connection than other, not so user's friendly tools before we will create our own one. And the 2D schematics is significantly more suitable for parallel tasks in FPGA than text files description. Last note - even large projects are composed from small block, so I do not agree the argument that schematics is not well suited for large designs...Article: 68209
When using modular design and partial reconfiguration options, the ISE translator replaces all FD-s with FDC-s, CLR-pin (SR) connected to constant GND. As SR is shared pin of the slice, SRL (or RAM) and flip-flop next to it can't reside in the same slice and if clock is 300+MHz, timings aren't meet. If partial configuration option isn't used, the implementation is correct. The FD replacing with FDC which has constantly grounded CLR is meanless. How to avoid this? Jaan.Article: 68210
I need sync separator IP which works like Gennum GS4982. Can I get any information about that? Or is there any web site that introduces existing IPs? Thank you for your answer.Article: 68211
On Tue, 30 Mar 2004 18:58:36 +0900, "coreDEVIL" <coredev@korea.com> wrote: >I need sync separator IP which works like Gennum GS4982. >Can I get any information about that? Gennum's website :-) But this is an analog function. You could not implement it in any FPGA I can think of. You could digitise the incoming video, remembering that your A/D conversion needs enough dynamic range to digitise sync tips as well as the full video span. That means you need one more bit of precision in the A/D than you would otherwise require. Having digitised it, you would then need some fairly simple DSP to identify the sync tips and black level, slice the sync signal at a threshold halfway between these two values, then black-level-clamp your video by subtracting the black level from every sample. Beware interactions between these DC-restoring operations in your DSP, and the AC coupling circuitry that is sure to exist at the input of your A/D. Note also that the GS4982 also performs various sanity checks on the incoming signal, such as checking that its line scan rate is reasonable. These are fairly easy to do in DSP, but need some careful thought to be sure that you are implementing the checks in a sufficiently general way. This is a fairly straightforward project and we would be happy to quote you for the development. >Or is there any web site that introduces existing IPs? www.opencores.org and www.free-ip.com are good places to start, although I wasn't hugely impressed with the free-ip CORDIC module when I looked at it. Caveat raptor. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 68212
Rudolf Usselmann wrote: > > So, I'm trying to use these fancy DCMs that everybody > is talking about ! Looking at the data sheet, these are > some damn impressive pieces of work. > > So I have a design that uses two clocks. Neither one is > available on my development PCB. Lets throw in some numbers > to make it a bit simpler: I need 60 and 75 MHz, my development > board only has a 100MHz oscillator. > > Hmm, sounds like a simple problem to solve. Pull up Arch. > Gen., configure two DCMs, one fo 60 the other for 75 MHz. > edit the files to pull out the IBUFG to serve both of the > DCMs, done, right ?! wrong ! > > Now the fight with the tools begins. First Synplify, had to > learn I had to put the clock in to separate groups so it > will constrain them independently. So far so good. > > No I want for ISE to treat them separate as well. But it > just refuses. It will accept the input clock as 100MHz, > and one of the other once (either 60 or 75) as an independent > clock, but the other one it will make dependent on the input > clock, and come up with cycle times of 22++ nS. > > Now I did do a trial synthesis and P&R without the DCMs > and know that theoretically there should be no problems > whatsoever to meet the required timing. But ISE starts of > the timing report with some 10 ns as the first entry: > Slack: -9.417ns (requirement - (data path - clock path > skew + uncertainty)) > > I have no idea where it is taking this from ! > > How do I tell ISE to treat ALL clocks separate, even though > some of them are used in the same module ? > > Thanks, > rudi I'm following up to my own message, I made some additional discoveries: 1) It appears the architecture wizard is instantiating BUFGs and IBUFG. Both of them are modeled as a simple buffer, with out the "synthesis black box" directive, which makes the syntheis took remove them. Adding "synthesis black_box" to both modules in the xilinx libraries, leaves them. 2) If I use different clock inputs for both DCMs all my problems seem to go away. How can I use a single clock input for both DCMs ??? Thanks, rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> http://www.asics.ws/ <- FREE EDA ToolsArticle: 68213
Hi, I have often seen the question "How do you calculate the required FIFO depth (length) ?" been asked. How do you answer this question? I wonder if this is what people mean: Consider two asynchronous blocks each generating data at rates R1 and R2 such that R1 > R2. Calculate the depth of a FIFO required between these two blocks so that there is no data dropped. No feedback/handshake mechnism should be assumed between the two blocks. In such a case, do we have a general solution? Thanks, AnandArticle: 68214
"Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in message news:9fki60l45bt7p7eu8l0ojttb9ju30klue0@4ax.com... > On Tue, 30 Mar 2004 18:58:36 +0900, "coreDEVIL" > <coredev@korea.com> wrote: > > >I need sync separator IP which works like Gennum GS4982. > >Can I get any information about that? > > Gennum's website :-) > > But this is an analog function. You could not implement > it in any FPGA I can think of. > > You could digitise the incoming video, remembering that > your A/D conversion needs enough dynamic range to digitise > sync tips as well as the full video span. That means you > need one more bit of precision in the A/D than you would > otherwise require. Having digitised it, you would then > need some fairly simple DSP to identify the sync tips > and black level, slice the sync signal at a threshold > halfway between these two values, then black-level-clamp > your video by subtracting the black level from every > sample. Beware interactions between these DC-restoring > operations in your DSP, and the AC coupling circuitry that > is sure to exist at the input of your A/D. > > Note also that the GS4982 also performs various sanity > checks on the incoming signal, such as checking that its > line scan rate is reasonable. These are fairly easy to > do in DSP, but need some careful thought to be sure that > you are implementing the checks in a sufficiently > general way. > > This is a fairly straightforward project and we would be > happy to quote you for the development. > > >Or is there any web site that introduces existing IPs? > > www.opencores.org and www.free-ip.com are good places to > start, although I wasn't hugely impressed with the free-ip > CORDIC module when I looked at it. Caveat raptor. > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services > > Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK > Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com > Fax: +44 (0)1425 471573 Web: c > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. I forgot to say "I use that IP on asic work". I know this is FPGA News group, but there's no asic news group that I know, so I asking in this group. Sorry. I visited Gennum web site but I can't get any information on that. I'm not searching for free IPs. I can pay for some GOOD IPs. Can anybody suggest me for some good commersial IP company? Sorry for my poor English, and Mr.Bromley, Thanks for your answer.Article: 68215
On Tue, 30 Mar 2004 18:01:23 +0530, Anand P Paralkar
<anandp@sasken.nospam.com> wrote:
> Consider two asynchronous blocks each generating data
> at rates R1 and R2 such that R1 > R2. Calculate the depth
> of a FIFO required between these two blocks so that there
> is no data dropped. No feedback/handshake mechnism should
> be assumed between the two blocks.
>
>In such a case, do we have a general solution?
If you insist on no feedback, how can you ever possibly
solve the problem of data overrun in the R1->R2 direction
when R1 > R2 ?
FIFOs are good when you have "bursty" data transfer,
so that the long-term data rate is slow enough for the
slower receiver to catch up during idle times. If
that's what you mean, it seems to me that the calculation
is fairly simple. Given a burst of N data items transmitted
at the higher rate R1, and received at the slower rate R2:
burst duration = N/R1
items received in that time = (N.R2)/R1
backlog that must be stored in FIFO = N - (N.R2)/R1
= N.(R1-R2)/R1
Any sensible designer will then make the FIFO somewhat
longer than this, to accommodate any latency or response
time in the receiver. Given a response time T, you need
an additional T.R1 locations in the FIFO.
It's also clear that the receiver will need some time
to consume this backlog, so the idle time between bursts
must be long enough; the minimum time is of course
mop-up time = backlog/R2 = N.(R1-R2)/(R1.R2)
Going in the other direction, from a slow transmitter to
a fast receiver, the FIFO needs to be only long enough
to hold any data items that might be received during
the receiver's response time, T.R2
Have I missed something, or is it really that easy?
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 68216Hi Marija, The delay of a path includes delays of the components and delays of the routing. Synthesis knows nothing about routing delays. Don't pay attention to the frequency, synthesis shows, it just a estimated number. You have to run PAR, then Timing Analyser and then go back to the source. Jaan.Article: 68217
On Tue, 30 Mar 2004 21:53:07 +0900, "coreDEVIL" <coredev@korea.com> wrote: [...] >> >I need sync separator IP which works like Gennum GS4982. [...] >I forgot to say "I use that IP on asic work". OK - so you have analog cells in your process, I guess. >I know this is FPGA News group, but there's no asic news > group that I know, >so I asking in this group. Sorry. No problem. >I visited Gennum web site but I can't get any information on that. >I'm not searching for free IPs. I can pay for some GOOD IPs. >Can anybody suggest me for some good commersial IP company? Did you ask Gennum? They also do custom ICs, and they have very good expertise in mixed-signal. In the UK, you could try Wolfson Microelectronics: http://www.wolfsonmicro.com/ >Sorry for my poor English It is **MUCH** better than my Korean :-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 68218
On a sunny day (Tue, 30 Mar 2004 12:05:34 +0100) it happened Jonathan Bromley <jonathan.bromley@doulos.com> wrote in <9fki60l45bt7p7eu8l0ojttb9ju30klue0@4ax.com>: >On Tue, 30 Mar 2004 18:58:36 +0900, "coreDEVIL" ><coredev@korea.com> wrote: > >>I need sync separator IP which works like Gennum GS4982. >>Can I get any information about that? > >Gennum's website :-) > >But this is an analog function. You could not implement >it in any FPGA I can think of. > >You could digitise the incoming video, remembering that >your A/D conversion needs enough dynamic range to digitise >sync tips as well as the full video span. That means you >need one more bit of precision in the A/D than you would >otherwise require. Having digitised it, you would then >need some fairly simple DSP to identify the sync tips >and black level, slice the sync signal at a threshold >halfway between these two values, then black-level-clamp >your video by subtracting the black level from every >sample. Beware interactions between these DC-restoring >operations in your DSP, and the AC coupling circuitry that >is sure to exist at the input of your A/D. > >Note also that the GS4982 also performs various sanity >checks on the incoming signal, such as checking that its >line scan rate is reasonable. These are fairly easy to >do in DSP, but need some careful thought to be sure that >you are implementing the checks in a sufficiently >general way. > >This is a fairly straightforward project and we would be >happy to quote you for the development. > >>Or is there any web site that introduces existing IPs? > >www.opencores.org and www.free-ip.com are good places to >start, although I wasn't hugely impressed with the free-ip >CORDIC module when I looked at it. Caveat raptor. >-- >Jonathan Bromley, Consultant Him, jou mention DSP. I did this without, but there are some catches. First of cause there is thr DC level, it is not that you need ONE more bit (although theoretically you are right), you just need to dedicate the ful 256 steps to the composite, and sync will be 30% of that. So you would likely want to slice at 15 %. But this requires a GOOD DC sync tip clamp, and that clamp needs a clamp pulse, which wont't be there until you slice sync right :-) So, to 'lock in' I just made (without DSP) a register that kept the minimum (bottom sync) everytime the signal was lowest, and then each frame (or was it several lines) increased, so slowly increased. Also some limit against overflow :-) So now, the 'syn tip register' slowly follows the sync tip. Add some counts to that and slice there. This works very well. Once the H PLL is locked (to the sync), you can do more.. But main point no DSP whatsover I used. I am a bit reluctant to release the Verilog code, as this project is one I hope to actually sell, but this should help one on the way. JPArticle: 68219
>>I have pic (12f675) which is conected to a sensor. PIC will digitise the >>signal from sensor and sends it over one of the on of IO pins. This pin >>is connected to Rx wire of the rs232 cable. the other end of rs232(male) >>is connected to console port of Altera nios board. the PIC continuously >>sends 8 bit data over the Rx line of the console. My problem is, when I >>am trying to read a byte from console using the default function >>provided ie nr_uart_rxchar(). Its always returning -1. I have tested >>the my program on PIC by connecting it to serial line of a pc and >>reading the serial line using a program. It just works fine. I did not >>change any parameters on nios board as I am using the default nios > Gabor Szakacs wrote: > If you're really connecting the I/O pin of the PIC directly > to the RS232 line, you must be aware that you're not meeting > the standard voltage levels. It probably works with the PC > because they don't use standard circuits, either. True RS232 > requires voltages to swing below ground to guarantee switching > the receiver. Some receivers are modified with positive > threshold offset to accommodate TTL input signals. I don't > know what's used on the nios, but you should probably look at > the output of the receiver to see if your signal gets through. I was actually just using the serial port on the Nios Development board... The development board uses a Maxim RS232 transceiver (MAX3237). I looked really quickly at the datasheet, and it seems like it should be okay with a TTL input--input threshold low and high are 1.2/1.5 V. You should probably check yourself to make sure. One other thing that you can check once you're happy with the levels is the type of cable you're using to connect. For a normal PC serial port, pin 2 is receive, and pin 3 is transmit. http://www.interfacebus.com/Design_Connector_RS232.html But on the Nios development board, Pin 3 is receive and 2 is transmit. As a result, you can connect the Nios board to the PC using a regular serial cable (without a null-modem adaptor). I'm thinking that since you with no problem connecting the PIC to the PC, the serial connection probably needs to be switched in order to connect to the Nios. Hope that helps... DerekArticle: 68220
Hi, I've been happily using Chipscope Pro 5.2i (Release 2) together with ISE5.2.03i for quite awhile. Now suddenly it won't connect to the target anymore: COMMAND: open_cable ERROR: <P4JTAGCable> Error during Parallel 4 TAP Navigation ERROR: Failed detecting JTAG device chain ERROR: Opened Xilinx Parallel Cable but failed to detect JTAG Chain. This is exactly what is talked about in Xilinx Answer Record #17079, but the patch mentioned there a) does not help and b) should not be necessary for ChipScope Pro 5.2i (Release 2). iMPACT runs fine on the same machine, so the cable and the connection are perfectly ok, it is just ChipScope that won't connect anymore. Of course I tried reinstalling and such, doesn't help... I guess I must've done something to mess it up, but I haven't the slightest idea what could possibly have caused this. Any ideas? Best regards, Sean DurkinArticle: 68221
Hi, we are planning to upgrade our Linux cluster with new nodes. These machines will be maily dedicated to run Place&Route and, as we are mainly targetting Xilinx devices, the main performance criteria will be P&R times. has anyone benchmarks showing run times for both these processors? Does anyone know if Xilinx is coming with a 64 bits native code? I think that this is happening with Altera's Quartus 4.1. Thanks in advance for the answers! Regards TomasArticle: 68222
Hi Hendra, Yes Maxplus II/Quartus only support synthesizable code. You can simulate using waveforms but no behavioural testbenching. -- Pete "Hendra Gunawan" <u1000393@email.sjsu.edu> wrote in message news:<c4a458$6gkqf$1@hades.csu.net>... > "Peter Sommerfeld" <petersommerfeld@hotmail.com> wrote in message > news:5c4d983.0403271458.43ee7ad9@posting.google.com... > > Unfortunately the AHDL > > stuff could not be testbenched though > > Is that why Altera MaxPlus II does not support testbench for Verilog either? > Other tools support testbench, MaxPlus II doesn't! > > HendraArticle: 68223
On Tue, 30 Mar 2004 14:22:09 GMT, Jan Panteltje <pNaonSptaemltje@yahoo.com> wrote: > >Him, jou mention DSP. >I did this without, but there are some catches. >First of cause there is thr DC level, it is not that you need ONE >more bit (although theoretically you are right), you just need to >dedicate the ful 256 steps to the composite, and sync will be 30% >of that. Leaving only about 200 grey levels. That's approaching poor quality, I suggest. >So you would likely want to slice at 15 %. >But this requires a GOOD DC sync tip clamp, and that clamp needs a >clamp pulse, which wont't be there until you slice sync right :-) Yes. But you can DC-clamp to the negative peaks (sync tips), then reference everything off that - just as you describe below. >So, to 'lock in' I just made (without DSP) a register that kept >the minimum (bottom sync) everytime the signal was lowest, and then >each frame (or was it several lines) increased, so slowly increased. I hate to say this, Jan, but that sounds an awful lot like DSP to me. Not very hard DSP, but you're processing a signal, and it's been digitised... fits my definition of DSP. >Also some limit against overflow :-) I would suggest that it would be better to use 9-bit or even 10-bit data, and allow yourself plenty of dynamic range. That way, it is no longer essential for your analog sync-tip tracking to be excellent, and you can still get 8 bits or even 9 bits of precision in digitising the true video signal. 8 bits is IMHO the absolute minimum that you need for good visual quality on a good monitor. 7 bits looks imperfect, 6 bits is rubbish. >So now, the 'syn tip register' slowly follows the sync tip. >Add some counts to that and slice there. >This works very well. Agreed. >Once the H PLL is locked (to the sync), you can do more.. >But main point no DSP whatsover I used. I've disagreed with you, and you can make your own judgment. OK, it has no large FIR filter and no FFT; but why are those things needed to qualify as DSP? >I am a bit reluctant to release the Verilog code, as this project >is one I hope to actually sell, but this should help one on the way. It seems to me that the Verilog is pretty simple stuff. The clever part is getting the sync-tip tracking right, in all possible combinations of noisy sync signals, occasional spikes on the signal, a DC level that drifts around, lots of jitter on the sync (thank you very much for nothing, VCRs!), colour signals that can push the video level below black, out-of-spec slew rate on the sync edges, non-monotonic edges on the sync, ... OK, I'll stop now. You get the idea. My point to Jan is that he already knows about all this terrible stuff, and knows the tricks (analogue or digital) to get around them. It's that special application knowledge that will make or break your product - the Verilog code is easy once you have the design sorted out. Good luck with it. Good to know that you are making interesting progress with your Verilog-driven video processing. It's something that has been close to my heart for some time :-) Did you get anywhere with your R-2R ladder successive-approximation converter in a Xilinx FPGA, using an LVDS receiver as a comparator??? -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 68224
hey, i'm just trying out the incremental design flow (and modular) and when i was reading the xapp from xilinx it said that the slice utilization of the area groups have to have a similar percentage. how come? and i was just wondering, do a lot of designers use this type of design flow (or the modular)? thanx for your reply's in advance, kind regards, Yttrium
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