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Messages from 68675

Article: 68675
Subject: Re: VirtexII : XC2V2000 Design
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Tue, 13 Apr 2004 21:01:32 +0000 (UTC)
Links: << >>  << T >>  << A >>
Steve Merritt <steveb_merritt@nospamhotmail.com> wrote:
: Hi Saleem,

: Firstly - unless there are reasons you haven't yet explained I would use the
: platform flash parts for configuration, not the XC18V04.  The XC2V2000
: requires 7.5Mbits of config memory so you would be able to use a single
: 8Mbit part with no problems at all.  The platform flash parts are cheaper
: and available in much larger sizes (see here:
: http://www.xilinx.com/publications/matrix/prom_color.pdf)

As with other (Xilinx) parts, availability _is_ a thing to consider...

For example nuhorizons only shows the XCF01 in one single package available...
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 68676
Subject: pi/4 DQPSK demapping
From: kyrten <kyrten@noreply.com>
Date: Tue, 13 Apr 2004 23:27:25 +0100
Links: << >>  << T >>  << A >>
In a project at university, I'm using 2048 pt FFT core from Xilinx
CoreGenerator and the output data are modulated with pi/4 DQPSK.

What's the best way to demapping the symbols?
Should I use comparators and decision boundary?

Any info or papers related to this will help.


Thanks in advance. 

Article: 68677
Subject: Re: Problem downloading with parallel converter
From: "Hendra Gunawan" <u1000393@email.sjsu.edu>
Date: Tue, 13 Apr 2004 17:59:13 -0700
Links: << >>  << T >>  << A >>
"Peter Seng" <NOSPAM@seng.de> wrote in message
news:c5g43e$jhp$1@online.de...
> Hello,
>
> 1.) what are the parallel port settings You use? SPP,  PS2, EPP or  ECP
> mode?
> If possible, try all in above order. Most incompatible mode is ECP mode.
> We randomly suggested Quatech SPP-100 to our customers using our
> parallel-port based products, never had problems...

Hi Peter, first of all, thanks for answering my questions.
How do I know which settings I have?
In device manager, it shows that I have LPT1, no interrupt and IO range but
it doesn't say anything about the port settings.

> 2.) what kind of download cable do You use?
> Xilinx parallel cable III (DLC5) or newer cable (parallel cable IV)?

I have regular parallel cable. I believe it is the same with the parallel
cable that people use for parallel scanner and backup tape drive.
Thanks in advance!

Hendra



Article: 68678
Subject: Re: What is the use of MAX7128?
From: "Kelvin @ SG" <kelvin8157@hotmail.com>
Date: Wed, 14 Apr 2004 10:29:37 +0800
Links: << >>  << T >>  << A >>
anyway, some chinese laboratories are selling EPM7128SLC84 boards for
50US$...targetting
the college students there...It looks impressive but I don't know how it
competes with other board...

http://www.fpga.com.cn/solution/jx002b.htm

Kelvin




Andy Peters <Bassman59a@yahoo.com> wrote in message
news:9a2c3a75.0404080941.3fa6a305@posting.google.com...
> "Kelvin" <kelvin8157@hotmail.com> wrote in message
news:<c53nnm$nf0$1@reader01.singnet.com.sg>...
> > Hi, there:
> >
> > I saw some boards with a EPM7128SLC84...which I found can only implement
a
> > simple 8-bit multiplier...
> > For example, http://www.fpga.com.cn/solution/jx002b.htm ...
> >
> > Is there any market for such tiny FPGA chips? What are they?
>
> Well, #1 is that it's a CPLD.  #2 is that a 128-macrocell CPLD was
> certainly sufficient for me to use as the controller for a audio
> digital delay.  I2S in, I2S out, SRAM controller, digital input level
> meter, the works.
>
> Not every design needs that multi-million-gate thousand-ball
> thousand-dollar FPGA, ya know.  Betcha that brands A, L and X sell
> more of the small/midsize CPLDs than they do of the
> super-big/super-fast devices.
>
> -a-



Article: 68679
Subject: Re: SAA7111 YUV
From: "Kelvin @ SG" <kelvin8157@hotmail.com>
Date: Wed, 14 Apr 2004 10:35:41 +0800
Links: << >>  << T >>  << A >>
a simple C program can do that...one RGB format is called BMP...
google YUV to RGB conversion and see...

Kelvin





Wang Feng <fwang11@pub3.fz.fj.cn> wrote in message
news:c4l7v6$rkf$1@news.yaako.com...
>
> Hi,
>
> I have stored YUV422 16 bit data from Philips SAA7111A. The Y data and UV
> data
> in 2 files. Now how to combine Y and UV
> into RGB format for display on PC?
>
> Please reply to fwang11@pub3.fz.fj.cn
>
> Thanks in advance.
>
> Wang, Feng
>
>
>



Article: 68680
Subject: Help - DDS Control in Virtex II
From: "jonathan" <dodgepickup318@yahoo.com>
Date: Tue, 13 Apr 2004 22:37:33 -0500
Links: << >>  << T >>  << A >>
Hi All,

    I am not looking for an easier answer (unless one wants to offer it :-))
as I am looking for a good source to learn from or a place to begin looking
for answers.
I have a Xilinx Virtex II as part of the Xilinx ExtremeDSP Kit and I am
building a digital mixer as my first step in learning. My problem is this:
I need a program written in C++ to have control of the DDS frequency running
in the FPGA. I need to find an answer such as where is the memory or
register location going to be set in the fpga? Or, specific information
about how to use the ZBT ram as an interface between a C program and the
DDS? I am also using Xilinx System Generator if anyone is familiar with it.
Thanks for any pointers or information sources.

Jonathan
dodge318@tamu.edu



Article: 68681
Subject: Re: Writing PCI constraints in Altera
From: "Subroto Datta" <sdatta@altera.com>
Date: Wed, 14 Apr 2004 03:42:02 GMT
Links: << >>  << T >>  << A >>

"tushit" <tushitjain@yahoo.com> wrote in message
news:ec6aab0.0404130920.42fa2dfd@posting.google.com...
> Hi,
> I am fairly new to FPGAs. I am trying to write the constraints for the
> PCI module on an Altera Stratix device. I am using QuartusII for all
> synthesis and P&R.
> The PCI spec says I need to ensure a setup time of 7ns for all pins.
> The PCI clock itself works at 33Mhz. I want to know the following:
> 1) Is it okay if I just constraint the PCI clk of my design to 50Mhz
> (30ns for the 33Mhz clock and another 10ns to ensures that the setup
> time is met)? I realise this will be an overkill on the internal logic
> but may save me some effort.
> 2) The other way I think to do this is to constraint the PCI clk to
> 33MHz and specify the external delay on all the PCI signals to 7 or
> 8ns. While setting PCI clk to 33Mhz I also ticked the option of
> including external delays in the frequency calculation. Is this the
> correct approach? OR do I need to setup the tco.
> Thanks in advance.
> Regards
> Tushit

Hi Tushit,

   You can get an idea of the type of constraints required by downloading
the Altera  PCI Megacore and studying the constraint files that ship with
it. To download the PCI Megacore:

1. Open http://www.altera.com/products/ip/ipm-index.html
2. Type in PCI in the IP Megasearch box.
3. Click on the Try OpenCorePlus for PCI Compiler, 32 bit Master/Target.
4. Download the Free Evaluation.
5. Install it into a directory.
6. cd to pci_compiler-v3.0.0\pci_mt32\const_files
7. There are three constraint file scripts in this directory
a. mt32_66_30_ep1c12f324c7_q40.tcl
b. mt32_66_30_ep1s40f1020c6_q40.tcl
c. mt32_stratixii.tcl

Study the constraints created in the mt32_stratixii.tcl in particular the
procs set_pci_timing and constraint_file.

That should help answer your questions.

- Subroto Datta
Altera Corp.



Article: 68682
Subject: Re: Problem downloading with parallel converter
From: Matthew E Rosenthal <mer2@andrew.cmu.edu>
Date: Wed, 14 Apr 2004 00:12:49 -0400 (EDT)
Links: << >>  << T >>  << A >>
Hendra,
I doubt this will help much but I have a parallel IV cable and I have had
some times where it only works intermittently.  It works pretty
consistently for days and then for no apparent reason in starts acting
real wacky.  i.e. done did not go high, parallel tap navigation failure
I hypothesize that sometimes its cuz something is wrong with the jtag
chain but 2 things i try to fix the issue are.
1.  try downloading the design with chipscope instead of impact.
2.  try to program any proms on your board instead of programming the
device itself.

Those steps may lead to some more useful debug output.
for some reason the d/l in chipscope seems to work a higher percentage of
time.

matt

On Tue, 13 Apr 2004, Hendra Gunawan wrote:

> "Peter Seng" <NOSPAM@seng.de> wrote in message
> news:c5g43e$jhp$1@online.de...
> > Hello,
> >
> > 1.) what are the parallel port settings You use? SPP,  PS2, EPP or  ECP
> > mode?
> > If possible, try all in above order. Most incompatible mode is ECP mode.
> > We randomly suggested Quatech SPP-100 to our customers using our
> > parallel-port based products, never had problems...
>
> Hi Peter, first of all, thanks for answering my questions.
> How do I know which settings I have?
> In device manager, it shows that I have LPT1, no interrupt and IO range but
> it doesn't say anything about the port settings.
>
> > 2.) what kind of download cable do You use?
> > Xilinx parallel cable III (DLC5) or newer cable (parallel cable IV)?
>
> I have regular parallel cable. I believe it is the same with the parallel
> cable that people use for parallel scanner and backup tape drive.
> Thanks in advance!
>
> Hendra
>
>
>

Article: 68683
Subject: Re: Problem downloading with parallel converter
From: "Peter Seng" <NOSPAM@seng.de>
Date: Wed, 14 Apr 2004 09:22:09 +0200
Links: << >>  << T >>  << A >>
Hello Hendra,

comments see down:


"Hendra Gunawan" <u1000393@email.sjsu.edu> schrieb im Newsbeitrag
news:c5i2ao$6mpr9$1@hades.csu.net...
> "Peter Seng" <NOSPAM@seng.de> wrote in message
> news:c5g43e$jhp$1@online.de...
> > Hello,
> >
> > 1.) what are the parallel port settings You use? SPP,  PS2, EPP or  ECP
> > mode?
> > If possible, try all in above order. Most incompatible mode is ECP mode.
> > We randomly suggested Quatech SPP-100 to our customers using our
> > parallel-port based products, never had problems...
>
> Hi Peter, first of all, thanks for answering my questions.
> How do I know which settings I have?
> In device manager, it shows that I have LPT1, no interrupt and IO range
but
> it doesn't say anything about the port settings.

First try to make changes to the parallel port settings - see Quatech
documentation. If You can not change the mode, try to set base adress to
3BCh (this address should not be capable to work in EPP or ECP mode) or
contact Quatech and ask if the mode can be set to a user defined status.
Interupts are of no interest - they are not used by parallel cable III.
SPP and PS2 ports use a range of  3 adresses, EPP uses a range of 8 adresses
and ECP uses two ranges of  8 adresses.
Which I/O adresses are accessed (adresses and range)?

>
> > 2.) what kind of download cable do You use?
> > Xilinx parallel cable III (DLC5) or newer cable (parallel cable IV)?
>
> I have regular parallel cable. I believe it is the same with the parallel
> cable that people use for parallel scanner and backup tape drive.
> Thanks in advance!

??? do You use the Xilinx cable and a standard parallel cable to make the
Xilinx cable longer? If yes, try to use the Xilinx cable without the
extension. If You need to make the Xilinx cable longer be shure to use a
cable with all pins connected, meaning all ground and all signal pins of the
25-pin connectors are connected in a 1:1 fashion.
Look at the hints in the archieve of this newsgroup for any topics
concerning parallel cable III. Can´t give you hints cause we never had
problems with this cable, and most times we use our own download device,
emulating parallel cable III (but with very different hardware, amplifieing
and filtering).

>
> Hendra
>
>


good luk,

Peter Seng


#############################
SENG digitale Systeme GmbH
Im Bruckwasen 35
D 73037 Göppingen
Germany
tel  +7161-75245
fax  +7161-72965
eMail  p.seng@seng.de
net  http://www.seng.de
#############################



Article: 68684
Subject: Re: XPower: -tb switch
From: Brendan Cullen <bcullen@xilinx.com>
Date: Wed, 14 Apr 2004 09:07:59 +0100
Links: << >>  << T >>  << A >>
Hi Edward,

Edward wrote:

> Hello, I am currently using the command line version of XPower to
> estimate power consumption on my designs. A -tb <time> switch is
> avialable that produces power estimates for every time interval
> specified in <time>. Does it just take into account the activity rate
> simply for that time interval or the activity rate so far i.e.
> starting from 0s?

Short answer : "so far"

Longer answer : Time based simulation file analysis can be performed any
time a VCD file is loaded.  It will be performed if the file is being
loaded from the command line and the -tb switch is used, or if it is
being loaded in the Gui and the "Do Time based Simulation" box is
selected.  This will read in the VCD file and for every time indication
it will record the number of transitions between this and the last and
calculate how much power has been generated for that time period.  It
records the highest value, and this will be displayed as "Peak Power" in
the Summary view (Summary Tab) and in the text and html report.  It
always writes out a text file recording the power for each time period.
This file can be read into Excel or other graph making utility to produce
a graph of power over time.

Brendan


Article: 68685
Subject: what is a better approach to synthezise synchronous reset on FPGA?
From: "valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com>
Date: Wed, 14 Apr 2004 14:23:21 +0300
Links: << >>  << T >>  << A >>
  if Rising_Edge(Clk) then
   if RESET = '1' then
    ERROR_CODE <= (others => '0');
   elsif ENABLE = '1' then
        ...
or

  if Rising_Edge(Clk) then
   if ENABLE = '1' then
        if RESET = '1' then
            ERROR_CODE <= (others => '0');
        else
            ...



Article: 68686
Subject: Price of a Virtex-2 6000 chip...
From: "Kelvin @ SG" <kelvin8157@hotmail.com>
Date: Wed, 14 Apr 2004 19:23:53 +0800
Links: << >>  << T >>  << A >>
Hi, there:

I was browsing through my emails and discovered a dude claiming a
xc2v6000 costs US$4000 and a xc2v8000 for US$6000...is that true?

Kelvin





Article: 68687
Subject: Rocket IO : How to put K Characters on LSB of Output Data
From: "Adarsh Kumar Jain" <Adarsh.Jain@cern.ch>
Date: Wed, 14 Apr 2004 14:53:56 +0200
Links: << >>  << T >>  << A >>
Hi All,
I am using the Rocket IOs in V2 Pros.
My problem is that when i play with the phase of the RefClk,
the K character is sometimes output on the MSB and Sometimes on the LSB,
(the former throws my whole systems off track, as all subsequent data is
misaligned on the byte boundary)
Can i force the K char to be output on the LSB of the 16 bit RXDATA path ?
How ?
Thanks
Adarsh



Article: 68688
Subject: Re: Price of a Virtex-2 6000 chip...
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Wed, 14 Apr 2004 13:16:23 +0000 (UTC)
Links: << >>  << T >>  << A >>
Kelvin @ SG <kelvin8157@hotmail.com> wrote:
: Hi, there:

: I was browsing through my emails and discovered a dude claiming a
: xc2v6000 costs US$4000 and a xc2v8000 for US$6000...is that true?

Go to e.g. www.nuhorizons.com and search for XC2V6000. 

XC2V6000-4FF1517C is listed there for $2.984.00.

What a bargain ;-)

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 68689
Subject: Re: Yet Another Altera Online Support Is USELESS Rant...
From: george.martin@att.net (George)
Date: 14 Apr 2004 06:56:41 -0700
Links: << >>  << T >>  << A >>
"Kenneth Land" <kland1@neuralog1.com1> wrote in message news:<107o7v6msti5u64@news.supernews.com>...
> What a waste of time and bandwidth.
> 
> I ask a simple question about SPI ports on Nios and I get an unrelated link
> to read as a response.
> 
> ARGHHHHH!!!!!!!!!!!!!!!!!!!!!!!!!
> 
> Ken

Post the question here!!!

Article: 68690
Subject: Re: Yet Another Altera Online Support Is USELESS Rant...
From: "Kenneth Land" <kland1@neuralog1.com1>
Date: Wed, 14 Apr 2004 11:04:18 -0500
Links: << >>  << T >>  << A >>

"George" <george.martin@att.net> wrote in message
news:e9d879fa.0404140556.4f340172@posting.google.com...
> "Kenneth Land" <kland1@neuralog1.com1> wrote in message
news:<107o7v6msti5u64@news.supernews.com>...
> > What a waste of time and bandwidth.
> >
> > I ask a simple question about SPI ports on Nios and I get an unrelated
link
> > to read as a response.
> >
> > ARGHHHHH!!!!!!!!!!!!!!!!!!!!!!!!!
> >
> > Ken
>
> Post the question here!!!

Original Question:

Can't get SPI port working in design.  Can you tell me if the SCLK should be
oscilating all the time?  It's not.

SDRAM, USB, UART, PIO, ASMI, TIMERs, DMAs all working in design but having
trouble getting SPI going.

Can you have someone contact me that may help?  Or at least answer my
question about the clk and offer some advice?

Thanks,
Ken Land
klandX@Xneuralog.comX
281-240-XXXX voice



Article: 68691
Subject: Re: Yet Another Altera Online Support Is USELESS Rant...
From: Derek Young <LL_mit_edu@dereky.nospam>
Date: Wed, 14 Apr 2004 12:13:31 -0400
Links: << >>  << T >>  << A >>

> Original Question:
> 
> Can't get SPI port working in design.  Can you tell me if the SCLK should be
> oscilating all the time?  It's not.

I got SPI working with NIOS.  sclk only oscillates when transferring 
data.  Make sure you're using the right phase setting for the chip 
you're trying to talk to (you'll need to check the data sheet).

Derek

P.S.  Yes, I'm not getting anything useful out of Altera web support either.


Article: 68692
Subject: Re: Apples to Apples? Stratix II <> Virtex-II Pro
From: paul.leventis@utoronto.ca (Paul Leventis at home)
Date: 14 Apr 2004 09:34:32 -0700
Links: << >>  << T >>  << A >>
Hi Austin,

> The questions I posed are legit, however.  As well as comparing 90nm to 
> 90nm ('Our latest announced yet to be shipped chip is better than your 2 
> year 130nm technology chip...')

To be fair, we do have comparisons posted of Cyclone vs. Spartan-3
(our 1.5 year old 130 nm chip vs. your recently released 90 nm one). 
Despite the process disadvantage and its age, Cyclone offers 70%
better performance.  See
http://www.altera.com/products/devices/performance/per-index.html for
details.

It's worth pointing out that 90 nm is not really buying a huge amount
of performance as compared to 130 nm -- nothing like the good old days
of process scaling.  The static power problem posed by <=90 um
processes leads to trade-offs in process technology and circuit design
that can eat into this traditional source for increased performance. 
For example, the use of high-Vt transistors and longer gate lengths
allows the circuit designer to trade-off leakage for performance. 
There are many other techniques that can be employed -- there is a
huge body of academic/industry literature published on the topic of
low-power design for those interested.

Much of the Stratix II performance advantage comes not from the
process shift but from the new logic architecture.

I'm sure when you guys finally come out with a 90nm FPGA to compete
with Stratix II, both companies will be publishing head-to-head
performance comparisons.

Regards,

Paul Leventis
Altera Corp.

Article: 68693
Subject: Re: VirtexII : XC2V2000 Design
From: "Steve Merritt" <steveb_merritt@NOSPAMhotmail.com>
Date: Wed, 14 Apr 2004 17:55:06 +0100
Links: << >>  << T >>  << A >>
Uwe -

The XCF32 _is_ available now.  Please feel free to contact Insight UK for a
quote.

Best Regards

-- 
Steve Merritt BEng (Hons) CEng MIEE
XILINX Gold Certified Field Applications Engineer
Insight MEMEC +44 (0) 1296 330061

Click link below for more information on :
XILINX Free Training
<http://www.xilinx.com/support/training/europe-home-page.htm>
XILINX Design Services
<http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Design+Service
s>
10 Gbps Serial IO on FPGA <http://www.xilinx.com/systemio/10gig/index.htm>

Or Tel - 08707 356532 for more information







"Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message
news:c5hkfc$vr0$1@news.tu-darmstadt.de...
> Steve Merritt <steveb_merritt@nospamhotmail.com> wrote:
> : Hi Saleem,
>
> : Firstly - unless there are reasons you haven't yet explained I would use
the
> : platform flash parts for configuration, not the XC18V04.  The XC2V2000
> : requires 7.5Mbits of config memory so you would be able to use a single
> : 8Mbit part with no problems at all.  The platform flash parts are
cheaper
> : and available in much larger sizes (see here:
> : http://www.xilinx.com/publications/matrix/prom_color.pdf)
>
> As with other (Xilinx) parts, availability _is_ a thing to consider...
>
> For example nuhorizons only shows the XCF01 in one single package
available...
> -- 
> Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de
>
> Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------



Article: 68694
Subject: Re: Apples to Apples? Stratix II <> Virtex-II Pro
From: Austin Lesea <austin@xilinx.com>
Date: Wed, 14 Apr 2004 10:05:50 -0700
Links: << >>  << T >>  << A >>
Paul,

Hi.

Yes, S3 is 90nm, but it addresses a completely different market than the 
Virtex line.  S3 was not intended to be 'faster', as the low cost high 
volume market doesn't care about fast -- they just want to use FPGAs 
instead of ASICs.

As for 90nm 'not buying a huge performance improvement', that remains to 
be seen when we announce V4 and publish its specifications.  Intel has 
made performance gains, so has TI.  It can be done.

We did not intend to get any improvement in performance at all in S3 
(over Virtex II at 150 nm) but just crash through the $$$ barrier for 
logic per dollar, which is totally different that what we are doing for V4.

So to compare our 90nm S3 product to your 130nm one, is also not 
relevant:  cost is the issue, not speed.  Cost wins in this market.

The one thing that I don't understand, is why do you not have SRL16s?

The architecture of having these SRL16s is such a huge advantage (for 
us), I am amazed you haven't provided a competitive answer to them. 
Now you have reached parity with the ALM (which is all that we see in 
our benchmarks), what happened to putting in SRLs?

Austin

Paul Leventis at home wrote:
> Hi Austin,
> 
> 
>>The questions I posed are legit, however.  As well as comparing 90nm to 
>>90nm ('Our latest announced yet to be shipped chip is better than your 2 
>>year 130nm technology chip...')
> 
> 
> To be fair, we do have comparisons posted of Cyclone vs. Spartan-3
> (our 1.5 year old 130 nm chip vs. your recently released 90 nm one). 
> Despite the process disadvantage and its age, Cyclone offers 70%
> better performance.  See
> http://www.altera.com/products/devices/performance/per-index.html for
> details.
> 
> It's worth pointing out that 90 nm is not really buying a huge amount
> of performance as compared to 130 nm -- nothing like the good old days
> of process scaling.  The static power problem posed by <=90 um
> processes leads to trade-offs in process technology and circuit design
> that can eat into this traditional source for increased performance. 
> For example, the use of high-Vt transistors and longer gate lengths
> allows the circuit designer to trade-off leakage for performance. 
> There are many other techniques that can be employed -- there is a
> huge body of academic/industry literature published on the topic of
> low-power design for those interested.
> 
> Much of the Stratix II performance advantage comes not from the
> process shift but from the new logic architecture.
> 
> I'm sure when you guys finally come out with a 90nm FPGA to compete
> with Stratix II, both companies will be publishing head-to-head
> performance comparisons.
> 
> Regards,
> 
> Paul Leventis
> Altera Corp.

Article: 68695
Subject: Re: what is a better approach to synthezise synchronous reset on FPGA?
From: "Steve Merritt" <steveb_merritt@NOSPAMhotmail.com>
Date: Wed, 14 Apr 2004 18:09:11 +0100
Links: << >>  << T >>  << A >>
Hi Valentin,

The first one is the better way to do it.  The second will only work if your
enable is high.

Let me open another can of worms by saying 'why do you want a reset at
all?'.  Resets in *most* cases simply use up logic and routing resources
unnecessarily as all the fpga elements are initialised on powerup.  You can
even control the initialisation states of individual registers if necessary.
In *most* cases resets are mainly there to make simulations look good by
removing unknown signal conditions.

You may even miss out on some very useful resources if you automatically
apply resets to all your code... for example if you are using a Xilinx
Virtex device and you infer a shift register (i.e. 16 bits) in your HDL, you
will not be using a single SRL (Shift Register LUT) element, you will be
using 16 registers.

Food for thought ;)

Regards,


-- 
Steve Merritt BEng (Hons) CEng MIEE
XILINX Gold Certified Field Applications Engineer
Insight MEMEC

Click link below for more information on :
XILINX Free Training
<http://www.xilinx.com/support/training/europe-home-page.htm>
XILINX Design Services
<http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Design+Service
s>
10 Gbps Serial IO on FPGA <http://www.xilinx.com/systemio/10gig/index.htm>

Or Tel - 08707 356532 for more information

"valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> wrote in
message news:c5j6rg$2bkqr$1@ID-212430.news.uni-berlin.de...
>   if Rising_Edge(Clk) then
>    if RESET = '1' then
>     ERROR_CODE <= (others => '0');
>    elsif ENABLE = '1' then
>         ...
> or
>
>   if Rising_Edge(Clk) then
>    if ENABLE = '1' then
>         if RESET = '1' then
>             ERROR_CODE <= (others => '0');
>         else
>             ...
>
>



Article: 68696
Subject: Re: VirtexII : XC2V2000 Design
From: "Steve Merritt" <steveb_merritt@NOSPAMhotmail.com>
Date: Wed, 14 Apr 2004 18:13:13 +0100
Links: << >>  << T >>  << A >>
Of course - I meant the XCF08 ;)

Cheers

-- 
Steve Merritt BEng (Hons) CEng MIEE
XILINX Gold Certified Field Applications Engineer
Insight MEMEC

Click link below for more information on :
XILINX Free Training
<http://www.xilinx.com/support/training/europe-home-page.htm>
XILINX Design Services
<http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Design+Service
s>
10 Gbps Serial IO on FPGA <http://www.xilinx.com/systemio/10gig/index.htm>

Or Tel - 08707 356532 for more information

"Steve Merritt" <steveb_merritt@NOSPAMhotmail.com> wrote in message
news:x1efc.119$QB3.35@newsfe5-gui.server.ntli.net...
> Uwe -
>
> The XCF32 _is_ available now.  Please feel free to contact Insight UK for
a
> quote.
>
> Best Regards
>
> -- 
> Steve Merritt BEng (Hons) CEng MIEE
> XILINX Gold Certified Field Applications Engineer
> Insight MEMEC +44 (0) 1296 330061
>
> Click link below for more information on :
> XILINX Free Training
> <http://www.xilinx.com/support/training/europe-home-page.htm>
> XILINX Design Services
>
<http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Design+Service
> s>
> 10 Gbps Serial IO on FPGA <http://www.xilinx.com/systemio/10gig/index.htm>
>
> Or Tel - 08707 356532 for more information
>
>
>
>
>
>
>
> "Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message
> news:c5hkfc$vr0$1@news.tu-darmstadt.de...
> > Steve Merritt <steveb_merritt@nospamhotmail.com> wrote:
> > : Hi Saleem,
> >
> > : Firstly - unless there are reasons you haven't yet explained I would
use
> the
> > : platform flash parts for configuration, not the XC18V04.  The XC2V2000
> > : requires 7.5Mbits of config memory so you would be able to use a
single
> > : 8Mbit part with no problems at all.  The platform flash parts are
> cheaper
> > : and available in much larger sizes (see here:
> > : http://www.xilinx.com/publications/matrix/prom_color.pdf)
> >
> > As with other (Xilinx) parts, availability _is_ a thing to consider...
> >
> > For example nuhorizons only shows the XCF01 in one single package
> available...
> > -- 
> > Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de
> >
> > Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
> > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
>
>



Article: 68697
Subject: Re: Yet Another Altera Online Support Is USELESS Rant...
From: "Kenneth Land" <kland1@neuralog1.com1>
Date: Wed, 14 Apr 2004 13:36:22 -0500
Links: << >>  << T >>  << A >>

"Derek Young" <LL_mit_edu@dereky.nospam> wrote in message
news:Lqdfc.153$9m.28@llnews.ll.mit.edu...
>
> > Original Question:
> >
> > Can't get SPI port working in design.  Can you tell me if the SCLK
should be
> > oscilating all the time?  It's not.
>
> I got SPI working with NIOS.  sclk only oscillates when transferring
> data.  Make sure you're using the right phase setting for the chip
> you're trying to talk to (you'll need to check the data sheet).
>
> Derek
>
> P.S.  Yes, I'm not getting anything useful out of Altera web support
either.
>

Thanks Derek,

After everything else went pretty easy, I was surprised not to see my SCLK
even when writing to the device.
Double checked my pin assignments, double checked my board wiring.  Any
ideas?

Some background:
Nios 32 version 3.1 running at 100MHz in Cyclone
SPI is setup as Master with one SS_n talking to a ST 8Mb serial flash.
(M25P80. Similar chip to the 4 Mb ASMI config)

I've tried different clock speeds, (128 Khz - 15 MHz) with and without
delay, but still no meaningful output on the SCLK.  I see activity but
nothing resembling a clock.  Also tried clocking back the Nios to 60 MHz.

Is there any possible input or actions the P80 could take to cause the the
SPI clock not to function?

What would/should be the effect of operating a SPI port on unused pins?
Should it function or do I have to do something meaningful will the MISO
input?

TIA,
Ken





Article: 68698
Subject: Re: Yet Another Altera Online Support Is USELESS Rant...
From: hmurray@suespammers.org (Hal Murray)
Date: Wed, 14 Apr 2004 19:20:45 -0000
Links: << >>  << T >>  << A >>
>I've tried different clock speeds, (128 Khz - 15 MHz) with and without
>delay, but still no meaningful output on the SCLK.  I see activity but
>nothing resembling a clock.  Also tried clocking back the Nios to 60 MHz.

I could (easily) be wrong here, but I think SPI is one of several
data transfer protocols that don't use many pins.  They are great
for low bandwidth setup sort of work.  For example, talking to
a tiny flash chip to store parametersm ir the control path on
something like a CODEC to setup various parameters.

The "clock" does not normally run continiously.  This type of
interface is often run by big-banging from software using GPIO
pins.  The general idea is that you setup the data, wait a while,
and then change the clock from 0 to 1.  The chip you are talking
to doesn't need a clock for internal operations.  It just grabs
a data bit on the rising edge of the clock.  As long as there
is plenty of setup/hold time you shouldn't have any troubles.

You can easily add hardware to do the low level part of sending
a byte and such.

Do you have good pullups?  That type of system is usually open
collector/drain.  (so you can hang several chips on the "bus".
part of the protocol is an address)

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 68699
Subject: Re: Cyclone and ByteBlasterMV?
From: "Nial Stewart" <nial@nialstewartdevelopments.co.uk>
Date: Wed, 14 Apr 2004 20:23:48 +0100
Links: << >>  << T >>  << A >>
> > That schematic looks nothing like the insides of the
> > ByteBlaster II cable I had (I've just shipped it off
> > to a client and am awaiting a new one).
>
> What chip(s) did it use? If I know the logic family, I can probably work
the
> rest of it out for myself.
> Leon

Leon,

From memory it was a sea of transistors on both sides with an 8 pin
SOIC on one side.


Nial.






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