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(2nd version of the message... more correct English this time) Hello, I would like to request some help for some students that work on an Altera Stratix EP1S25 development board http://www.altera.com/products/devkits/altera/kit-dsp_stratix.html They try to deal with the Digital Analog Conversion , so they wrote programs on VHDL where they declare a bit vector with a certain value, and send it to the Digital Analog Converter to see the values on the output. But... no matter the value they use, they always have zero volt on the outputs However, I think they were very careful with the pins numbers assignements of the components on the board. And it seems they have the same kind of problem with the ADC (receiving a simple voltage, and transfer it directly to the outputs via the Stratix). Can someone please help them (and me, by the way ?). I'm just searching for some VHDL code to test the DAC and ADC conversions. Many thanks, Regards, A. AbellardArticle: 68476
Hi! I am using a Virtex2PV20, and one PPC core is used in my design. I drag a PPC Jtag controller core into the design in order to debug my SW code. however, I failed to program the device with the generated bitstream. iMPACT reports the DONE pin doesn't go high. In Bitgen, Jtag clock has been explicitly specified. I think the main reason of programming failure is that some wrong options were selected in Bitgen phase due to the fact that I am not familiar with how JTAG works. could someone guide me how to work out the problem? thank you! BRs. --yangArticle: 68477
Michael S wrote:
> "Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in message ne=
ws:<406c0218$0$31716$fa0fcedb@lovejoy.zen.co.uk>...
>=20
>>>1. result port is connected to internal bus in your design.
>>
>>But he has said only the pin out is tri-stated.
>>
>=20
>=20
> In the original post he said:
>=20
> "
> hi data bus driver : lpm bustri GENERIC MAP (LPM WIDTH =3D> 30)
> PORT MAP (
> <snip>
> result =3D> dnio_inbus,
> <snip>
> dnio and dnio_inbus are internal data buses.
> "
IMO the word =A8bus=A8 does not mean necesserily a tri-stated _multisourc=
e_=20
data path. In my case these =A8internal data buses=A8 are NOT tri-stated =
and=20
they have one single source, is the case of dnio_inbus this is the=20
lpm_tribuf.
>>I presume the structure is something like
>>
>>
>>pin <=3D int_dnio if (n0_dir =3D '?') else 'Z'
>>dnio_inbus <=3D pin;
This is not correct. The structure is exactly that as covered in my=20
posting. I do not use 'Z' value anywhere. I only connect signals to lpm=20
ports.
>=20
>=20
> I guess he tried to do something like (sorry for my syntax, i'm not a
> native VHDL speaker):
>=20
> if (n0_dir =3D '1')=20
> {
> // enabletr =3D '1'
> dnio_inbus <=3D dnio_rec;
> // enabledt =3D '0'
> dnio_rec <=3D 'Z';
> }
> else
> {
> // enabletr =3D '0'
> dnio_inbus <=3D 'Z'; // the assignment is illegal in Altera FPGAs!!!!=
!
> // enabledt =3D '1'
> dnio_rec <=3D data;
> }
As I mentioned above, this is not the case. No 'Z' assignment.
> Altera (and I) had in mind AHDL. AHDL syntax lacks tri-state literal
> ('Z') so in order to implement tristate pin you have to use either
> TRI primitive or lpm_bustri() function. Of coarse for VHDL your syntax
> is better.
As I understand the VHDL lpm_tribuf will be translated to TRI primitive. =
It also happens in many of my designs. But sometimes - and this was the=20
original question - Quartus replaces the TRI buffer by an OR gate and I=20
do not know why. There is no visible reason. When I connect the input=20
and control input of such a buffer to testpoints, they change their=20
state correctly.
Thanks,
Janos Ero
CERN Div. EP
Article: 68478Dear All: I have tried the reset circuit for external feedback DCM on XAPP462 Figure 20. Is it ok to use feedback clock input as the shift register to generate DCM reset? Modelsim's wave tell me that DCM will not output clock when it is at reset. A miss for XAPP462 Figure 20? Or I made the misunderstanding. http://www.xilinx.com/bvdocs/appnotes/xapp462.pdf regards, seyiorArticle: 68479
HI, "-lable" may help you. ---e.g.-- add wave -noupdate -label CLK -radix hexadecimal TB_SDT_TOP/UUT/CLK Regards, seyiorArticle: 68480
"Hendra Gunawan" <u1000393@email.sjsu.edu> wrote in message news:<c4qr0p$6j7q9$1@hades.csu.net>... > Hi folks, > I want to learn Hardware Verification Language (HVL). Which HVL is the most > popular for FPGA design? > I have seen "e" and "Open Vera" from Samir Palnitkar and Janick Bergeron > books. Are there other Hardware Verification Languages? > Say I designed something in FPGA with Verilog or VHDL. How do I know that it > is time to verify my design with HVL as opposed to Verilog/VHDL testbenches? > > Hendra http://www.jeda.org/ Cheers, JonBArticle: 68481
> When will we use C for circuit design? ;-) Why the hell would you want to? Its not even that good a language for writing software in. Cheers, JonBArticle: 68482
Hello all, in the Spartan-II documentation, one can find that the xc2s100 has 10 on-chip BRAMs. At the other hand, the ISE software reports only 5 of them! Is there some kind of catch I haven't cought? Is it possible that one neeeds to install the ISE Service Pack to override this kind of problems? Thanks in advance! MarijaArticle: 68483
Hi, Yes, you must check in Generate Programming File properties about JTAG, and put the PORT switch of the Nu board in the JTAG position. Anyway, have you seen if the design has gone correctly to the FPGA? I have the same problem with the same message, but the bit sequence transfer works for me. Luck, Santiago.Article: 68484
Hello, I am currently using the command line version of XPower to estimate power consumption on my designs. A -tb <time> switch is avialable that produces power estimates for every time interval specified in <time>. Does it just take into account the activity rate simply for that time interval or the activity rate so far i.e. starting from 0s?Article: 68485
WIth virtexII, you can use the cascade OR's which run horizontally.
Hal Murray wrote:
> TBUFs are (were?) nice for the job where you had a batch of registers
> and a microcoded machine to read them onto a shared bus and load
> them from the bus.
>
> Is there some obvious pattern to build a mux-equivalent that works
> well for reading one of 5 or 10 registers?
>
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 68486Hi All, I am currently using XPower 5.2.03i with Modelsim 5.7d. To ensure that the actual low-level design is condidered, I used the post place and route Simulation model (i.e. vhd file generated in Project Navigator) to generate a vcd file in modelsim. The power estimate that results is far larger than that power measurements made on hardware for the same set of inputs. Could it be due to the fact that the model instead of the original high-level vhdl files are used in the simulation in Modelsim. If so, what is the remedy that would consider all the low-level aspects of the design aside from adding the *.sdf file during modelsim simulation as well as taking into account all nets. Thanks a mil! EdArticle: 68487
I want to be able to use the fastest possible paths within a SpartanII FPGA to create internal signals which are simple copies of each other linked in a chain. Delay between each should be in the order of a few tens to hundreds of picoseconds. All of the created signals should however be usable by other internal logic (in fact on D inputs of a chain of flip-flops clocked all the same) My first idea was to define a chain of BUF "components", and see what happens. As feared, the (Foundation) development tool just merged all the signals (No BUF generated). Forcing a KEEP attribute on all the signals just did not help. I tried with LUT1's. This works but is much too slow for the application. Looking at the FPGA Editor gave me the idea of using the MUXCY, MUXCY_L or MUXCY_D components of the SpartanII library. Some sort of a miracle happened then: the dedicated carry chain was selected, running thru the expected number of CLB's, and speed was excellent. But to my great surprise, only one flip-flop out of two hooked onto the outputs of the MUXCY components was selected as being part of the same cell. The second FF was placed in a totally different CLB. This is not exactly what I expected, since the application requires a very close matching of delays. Any idea why this happens ? Possible corrections ? Thank you beforehand.Article: 68488
There may be other controls in your registers that make packing both registers in one slice illegal. There can only be one clock enable or set/reset for both registers in a slice. You can extend your chain to twice the length and use one register per slice and everything should flow. "A Beaujean" <abeaujean@gillam-fei.be> wrote in message news:8211d046.0404060730.5e01e294@posting.google.com... > I want to be able to use the fastest possible paths within a SpartanII > FPGA to create internal signals which are simple copies of each other > linked in a chain. Delay between each should be in the order of a few > tens to hundreds of picoseconds. > All of the created signals should however be usable by other internal > logic (in fact on D inputs of a chain of flip-flops clocked all the > same) > My first idea was to define a chain of BUF "components", and see what > happens. > As feared, the (Foundation) development tool just merged all the > signals (No BUF generated). > Forcing a KEEP attribute on all the signals just did not help. > I tried with LUT1's. This works but is much too slow for the > application. > Looking at the FPGA Editor gave me the idea of using the MUXCY, > MUXCY_L or MUXCY_D components of the SpartanII library. Some sort of a > miracle happened then: the dedicated carry chain was selected, running > thru the expected number of CLB's, and speed was excellent. But to my > great surprise, only one flip-flop out of two hooked onto the outputs > of the MUXCY components was selected as being part of the same cell. > The second FF was placed in a totally different CLB. This is not > exactly what I expected, since the application requires a very close > matching of delays. > Any idea why this happens ? Possible corrections ? Thank you > beforehand.Article: 68489
Matt, The least expensive way to get Xilinx ISE tools is to get the ISE Eval: http://www.xilinx.com/xlnx/xebiz/productview_ise.jsp?category=-21393 It's free, provides a 60 day evaluation, and supports all the VirtexII Pro devices. If you want to use the Power PC, you should get the EDK for $495. Steve myren wrote: > what is the minimum software required to take advantage of a virtex II > pro (in terms of cost)? > > just a poor college student trying to learn fpga's. Virtex II pro is > obviously a bit excessive, but my main reason for learning fpga's is > to begin to do high bandwidth data shuffling. the rocketio seems well > suited to that, and i'm hoping with EDK i might actually be able to > implement gigabit ethernet within my lifetime. > > > i found a dev kit with EDK for $500. EDK has ISE demo, but i'm not > sure how much that will cover me for, ie: if its usable & relatively > fully featured. it says the free web pack is not good for any but > the simplest of virtex II pro's, presuambly in powerpc core support > (which baseline vII pro lacks) > > this is just for learning, i dont need a license to produce or > distribute anything, although it would be nice (not required) if i > could eventually like to release some of my work for free online. > > kit is memec design one featuring xc2vp4: > http://www.insight-electronics.com/cgi-bin/bvutf8memec/scripts/local/manuDetailArticle.jsp?catPath=/INSIGHT/AMERICAS/UNITED_STATES/MANUFACTURERS/MD_XILINX/EVALUATION_KITS/Virtex%20Series%20Kits&Manu=10089&isDetailPage=true&EDOID=209000&Div=INSIGHT&Reg=AMERICAS&Country=UNITED_STATES&Lang=EN&PnACountry=UNITED_STATES > > > > thanks > matt fowleArticle: 68490
Hi, I am simulating a Xilinx Design which uses all of the 8 Rocket IOs present in the V2P7. All the Rocket IOs are identical except for their Differential Data Inputs. I use the Transceivers as Receivers only and am using the Gigabit Ethernet mode with 2 byte path. The problem is that out of the 8 channels I have, 5 of them see the idle (D16.2/K28.5) correctly and accordingly align the data at the right boundary. The other three channels don't seem to work. The output from them is XXXX. Also another thing i noticed is that if i introduce a slight delay into the refclk input, the behaviour of the 5 previously Ok channels also changes. Instead of seeing a 50BC(D16.2/K28.5), they seem to lock on K28.5/D16.2(BC50) and thus the data gets misaligned (a 1 byte shift in the data out from the Transceivers). I am implementing the clock scheme as suggested in the Rocket IO transceiver user guide for the two byte path. Could this be a timing issue with the RefClk ? What about the XXXXs ? I will greatly appreciate any suggestions with regards to this. Anyone who has successfully simulated and used these Transceivers, could be of great help. PLEASE HELP ! Thanks a lot, AdarshArticle: 68491
Antti Lukats <antti@case2000.com> wrote: Hi Antti! > >> Your USB clock needs a 48MHz clock speed. I have a Nios Development Board >> with a 50MHz oscillator. I'm using a PLL to drop the speed to 48.076923MHz >> (ratio of 25/26). Is that OK or does it have to be ditto 48MHz cuz that's >> the best that I can get. > > it will receive 100% ok also with 50MHz clock > I once tested accidently, not sure if the hosts will accept 50MHz transmit > 48.08 will defenetly work both ways, not matter if it is withing spec range > or not At work we have also worked on USB devices which are connected to a PC. In this case the tolerance of ceramic resonator can be too much. I am not sure about the exact figures, if I am not wrong the spec is about +/-100ppm or slightly more. In some application notes you can find also statements like "should not work with ceramic resonators but no problems in practice". So using a 50MHz clock does not sound too much promising for me. Best regards, Christoph >Article: 68492
Hendra, Both VHDL (vhdl-200x) and Verilog (SystemVerilog) are being extended to include HVL constructs. For education, either e or Vera would be ok, but perhaps long term we can be back at one language for all of the design (be it your choice of VHDL or Verilog). Cheers, Jim Hendra Gunawan wrote: > Hi folks, > I want to learn Hardware Verification Language (HVL). Which HVL is the most > popular for FPGA design? > I have seen "e" and "Open Vera" from Samir Palnitkar and Janick Bergeron > books. Are there other Hardware Verification Languages? > Say I designed something in FPGA with Verilog or VHDL. How do I know that it > is time to verify my design with HVL as opposed to Verilog/VHDL testbenches? > > Hendra -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Article: 68493
The OP provided me with a test case and the problem turns out to be that the INIT values on the LUTs were not being passed to the implementation tools correctly. The values were being passed as "00" and the LUTs were being optimized to GND. This is known problem with XST generating VHDL from XCS schematics. It's fixed already for 6.2i SP2. Meanwhile a work around is to specify a Verilog flow. In ISE Project Properties, set "Generated Simulation Language" to Verilog. See Answer 18350 for details of the issue: http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=18350 Bret BrakePiston wrote: > Thank you all for your replies. > > I have tried debugging mi design using simple AND and OR gates, and > what I found is that all my LUTs are being optimized!! > > So I did a simple design, one 2 4-input LUTs, one and gate, 8 inputs > and 1 output.The LUTs are initialized with different numbers. All gets > optimized away. Obviously, it works if I only have other components, > such as gates. > > Anyone has any idea what's going on? > Thanks > > > > > On Thu, 01 Apr 2004 10:53:05 -0700, Bret Wade <bret.wade@xilinx.com> > wrote: > > >>PO Laprise wrote: >> >>>John Retta wrote: >>> >>> >>>>This typically happens when output signals from a logic block are not >>>>connected (though a typo or some other unintended reason) ... as >>>>MAP works backwards it trims away. >>>> >>>>To find the offending path, either use a simulator (highly recommended), >>>>or add some "debug only signals" .... which are the OR of all output >>>>signals from a suspected block .... whose output is brought to a top >>>>level I/O. If this small logic addition suddenly adds large amounts >>>>of previously trimmed logic, then you know that the downstream signals >>>>are being optimized away. >>>> >>>>Good luck. >>>> >>> >>>It can also happen if a) the clock signal to your output flip-flops is >>>unconnected somehow or (more common) b) the enable signal to these >>>flip-flops is stuck low for some reason. >>> >> >>This is true and the trim report in the .mrp file can sometimes be >>misleading about where the trimming originated. I use the following >>iterative process to debug unexpected trimming behavior: >> >>1. Pick an instance (usually a FF) from the logical design that is being >>trimmed unexpectedly and apply an "S" property to all input/output nets. >> >>2. Rerun map and examine the resulting NCD in FPGA Editor. Note which >>inputs/ouputs are undriven/unloaded or optimized to constants and what >>affect this would have on the trimmed logic. This should identify the >>direction that the trimming is coming from. For example, the CE input >>may be GND. >> >>3. Once the direction of the trimming has been identified. apply more >>"S" properties on the logic in that direction and repeat step 2. >>Continue until the source of the trimming has been identified. >> >>Other tips: >> >>If you suspect that a FF is never going high, try applying an INIT=1 >>property to it as a test. Does the trimming behavior change? >> >>If you reach a point where the "S" properties don't successfully block >>some trimming, this is a sign that the logic is being removed due to >>optimization. Usually one or more of the inputs has been optimized to a >>constant. >> >>Bret Wade >>Xilinx Product Applications > >Article: 68494
erojr wrote: > hi data bus driver : lpm bustri > GENERIC MAP (LPM WIDTH => 30 > ) > PORT MAP (data => int dnio, > enableDT => NOT n0 dir, > enableTR => n0 dir, > result => dnio inbus, <<*** this is the problem > tridata => dnio rec > ); > > dnio rec is the FPGA pin, int dnio and dnio inbus are internal data buses Michael S (and earlier Martin Schoeberl) had written > 1. result port is connected to internal bus in your design. > 2. Internal nodes (buses) can't be tristated in Altera FPGAs (AFAIK, > that's true for newer Xilinx FPGAs as well). Internal nodes are '0' or > '1' - no 'Z'. erojr wrote: > I do not use 'Z' value anywhere. > I only connect signals to lpm ports. Well I think I understand what you're both saying, so let me make a total fool of myself and put my two cents in... You may not be directly assigning Z to any signal, but that's what you're asking for inside lpm_bustri. ------------------------------------------------------- A. Quartus II Help says: - - - - - - - - - - - - - - - - - - - - - - - - - - - - WOPT_MLS_SIGNALS_FEEDING_IN_LOGIC_WILL_NOT_BE_TRISTATED CAUSE: You connected the specified logic gate to a tri-state signal (Z logic value), but you cannot create internal tri-state buffers. Therefore, if the signal feeding into the node is Z, it will become a "1" instead. ACTION: No action is required. ------------------------------------------------------- B. Quartus II Help on LPM_BUSTRI - - - - - - - - - - - - - - - - - - - - - - - - - - - - <...> The following three configurations are valid: <...> 3. All ports are present: input ports data[LPM_WIDTH-1..0], enabledt, and enabletr; output ports result[LPM_WIDTH-1..0]; and bidirectional ports tridata[LPM_WIDTH-1..0]. This configuration has the following function: Input Bidirectional Output enabledt enabletr tridata[LPM_WIDTH-1..0] result[LPM_WIDTH-1..0] 0 0 Z (input) Z 0 1 Z (input) tridata[LPM_WIDTH-1..0] 1 0 data[LPM_WIDTH-1..0] Z 1 1 data[LPM_WIDTH-1..0] data[LPM_WIDTH-1..0] <...> ------------------------------------------------------- This is the configuration that corresponds to your connections. But "result" is an internal bus, and it is not allowed to be assigned a value "Z". So Z => 1, and (I imagine) you're getting something like: signal dtvector : std_logic_vector(result'length-1 downto 0); dtvector <= (others => enabledt); -- vector of enabledt repeated result <= tridata OR dtvector; Incidentally it appears to me that you could fix your problem by setting enabletr<='1' and using only enabledt, ie > hi data bus driver : lpm bustri > GENERIC MAP (LPM WIDTH => 30 > ) > PORT MAP (data => int dnio, > enableDT => NOT n0 dir, > enableTR => '1', > result => dnio inbus, <<*** this is the problem > tridata => dnio rec > ); It sure gets frustrating at times. Hope this helps, -rajeev-Article: 68495
Jim Lewis <Jim@SynthWorks.com> wrote in message news:<407172DA.4060907@SynthWorks.com>... > Rajeev, > Make sure to turn on the VHDL-93 switch. > > You can do this in the compile options menu item under > compile in 5.7. > > Cheers, > Jim Jim, Thanks much ! That did it. -rajeev- <...>Article: 68496
Dwayne Surdu-Miller <miller@SEDsystems.nospam.ca> wrote in message news:<106rehso9socie1@corp.supernews.com>... > Hi Subhek, > > Here's a link to some fairly modest Virtex II / PCI development boards > > http://www.dinigroup.com/ > > Best regards, > Dwayne Surdu-Miller Hi Thanks for the reply. Does any of the design contain ethernet connector? SubhekArticle: 68497
There are a couple things that can cause that. First, the clock enable
and resets at the register have to be common to both registers in a slice,
if not the placer won't allow both to go in the same slice. If that is
not the case (check the edif netlist to make sure CE's were not duplicated
and therefore different signal names), then it is possible the mapper
aligned the carry chain and the flip-flops differently. This can happen
if the first muxcy has something coming in the ci that causes it to stick
another muxcy at the bottom of the chain. It can also happen if the lsb
of either the carry chain or the flip-flops gets optimized out causing one
or the other to get mis-aligned. You can fix that by instantiating
primitives and putting placement constraints (RLOCs) on them.
A Beaujean wrote:
> I want to be able to use the fastest possible paths within a SpartanII
> FPGA to create internal signals which are simple copies of each other
> linked in a chain. Delay between each should be in the order of a few
> tens to hundreds of picoseconds.
> All of the created signals should however be usable by other internal
> logic (in fact on D inputs of a chain of flip-flops clocked all the
> same)
> My first idea was to define a chain of BUF "components", and see what
> happens.
> As feared, the (Foundation) development tool just merged all the
> signals (No BUF generated).
> Forcing a KEEP attribute on all the signals just did not help.
> I tried with LUT1's. This works but is much too slow for the
> application.
> Looking at the FPGA Editor gave me the idea of using the MUXCY,
> MUXCY_L or MUXCY_D components of the SpartanII library. Some sort of a
> miracle happened then: the dedicated carry chain was selected, running
> thru the expected number of CLB's, and speed was excellent. But to my
> great surprise, only one flip-flop out of two hooked onto the outputs
> of the MUXCY components was selected as being part of the same cell.
> The second FF was placed in a totally different CLB. This is not
> exactly what I expected, since the application requires a very close
> matching of delays.
> Any idea why this happens ? Possible corrections ? Thank you
> beforehand.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 68498Hi everybody, I'm a student and for a project at school we have to make a VGA controller. Does anyone have a good customizable example or does anyone know where to download one? What do I have to do if I want to make one of my own. The input datawidth = 16 bit & the target device is a Xilinx Spartan IIE FPGA. Thanks in advance, Sander OdekerkenArticle: 68499
Hey all, A quick note on getting EDK 6.2 to work on (a modern distribution) Linux. Since I am using a "non-xilinx-supported Linux distribution," Xilinx hotline would not help me in this matter. However, I believe this problem _may_ apply to those running the supported distributions. After getting the EDK running (see tips below) when I attempted to compile a design using a licensed core (i2c, 16550 uart, ethernet) the EDK 6.2 reported that it could not find a license for those files. I saw a few comments on EDK 6.1 solaris installs about using xlicmgr to determine which licenses are installed. The utility reported no licenses found, though they were there. The solution: 1) in addition to the environment variables in setup.csh, another variable MUST be added to detect the licenses. Mine looks as follows: export XIL_CG_LICENSE_DIR=/usr/local/EDK/data/core_licenses 2) for some very odd reason, EDK 6.2 linux does not look for licenses such as "opb_uart16550_v1_00_c.lic", but looks for "pb_uart16550_v1_00_c.lic" This was first noticed when the edk could not find these "pb...lic" files. The solution was to copy the offending opb licenses to "pb" licenses. Hope this helps others. I'm gratefulthat the EDK works under Linux. Note: to get Xilinx ISE/EDK setup in Linux under "non-supported Linux distributions" these tips may be of assistance: Run Xilinx6.2/settings.sh and EDK6.2/setup.csh or add the environment exports to your ~/.bashrc. add: export LD_ASSUME_KERNEL=2.4.1 (necessary for Wind/U) if using GDM as your xfree86 login manager, edit gdm.conf (i.e. /etc/gdm/gdm.conf) and in the "command=" remove "-nolisten tcp". This may pose a security risk to some, but it lets Wind/U operate locally. Tony
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