Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
I work for a company who recently released a new Spartan 2E 300 board and we would like to list it in the www.fpga-faq.com/FPGA_Boards.shtml site. Does anybody know how to do this ? Thanks JoseArticle: 68326
This typically happens when output signals from a logic block are not connected (though a typo or some other unintended reason) ... as MAP works backwards it trims away. To find the offending path, either use a simulator (highly recommended), or add some "debug only signals" .... which are the OR of all output signals from a suspected block .... whose output is brought to a top level I/O. If this small logic addition suddenly adds large amounts of previously trimmed logic, then you know that the downstream signals are being optimized away. Good luck. -- Regards, John Retta Owner and Designer Retta Technical Consulting Inc. email : jretta@rtc-inc.com web : www.rtc-inc.com "BrakePiston" <brakepiston@REMOVEyahoo.co.uk> wrote in message news:lnsl60dsrdvqv78qhoubp9r4s2unqifnm2@4ax.com... > Hi guys, > > I am having a strange problem. > > I have my schematic file, made up of lots of nice LUTs, gates, etc. My > inputs are represented by an I/O marker followed by either an IBUF, > OBUF, or BUFG for input, output and clock signals. > > The synthetiser works perfectly. > > The translator works perfectly. > > The mapper gets rid of all my logic. > > Here is the relevant section on the report: > > Section 5 - Removed Logic > ------------------------- > > The trimmed logic reported below is either: > 1. part of a cycle > 2. part of disabled logic > 3. a side-effect of other trimmed logic > > The signal "XLXN_421" is unused and has been removed. > Unused block "XLXN_421" (PAD) removed. > The signal "XLXN_422" is unused and has been removed. > Unused block "XLXN_422" (PAD) removed. > The signal "XLXN_423" is unused and has been removed. > Unused block "XLXN_423" (PAD) removed. > The signal "XLXN_424_IBUFG" is unused and has been removed. > Unused block "XLXN_424_IBUFG" (CKBUF) removed. > The signal "XLXN_424" is unused and has been removed. > Unused block "XLXN_424" (PAD) removed. > The signal "XLXN_427" is unused and has been removed. > Unused block "XLXN_427" (PAD) removed. > The signal "XLXN_402" is unused and has been removed. > Unused block "B2_2_FF" (FF) removed. > The signal "XLXN_408" is unused and has been removed. > Unused block "B2_1_FF" (FF) removed. > The signal "XLXN_416" is unused and has been removed. > Unused block "XLXI_53" (BUF) removed. > The signal "XLXN_419" is unused and has been removed. > Unused block "XLXI_61" (CKBUF) removed. > The signal "XLXN_353" is unused and has been removed. > Unused block "XLXI_60" (BUF) removed. > The signal "XLXN_361" is unused and has been removed. > Unused block "XLXI_55" (BUF) removed. > The signal "XLXN_357" is unused and has been removed. > Unused block "XLXI_54" (BUF) removed. > The signal "XLXN_371" is unused and has been removed. > Unused block "B1_1_FF" (FF) removed. > The signal "XLXN_377" is unused and has been removed. > Unused block "B1_2_FF" (FF) removed. > > I know I should have named my instances!! :-P > > Anyway, it all starts with my input pads being removed because they > are unused. Anyone got any idea what am I doing wrong? > > Thanks!! > >Article: 68327
Try the IEEE site .... it is a terrific site both for employers and employees. -- Regards, John Retta Owner and Designer Retta Technical Consulting Inc. email : jretta@rtc-inc.com web : www.rtc-inc.com "Kelly" <kellydingee@adelphia.net> wrote in message news:62b176ec.0404010330.4b48899d@posting.google.com... > Thanks - we use those - but I was hoping for a niche or even > association type site that had career listings.... > > KellyArticle: 68328
John, My favorite is when you forget to have an output pin to your logic, and it just optimizes everything away. Austin John Retta wrote: > This typically happens when output signals from a logic block are not > connected (though a typo or some other unintended reason) ... as > MAP works backwards it trims away. > > To find the offending path, either use a simulator (highly recommended), > or add some "debug only signals" .... which are the OR of all output > signals from a suspected block .... whose output is brought to a top > level I/O. If this small logic addition suddenly adds large amounts > of previously trimmed logic, then you know that the downstream signals > are being optimized away. > > Good luck. >Article: 68329
kellydingee@adelphia.net (Kelly) wrote in message news:<62b176ec.0404010330.4b48899d@posting.google.com>... > Thanks - we use those - but I was hoping for a niche or even > association type site that had career listings.... > > Kelly In Western suburbs of Boston I495 there is 495.org http://www.495nsgmembers.org/default.asp Since this area has lots of defence jobs ie raytheon etc there may well be some available secret clearances out of the 1000s or so members looking for work beside the networking guys. You could look for similar groups around the country regardsArticle: 68330
George wrote: > I am sorry I cannot help you with the Xapp134 SDRAM controller, but > you might consider checking the new version of the SDRAM controller > from XESS ( you can get it free from www.xess.com ). I haven't tried > it myself, but it seems like a really neet and fast controller. It is > also reasonably well documented, although not as good as the Xapp134 > may I add. > > Best of luck with your project, > George Mercury There is also a decent open source DDR SDRAM controller on opencores.org. Be warned, although it could be that I was misusing it, I've had to modify the code slightly to get it to work bug free (there were issues with the refresh cycle canceling commands that had been "accepted"). I could make my changes available on demand, but I haven't had time to fully verify and document, so standard disclaimers apply... One comment about this code: it sometimes seemed to do some weird things when I (inadvertently) sent it NOP commands. Also, the read/writes are currently limited to bursts of 2, along with other slight limitations (the author works for a company that sells the full core). -- Pierre-Olivier -- to email me directly, remove all _N0SP4M_ from my address --Article: 68331
John Retta wrote: > This typically happens when output signals from a logic block are not > connected (though a typo or some other unintended reason) ... as > MAP works backwards it trims away. > > To find the offending path, either use a simulator (highly recommended), > or add some "debug only signals" .... which are the OR of all output > signals from a suspected block .... whose output is brought to a top > level I/O. If this small logic addition suddenly adds large amounts > of previously trimmed logic, then you know that the downstream signals > are being optimized away. > > Good luck. > It can also happen if a) the clock signal to your output flip-flops is unconnected somehow or (more common) b) the enable signal to these flip-flops is stuck low for some reason. -- Pierre-Olivier -- to email me directly, remove all _N0SP4M_ from my address --Article: 68332
"sandy" <sand26y@hotmail.com> wrote in message news:15d80e08.0403312105.3e4b28b4@posting.google.com... > Hi all, > i have a verilog design in which some of the modules are similar to > the one given below. it has to shift right the input by 4 for first 10 > clock cycles and shift right by 5 from the next clock cycle. it works > fine in the simulator. > > but when i actually tested it in hardware(fpga), tmp register does not > increase at the rising clock cycle. it keeps increasing, so the output > is always shown right shifted by 5. > how do i make it work. do i have to send the tmp out and read it in > the next clock cycle. is there any other way to do it, because there > are many counters used in the design. [ unindented code snipped ] It looks like your code will shift by 4 for the first 10 cycles after the reset then shift by 5 for the following 4294967286 cycles before shifting by 4 again. Is this what you want? If you're looking for the behavior as a startup condition, did you apply the reset? Your statement is unclear because it contradicts itself - please explain what you mean by "...tmp register does not increase at the rising clock cycle. it keeps increasing..."Article: 68333
ram wrote: > Hi Group, > I need help on using the XilNet libraray and Xilinx EMAC core. > ( www.xilinx.com) > I am a newbie to TCP/IP stack , so I need some pointers on where to > get started. > I have seen Xilinx App notes , but the C files are too confusing for > me, and it has plethora of socket functions,. > Can anybody please point me how to get started and going. > I appreciate your help in advance > Thank you > Ram The xilinx sockets are very similar to standard UNIX/Berkeley Sockets. These have been around a long time, and there are multiple great references, so if you Google "BSD Sockets" (for Berkeley Systems Distribution, IIRC), it should give you some good introductory material that will get you enough background to understand the Xilinx documentation (since it isn't _exactly_ the same thing). -- Pierre-Olivier -- to email me directly, remove all _N0SP4M_ from my address --Article: 68334
On 1 Apr 2004 07:07:40 -0800, jose.desousa@inesc-id.pt (Jose T. de Sousa) wrote: >I work for a company who recently released a new Spartan 2E 300 board >and we would like to list it in the www.fpga-faq.com/FPGA_Boards.shtml >site. > >Does anybody know how to do this ? > >Thanks > >Jose I guess you could send email to the maintainer of the site. I guess the maintainer could have made it easier for you by putting an email at the bottom of the page. Also, it isn't an advertisement, it is a free listing (at least up to now). =================== Philip Freidin philip@fliptronics.com Host for WWW.FPGA-FAQ.COMArticle: 68335
PO Laprise wrote: > John Retta wrote: > >> This typically happens when output signals from a logic block are not >> connected (though a typo or some other unintended reason) ... as >> MAP works backwards it trims away. >> >> To find the offending path, either use a simulator (highly recommended), >> or add some "debug only signals" .... which are the OR of all output >> signals from a suspected block .... whose output is brought to a top >> level I/O. If this small logic addition suddenly adds large amounts >> of previously trimmed logic, then you know that the downstream signals >> are being optimized away. >> >> Good luck. >> > > It can also happen if a) the clock signal to your output flip-flops is > unconnected somehow or (more common) b) the enable signal to these > flip-flops is stuck low for some reason. > This is true and the trim report in the .mrp file can sometimes be misleading about where the trimming originated. I use the following iterative process to debug unexpected trimming behavior: 1. Pick an instance (usually a FF) from the logical design that is being trimmed unexpectedly and apply an "S" property to all input/output nets. 2. Rerun map and examine the resulting NCD in FPGA Editor. Note which inputs/ouputs are undriven/unloaded or optimized to constants and what affect this would have on the trimmed logic. This should identify the direction that the trimming is coming from. For example, the CE input may be GND. 3. Once the direction of the trimming has been identified. apply more "S" properties on the logic in that direction and repeat step 2. Continue until the source of the trimming has been identified. Other tips: If you suspect that a FF is never going high, try applying an INIT=1 property to it as a test. Does the trimming behavior change? If you reach a point where the "S" properties don't successfully block some trimming, this is a sign that the logic is being removed due to optimization. Usually one or more of the inputs has been optimized to a constant. Bret Wade Xilinx Product ApplicationsArticle: 68336
"Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in message news:<406c0218$0$31716$fa0fcedb@lovejoy.zen.co.uk>...
> > 1. result port is connected to internal bus in your design.
>
> But he has said only the pin out is tri-stated.
>
In the original post he said:
"
hi data bus driver : lpm bustri GENERIC MAP (LPM WIDTH => 30)
PORT MAP (
<snip>
result => dnio_inbus,
<snip>
dnio and dnio_inbus are internal data buses.
"
> I presume the structure is something like
>
>
> pin <= int_dnio if (n0_dir = '?') else 'Z'
> dnio_inbus <= pin;
>
I guess he tried to do something like (sorry for my syntax, i'm not a
native VHDL speaker):
if (n0_dir = '1')
{
// enabletr = '1'
dnio_inbus <= dnio_rec;
// enabledt = '0'
dnio_rec <= 'Z';
}
else
{
// enabletr = '0'
dnio_inbus <= 'Z'; // the assignment is illegal in Altera FPGAs!!!!!
// enabledt = '1'
dnio_rec <= data;
}
When what he wants to say this:
if (n0_dir = '1')
{
dnio_inbus <= dnio_rec;
dnio_rec <= 'Z';
}
else
{
dnio_inbus <= 'X';
dnio_rec <= data;
}
I think it's impossible to say exactly what he wants with lpm_bustri()
so he should settle for:
if (n0_dir = '1')
{
dnio_inbus <= dnio_rec;
dnio_rec <= 'Z';
}
else
{
dnio_rec <= data;
dnio_inbus <= data;
}
Or to say it in a weird lpm_bustri language:
hi data bus driver : lpm bustri GENERIC MAP (LPM WIDTH => 30)
PORT MAP (data => int_dnio,
enableDT => NOT n0_dir,
enableTR => '1',
result => dnio_inbus,
tridata => dnio_rec
);
>
> > Altera recommends using TRI primitives rather than lpm_bustri(). Very
> > good recommendation! lpm_bustri() function is poorly designed and
> > misleading.
>
>
> Why use primitives? Is it not easier to infer the tr-state
> as above? This makes device/manufacturer migration easier
> too.
>
Altera (and I) had in mind AHDL. AHDL syntax lacks tri-state literal
('Z') so in order to implement tristate pin you have to use either
TRI primitive or lpm_bustri() function. Of coarse for VHDL your syntax
is better.
Article: 68337Hi all, I have a problem where my functional simulations are perfect, my timing constraints are all met, my post-par timing simulation doesn't violate any timing checks, but the results from my timing simulation are not the same as for my fuctional simulation. I suspect the culprits are some multi-cycle paths that must not be so multi-cycle as I thought (if there are other possibilities, please let me know), and I was hoping to debug this by inserting delays on these paths to verify whether this is the case. I would use my post-par model, but it seems to take 3 days to run instead of the several hours for my functional model (Ahhh, to have a faster computer with more RAM!;) I was therefore hoping to simply insert a simulation delay on these nets and was wondering what the best method might be? I'd prefer not to edit the VHDL code if possible, I was thinking along the lines of an SDF file, but this format seems more suited to structural code, since it only allows for delays between ports (since the NETDELAY keyword was removed from version 3.0). Thanks in advance, -- Pierre-Olivier -- to email me directly, remove all _N0SP4M_ from my address --Article: 68338
GlennH <glenn@abcd.glennh.com> writes: > Whats a normal execution time for a testbench? Anywhere from a few seconds to a several months. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 68339
jose.desousa@inesc-id.pt (Jose T. de Sousa) wrote in message news:<4694c849.0404010707.10064885@posting.google.com>... > I work for a company who recently released a new Spartan 2E 300 board > and we would like to list it in the www.fpga-faq.com/FPGA_Boards.shtml > site. > > Does anybody know how to do this ? > > Thanks > > Jose >From the bottom of the web page: To have your board added to this list, or if you have updated information, please email me: philip dot freidin AT fpga dash faq dot comArticle: 68340
Matthias Müller <spam*mur@iis.fhg.de> wrote in message news:<406BE4EF.4B1DEC3F@iis.fhg.de>... > Hello, > I have cascaded two Xilinx PROM's: XC18V04 + XC18V512 in order to > configure a XC2VP7 in Master-Parallel mode. Impact 6.2i only offers the > option Xilinx Serial PROM. Also if I use the non xilinx-specificl option > "Parallel PROM" it seems not to be possible to run the PROM's for > paralle configuration! I can only configure the FPGA in Maste serial > mode! Does anyone know how I can run the cascaded PROM's in > Master-Parallel mode? > Thank you, > Matthias The parallel mode of the XC18V00 series is set during configuration, not at the time you generate the PROM file. You would therefore select the parts during PROM file generation as if you were using them in the serial mode. Then when you configure the devices over JTAG, right click on the XC18Vxx parts and check the Parallel Mode box in the programming options.Article: 68341
Matthias, You'll still generate the Xilinx PROMs with teh Xilinx Serial PROMs option. To program the FPGA from the prom in Parallel mode, you'll have to set the option when you program the MCS file to the PROM. After you've generated MCS file from the Xilinx Serial PROMs option, you should detect the JTAG chain. You'll then proceed to assign the MCS file to the PROM. If you then right click on the PROM and select Program, a program Options dialogue would pop up. To the right of the dialogue box, you'll see options such a Load FPGA or Parallel Mode. If you check the Parallel Mode option, the PROM will configure the FPGA in parallel mode. Regards, Wei Xilinx Applications Matthias Müller wrote: > Hello, > I have cascaded two Xilinx PROM's: XC18V04 + XC18V512 in order to > configure a XC2VP7 in Master-Parallel mode. Impact 6.2i only offers the > option Xilinx Serial PROM. Also if I use the non xilinx-specificl option > "Parallel PROM" it seems not to be possible to run the PROM's for > paralle configuration! I can only configure the FPGA in Maste serial > mode! Does anyone know how I can run the cascaded PROM's in > Master-Parallel mode? > Thank you, > Matthias >Article: 68342
Hello, I'm having a problem reading a single one byte register on a Nios/Cyclone board. I've seen this on the devkit board as well. Every time I read a single memory location, the Nios is automatically generating reads for the next 3 locations as well. This causes bad things to happen when you are reading a location that is within 3 bytes of a location that does not want to be read. There doesn't appear to be a setting in the SOPC User Logic GUI. Is there a .ptf file entry I can edit to stop this behavior? The UL has 5 address bits, 8 databits, (RD#,WR#,CS#) and is an Avalon Memory Slave. Thanks, KenArticle: 68343
Hi Hendra, Hope you won't mind my providing some clarification regarding availability of ModelSim from Altera. Your post suggested we don't provide ModelSim, when in fact we do. At Altera, one way we provide our software development tools is through the Altera Subscription program (more details at http://www.altera.com/products/software/order/ord-subscription.html and http://www.altera.com/products/software/pld/products/partners/eda-ms.html). In addition to our Quartus II software development tool, this subscription *does include* an Altera-only version of ModelSim. The second way we provide our tools is through our free Web Edition version of Quartus II. This version is identical to our Subscription Edition, with the exception of a few software features and device support for our high density FPGAs and HardCopy structured ASIC. This version, however, does not include ModelSim. Quartus II (both Subscription and Web Editions) does include a graphical waveform simulator, which sees a lot of use from our customers. I'm not aware of any FPGA vendor that provides 3rd party simulation tools along with the free version of their software. There's a couple places to check out to learn more about design simulation with Altera: 1) is our Online Demo Center (www.altera.com/quartusdemos)--click on simulation in the "Basic FPGA/CPLD Design" chapter; and 2) Our Quartus II Handbook contains a nice chapter on simulating with ModelSim (Volume 3, Chapter 1 at http://www.altera.com/literature/lit-qts.jsp) I hope this has been useful. Cheers, Chris Balough Director, Software & Tools Marketing, Altera "Hendra Gunawan" <u1000393@email.sjsu.edu> wrote in message news:<c4de2n$6gue0$1@hades.csu.net>... > "Matt" <bielstein2002@comcast.net> wrote in message > news:z_pac.40715$w54.264141@attbi_s01... > > Hendra, > > > > You're just too young. :-) MaxPlus II was a rock'n tool for its time. > > And what year was it? > > > Very > > well received by the engineering community. > > At that time may be! But why bother using outdated tool while you can have a > better one? > I don't mind using Altera FPGAs, but the tool must be something other than > MaxPlus II or Quartus. I just don't like any tool from any vendor that does > not support testbench. Specifying your inputs by dragging your mouse instead > of writing a code is just dumb! It may work for very small design, but for > large design, it won't work! To my knowldege, due to the nature of > synthesis, none of the synthesis tool supports testbench, including Xilinx > XST. But Xilinx allows me to use their free ModelSim simulator to be > incorperated with their synthesis tool. While Altera, from my understanding, > doesn't have the free version of their ModelSim. > > HendraArticle: 68344
Hi folks, I am thinking of buying Xilinx ISE BaseX but I am not clear about their license policy. The written policy in their website is not very clear. 1. What exactly is going to happen after one year has passed? Will the software stop working? Or may be they just don't send me major update anymore but I still can use the older version with the latest service pack?! 2. Does ISE BaseX comes with a dongle? 3. If I need to reformat and reinstall the OS + ISE, do I need to re-register similar to those activation mechnism that comes with Windows XP? 4.How much will it cost to estend the license for another year? Thanks! HendraArticle: 68345
Brian Philofsky <brian.philofsky@no_xilinx_spam.com> wrote in message news:<40645BBE.9010507@no_xilinx_spam.com>... > Looks to me that P207 on the Spartan-3 parts is the dedicated PROGRAM > pin for the FPGA and thus a user signal can not be assigned to that pin. > It is and always will be the pin to reset configuration and thus the > software can not do anything to change that pin and does not even really > know of its existance because of this. That pin should be properly > connected to the board as said in the documentation for Spartan-3 but > nothing should be done with that pin from within the software. > > > -- Brian Thanks,Brian. Meantime I have looked at the pin description of S3 board and P207 belongs to the CONFIG pin type which is not available for user I/O. Thanks anyway for your explanation. Chao.Article: 68346
Consider that the Virtex-II Pro has a wide mux structure available to implement 32 input multiplexers through "one" stage of logic using the dedicated multiplexing elements up through MUXF8. If you have more than 32 inputs, you can go for more than one of these in series *or* use the Sum Of Products logic outlined in the Virtex-II Pro Platform FPGA User Guide to have the familiar-looking horizontal segmenting. I would only expect someone to use the SOP logic for some extremely wide muxing since it may take some hand-coding. Your synthesizer might even optimize this for you, specified as a mux *or* tristates! Bottom line, you can go very wide and have great access times. "Matthew E Rosenthal" <mer2@andrew.cmu.edu> wrote in message news:Pine.LNX.4.58-035.0403311916001.9835@unix45.andrew.cmu.edu... > Hi, > I am trying to create a large bus(32 bits wide), with many slaves > recieving and sending data. > Should I look for tristates on my V2pro or giant MUX or any other > suggestion anyone has? > > Thanks > > MattArticle: 68347
Look at the On-Line help under script files. The following is a possible command line. The "script_file.dsf" is a file of commands to be run. The "script_mode:batch" indicates run the script file and then exit. C:\Actel\bin\designer script:dummy.dsf script_mode:batch I have NOT used this method, except that the front end software I use calls the Designer functions using a Sript file with what I can only assume is this method. Good luck. BTW, what size part are you using? For the smaller parts, you can get the Designer Software for free and do it locally. -- Greg readgc.invalid@hotmail.com.invalid (Remove the '.invalid' twice to send Email) "Wojciech Zabolotny" <wzabolot@elka.pw.edu.pl> wrote in message news:Pine.SOL.4.33.0403291857050.2862-100000@elektron.elka.pw.edu.pl... > Hi All, > > I'm working on the design which needs to be implemented in radiation > tolerant Actel chips. Unfortunately I have only remote access to the > machine with the Actel Designer installed, so it is painfully slow. > Is it possible to compile the design from the command line? > Where can I find info about using the Actel tools from CLI instead of > GUI? > -- > TIA & Regards, > Wojtek Zabolotny > >Article: 68348
"Chris Balough" <cbalough@altera.com> wrote in message > Hi Hendra, > Hope you won't mind my providing some clarification regarding > availability of ModelSim from Altera. Your post suggested we don't > provide ModelSim, when in fact we do. I quoted my previous message: " While Altera, from my understanding, doesn't have the free version of their ModelSim." My post suggested that Altera does not provide the FREE version of ModelSim. It does not say that Altera does not provide the paid version of ModelSim. > At Altera, one way we provide our software development tools is > through the Altera Subscription program Which means unlike Xilinx, Altera does not provide the free version of ModelSim. > The second way we provide our tools is through our free Web Edition > version of Quartus II. This version is identical to our Subscription > Edition, with the exception of a few software features and device > support for our high density FPGAs and HardCopy structured ASIC. This > version, however, does not include ModelSim. Quartus II (both > Subscription and Web Editions) does include a graphical waveform > simulator, which sees a lot of use from our customers. Does Quartus Web Edition support VERILOG BASED testbenches? By testbenches I mean I write a program in Verilog that injects signal to the Unit Under Test (UUT). I know MaxPlus II doesn't support it because in order to test my circuit, I have to drag the mouse in the waveform or specify the signal in a text file without any support of loop, or any other data manipulation technique (such as self checking testbench) commonly found in programming language. > I'm not aware of any FPGA vendor that provides 3rd party simulation > tools along with the free version of their software. Xilinx does provide the free version of ModelSim along with the free Xilinx Webpack. www.xilinx.com/ise for the free Xilinx Webpack http://www.xilinx.com/ise/mxe2/ for the free version of ModelSim Xilinx Edition Note: the common misconception about the free version of ModelSim Xilinx Edition is the software stops working after 500 lines of code. That is not true! The software still works after 500 lines of code, it just run slower but still works. HendraArticle: 68349
On Thu, 01 Apr 2004 15:35:25 -0800, Hendra Gunawan wrote: > Hi folks, > I am thinking of buying Xilinx ISE BaseX but I am not clear about their > license policy. The written policy in their website is not very clear. > > 1. What exactly is going to happen after one year has passed? Will the > software stop working? Or may be they just don't send me major update > anymore but I still can use the older version with the latest service pack?! > 2. Does ISE BaseX comes with a dongle? > 3. If I need to reformat and reinstall the OS + ISE, do I need to > re-register similar to those activation mechnism that comes with Windows XP? > 4.How much will it cost to estend the license for another year? > > Thanks! > > Hendra The software will work forever you just won't get updates if you don't renew your service agreement. There is no license file or dongle just a license number for the installer.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z