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Hi Rudolf This is with regards to your usb 1.1 function core from opencores.org. Your USB clock needs a 48MHz clock speed. I have a Nios Development Board with a 50MHz oscillator. I'm using a PLL to drop the speed to 48.076923MHz (ratio of 25/26). Is that OK or does it have to be ditto 48MHz cuz that's the best that I can get. RegardsArticle: 68301
"V Madhuri" <madhuri@india.nsc.com> wrote in message news:d0ed672e.0403310210.57cac1ed@posting.google.com... > Hi, > I have a esf file with me that contains information about > multi_cycle_paths and false paths. I want to know if there is a > utility that will convert this esf file to a tcl format that can be > used with synopsys primetime tool. > > Thanks for your time > Madhuri Here are the steps to generate the Tcl file with Quartus II 4.0. 1. Open the project in Quartus. 2. From the menu choose Assignments->EDA Tool Settings 3. Click on Timing Analysis to open up the Timing Analysis Panel. 4. In the Timing Analysis Panel, select Tool Name to be Prime Time (VHDL Output from Quartus II). 5. From the menu choose Processing->Start->Start EDA Netlist Writer 6. This will create a directory called Timing in your project directory. 7. The Timing directory will have a subdirectory called Primetime. 8. The Primetine directory wil have the Tcl file with the name projectname_pt_vhd.tcl - Subroto Datta Altera Corp.Article: 68302
Try checking the testbenches provided with the USB cores in www.opencores.org > Hi, > > the data is itself the USB packets for my USB application. > It is the data we see on the USB. > > Rgds > Andrés V.Article: 68303
Hi all, i have a verilog design in which some of the modules are similar to the one given below. it has to shift right the input by 4 for first 10 clock cycles and shift right by 5 from the next clock cycle. it works fine in the simulator. but when i actually tested it in hardware(fpga), tmp register does not increase at the rising clock cycle. it keeps increasing, so the output is always shown right shifted by 5. how do i make it work. do i have to send the tmp out and read it in the next clock cycle. is there any other way to do it, because there are many counters used in the design. module app(ain,aout,clk,reset); input [31:0] ain; input clk,reset; output [31:0] aout; reg [31:0] aout; reg [31:0] tmp; // here i am using tmp just as a counter. always @ (posedge clk or negedge reset) begin if (!reset) begin aout=0; tmp=0; end else begin if(tmp<10) begin aout=ain>>4; tmp=tmp+1; end else begin aout=ain>>5; tmp=tmp+1; end end end endmodule thanks a lot, srArticle: 68304
Allan,
Does that switch do anything in the hardware, or is it there just as a
software thing to handle the flavors with and without the PPC black
holes? Somehow I doubt the 'recovery' happens in the real FPGA.
Allan Herriman wrote:
> Hi,
>
> I was poking around in FPGA Editor, and I found a switch I hadn't
> noticed before. There's an Virtex2Pro-specific option to disable the
> PowerPC cores and "recover" the FPGA fabric that they overlay.
>
> Yay! No more PPC cores getting in the way of my floorplan and RPMs.
>
> Question: is there a command line option (on Map or PAR) for this so
> that I don't have to use FPGA Editor?
>
> Cheers,
> Allan.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 68305On Thu, 01 Apr 2004 00:15:51 -0500, Ray Andraka <ray@andraka.com> wrote: >Allan, > >Does that switch do anything in the hardware, or is it there just as a >software thing to handle the flavors with and without the PPC black >holes? Somehow I doubt the 'recovery' happens in the real FPGA. Sure Ray, something happens in the real FPGA, but only on April 1. Cheers, Allan.Article: 68306
Ben Howe wrote: > Rudi, > > The Architecture Wizard should generate a component with a > CLKIN_IBUFG_OUT output port (if the 100 MHz clock is coming from a > pad). Send that signal from the dcm60 into the CLKIN_IN port of the > dcm75. Also, for your dcm75, in the Architecture Wizard, specify that > the clk is coming from an internal source. This will prevent an IBUFG > from being inserted in the dcm75 file. This worked for me. > > Code snippet below: > > Inst_dcm60: dcm60 PORT MAP( > CLKIN_IN => clk100, > LOCKED_OUT => open, > CLKFX_OUT => clk60, > CLKIN_IBUFG_OUT => clk100_ibufg_out, > CLK0_OUT => open > ); > > Inst_dcm75: dcm75 PORT MAP( > CLKIN_IN => clk100_ibufg_out, > LOCKED_OUT => open, > CLKFX_OUT => clk75, > CLK0_OUT => open > ); > > If you need the rest of the code, I can send it to you. > > Regards, > Ben Hi Ben, yes I have tried that as well, and yes it does work, except the timing between the 60 and 75 MHz clocks can not be separated (at least thats what it seems to me). It creates a dependency between the clocks (I think). I meet the 60 MHZ timing but the 75MHz timing is off by a factor of 2 ! (I meet all timing if I use separate clock inputs for the DCMs.) How do you constrain the outputs of the DCMs in your UCF file ? Thanks ! rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> http://www.asics.ws/ <- FREE EDA ToolsArticle: 68307
Meanwhile I received a confirmation about this from xilinx. The gmac core can only simulated with modelsim xe (starter or full) if the gmii interface is choosen. For the simulation of the other configurations, you'll need modelsim pe (with swift license) or modelsim se. Frank "Frank van Eijkelenburg" <someone@work.com> wrote in message news:406a6947$0$18995$ee9da40f@news.versatel.net... > I get the impression that I can not simulate the gigabit ethernet mac IP > from xilinx with modelsim xe starter or modelsim xe. Only modelsim se or pe > are able to do this (if you have the swift license). Can anyone confirm > this? > > TIA, > Frank > >Article: 68308
Modelsim PE (with swift license) or modelsim SE is required to simulate. "Frank van Eijkelenburg" <someone@work.com> wrote in message news:40682cf8$0$151$1b2cd167@news.versatel.net... > Hi, > > I downloaded the 6.1i Update #1 in order to be able to generate the 1 > gigabit ethernet mac with coregen. It should be possible to simulate the > generated ip. However, I'am not able to do so. After running the > implement.bat file from a command line, I start modelsim XE (full edition). > I navigate to the test/vhdl directory and run the command "do > simulate_mti.do". Two warnings are generated and the simulator is being very > very busy? It's very slow in generating the results in the wave window. Is > this normal, or should the testbench be executed in "no time"? And what > about the warnings that are generated?? > > Modelsim output generated: > > # Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003 > # -- Loading package standard > # -- Loading package std_logic_1164 > # -- Loading package vital_timing > # -- Loading package vcomponents > # -- Loading package vital_primitives > # -- Loading package textio > # -- Loading package vpackage > # -- Compiling entity netlist > # -- Compiling architecture structure of netlist > # -- Loading entity x_zero > # -- Loading entity x_ff > # -- Loading entity x_buf > # -- Loading entity x_ibufds > # -- Loading entity x_dcm > # -- Loading entity x_ckbuf > # -- Loading entity x_lut3 > # -- Loading entity x_one > # -- Loading entity x_lut4 > # -- Loading entity x_lut2 > # -- Loading entity x_mux2 > # -- Loading entity x_sff > # -- Loading entity x_srlc16e > # -- Loading entity x_xor2 > # -- Loading entity x_and2 > # WARNING[1]: routed.vhd(38389): No default binding for component: "x_gt". > (No entity named "x_gt" was found) > # -- Loading entity x_or2 > # -- Loading entity x_tri > # -- Loading entity x_inv > # -- Loading package vital_timing > # -- Loading entity x_roc > # -- Loading entity x_toc > # Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003 > # -- Loading package standard > # -- Compiling entity testbench > # -- Loading package std_logic_1164 > # -- Loading package numeric_std > # -- Compiling architecture behav of testbench > # -- Loading package vital_timing > # -- Loading package vcomponents > # -- Loading package vital_primitives > # -- Loading package textio > # -- Loading package vpackage > # -- Loading entity netlist > # vsim -t ps work.testbench > # Loading C:/Modeltech_xe/win32xoem/../std.standard > # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) > # Loading C:/Modeltech_xe/win32xoem/../ieee.numeric_std(body) > # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) > # Loading C:/Modeltech_xe/win32xoem/../vital2000.vital_timing(body) > # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.vcomponents > # Loading C:/Modeltech_xe/win32xoem/../vital2000.vital_primitives(body) > # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.vpackage(body) > # Loading work.testbench(behav) > # Loading C:/Modeltech_xe/win32xoem/../ieee.vital_timing(body) > # Loading work.netlist(structure) > # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_zero(x_zero_v) > # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_ff(x_ff_v) > # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_buf(x_buf_v) > # Loading > C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_ibufds(x_ibufds_v) > # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_dcm(x_dcm_v) > # Loading > C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.dcm_clock_divide_by_2(dcm_c > lock_divide_by_2_v) > # Loading > C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.dcm_maximum_period_check(dc > m_maximum_period_check_v) > # Loading > C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.dcm_clock_lost(dcm_clock_lo > st_v) > # Loading > C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_ckbuf(x_ckbuf_v) > # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_lut3(x_lut3_v) > # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_one(x_one_v) > # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_lut4(x_lut4_v) > # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_lut2(x_lut2_v) > # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_mux2(x_mux2_v) > # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_sff(x_sff_v) > # Loading > C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_srlc16e(x_srlc16e_v) > # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_xor2(x_xor2_v) > # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_and2(x_and2_v) > # ** Warning: (vsim-3473) Component > 'gmac_core_bu2_u0_gpcs_pma_inst_mgt_mgt_gt' is not bound. > # Time: 0 ps Iteration: 0 Region: /testbench/dut File: routed.vhd > # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_or2(x_or2_v) > # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_tri(x_tri_v) > # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_inv(x_inv_v) > # Loading C:/Modeltech_xe/win32xoem/../ieee.vital_primitives(body) > # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_roc(x_roc_v) > # Loading C:/Modeltech_xe/win32xoem/../xilinx/vhdl/simprim.x_toc(x_toc_v) > # WARNING: No extended dataflow License exists > # .source .process .signals .variables .dataflow .list .wave > # ** Note: Resetting core... > # > # Time: 0 ps Iteration: 0 Instance: /testbench > # ** Note: Timing checks are valid > # > # Time: 700 ns Iteration: 0 Instance: /testbench > # ** Note: Disabling Auto-Negotiation in PCS sublayer.... > # > # Time: 700 ns Iteration: 0 Instance: /testbench > # ** Note: Transmitting four frames... > # > # Time: 27600 ns Iteration: 1 Instance: /testbench > > TIA, > Frank > >Article: 68309
SneakerNet wrote: > Hi Rudolf > > This is with regards to your usb 1.1 function core from opencores.org. > > Your USB clock needs a 48MHz clock speed. I have a Nios Development Board > with a 50MHz oscillator. I'm using a PLL to drop the speed to 48.076923MHz > (ratio of 25/26). Is that OK or does it have to be ditto 48MHz cuz that's > the best that I can get. > > Regards I don't know from the top of my head, you need to check the USB spec. Look at the max error rate they allow. Please post follow up messages to the usb forum at OpenCores.org. Thanks, rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> http://www.asics.ws/ <- FREE EDA ToolsArticle: 68310
"SneakerNet" <nospam@nospam.org> wrote in message news:ILMac.1374$d%6.39465@news.xtra.co.nz... > Hi Rudolf > > This is with regards to your usb 1.1 function core from opencores.org. > > Your USB clock needs a 48MHz clock speed. I have a Nios Development Board > with a 50MHz oscillator. I'm using a PLL to drop the speed to 48.076923MHz > (ratio of 25/26). Is that OK or does it have to be ditto 48MHz cuz that's > the best that I can get. it will receive 100% ok also with 50MHz clock I once tested accidently, not sure if the hosts will accept 50MHz transmit 48.08 will defenetly work both ways, not matter if it is withing spec range or not Antti LukatsArticle: 68311
Try at Memec. website : http://www.insight.na.memec.com/cgi-bin/bvutf8/memec/scripts/local/mc_loc_home.jsp?Div=INSIGHT&Reg=AMERICAS&Country=UNITED_STATES&Lang=EN RamArticle: 68312
"B. Joshua Rosen" <bjrosen@polybus.com> writes: > The spec marks aren't a good indicator because the Intel numbers are > using the Intel compilers which are much better than any other > compilers. The tools are probably compiled using GCC not Intels > compilers. Some of the AMD SPEC benchmarks are done using the Intel compiler. I think Altera is using the Intel compiler for Quartus. I don't know what compiler Xilinx are using though. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 68313
Hi Group, I need help on using the XilNet libraray and Xilinx EMAC core. ( www.xilinx.com) I am a newbie to TCP/IP stack , so I need some pointers on where to get started. I have seen Xilinx App notes , but the C files are too confusing for me, and it has plethora of socket functions,. Can anybody please point me how to get started and going. I appreciate your help in advance Thank you RamArticle: 68314
GlennH <glenn@abcd.glennh.com> wrote: > Whats a normal execution time for a testbench? There is no such thing as "normal execution time" for a testbench. It depends of course on your simulation system (P3 800 MHz has other Perfomance than a P4 3GHz). Further on the complexity of your design, next point is the average switching frequency for your design, as a simulator needs to calculate every signal switching. Another point is the testbench itself. You could programm fast testbenches or slow testbenches. A testbench using only sequential signalassignments an wait statements will be quite faster than a testbench, that calculates the stimuli and waittimes or reads them from external stimuli files. > Is simulation the only verificationmethod used for fpga designs or do > people use function test too? Functional tests with Fpgas are typicaly done, when your satisfied about your simulation results. When doing a functional test, your debugging the whole system without exactly knowing wheter a failure was indicated by false logic inside the fpga. You could use property checking, model checking and equivalence checking as further methods to ensure the functionality of your design. Static timing analyses is done to verify the timing behavior of your netlist. bye ThomasArticle: 68315
Hello, I have cascaded two Xilinx PROM's: XC18V04 + XC18V512 in order to configure a XC2VP7 in Master-Parallel mode. Impact 6.2i only offers the option Xilinx Serial PROM. Also if I use the non xilinx-specificl option "Parallel PROM" it seems not to be possible to run the PROM's for paralle configuration! I can only configure the FPGA in Maste serial mode! Does anyone know how I can run the cascaded PROM's in Master-Parallel mode? Thank you, MatthiasArticle: 68316
erojr <janos.nojunk.nospam.ero@cern.nojunk.nospam.ch> wrote in message news:<c4dp03$dfl$1@sunnews.cern.ch>... > Martin Schoeberl wrote: > > The answer is simple: You don't have tristate busses inside (Altera) > > FPGAs. Tristate buffers are substituded by MUX. > > There are no tristate buses inside. The only tristate bus is directly > connected to the pins, in the lpm definition this is the pin name. The > internal buses have only one source, in the case of the result this > is the tristate buffer. > > Thanks for the help, but this is not the case. > > Janos Ero > CERN Div. EP 1. result port is connected to internal bus in your design. 2. Internal nodes (buses) can't be tristated in Altera FPGAs (AFAIK, that's true for newer Xilinx FPGAs as well). Internal nodes are '0' or '1' - no 'Z'. I don't understand what exactly you don't understand :( P.S. Altera recommends using TRI primitives rather than lpm_bustri(). Very good recommendation! lpm_bustri() function is poorly designed and misleading.Article: 68317
The bus macro doesn't seem to lack anything, but I discovered that if I route the concerned signal to a "pip" further to the left, the design finally routes. So it seems that the PAR needs to have that first part of the path to route the signal. Another question, are the bus macro really compulsory? If I use a custom bus macro, without TBUFs, just to be sure that the signal passes through the same nets, will it work? Your help was very useful. Regards, Amaury Anciaux > Yes, but in this case, even in the final assembly, this signal stays > unrouted. > I attach some example files: the NCD routed designs of the two modules, and > the final assembly. > The signals conerned are controlL<3> and controlL<7> (in module 1 and final > assembly). Other unrouted signals in the modules are normal. Try the following at the command prompt: xdl -ncd2xdl bm_v2p_4b.nmc This converts the bus macro to an XDL-description. Have a look at the .XDL-file this generates. For each net, there should be a section where it specifies which PIPs to use and such. For each net there should be an attribute like this: cfg "_NET_PROP::IS_BUS_MACRO:" , If there isn't, par sometimes doesn't route the corresponding output net. I have no idea why that is... In case this attribute is not set for the fourth bit of your bus macro, it could help to insert it manually in the .XDL-file and convert that back to ncd-format: xdl -xdl2ncd bm_v2p_4b.xdl This gives you an .ncd-file which you have to rename to .nmc to be able to use it as a macro. Don't know if this will help you, but I always had to manually insert the above attribute for all nets in the macros I did myself in FPGA Editor. FPGA Editor always seems to "forget" that, for whatever reason. BTW, I'm not sure if all of this works satisfactory with ISE6.1/6.2... When using XDL in ISE6, I always get a warning that "this is a new revision ncd, some features might be lost" or something. > As you can see, they are connected to the same TBUF in both bus macros. > BTW, do you know if the T input of a TBUF has to be "1" or "0" to be in high > impedance? "1" disables the tristate buffer, so "1" for high impedance. -- Best regards, Sean DurkinArticle: 68318
Thanks - we use those - but I was hoping for a niche or even association type site that had career listings.... KellyArticle: 68319
> 1. result port is connected to internal bus in your design. But he has said only the pin out is tri-stated. I presume the structure is something like pin <= int_dnio if (n0_dir = '?') else 'Z' dnio_inbus <= pin; > Altera recommends using TRI primitives rather than lpm_bustri(). Very > good recommendation! lpm_bustri() function is poorly designed and > misleading. Why use primitives? Is it not easier to infer the tr-state as above? This makes device/manufacturer migration easier too. Nial. ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 68320
PO Laprise <pl_N0SP4M_apri@cim._N0SP4M_mcgill.ca> wrote in message news:<ZXDac.73308$aC1.66125@charlie.risq.qc.ca>... > Marija wrote: > > Hi Jean, > > > > I know that the frequency > > synthesis shows is only estimated. > > The real problem is that I have > > a .xcf file in which I have > > defined clk freq constraint, and > > after PAR everything looks OK. ISE > > even reports that timing > > constraints are met. Later, when I > > run gate level simulation, using > > frequency which is close to the > > maximal, I do not get good > > results. > > > > BR, > > Marija > > > > Something similar just happened to me, and I believe I have fixed it > (I'm currently into the second day of error-free post-PAR timing > simulation). First of all, are you simulating using the SDF > back-annotations in your simulations? If so, your simulator should tell > you exactly where (if) any timing errors are happening. In my case, > when I first did the timing simulation, I was getting multiple > violations on the input flip-flops to my module (I have combinational > logic in between my inputs and the first synchronous elements) despite > having met all timing constraints in PAR. The problem seems to have > been that ISE assumed my signals were coming from pads instead of > another synchronous module, and I assume this changed its timing > analysis. By including the "wrapper" synchronous elements and logic in > my synthesis (which were already in my simulation), ISE seems to have > correctly routed to respect my timing. At the very least, Modelsim > hasn't given me any timing violations (cross fingers, knock wood ;). > Hope this helps, Another thing that happens in simulation is rounding errors. If the simulation is getting very near the maximum frequency, you may need to set the resolution to 1 ps if you haven't already done so. This is also necessary to get proper synthesis of DCM's and DLL's in Xilinx parts.Article: 68321
I'm looking into a crosspoint switching application where it appears FPGA's are the best choice even though I won't use much of the internals. What I'm looking for is the best price per I/O pin of relatively fast parts. Newer releases of FPGA seem to target better price per logic cell rather than I/O so I've already noticed that from Xilinx I can do better with Spartan 2e than Spartan 3 in terms of cost per I/O pin. Obviously smaller parts in each family also giver better price per I/O because there are more I/O's per logic cell. Any suggestions for a better price would be appreciated. Also the reason I'm not currently looking at CPLD's is that the application requires soft upload and I don't want parts with limited programming cycle life (EPROM or FLASH based). 256 I/O's per part is a good match for the design although even at this level I will need multiple parts. Right now I'm more interested in what family to use for the best price per I/O and then I'll pick the device size that fits best.Article: 68322
Rudolf Usselmann <russelmann@hotmail.com> wrote in message news:<c4gbkq$6gv$1@nobel.pacific.net.sg>... > Hi Ben, > > yes I have tried that as well, and yes it does work, > except the timing between the 60 and 75 MHz clocks > can not be separated (at least thats what it seems > to me). > > It creates a dependency between the clocks (I think). > I meet the 60 MHZ timing but the 75MHz timing is off > by a factor of 2 ! (I meet all timing if I use separate > clock inputs for the DCMs.) > > How do you constrain the outputs of the DCMs in your > UCF file ? Hi Rudi, I only constrain the input clock to the DCM and the constraints for the output clocks are automatically generated. Maybe you should try specifying a FROM-TO constraint across clock domains. Here is my UCF file: # Constrain the input to the DCMs NET "clk100" TNM_NET = "clk100"; TIMESPEC "TS_clk100" = PERIOD "clk100" 10 ns HIGH 50 %; # Create a timing constraint to constrain paths that cross clock domains NET "clk60" TNM_NET = "clk60"; NET "clk75" TNM_NET = "clk75"; TIMESPEC "TS_crosscycle" = FROM "clk60" TO "clk75" 5 ns; Regards, BenArticle: 68323
You got me!
Allan Herriman wrote:
> On Thu, 01 Apr 2004 00:15:51 -0500, Ray Andraka <ray@andraka.com>
> wrote:
>
> >Allan,
> >
> >Does that switch do anything in the hardware, or is it there just as a
> >software thing to handle the flavors with and without the PPC black
> >holes? Somehow I doubt the 'recovery' happens in the real FPGA.
>
> Sure Ray, something happens in the real FPGA, but only on April 1.
>
> Cheers,
> Allan.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 68324ram wrote: > Try at Memec. > website : > http://www.insight.na.memec.com/cgi-bin/bvutf8/memec/scripts/local/mc_loc_home.jsp?Div=INSIGHT&Reg=AMERICAS&Country=UNITED_STATES&Lang=EN > Ram Yes, thanks I looked at them. They do not have linux bundled, and are about $200 more than the Avnet board. Plus they charge an additional $100 because we are outside the US ! (not including shipping !) Cheers, rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> http://www.asics.ws/ <- FREE EDA Tools
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