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"Sink0" <sink00@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote in message news:EI6dnTVfBZtCPiXRnZ2dnUVZ_v2dnZ2d@giganews.com... >I dont really need LVDS as i am using an external tranceiver. Most of FPGAs > LVDS ports cant drive a MLVDS bus. Not enough current. The MachXO is more > expensive than a Cayclone and the smallest footprint is the same. But the > best point is no need of external flash. I am not totally disconsidering > other vendors, but i strongly prefer one that i got some experience and > tools. > > Thank you! > > --------------------------------------- > Posted through http://www.FPGARelated.com > Think in terms of system, not components only. What is more expensive in the long run for your project: MachXO (or other flash based part) or FPGA + Configuration memory? I am not saying the flash-based part will be the winner here, only saying that it is worth comparing, and it all depends on your project requirements. Regards, JaaCArticle: 149326
On Oct 15, 5:30=A0pm, "Sink0" <sink00@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > Hi, i need to create a M-LVDS nwtwork running at 50-100Mbps. As i could n= ot > find any driver that could be placed to run that multdrop network (any > protocol and datalink designed with small and size variable packet (Max 2= 56 > bytes) would be suitable) i designed one myself on a FPGA. On the on the > uC/DSP side there is a 8/16 bits parallel interface and at the M-LVDS the > clock is recovered with oversampling the data (using the rise and fall ed= ge > and a second clock with 90 degree phase as described in this paper:http:/= /www.date-conference.com/proceedings/PAPERS/2010/DATE10/PDFFILE... > . > > The fisrt questions is: Is possible to implement such oversampling on a > CPLD? Does CPLDs got any kind of PLL or something like that? > > Second: Do you think CPLDs are going to stay on the market for a long tim= e? > Or they are going to disapear and there will be just FPGAs? > > Third: This device must got a real small footprint. The best i found was = a > EP1C3 of Altera, but any one knows how long is going to take until this > device is discontinued? > > Any sugestion of using a CPLD or FPGA for this design, or sugestions of a= ny > small fottprint (no BGA) FPGA of Altera or Xilinx (i got the download cab= le > of both and dont want to get a new one). > > Thank you! =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com Did you consider completely dropping uC/DSP and building design in System-On-Programmable-Chip style? If the sw code and/or memory footprint is very small it's often no- brainier. If the sw code and/or memory footprint is too big to fit in on-chip memory of uC/DSP it's also often no-brainier. Only in the middle, where software fits in flash+SRAM of uC but doesn't fit in internal memory of low-cost FPGA, the uC+FPGA ends up more attractive.Article: 149327
The idea of using the uC or DSP is considered at some cases but not always. The processin requiriments of every node of the network are completely different. Some nodes might just need a simple 16 bits uC or maybe a 300Mhz DSP. I cannot say that it would be a general solution. About the price. Yes i still have to evaluate the price of the Flash+FPGA compared to the FPGA with internal Flash. About using an external PLL, i really cant answer as i never used one for clock generation. I dont know if i can find an external PLL that can generate 2 outputs, and one shifted 90 degrees from the other. How about the skew problem between both outputs. The clock lines would have to be very well designed no? Any comment about one Cyclone I is getting discontinued? Thank you! --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149328
Hi, I'm debugging the old design which now has been complemented with the MIG core accessing the DDR2 memory (platform: SP601, coded in VHDL). To analyze problems with not working MIG core, I have switched the debugging on, and added the chipscope definition (.cdc) file. However now, when I try to compile the design, I get errors like this: Checking expanded design ... ERROR:NgdBuild:604 - logical block 'memctl_1/gen_dbg_enable.my_vio_c3' with type 'vio' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'vio' is not supported in target 'spartan6'. ERROR:NgdBuild:604 - logical block 'memctl_1/gen_dbg_enable.my_icon_c3' with type 'icon' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'icon' is not supported in target 'spartan6'. ERROR:NgdBuild:604 - logical block 'memctl_1/gen_dbg_enable.my_ila_c3' with type 'ila' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'ila' is not supported in target 'spartan6'. Should I add a library to my top-level entity to clear this problem? Or should I add some additional sources? -- TIA & regards, WZabArticle: 149329
Hi, I normally use a microcontrollers for my projects - I have used PIC's and AVR's - I mainly use them for the quick and easy programming etc. (Arduinos are great!) I've come across a case where a microprocessor can't meet my performance requirements though, but parts of my problem is very parallel, so an FPGA would be good. The entire thing is too complex to do all in VHDL or something - I prefer C/C++ for the complex stuff. The exact use case is doing some linear arithmetic, using that to calculate a pointer, and outputting the data at that memory location serially to an IO device. Throughput needs to be around 3Mbits/sec, where each bit will require the above operations, but no bit depends on any other. Does any company sell a microprocessor what has a few thousand logic elements of FPGA "on the side", which can interface fast with the microprocessor, for example through shared memory. Ideally this would be cheap (ie. tens of dollars rather than hundreds of dollars), and easy to use (I don't want to have to be defining my own DMA controller or something...) I know one can implement a CPU on an FPGA, but all the CPU's I can find seem to be small and slow, and they somehow don't seem to be the same "point and click" ease of programming an Arduino - they also require development kits costing thousands of dollars. Also I need it to be self contained - ie. a chip and maybe a crystal clock. I don't really want to have to give it 3 regulated power supplies, 2 clocks, and an external program flash memory and controller. Ideas welcome! Thanks OliverArticle: 149330
On Oct 17, 3:31=A0pm, Oliver Mattos <omat...@gmail.com> wrote: > Hi, > > I normally use a microcontrollers for my projects - I have used PIC's > and AVR's - I mainly use them for the quick and easy programming etc. > (Arduinos are great!) > > I've come across a case where a microprocessor can't meet my > performance requirements though, but parts of my problem is very > parallel, so an FPGA would be good. =A0The entire thing is too complex > to do all in VHDL or something - I prefer C/C++ for the complex stuff. > > The exact use case is doing some linear arithmetic, using that to > calculate a pointer, and outputting the data at that memory location > serially to an IO device. =A0Throughput needs to be around 3Mbits/sec, > where each bit will require the above operations, but no bit depends > on any other. > > Does any company sell a microprocessor what has a few thousand logic > elements of FPGA "on the side", which can interface fast with the > microprocessor, for example through shared memory. =A0Ideally this would > be cheap (ie. tens of dollars rather than hundreds of dollars), and > easy to use (I don't want to have to be defining my own DMA controller > or something...) > > I know one can implement a CPU on an FPGA, but all the CPU's I can > find seem to be small and slow, and they somehow don't seem to be the > same "point and click" ease of programming an Arduino - they also > require development kits costing thousands of dollars. =A0Also I need it > to be self contained - ie. a chip and maybe a crystal clock. =A0I don't > really want to have to give it 3 regulated power supplies, 2 clocks, > and an external program flash memory and controller. > > Ideas welcome! > > Thanks > Oliver Check out the Lattice XP and XP2 parts and their 32 or 8 bit micros. I don't know what "fast" means in engineering terms, so I can't say which will work for you, but I'm sure one will. I'm pretty sure both of these processors are "free" since they are supposed to be open source. RickArticle: 149331
On Oct 16, 10:08=A0am, Ulf Samuelsson <u...@notvalid.atmel.com> wrote: > rickman skrev: > > > On Oct 9, 12:55 pm, Ulf Samuelsson <u...@notvalid.atmel.com> wrote: > >> Peter Alfke skrev: > > >>> On Oct 4, 7:27 pm, rickman <gnu...@gmail.com> wrote: > >>>> Rick > >>>> PS =A0I use the computer format for dates 20101004 or preferred 1010= 04, > >>>> at least in my code. > >>> Rick, your sequence is also the official method used in Sweden. > >> Yes, but it is actually an International Standard (ISO 8601). > >> You would normally write "2010-10-04" for readability. > >> "10-10-04" risk wraparound problems. > > > Not in my lifetime! =A0Six digits works just fine for my needs. =A0I do= n't > > expect any of my code to survive for 90 more years either. > > It is also a matter of clarity. > 101010 is clearly 10 October 2010. > What is 111210? > =A0 Is it: > =A0 Dec 11, 2010 ? > =A0 Dec 10, 2012 ? > > The standard is there to remove such abiguity. > 2010-11-12 is clear. > (Noone is using YYYY-DD-MM) "Noone" meaning, you know what it means so it doesn't matter if anyone else is confused. If anyone has not seen your system, it is no more clear than any other. My system is for the computer to read, the user is secondary. If it needs to be understood by the user, it is documented. That removes all doubt. > >> All Swedish citizens (and Companies) get a personal number: > >> "YYMMDD-XXXX" where YYMMDD is birthdate, and XXXX makes > >> the number unique. > > >> We have elderly people that get advertisement for baby stuff > >> after they reach 100+, since year is only two numbers. > > > Depending on the dental care in Sweden they may be ready for baby food > > again. ;-) > > >> The system copes with that, since your number changes to > >> "YYMMDD+XXXX" once you'r past 100, but it is rarely used > >> and many/most applications does not allow > >> you to feed in the "+" sign. > > > So their systems have a "negative" attitude towards age? > > No, just ignorance. I guess this didn't translate into Swedish very well... it was a joke. RickArticle: 149332
If you have generated the chipscope cores using coregen then the path to the edif files needs to be added to your ISE project. Otherwise if you have created a chipscope project in ISE then the edif files will be created before the design is synthesised and p&r. Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149333
On Oct 16, 10:55 am, Vips <thevipulsi...@gmail.com> wrote: > On Oct 15, 11:48 pm, steve ravet <steve.ra...@gmail.com> wrote: > > > > > Vipul, this is a pretty standard and common problem in FPGAs. You > > can't independently synchronize a bunch of control signals when > > crossing clock domains. They'll all cross individually OK, but > > there's no guarantee that they'll all end up in the same clock phase > > on the other side, especially if the destination domain is faster than > > the source domain. You need to have a send/receive handshake that > > consists of a single signal, synchronized in both directions. > > > The control signals that need to cross are flopped directly in the > > receiving domain without any synchronizers. The handshake signal is > > double flop synchronized and used as an enable on the flops that > > receive the control signals. By the time the double flopped sync > > signals make it through to the flop enable, the other control signals > > are stable and can be safely latched. > > > An async FIFO is another possibility. > > > Do a search on clock domain crossing and you'll come up with plenty of > > answers. > > > --steve > > > On Oct 13, 1:48 am, jas <thejaspr...@gmail.com> wrote: > > > > Hi Everyone, > > > > I am designing a system where I am interfacing a Motorolla processor > > > in my system for read and write data. This processor is on the board > > > where my fpga will interact with it. The processor is the master mode > > > always and the salave is my interface design and the fpga. > > > > The motoroll Processor will have LBC Local bus controller signals > > > will > > > be comunicating to my interface inside the FPGA. > > > > The processor can run at configurable clock of 33 MHz to 133 MHz. The > > > address bus is 24 Bits and tye data bus is 32 bits. > > > > I have to design an interface where the control signals from the > > > processor to my interface will be > > > > 1. LALE Used for latching address and making is two distict phases as > > > data and address phase. The LALE when HIgh is an Address phase and > > > when Address is low it is Data phase. (From processor to Design ) > > > 2. LWE it is a read and write signal single bit active low. (From > > > processor to Design ) > > > 3. LOE Output enable active low (From processor to Design ) > > > 4. LCS is active low signal from processor to my interface. It is > > > used > > > for selecting the chip/slave chip select > > > 5. LA address 24 bits ( From processor to Design ) > > > 6. LAD data 32 bits (Bidirectional) > > > > I am thinking about runing my design at 300 Mhx 3X then the processor > > > LBC clock . The LBC clock is not coming from the processor to my > > > interface in fpga . So in my Interface i dont have the reference > > > clock > > > from the processor and all the above mentioned signals are from > > > Processor to my design except LAD which is bidirectional . > > > > I am using 2 flop synchronisers for the control signals and MUX-Latch > > > model for data latching and synchronization across the cock domain . > > > > My Confusion is that when we have multiple control signal passing the > > > clock domain . Can we synchronize with 2 flops all the control > > > signals. > > > > Shall we use some glue logic to make sure we pass and synchronise > > > only > > > one control signal across the domain and later use this synchronous > > > signal value to select the mux-latch of other control signals that > > > are > > > input to a latch and sampled when we get the synchronized signal. > > > > In the scenario like this has anyone used multiple control signals to > > > pass the clock domain throgh individual 2 flop synchronizers for each > > > control lines. > > > > I am using 3X clock in the destination clock domain and has ample > > > time > > > to sample the signal in the interface block. > > > > Any suggestion ideas will be highly appreciated > > > > Thanks > > > > Vipul > > Hi Rick /Steve > > Thanks for your reply. The processor might send continuous data and i > don't have the control for the processor. In handshake mechanism the > processor might have to see my response then send the next data. Rick > you are right that we can use LOE for read case to latch data in the > LAD bus. All signals are mutually exclusive and it is typically like a > async memory interface. > > I have googled but did dot get any good relevant text on this that > talk about async memory interface . All talk about CDC issues and > control and data bus synchronization. I am looking for some thing on > async memory interface or something that is async and have to be > synchronized at the interface to be used by other logic in the design. > I will look into it the way you both have advised. > > Thanks > > Vipul I doubt that you will find much on how to design your circuit. This is very basic and you just need to understand the timing and function of the control signals. Just keep in mind that many signals won't need to be registered at all if they are stable at the time they are needed and only control signals need to be double registered for metastability. If you need any real help, drop me an email and send me details of your bus and FPGA interface. RickArticle: 149334
On Oct 17, 9:51 am, "Sink0" <sink00@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > The idea of using the uC or DSP is considered at some cases but not always. > The processin requiriments of every node of the network are completely > different. Some nodes might just need a simple 16 bits uC or maybe a 300Mhz > DSP. I cannot say that it would be a general solution. > > About the price. Yes i still have to evaluate the price of the Flash+FPGA > compared to the FPGA with internal Flash. About using an external PLL, i > really cant answer as i never used one for clock generation. I dont know if > i can find an external PLL that can generate 2 outputs, and one shifted 90 > degrees from the other. How about the skew problem between both outputs. > The clock lines would have to be very well designed no? > > Any comment about one Cyclone I is getting discontinued? In general, you don't need to worry about FPGA or CPLD parts being discontinued for many years. For example, if you really need them, Xilinx still ships parts they originally built 15 years ago! The other companies are the same. They just get more expensive after 8 or 10 years. If price and size is important I would recommend that you look at the XP Flash based FPGA family from Lattice. Yes, Lattice is not Atmel, but you said you wanted to optimize the design, not the development process. Pick one. You can get 3 kLUTs in a 100 pin QFP for under $10 in quantity, LFXP3C-3TN100C. Mouser typically has stock of a couple hundred or so. Otherwise it is 8 week delivery. RickArticle: 149335
Dnia 17.10.2010 maxascent <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote: > If you have generated the chipscope cores using coregen then the path to > the edif files needs to be added to your ISE project. Otherwise if you have > created a chipscope project in ISE then the edif files will be created > before the design is synthesised and p&r. Thanks, I've just stated, that I have to add the xco files generated by MIG: user_design/par/icon_coregen.xco user_design/par/via_coregen.xco user_design/par/ila_coregen.xco This process builds the icon.ngc, via.ngc and ila.ngc files, which I can add to my design to compile it successfully. -- Thanks, WZabArticle: 149336
> I don't know what "fast" means in engineering terms, so I can't say "fast" probably isn't an issue, provided I can offload the hard work to fpga logic, which it looks like this will let me do. > Check out the Lattice XP and XP2 parts and their 32 or 8 bit micros. These look interesting. I've always built programmers from scratch for microcontrollers, - is that sort of thing possible with these, or would purchasing just one Lattice XP chip be no use without full development kit(s)? How steep is the learning curve? For example, If I wanted to write a "flashing LED" program in C, and want to get it running on that FPGA in a soft-CPU, how long would it take to figure out and get working?Article: 149337
> "fast" probably isn't an issue, provided I can... By "fast" I mean memory mapped IO or DMA or something rather than an SPI link between an FPGA and a microcontroller...Article: 149338
> >In general, you don't need to worry about FPGA or CPLD parts being >discontinued for many years. For example, if you really need them, >Xilinx still ships parts they originally built 15 years ago! The >other companies are the same. They just get more expensive after 8 or >10 years. > >If price and size is important I would recommend that you look at the >XP Flash based FPGA family from Lattice. Yes, Lattice is not Atmel, >but you said you wanted to optimize the design, not the development >process. Pick one. > >You can get 3 kLUTs in a 100 pin QFP for under $10 in quantity, >LFXP3C-3TN100C. Mouser typically has stock of a couple hundred or >so. Otherwise it is 8 week delivery. > >Rick > Yea. I will take a look on that! Thank you for your advice! That might help a lot. But just wondering, why you wrote that Lattice is not Atmel? Did not understand that. Any other sugestions are still apreciated. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149339
"Oliver Mattos" <omattos@gmail.com> wrote in message news:11e5aa7b-def8-44a5-81b3-ab627929f61c@a36g2000yqc.googlegroups.com... > >> "fast" probably isn't an issue, provided I can... > > By "fast" I mean memory mapped IO or DMA or something rather than an > SPI link between an FPGA and a microcontroller... Any FPGA will have a fast set of I/O which will interface with virtually any micro. It just depends on the address and data widths you need, plus control signals.Article: 149340
> >These look interesting. I've always built programmers from scratch >for microcontrollers, - is that sort of thing possible with these, or >would purchasing just one Lattice XP chip be no use without full >development kit(s)? > >How steep is the learning curve? For example, If I wanted to write a >"flashing LED" program in C, and want to get it running on that FPGA >in a soft-CPU, how long would it take to figure out and get working? > > As far as i know you dont need to use Lattice's free soft processor on a Lattice FPGA. You could buy a FPGA kit from Digilent and use lattice processor on it. You could also buy a kit from e-bay. I am sure you can find everythink you need for under 100 dollars incluiding some sort of download cable. But the how fast question was aimed on the processor. How much processing power you need? And learning FPGA is not difficult as long you have some basic logic design background. You just need to learn some HDL language. As you like C i would recomend you Verilog. Before trying to use the soft processor i would recomend you spend a week just with the FPGA. Make yourself some simple design. After that go for the processor. As far as i remember to use the Lattice processor you are going to use the Eclipse. But i dont think is much more complicated than any other processor. If you are a good C programmer you can program any processor in one day. Cya --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149341
>On Oct 13, 6:50=A0pm, "PaulHam" ><hamsdeji@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: >> >> It's unbelievable and different from theasmi_paralleldata sheet. >> >> The data sheet shows that only 3 us is needed after single byte write >> >> operation. >> >> So, I'd like to get some advice here what makes unexpected result. >> >> The signals I giveasmi_parallelip core, the write/wren/addr/data are >> >> exact. >> >> >I'd check the data sheet for whatever flash device you're using, that >> will >> >be what determines the delay (mostly), not the core. >> >> >Nial. >> >> Thanks for checking my question. >> You mean, the Serial Configuration Device determines the speed of writing >> ? >> >> Paul. >> >> --------------------------------------- =A0 =A0 =A0 =A0 >> Posted throughhttp://www.FPGARelated.com > >Hi Paul, > >Take note that the waveforms in the ALTASMI_PARALLEL user guide do not >reflect the real time operation. Just like Nial said, the speed of >writing depends on the flash device used. > >When the IP receives any write command (either byte write or page >write), it will follow this procedure: >- Stage 1: read status register >- Stage 2: issue write enable command >- Stage 3: write data >- Stage 4: read busy bit from status register to end operation >If you are using single byte write, only 1 byte of data is sent at >stage 3 and repeat the process for the subsequent bytes. When page >write is used, the whole bunch of data can be transferred one shot in >stage 3. So if you are using single byte write to write a bunch of >data, it will definitely take longer time. The single byte write >shouldn't take longer time than page write if only 1 byte of data is >transferred. As for the 300us delay, is it the time taken to write a >bunch of data or you are just transferring a single byte? > Thanks for your concern. I understand 4 step stage you said. But I compare the only single byte "busy delay" with page(bunch) write. Every single byte write makes 300us "busy delay". So entirely, a single byte write takes (300us X 256)us differently with 30us of page write. As you said, single byte write shouldnot take longer time than page write. However, I found that they are quitely different. Actually, I use the EPCS4 as serial configuration device. But I think EPCS4,16,64,... have almost same performance except of flash memory size. I'm trying to find the missing point at that project today. But I have a confidence due to your help & advice. Thanks Paul --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149342
On Oct 17, 5:48=A0pm, Oliver Mattos <omat...@gmail.com> wrote: > > I don't know what "fast" means in engineering terms, so I can't say > > "fast" probably isn't an issue, provided I can offload the hard work > to fpga logic, which it looks like this will let me do. > > > Check out the Lattice XP and XP2 parts and their 32 or 8 bit micros. > > These look interesting. =A0I've always built programmers from scratch > for microcontrollers, - is that sort of thing possible with these, or > would purchasing just one Lattice XP chip be no use without full > development kit(s)? > > How steep is the learning curve? =A0For example, If I wanted to write a > "flashing LED" program in C, and want to get it running on that FPGA > in a soft-CPU, how long would it take to figure out and get working? I gave advice to someone here once who was a programmer wanting to do FPGA work in VHDL. He basically did everything different from the way I would have done it and made it all work, so there is more than one way to skin a cat. For example, I would write a flashing LED program (as you are thinking). He wanted to write a "Hello World" program... and did. I can't say how hard it is to use the CPU core as I have not done that yet. I do know that you don't have to recompile the FPGA code to change the program in the CPU. You can update the bitstream with new data in the on chip RAM blocks using a utility. If your program is external, then you don't even need to do that. My LFXP3C device takes around 15 to 20 seconds to reload via USB JTAG cable. I haven't seen a development board that doesn't use JTAG to configure the FPGA. You can either load directly to the RAM or your can burn it into the Flash. Going to RAM might be noticeably faster, I haven't tried it. As to the development kit, you can typically get free ones from the FPGA companies, but without hardware tools. In the case of Lattice, it may be without a simulator but that may not be true anymore. I find a simulator essential, so I paid about $900 for the low end tool with a simulator, no complaints. You can buy tools from others, but they universally need the "back end" tools from the FPGA company, the place and route tool and bit stream generator. Most companies don't release full info on the internal tools so no one else can provide a full tool set without these parts from the manufacturer. BTW, in the vein of doing things differently from software folks, I would do most designs fully in the FPGA without a CPU unless I had to save space. A stored program CPU can save a lot of logic in an FPGA. But software is a lot harder to debug in my opinion. RickArticle: 149343
On Oct 17, 6:07=A0pm, "Sink0" <sink00@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > >In general, you don't need to worry about FPGA or CPLD parts being > >discontinued for many years. =A0For example, if you really need them, > >Xilinx still ships parts they originally built 15 years ago! =A0The > >other companies are the same. =A0They just get more expensive after 8 or > >10 years. > > >If price and size is important I would recommend that you look at the > >XP Flash based FPGA family from Lattice. =A0Yes, Lattice is not Atmel, > >but you said you wanted to optimize the design, not the development > >process. =A0Pick one. > > >You can get 3 kLUTs in a 100 pin QFP for under $10 in quantity, > >LFXP3C-3TN100C. =A0Mouser typically has stock of a couple hundred or > >so. =A0Otherwise it is 8 week delivery. > > >Rick > > Yea. I will take a look on that! Thank you for your advice! That might he= lp > a lot. But just wondering, why you wrote that Lattice is not Atmel? Did n= ot > understand that. > > Any other sugestions are still apreciated. =A0 =A0 =A0 =A0 Opps, I meant Altera... you said you wanted to stick with Altera and Lattice is not Altera. BTW, even lower cost than the Lattice XP parts is the Silicon Blue iCE65 part line. The smallest parts are around $2-$3 and also come in 100 TQFP or even smaller chip scale packages. RickArticle: 149344
rickman wrote: > BTW, even lower cost than the Lattice XP parts is the Silicon Blue > iCE65 part line. The smallest parts are around $2-$3 and also come in > 100 TQFP or even smaller chip scale packages. Sounds interesting, but the shop at "buy online" shows only "call" for the price for all parts, and "call" for "quantity avail." for most parts. Are you sure you can really buy it in small quantities and less than some months delivery time? -- Frank Buss, http://www.frank-buss.de piano and more: http://www.youtube.com/user/frankbussArticle: 149345
I have checked this before. A guy from edaboard gave me this advice but they just got PLL with BGA package. About why i dont want to use BGA? Becouse is much more expensive for assemble. Well i cant say about other countries. But in Brazil it is. But thank you for the advice. And just for information. This is not intended for a comercial product in a low range time. Its for R&D purposes. Cya --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149346
Hello, For one of my project, I want to send data from zigbee to FPGA and vice versa. Can this possible? If anybody have any idea, please help me.Article: 149347
>Hello, > >For one of my project, I want to send data from zigbee to FPGA and >vice versa. Can this possible? >If anybody have any idea, please help me. > Zigbee is a wireless interface and not a device. Just to understand. You got a ZigBee module and a FPGA and you want to make the FPGA talk with the module (using coper and not wireless) right? If yes. First you need to figure out whats the interface of you module. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149348
Oliver Mattos <omattos@gmail.com> writes: > Does any company sell a microprocessor what has a few thousand logic > elements of FPGA "on the side", which can interface fast with the > microprocessor, for example through shared memory. Ideally this would > be cheap (ie. tens of dollars rather than hundreds of dollars), and > easy to use (I don't want to have to be defining my own DMA controller > or something...) Yes, Actel Smartfusion. It's a hard ARM Cortex M3 with hard basic peripherals and some programmable logic around that. Also, single 3.3V power supply. SW tools are free from Actel or you can buy from IAR or Keil. Eval kit is $99. I had a visit from Actel recently, SmartFusion seems very interesting, but I've never designed anything with their FPGAs. It's also interesting to note that Xilinx is going to do the same thing in their 7 series, hard ARM with hard peripherals ready to go, programmable logic around it.Article: 149349
Hi all, I'm using ISE 12.3 to implement a design. I generate a verilog netlist which contains cells of the simprim library. I used this command line to do that : netgen -w -ecn conformal -ne -mhf clockbuf I obtained 2 verilog files : glbl.v & clockbuf_ecn.v Then I take this netlist and do some changes on it ( split it in parts for example ). But if I start a new project whith the new files, ise can't find simprims library. I tried also to start another new project with these 2 files( with nochanges), and I included all verilog files of used cells from the simprim library. and here is what I obtain : ERROR:HDLCompilers:244 - "../../work/xilinx/opt1/ISE_DS/ISE/verilog/src/simprims/X_OBUF.v" line 36 Name 'glbl.GTS' could not be resolved ERROR:HDLCompilers:185 - "../../work/xilinx/opt1/ISE_DS/ISE/verilog/src/simprims/X_OBUF.v" line 36 Illegal right hand side of continuous assign ERROR:HDLCompilers:244 - "../../work/xilinx/opt1/ISE_DS/ISE/verilog/src/simprims/X_FF.v" line 42 Name 'glbl.GSR' could not be resolved ERROR:HDLCompilers:185 - "../../work/xilinx/opt1/ISE_DS/ISE/verilog/src/simprims/X_FF.v" line 42 Illegal right hand side of continuous assign ERROR:HDLCompilers:244 - "../../work/xilinx/opt1/ISE_DS/ISE/verilog/src/simprims/X_BUFGMUX.v" line 46 Name 'glbl.GSR' could not be resolved ERROR:HDLCompilers:185 - "../../work/xilinx/opt1/ISE_DS/ISE/verilog/src/simprims/X_BUFGMUX.v" line 46 Illegal right hand side of continuous assign Can anyone explain me what to do? thx for your help. --------------------------------------- Posted through http://www.FPGARelated.com
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