Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
On Oct 12, 4:09=A0am, "parvathi69" <parvathi69@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > Hi all, > > I am new FPGA. I have input data stored in a txt file. i have to read dat= a > from file to FPGA for further processing. How do i store this value in to > FPGA memory. > > Please help me. > > Thanks in advance =A0 =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com If it were me, I would use an embedded processor: NIOS, MicroBlaze, etc. Simple enough to write a program to read the data and write it to internal memory. Then the emb-proc can start up whatever FPGA hardware there is to process the data. RKArticle: 149276
On Oct 11, 12:16=A0pm, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > Hi, > I have a weird problem with my design. I am using xilinx 12.1 for its > synthesis and implementation. > The problem is that when i generate my bitstream with a chipscope core > inserted in the design and program my FPGA, programming fails saying that > "DONE did not go high" whereas when i take out the chipscope core or some > signals from the core, programming succeeds but after that my JTAG stops > working. If i try ti initialize JTAG chain in iMPACT it asks me whether i > have a BSDL or BIT file for this device or if i try to run chipscope,it > also gives a warning and doesn't start. I checked the JTAG voltages and > they were fine. > > Rarely does my design work, so, i am kind of stuck here as i cannot debug > my system altogether. Is there something wrong with the Bit file or my us= b > drivers? I tried reinstalling the drivers but didn't work. Then i > reinstalled xilinx 12.1,still same problem. > > Does it happen because of the size of the FPGA and the complexity of the > logic we are inserting in it ? I mean that if the FPGA is not big enough = to > hold the logic and it's a very tigh fit, can it lead to such behaviour ? > > Regards > SalimBaba =A0 =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com I would guess that there's something wrong with your ILA. RKArticle: 149277
On 10/12/2010 4:09 AM, parvathi69 wrote: > Hi all, > > I am new FPGA. I have input data stored in a txt file. i have to read data > from file to FPGA for further processing. How do i store this value in to > FPGA memory. > > Please help me. > > Thanks in advance > > --------------------------------------- > Posted through http://www.FPGARelated.com When? If you're looking to do so at compile time, you can use the std.textio library in an initialization function for the RAM. If you're looking to do so at run time, you need some means of getting the data from point A to point B. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 149278
On 12 Okt., 13:09, "parvathi69" <parvathi69@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > Hi all, > > I am new FPGA. I have input data stored in a txt file. i have to read dat= a > from file to FPGA for further processing. How do i store this value in to > FPGA memory. > > Please help me. > > Thanks in advance =A0 =A0 =A0 =A0 =A0 FPGA is all about hardware. The word "file" does not mean a lot in that context. What hardware is the file stored on? How it is accessible? If the file is on a compact flash you could use system ace to read it. If it is on a usb device you need an usb core to connect to the device. If it is accessible by TCP/IP you need an ethernet core or an RS232 UART and something you can talk PPP to. and so on and so on....Article: 149279
On Oct 13, 12:45=A0pm, d_s_klein <d_s_kl...@yahoo.com> wrote: > On Oct 13, 5:38=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrote: > > > > > > > > > > > A new release of FPGAOptim[1] is available. =A0Highlights of this > > release include: > > > =A0* Support for 12.x toolchain > > =A0* Support for S6/V6 devices > > =A0* EDIF and NGC netlists, so the tool can be used earlier in the > > =A0 =A0design process. =A0Especially useful when you are "overmapped" a= nd > > =A0 =A0don't know why :) > > =A0* More flexible column headings which will support future devices > > =A0 =A0much more easily. > > > (BTW, our website moved around, so those of you who have downloaded > > before should be receiving an email with a new link to the installer > > shortly) > > > Cheers, > > Martin > > > [1]http://www.conekt.co.uk/capabilities/49-fpga-optim > > > -- > > martin.j.thomp...@trw.com > > TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp:/= /www.conekt.co.uk/capabilities/39-electronic-hardware > > Just my $.02 - I would like to see a Linux version. =A0I am so tired of > the "looks great, who cares if it works" fluffiness of 'doze. > > RK Can you not do the same thing with planAhead? It has many netlist searching and display features. -- AmalArticle: 149280
The project has top level in ISE and it includes a PPC subsystem. The problem seems to be with the latest MPMC core, which, at least in DDR2 mode, instantiates IOs in the source code. There is a Xilinx Answer Record for this exact problem, but with regards to ISE11. However, the proposed solution doesn't work. Has anyone experienced this and found a workaround? The project was originally designed in 8.2 for V4FX (albeit it used much older MPMC with DDR1, not DDR2), then upgraded to version 10.x and now I am trying to move it to V5 platform. This is to say that there shouldn't be anything fundamentally wrong with the project itself. In fact it originally compiled in 12.2 after the upgrade, even after I had upgraded all the EDK cores, but then stopped compiling after I had cleaned all the generated files in ISE... And I've just tried the same project in ISE/EDK12.3 and got the same result. Thanks, /MikhailArticle: 149281
Hi all,
I have a very simple FSM which should drive some output signals of an
external RAM. The problem that I have comes with handling the data bus
which can be input as well as output... I am not too sure how I can handle
best this case in my FSM. The problem comes from the following line:
v.sram_data <= io_sram_data;
Obviously, the left hand side is a variable while the right hand side is
a signal. Is there a "nice" way how to handle inout signals in a FSM as
the one I have?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sram_fsm is
port (
clk : in std_logic;
reset : in std_logic;
out_sram_rd : out std_logic;
out_sram_wr : out std_logic;
out_sram_addr : out std_logic_vector(3 downto 0);
io_sram_data : inout std_logic_vector(7 downto 0)
);
end;
architecture Behavioral of sram_fsm is
type state_type is (wr_init, wr_data, rd_init, rd_data);
type reg_type is record
state : state_type;
sram_data : std_logic_vector(7 downto 0);
sram_addr : std_logic_vector(3 downto 0);
sram_rd : std_logic;
sram_wr : std_logic;
end record;
signal r, rin : reg_type;
begin
comb : process (r)
variable v : reg_type;
begin
v := r;
case r.state is
when wr_init =>
v.sram_data := "00000000";
v.sram_addr := "0000";
v.sram_rd := '0';
v.sram_wr := '0';
v.state := wr_data;
when wr_data =>
io_sram_data <= "00001000";
v.sram_wr := '1';
v.state := rd_init;
when rd_init =>
v.sram_addr := "0000";
v.sram_rd := '1';
v.sram_wr := '0';
v.state := wr_data;
when rd_data =>
v.sram_data <= io_sram_data;
v.state := wr_init;
end case;
out_sram_addr <= v.sram_addr;
out_sram_rd <= v.sram_rd;
out_sram_wr <= v.sram_wr;
rin <= v;
end process;
regs : process (reset, clk)
begin
if reset = '0' then
r.state <= wr_init;
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end Behavioral;
Many thanks for your inputs!
Article: 149282On Oct 13, 8:33=A0pm, Rob Tercher <R...@yahoo.com> wrote: > Hi all, > > I have a very simple FSM which should drive some output signals of an > external RAM. The problem that I have comes with handling the data bus > which can be input as well as output... I am not too sure how I can handl= e > best this case in my FSM. The problem comes from the following line: > > v.sram_data <=3D io_sram_data; > > Obviously, the left hand side is a variable while the right hand side is > a signal. Is there a "nice" way how to handle inout signals in a FSM as > the one I have? > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > > entity sram_fsm is > =A0 =A0port ( > =A0 =A0 =A0clk =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : in std_logic= ; > =A0 =A0 =A0reset =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : in std_logic; > =A0 =A0 =A0 out_sram_rd =A0 =A0 =A0 =A0 =A0 : out std_logic; > =A0 =A0 =A0 out_sram_wr =A0 =A0 =A0 =A0 =A0 : out std_logic; > =A0 =A0 =A0out_sram_addr =A0 =A0 =A0 : out std_logic_vector(3 downto 0); > =A0 =A0 =A0io_sram_data =A0 =A0 =A0 =A0: inout std_logic_vector(7 downto = 0) > > =A0 =A0); > end; > > architecture Behavioral of sram_fsm is > > =A0 =A0 type state_type is (wr_init, wr_data, rd_init, rd_data); > > =A0 =A0 type reg_type is record > =A0 =A0 =A0 state =A0 =A0 =A0 : state_type; > =A0 =A0 =A0 =A0sram_data =A0 : std_logic_vector(7 downto 0); > =A0 =A0 =A0 sram_addr =A0 : std_logic_vector(3 downto 0); > =A0 =A0 =A0 sram_rd =A0 =A0 : std_logic; > =A0 =A0 =A0 =A0sram_wr =A0 =A0 : std_logic; > =A0 =A0 end record; > > =A0 =A0 =A0signal r, rin : reg_type; > > begin > > =A0 =A0 comb : process (r) > =A0 =A0 variable v : reg_type; > =A0 =A0 =A0begin > =A0 =A0 =A0 =A0v :=3D r; > > =A0 =A0 =A0 =A0case r.state is > =A0 =A0 =A0 =A0 =A0when wr_init =3D> > =A0 =A0 =A0 =A0 =A0 =A0 v.sram_data =A0 =A0:=3D "00000000"; > =A0 =A0 =A0 =A0 =A0 =A0 =A0v.sram_addr =A0 =A0:=3D "0000"; > =A0 =A0 =A0 =A0 =A0 =A0 =A0v.sram_rd =A0 =A0 =A0:=3D '0'; > =A0 =A0 =A0 =A0 =A0 =A0 =A0v.sram_wr =A0 =A0 =A0:=3D '0'; > =A0 =A0 =A0 =A0 =A0 =A0 =A0v.state =A0 =A0 =A0 =A0:=3D wr_data; > =A0 =A0 =A0 =A0 =A0 =A0 when wr_data =3D> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 io_sram_data <=3D "00001000"; > =A0 =A0 =A0 =A0 =A0 v.sram_wr =A0 =A0 =A0:=3D '1'; > =A0 =A0 =A0 =A0 =A0 =A0 =A0v.state =A0 =A0 =A0 =A0:=3D rd_init; > =A0 =A0 =A0 =A0 =A0when rd_init =3D> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 v.sram_addr =A0 :=3D "0000"; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 v.sram_rd =A0 =A0 :=3D '1'; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 v.sram_wr =A0 =A0 :=3D '0'; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 v.state =A0 =A0 =A0 :=3D wr_data; > =A0 =A0 =A0 =A0 =A0when rd_data =3D> > =A0 =A0 =A0 =A0 =A0 =A0 =A0v.sram_data <=3D io_sram_data; > =A0 =A0 =A0 =A0 =A0 =A0v.state =A0 =A0 =A0 :=3D wr_init; > =A0 =A0 =A0 =A0 end case; > > =A0 =A0 =A0out_sram_addr <=3D v.sram_addr; > =A0 =A0 =A0out_sram_rd <=3D v.sram_rd; > =A0 =A0 =A0out_sram_wr <=3D v.sram_wr; > > =A0 =A0 =A0 rin <=3D v; > > =A0 =A0 end process; > > =A0 =A0 =A0regs : process (reset, clk) > =A0 =A0 =A0begin > =A0 =A0 =A0 =A0if reset =3D '0' then > =A0 =A0 =A0 =A0 =A0 =A0r.state <=3D wr_init; > =A0 =A0 =A0 =A0elsif rising_edge(clk) then > =A0 =A0 =A0 =A0 =A0 r <=3D rin; > =A0 =A0 =A0 =A0end if; > =A0 =A0 end process; > > end Behavioral; > > Many thanks for your inputs! One way... Add the statement io_sram_data <=3D (others =3D> 'Z')' as a default statement at the begining of your process. Another way... 1. Define some internal signals signal io_sram_data_int: std_logic_vector(io_sram_data'range); signal Output_Enable: std_ulogic; 2. Within your state machine, drive the signal io_sram_data_int rather than io_sram_data; 3. Add the following io_sram_data <=3D io_sram_data_int when (Output_Enable =3D '1') else (others =3D> 'Z'); where you then have to define the logic for when Output_Enable where it is active when you want to drive it I'd also suggest not using combinatorial processes, use a synchronous process and concurrent statements. Kevin JenningsArticle: 149283
On Oct 13, 6:50=A0pm, "PaulHam" <hamsdeji@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > >> It's unbelievable and different from theasmi_paralleldata sheet. > >> The data sheet shows that only 3 us is needed after single byte write > >> operation. > >> So, I'd like to get some advice here what makes unexpected result. > >> The signals I giveasmi_parallelip core, the write/wren/addr/data are > >> exact. > > >I'd check the data sheet for whatever flash device you're using, that > will > >be what determines the delay (mostly), not the core. > > >Nial. > > Thanks for checking my question. > You mean, the Serial Configuration Device determines the speed of writing > ? > > Paul. > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com Hi Paul, Take note that the waveforms in the ALTASMI_PARALLEL user guide do not reflect the real time operation. Just like Nial said, the speed of writing depends on the flash device used. When the IP receives any write command (either byte write or page write), it will follow this procedure: - Stage 1: read status register - Stage 2: issue write enable command - Stage 3: write data - Stage 4: read busy bit from status register to end operation If you are using single byte write, only 1 byte of data is sent at stage 3 and repeat the process for the subsequent bytes. When page write is used, the whole bunch of data can be transferred one shot in stage 3. So if you are using single byte write to write a bunch of data, it will definitely take longer time. The single byte write shouldn't take longer time than page write if only 1 byte of data is transferred. As for the 300us delay, is it the time taken to write a bunch of data or you are just transferring a single byte?Article: 149284
On Oct 6, 12:06=A0am, rickman <gnu...@gmail.com> wrote: > On Oct 5, 5:50 pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > On Oct 5, 12:43 pm, rickman <gnu...@gmail.com> wrote: > > > > I am listening to the Xilinx webinar on partial reconfiguration and > > > they say the Artix 7 will be the first "spartan" type device that wil= l > > > be supported under the ISE software for partial reconfiguration. > > > Anyone heard when the Artix 7 devices are supposed to be in > > > production? =A0Are we talking about a practical time frame such as 6 = to > > > 9 months or is it being stated as a year or more? =A0Or have they onl= y > > > talked about when they will be shipping "samples"? =A0I know there ca= n > > > be quite a difference. > > > There is no announced date for Artix-7 device availability at this > > time. > > Ok, so if I understand what was said in the presentation today, there > is no support for partial reconfiguration in any of the available > Spartan devices, right? =A0I remember looking into PR for quite a while > some years back and had been told that Xilinx "was committed" to > supporting PR in Spartan parts. =A0That was literally 8 years ago. =A0A > lot of the presentation talked to the cost savings that was possible > using PR. =A0But that only makes sense to me if it can be used with low > cost parts. =A0Reducing the cost of using a more expensive part by using > a complex process is a poor substitute to just using a part that costs > less. =A0But if I can use the less expensive part and cut my costs > further by using PR, that can make a number of projects practical that > otherwise wouldn't be. > > I don't even want to do "dynamic" PR, I just want to have the > flexibility of configuring the modules when I configure the full part > initially. =A0Would that be "static" PR? =A0This makes a huge difference > in the exact scenario they described for a product with multiple > interface modules, but the number of possible modules larger than just > three. =A0Instead of a 100,000 LUT Spartan, I would be able to use a > 10,000 LUT device and have room to spare. =A0This could be such a > enabler of projects. > > Rick You can sort of do what you describe now with a Spartan 3E and multi- boot. It's obviously not the same as partial reconfiguration, but with a bit of clever design, it can serve a similar purpose. It can also be entirely implemented in-chip. I have a little business-card sized demo board from an Avnet rep that does this. It boots up with a simple animation, but when you press a button, it turns into an electronic die (simulates rolling dice) While nifty, there are some real limitations, though. For one, you need external RAM if you want the two images to be able to pass data to each other - since all of the internal block RAM will get reinitialized. For another, there is a fairly significant delay where the FPGA is "dead" - meaning you need to be careful about when the switchover occurs.Article: 149285
On Oct 13, 11:12 pm, radarman <jsham...@gmail.com> wrote: > On Oct 6, 12:06 am, rickman <gnu...@gmail.com> wrote: > > > > > On Oct 5, 5:50 pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > On Oct 5, 12:43 pm, rickman <gnu...@gmail.com> wrote: > > > > > I am listening to the Xilinx webinar on partial reconfiguration and > > > > they say the Artix 7 will be the first "spartan" type device that will > > > > be supported under the ISE software for partial reconfiguration. > > > > Anyone heard when the Artix 7 devices are supposed to be in > > > > production? Are we talking about a practical time frame such as 6 to > > > > 9 months or is it being stated as a year or more? Or have they only > > > > talked about when they will be shipping "samples"? I know there can > > > > be quite a difference. > > > > There is no announced date for Artix-7 device availability at this > > > time. > > > Ok, so if I understand what was said in the presentation today, there > > is no support for partial reconfiguration in any of the available > > Spartan devices, right? I remember looking into PR for quite a while > > some years back and had been told that Xilinx "was committed" to > > supporting PR in Spartan parts. That was literally 8 years ago. A > > lot of the presentation talked to the cost savings that was possible > > using PR. But that only makes sense to me if it can be used with low > > cost parts. Reducing the cost of using a more expensive part by using > > a complex process is a poor substitute to just using a part that costs > > less. But if I can use the less expensive part and cut my costs > > further by using PR, that can make a number of projects practical that > > otherwise wouldn't be. > > > I don't even want to do "dynamic" PR, I just want to have the > > flexibility of configuring the modules when I configure the full part > > initially. Would that be "static" PR? This makes a huge difference > > in the exact scenario they described for a product with multiple > > interface modules, but the number of possible modules larger than just > > three. Instead of a 100,000 LUT Spartan, I would be able to use a > > 10,000 LUT device and have room to spare. This could be such a > > enabler of projects. > > > Rick > > You can sort of do what you describe now with a Spartan 3E and multi- > boot. It's obviously not the same as partial reconfiguration, but with > a bit of clever design, it can serve a similar purpose. It can also be > entirely implemented in-chip. > I have a little business-card sized demo board from an Avnet rep that > does this. It boots up with a simple animation, but when you press a > button, it turns into an electronic die (simulates rolling dice) > > While nifty, there are some real limitations, though. For one, you > need external RAM if you want the two images to be able to pass data > to each other - since all of the internal block RAM will get > reinitialized. For another, there is a fairly significant delay where > the FPGA is "dead" - meaning you need to be careful about when the > switchover occurs. Some eight years ago I built a DSP board which used small daughter cards for I/O. The idea was to build the minimum amount of hardware possible and to do the bulk of the design in the FPGA. A variety of different module types would be supported by the CPU being able to poll the daughter cards at boot up to determine their type and using partial configuration to load in the appropriate module. This didn't even require that it be done while the FPGA was live, just that the modules could be loaded independently. Although I was told that the Spartan could support this and that Xilinx was committed to supporting Spartan PR in the tools, it never happened. So instead I had to configure a unique load for each customer on request. That was not very easy to support. That is basically the "multi-boot" approach. It's ok until the number of permutations gets too large. RickArticle: 149286
hello guys! I 've a question how can i change this istructions in my structural with simple sums and shifts operations? pOut <= CONV_STD_LOGIC_VECTOR((2* CONV_INTEGER(pIn) + 1), bitWidth/2 + 1); pOut <= CONV_STD_LOGIC_VECTOR((2* CONV_INTEGER(pIn)), bitWidth/2 + 1); thank you in advanceArticle: 149287
> Just my $.02 - I would like to see a Linux version. I am so tired of > the "looks great, who cares if it works" fluffiness of 'doze. I don't want to start a flame war but I installed XP on this machine 5 years ago and apart from installing and running a decent anti-virus system (NOD32) it's worked flawlessly. How much time and effort would I have had to spend playing with the OS if I'd been on Linux? I'm not interested in the OS, I just need it to work. :-) Nial.Article: 149288
Amal <akhailtash@gmail.com> writes: > Can you not do the same thing with planAhead? It has many netlist > searching and display features. You may well be able to now - Planahead didn't exist when I first wrote FPGAOptim :) But, how long does planahead take to update a netlist? Many tens of seconds in my experience on a 80% full S3ADSP3400 EDK design, vs about 5 secs for FPGAOptim. Admittedly, I haven't tried Planahead 12.x yet... Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardwareArticle: 149289
On Wed, 13 Oct 2010 19:38:35 -0400, "MM" <mbmsv@yahoo.com> wrote: >The project has top level in ISE and it includes a PPC subsystem. The >problem seems to be with the latest MPMC core, which, at least in DDR2 mode, >instantiates IOs in the source code. There is a Xilinx Answer Record for >this exact problem, but with regards to ISE11. However, the proposed >solution doesn't work. Has anyone experienced this and found a workaround? It might be useful to mention which Answer Record. - BrianArticle: 149290
>hello guys! > >I 've a question how can i change this istructions in my structural with >simple sums and shifts operations? > >pOut <= CONV_STD_LOGIC_VECTOR((2* CONV_INTEGER(pIn) + 1), bitWidth/2 + 1); > >pOut <= CONV_STD_LOGIC_VECTOR((2* CONV_INTEGER(pIn)), bitWidth/2 + 1); > >thank you in advance > What's the problem? Apart from it not using the numeric_std package, of course! Does the synthesis tool actually infer a multiplier? BTW, if this is course homework, kindly go elsewhere... --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149291
"parvathi69" <parvathi69@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote in message news:w9mdneqc-_5r3CnRnZ2dnUVZ_rWdnZ2d@giganews.com... > Hi all, > I am new FPGA. I have input data stored in a txt file. i have to read data > from file to FPGA for further processing. How do i store this value in to > FPGA memory. > Please help me. > Thanks in advance You don't say when, but if it was during debug this is an ideal application for the 1 pin interface... http://www.1pin-interface.com/ Easily driven PC interface to get data in and out of FPGAs. Nial.Article: 149292
Yes, sorry, it's here: http://www.xilinx.com/support/answers/32847.htm /Mikhail "Brian Drummond" <brian_drummond@btconnect.com> wrote in message news:g3mdb6t8pcvphccc7av2roq1icb1u383a6@4ax.com... > On Wed, 13 Oct 2010 19:38:35 -0400, "MM" <mbmsv@yahoo.com> wrote: > >>The project has top level in ISE and it includes a PPC subsystem. The >>problem seems to be with the latest MPMC core, which, at least in DDR2 >>mode, >>instantiates IOs in the source code. There is a Xilinx Answer Record for >>this exact problem, but with regards to ISE11. However, the proposed >>solution doesn't work. Has anyone experienced this and found a workaround? > > It might be useful to mention which Answer Record. > > - Brian >Article: 149293
While I greatly prefer single, clocked processes over separate clocked and combinatorial ones, here is how you can fix what you have: Add io_sram_data to the sensitivity list for your comb process. After the "v := r;" statement, before anything else, insert; io_sram_data <= (others => 'Z'); This does two things. First, it avoids a latch because you had many states where you did not assign io_sram_data, and in your combinatorial process, failing to assign a value to a signal will get you a latch. By making sure you always drive it with something, it will eliminate any chance of a latch. This is just one of the reasons I don't like split combo/ clocked processes. Second, it defaults to driving the output to high-Z, unless you drive it with data when in a specific state(s). Driving the output to Z allows whatever is on the outside of the device to drive it's value, and for your statemachine to see that value on the signal. The synthesis tool will create the tri-state drivers and enables for them. Other reasons I prefer single, clocked process descriptions: It allows you to use local variables and actually "hide" data to keep it local and free from external interference. By keeping local things local, it isolates changes to that local data (state definitions, etc.) from other processes that may depend on it being a certain way you once defined it. I'm not really sure why you used a variable, since you still have to transfer the data to/from external signals to interact with the clocked process. It avoids latches. It avoids splitting reset or clock enable functionality into a separate process from the rest of the logic. It avoids duplicate signal declarations and assignments. It avoids issues with incomplete sensitivity lists. Hope this helps, AndyArticle: 149294
Happy birthday, Bernie! We miss you! Bernie (V. for Victory) Vonderschmitt was born this day back on October 14, 1923. Many FPGA users may not recognize the name anymore but those of us who fortunate enough to have worked with this remarkable human being still fondly remember him. Who was he? Bernie was one of the founders of Xilinx, Inc. and helped shape the early company and its culture and ultimately the semiconductor industry. In an era when newspapers are filled with stories of business failures, Bernie was a beacon and practitioner of free-market principles. He started his career in engineering and science and then, much later in life, became a well-respected business leader-- certainly the gentleman of the electronics industry. During his long life, Bernie helped pioneer a variety of technologies including color television at RCA, commercialization of CMOS logic, co-founding the first FPGA company, and developing the fabless semiconductor business model. Most people would be considered successful with just one such accomplishment. Then again, Bernie waited until age 58 to pursue his MBA and to age 60 to co-found Xilinx. Bernie's influence at Xilinx was obvious and legendary. His organization chart put customers at the top, in the most important position, and the board and the CEO at the bottom. Bernie's intellect was detailed and data driven. After an hours long meeting filled with detailed spreadsheets and tedious presentation foils (it was before the PowerPoint era), Bernie asked the presenter for the source material because he wanted more detail. On business matters, Bernie was infamously frugal. I think he knew the serial number of every dollar spent and parted with company money like beloved children. Despite his frugal reputation, Bernie was personally very generous, funding a variety of charitable projects. Despite his many talents, Bernie was also quite humble and approachable. He freely gave credit to others for the company's success. His management skills won him a prized reputation with investors, who claimed of the early Xilinx that Bernie delivered Vegas-style returns with insurance-company predictability. Yep, they certainly don't make =91em like that anymore! "Xilinx Chairman and respected electronics industry veteran 'Bernie' Vonderschmitt to retire" http://www.xilinx.com/prs_rls/xil_corp/0341bernie.htm "TV Pioneer Still Chipping Away" http://articles.sfgate.com/1998-12-21/business/17739482_1_bernie-vonderschm= itt-tv-sets-rca "Engineering and Entrepreneurial Pioneer, Bernard 'Bernie' Vonderschmitt Passes Away" http://www.rose-hulman.edu/echoes/summer2004/vonderschmitt.htm "Silicon Valley's septuagenarian" http://business.highbeam.com/392705/article-1G1-14570814/silicon-valley-sep= tuagenarian Bernie Vonderschmitt Patents http://www.google.com/patents?q=3Dbernard+vonderschmitt&btnG=3DSearch+Paten= tsArticle: 149295
I am trying to run a Hyperlynx simulation for LVDS in a Spartan 6 FPGA. I would like to use the DCI termination but when I select this model the simulation complains that it cant perform it because it cant model a series resistor at the receiver input. I assume this is something to do with the termination but I am not sure what I am supposed to do. Thanks Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149296
This is a more generic question following up my previous question on translation failing because of the IOBs instantiated in one of the EDK cores. I was wondering if there is a way (short of hacking the core) to either disable IOB instantiation in EDK altogether or vice-versa to disable IOB instantiation in ISE, but only for those pins, which already have IOBs instantiated by EDK. I tried implementing the latter idea by assigning synthesis iob attribute for these pins and setting it to FALSE, but got an INTERNAL_ERROR in XST... I can't believe there is no simple solution... In the past ISE somehow managed to figure this out. I also vaguely remember that at some point long ago I had a similar problem and did something with some of the cores, but can't remember what... In any case latest MPMC core has these IOB instantiations scattered through many files and hacking them all doesn't appear to be a nice solution. Any ideas will be highly appreciated! /MikhailArticle: 149297
On Thu, 14 Oct 2010 10:54:12 -0400, "MM" <mbmsv@yahoo.com> wrote: >Yes, sorry, it's here: >http://www.xilinx.com/support/answers/32847.htm I don't have the exact answer, but after looking at http://www.xilinx.com/support/answers/37204.htm my next move would be to find the 12.x Constraints Guide (cgd.pdf) and look up the "buffer_type" attribute - is there a "none" value for it? Then try adding attribute buffer_type: string; attribute buffer_type of my_sig: signal is "none"; to all the relevant signals - if you can suppress XST's desire to insert buffers on these specific signals you should be good. Alternatively, have there been changes to 12.x's way of handling precompiled cores? If so, there may be messages in the synthesis report hinting why it can't find the precompiled MPMC core, and that it is "black boxing" the core for NGDbuild to deal with. Making XST see the cores is the best answer, but failing that, the "buffer_type" constraints ought to work. This is all the more frustrating because the EDK cores like MPMC are supplied as source, and the only reason they have to be precompiled (thus hiding the buffers from XST) is because the Xilinx tools can't handle VHDL libraries. (versions 6.x to 11, I haven't tested 12 yet) - BrianArticle: 149298
> I don't have the exact answer, but after looking at > http://www.xilinx.com/support/answers/37204.htm > my next move would be to find the 12.x Constraints Guide (cgd.pdf) and > look up > the "buffer_type" attribute - is there a "none" value for it? > > Then try adding > > attribute buffer_type: string; > attribute buffer_type of my_sig: signal is "none"; > > to all the relevant signals - if you can suppress XST's desire to insert > buffers > on these specific signals you should be good. > I tried this: attribute iob: string; attribute iob of Ddr_Ck_N : signal is "FALSE"; attribute iob of Ddr_Ck_P : signal is "FALSE"; attribute iob of Ddr_A : signal is "FALSE"; attribute iob of Ddr_D : signal is "FALSE"; It results in an internal error in XST :( /MikhailArticle: 149299
> Alternatively, have there been changes to 12.x's way of handling > precompiled > cores? I guess there have, because it doesn't copy anymore all the ngc files from the EDK implementation directory to the main project folder, only the system.ngc.... /Mikhail
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z