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Aditi wrote: > Hi, > > I have installed a PCI parallel port card on my PC. And I want to run > XILINX and let it detect the card > so that I can use a XILINX Parallel Cable IV to work with it. > XILINX detects the card but gives an error message saying > "ECP port test failed." and does not work. > > How do I get the PCI parallel card to work with XILINX? > > Is there a particular PCI card which someone has worked with and knows > for sure will work with XILINX? > > Can somebody please help me with this? > > Note: I am using a PCI card from Chronos MP9715P-2 which has the > NetMos 9715 chipset. > I also tried it with another card from Syba (SD-PEX-1005), > which has the MosChip 9901 chipset. Save yourself the trouble and get a Xilinx USB Cable. I wasted many hours with that crappy Parallel Cable. Even if you finally do get it to work at all with a NetMos Plugin-Card, it only works in the slowest config mode, and then FPGA loading takes forever. The USB cable is expensive but it will save you so much trouble and work in the long run. cu, Sean -- Replace "MONTH" with the three-letter abbreviation of the current month and the two-digit code for the current year (simple, eh?).Article: 149576
Hi all,
I have a very simple question. I have a statemachine, where the states
are declared as follows:
type SM_TYPE is (IDLE,WRITE0,WRITE1,READ1,ABORT0, ABORT1,ABORT2,ABORT3,
ABORT4, DONE);
signal nstate : SM_TYPE;
I would like to have now an output signal of my state machine which
encodes the state to that I can use this signal to debug the
statemachine with Chipscope. I am just wondering what kind of signal
the output port that encodes the state has to be. I think one-hot
encoding is used, and I have 10 states, so I would assume that
I could declare it like that
port (
...
dbg_state_out : out std_logic_vector(9 downto 0);
...
);
...
dbg_state_out <= nstate;
Is my approach right, or is the state encoded in something different
than a std_logic_vector.
Many thanks
Article: 149577On Nov 5, 3:21=A0am, Angus <angusdun...@googlemail.com> wrote: > all right here you go (I read there was A problem with MODELSIM in > simulating combinatorial processes): > > SIGNAL DATA1 : Data_t:=3D(7,3,2); > SIGNAL DATA2 : Data_t :=3D(9,5,1); > > PROCESS (SEL) > BEGIN > -- > =A0 =A0 =A0 =A0 =A0CASE SEL IS > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "00" =3D>temp<=3DDATA1; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "01" =3D>temp<=3DDATA2; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN OTHERS =3D>NULL; > =A0 =A0 =A0 =A0 END CASE; > > =A0 =A0 =A0 =A0 Data<=3DCONV_STD_LOGIC_VECTOR(temp(2),4)&CONV_STD_LOGIC_V= ECTOR(temp(1), > 4)&CONV_STD_LOGIC_VECTOR(temp(0),4); > END PROCESS; > when i change SEL in my testbench, Data does not change. I had to > embed my CASE within a clk edge detection to see the changes on > modelsim > > CHEERS ---------------------------------------------------------------------------= -------- items to the right of <=3D are typically in the sensitivity list DATA1, DATA2, temp, SEL You may have to play around with the vector notation in the sensitivity list. You forgot tempArticle: 149578
Richard G. wrote:
> Hi all,
>
> I have a very simple question. I have a statemachine, where the states
> are declared as follows:
>
> type SM_TYPE is (IDLE,WRITE0,WRITE1,READ1,ABORT0,
> ABORT1,ABORT2,ABORT3, ABORT4, DONE);
>
> signal nstate : SM_TYPE;
>
> I would like to have now an output signal of my state machine which
> encodes the state to that I can use this signal to debug the
> statemachine with Chipscope. I am just wondering what kind of signal
> the output port that encodes the state has to be. I think one-hot
> encoding is used, and I have 10 states, so I would assume that
> I could declare it like that
>
> port (
> ...
> dbg_state_out : out std_logic_vector(9 downto 0);
> ...
> );
>
> ...
>
> dbg_state_out <= nstate;
>
> Is my approach right, or is the state encoded in something different
> than a std_logic_vector.
>
> Many thanks
I didn't think you could cast a statemachine signal into a vector.
I've used the long hand way of putting statemachine in another process to
convert the state into a std_logic_vector
nstate_proc : process(nstate)
begin
case nstate is
when IDLE => dbg_state_out <= "000000000"
....
....
....
end case;
end process;
Article: 149579Just to expound on what Fredxx described, I usually binary encode my one-hot state machine bits to reduce the bits (e.g. 16 states gets reduced to 4 bits) before reporting the state to a status reg. Just remember to pipeline properly to isolate from the one-hot implementation. For example, register the one-hots into another register, then do the double-ranking into another set of regs. Also remember to use a "capture_status" signal if multiple clock domains are used to synchronize your binary-encoded state bits. For chipscope purposes, simply add these binary-encoded bits into your signal monitoring list, but remember to account for coherency between the binary-encoded bits and other signals you may be monitoring.Article: 149580
Hello, On a design I'm working Modelsim (Altera edition) doesn't like that I reset the simulation to rerun again. (for example I change the run length and restart the simulation again) it reports. # ** Error: (vsim-3170) Could not find 'D:\..myworkingpath...\simulation\modelsim\rtl_work.tb_port'. and I did not anything whatsoever outside modelsim to make the file disapear !!! and only cure is to start it all over compiling it all etc etc. Even so it is not enough to compile just the test bench, I need to do it all from the beginning... On the few examples provided by them, all works without issues... albeit I use the exact same sequence of operation that works on the examples, while on my design it works fine only the first run but errors as soon as I reset simulation. Very strange !!! Anyone knows a cure for this ? Many Thanks. Luis C.Article: 149581
On Nov 8, 7:40=A0am, jc <jcappe...@optimal-design.com> wrote: > Just to expound on what Fredxx described, I usually binary encode my > one-hot state machine bits to reduce the bits (e.g. 16 states gets > reduced to 4 bits) before reporting the state to a status reg. Just > remember to pipeline properly to isolate from the one-hot > implementation. For example, register the one-hots into another > register, then do the double-ranking into another set of regs. Also > remember to use a "capture_status" signal if multiple clock domains > are used to synchronize your binary-encoded state bits. For chipscope > purposes, simply add these binary-encoded bits into your signal > monitoring list, but remember to account for coherency between the > binary-encoded bits and other signals you may be monitoring. One more point, if you will be using the ChipScope inserter, you may need to add a KEEP attribute on your encoded state vector to prevent it from being removed from the design before the translate phase where the inserter grabs its connections. Also I have used the inserter to attach to state machine state variables without encoding them first. They tend to keep the same name as the original state variable with a numeric suffix. However you would need to figure out the encoding (usually reported in the synthesis report) in order to use these directly. I found that in the case of binary encoding, the post-translate signals have numeric suffixes 1 to N that roughly match N-1 downto 0 of the encoded bits. This means you probably have to reverse the bus order in the ChipScope viewer. regards, GaborArticle: 149582
"Richard G." <Richard@yahoo.com> writes: > Hi all, > > I have a very simple question. I have a statemachine, where the states > are declared as follows: > > type SM_TYPE is (IDLE,WRITE0,WRITE1,READ1,ABORT0, ABORT1,ABORT2,ABORT3, > ABORT4, DONE); > > signal nstate : SM_TYPE; > > I would like to have now an output signal of my state machine which > encodes the state to that I can use this signal to debug the > statemachine with Chipscope. If you use the chipscope core inserter, you can just probe the state directly. I usually put an attribute on my state machine to stop it being one-hot encoded in these cases if I can get away with it as it means the signal is much narrower, so less BRAMs are used. Check the synth reports very carefully as the state mapping is unlikely to be anything you expect it to be once the optimiser has finished :) If you are wanting to instantiate the ILA within your HDL the solution already presented of a separate process with explicit decode works fine, if a little verbose (and potentially error-prone if you're changing the content of SM_TYPE a lot). As an alternative, you could try using the "'pos method" (XST seems to accept this, although I haven't taken it through to a bitstream): debug_sig <= std_logic_vector(to_unsigned(nstate'pos, debug_sig'length)); This may have the side-effect of forcing state to be binary-encoded, depending on the logic around it I think. > I am just wondering what kind of signal the output port that encodes > the state has to be. I think one-hot encoding is used, and I have 10 > states, so I would assume that I could declare it like that > > port ( > ... > dbg_state_out : out std_logic_vector(9 downto 0); > ... > ); > > ... > > dbg_state_out <= nstate; > > Is my approach right, or is the state encoded in something different > than a std_logic_vector. > VHDL is strongly typed, so you can't do anything like that. Within the VHDL language, there is no concept of "state encodings". They are just elements of an enumerated type, with no other existence - other than the fact you can use the 'pos attribute to get a numerical position for them. HTH, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardwareArticle: 149583
On Nov 8, 10:44=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrote: [snip] > > debug_sig <=3D std_logic_vector(to_unsigned(nstate'pos, debug_sig'length)= ); > > This may have the side-effect of forcing state to be binary-encoded, > depending on the logic around it I think. > My experience has been that no matter how you use state variables in your code, the encoding is based on optimization. So even if your states are listed in a binary fashion AND you use the state variable externally, e.g. in a status register, you may still have one-hot encoding if that makes the synthesizer happy. The state will then be re-encoded for external use. This of course masks problems with one-hot encoding, as the "zero hot" state usually shows up in the re-encoded binary state as state "0" rather than no state. Regards, GaborArticle: 149584
On Nov 6, 4:03=A0am, Sean Durkin <news_MO...@tuxroot.de> wrote: > Aditi wrote: > > Hi, > > > I have installed a PCI parallel port card on my PC. And I want to run > > XILINX and let it detect the card > > so that I can use a XILINX Parallel Cable IV to work with it. > > XILINX detects the card but gives an error message saying > > "ECP port test failed." and does not work. > > > How do I get the PCI parallel card to work with XILINX? > > > Is there a particular PCI card which someone has worked with and knows > > for sure will work with XILINX? > > > Can somebody please help me with this? > > > Note: I am using a PCI card from Chronos MP9715P-2 which has the > > NetMos 9715 chipset. > > =A0 =A0 =A0 =A0 =A0I also tried it with another card from Syba (SD-PEX-= 1005), > > which has the MosChip 9901 chipset. > Hi All, Thanks for your suggestions. Even with that ECP port failed message, I could get the PROM to be programmed. Will surely go with the USB cable in future. But as of now, we are not thinking of going for USB atleast this year. Another quick question, Is there a way to tell iMPACT not to run the ECP test? Thanks, Regards, Aditi. > Save yourself the trouble and get a Xilinx USB Cable. I wasted many > hours with that crappy Parallel Cable. Even if you finally do get it to > work at all with a NetMos Plugin-Card, it only works in the slowest > config mode, and then FPGA loading takes forever. > > The USB cable is expensive but it will save you so much trouble and work > in the long run. > > cu, > Sean > > -- > Replace "MONTH" with the three-letter abbreviation of the current month > and the two-digit code for the current year (simple, eh?).Article: 149585
On Nov 3, 1:57=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > On Nov 3, 1:22=A0pm, Gabor <ga...@alacron.com> wrote: > > > On Nov 3, 1:08=A0pm, Mike Santarini <mike.santar...@gmail.com> wrote: > > > > We are awarding a SP601 Spartan-6 board to the winner of our You Writ= e > > > the Caption contest. =A0To enter, visithttp://cde.cerosmedia.com/1N4c= c1a89f283a0012.cde/page/66 > > > (this is a flash page). Here is a link to the latest issue if you > > > prefer PDF (see page 66):http://www.xilinx.com/publications/xcellonli= ne/index.htm. > > > > You have to be from North America (excluding Quebec) to officially > > > participate in the contest. > > > > Mike Santarini, publisher/editor Xcell > > > O.K. =A0I have to ask. =A0What did Quebec do wrong? > > Evidently they made some onerous laws:http://contests.about.com/od/sweeps= takes101/f/VoidinQuebec.htm > > Ed McGettigan > -- > Xilinx Inc. As I understand it, they require the contest be translated into French among other requirements that were a bit too restrictive for the spirit of the contest. As of today, November 8th, the contest has received thousands of hits and unique visitors but I've only received a handful of submissions so if you live in North America (excluding Quebec), send me a caption.Article: 149586
I've had success referencing variables in binary-encode construct: CASE is pstate WHEN idle => pstate_binencode <= X"0"; WHEN st_s1 => pstate_binencode <= X"1"; : WHEN st_term => pstate_binencode <= X"A"; WHEN OTHERS => pstate_binencode <= X"F"; END CASE; In this case, my binencode sequence will follow what I expect from the way the fsm was coded, regardless of how bits were synthesized or what new labels are used. The "pstate_binencode" signal should appear in chipscope as a 4-bit vector that sequences from 0x0, 0x1, etc., for normal sequence. The "OTHERS" clause even has built-in illegal state detection in case you'd want to add some fault tolerance.Article: 149587
Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in news:ib254t$hvq $1@lnx107.hrz.tu-darmstadt.de: > d_s_klein <d_s_klein@yahoo.com> wrote: >> On Nov 5, 10:18 am, Aditi <aditi.gro...@gmail.com> wrote: >> > Hi, >> > >> > I have installed a PCI parallel port card on my PC. And I want to run >> > XILINX and let it detect the card >> > so that I can use a XILINX Parallel Cable IV to work with it. >> > XILINX detects the card but gives an error message saying >> > "ECP port test failed." and does not work. >> > >> > How do I get the PCI parallel card to work with XILINX? >> > >> > Thanks, >> > Regards, >> > Aditi. > >> "ECP port test failed." usually means that the port is not in ECP >> mode. > > The original poster sould check in the BIOS It's an add-in card. I don't think that the PC BIOS is going to help.Article: 149588
Gabor <gabor@alacron.com> wrote: (snip) > My experience has been that no matter how you use state variables > in your code, the encoding is based on optimization. > So even if your states are listed in a binary fashion AND you > use the state variable externally, e.g. in a status register, > you may still have one-hot encoding if that makes the synthesizer > happy. The state will then be re-encoded for external > use. This of course masks problems with one-hot encoding, as the > "zero hot" state usually shows up in the re-encoded binary state > as state "0" rather than no state. Just as long as it doesn't do what one did to me some years ago. I had a two bit/four state machine, using the state externally. The software recoded it as one-hot, and gave two of the bits as the output, without re-encoding them. -- glenArticle: 149589
On Nov 8, 7:19=A0pm, Ian Shef <inva...@avoiding.spam> wrote: > Uwe Bonnes <b...@elektron.ikp.physik.tu-darmstadt.de> wrote in news:ib254= t$hvq > $...@lnx107.hrz.tu-darmstadt.de: > > > > > > > > > > > d_s_klein <d_s_kl...@yahoo.com> wrote: > >> On Nov 5, 10:18=A0am, Aditi <aditi.gro...@gmail.com> wrote: > >> > Hi, > > >> > I have installed a PCI parallel port card on my PC. And I want to ru= n > >> > XILINX and let it detect the card > >> > so that I can use a XILINX Parallel Cable IV to work with it. > >> > XILINX detects the card but gives an error message saying > >> > "ECP port test failed." and does not work. > > >> > How do I get the PCI parallel card to work with XILINX? > > >> > Thanks, > >> > Regards, > >> > Aditi. > > >> "ECP port test failed." usually means that the port is not in ECP > >> mode. > > > The original poster sould check in the BIOS > > It's an add-in card. =A0I don't think that the PC BIOS is going to help. Your quite right. An add in card, plugged into a PCI slot, does not become a true (legacy) Parallel port. Xilinx can cope with this with the right driver. Altera however insists on a "proper" parallel port at the correct place in IO space (ie not address space) which plug and play cannot give you.Article: 149590
On Nov 8, 1:56=A0pm, Mike Santarini <mike.santar...@gmail.com> wrote: > > As I understand it, they require the contest be translated into French > among other requirements that were a bit too restrictive for the > spirit of the contest. > And here I was thinking that VHDL & Verilog would meet the dual- language requirement... BrianArticle: 149591
jc <jcappello@optimal-design.com> writes: > I've had success referencing variables in binary-encode construct: > > CASE is pstate > WHEN idle => pstate_binencode <= X"0"; > WHEN st_s1 => pstate_binencode <= X"1"; > : > WHEN st_term => pstate_binencode <= X"A"; > WHEN OTHERS => pstate_binencode <= X"F"; > END CASE; > Is this not just a longer-winded version of pstate'pos (barring the "others" bit...) > In this case, my binencode sequence will follow what I expect from the > way the fsm was coded, regardless of how bits were synthesized or what > new labels are used. The "pstate_binencode" signal should appear in > chipscope as a 4-bit vector that sequences from 0x0, 0x1, etc., for > normal sequence. The "OTHERS" clause even has built-in illegal state > detection in case you'd want to add some fault tolerance. If you're using an enumerated type, and you've covered all the elements in the "real" cases, I'd expect the "others" clause will just be chucked away by the synth - unless you have one with special pragma's for making safe state-machines. Have you seen otherwise? Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardwareArticle: 149592
Gabor <gabor@alacron.com> writes: > On Nov 8, 10:44 am, Martin Thompson <martin.j.thomp...@trw.com> wrote: > [snip] >> >> debug_sig <= std_logic_vector(to_unsigned(nstate'pos, debug_sig'length)); >> >> This may have the side-effect of forcing state to be binary-encoded, >> depending on the logic around it I think. >> > > My experience has been that no matter how you use state variables in > your code, the encoding is based on optimization. Indeed - that's what I meant. [Depending on the other logic around the SM] the synth may decide that the best encoding (now that you've said you want a numerical representation of the states) is to keep them binary coded. Or it might not and produce a 1-hot SM with some 1-hot to integer decode logic (as you pointed out later). Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardwareArticle: 149593
On Nov 9, 8:42=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrote: > jc <jcappe...@optimal-design.com> writes: > > I've had success referencing variables in binary-encode construct: > > > CASE is pstate > > =A0 WHEN idle =3D> pstate_binencode <=3D X"0"; > > =A0 WHEN st_s1 =3D> pstate_binencode <=3D X"1"; > > =A0 : > > =A0 WHEN st_term =3D> pstate_binencode <=3D X"A"; > > =A0 WHEN OTHERS =3D> pstate_binencode <=3D X"F"; > > END CASE; > > Is this not just a longer-winded version of pstate'pos (barring the > "others" bit...) > I suppose... > > In this case, my binencode sequence will follow what I expect from the > > way the fsm was coded, regardless of how bits were synthesized or what > > new labels are used. The "pstate_binencode" signal should appear in > > chipscope as a 4-bit vector that sequences from 0x0, 0x1, etc., for > > normal sequence. The "OTHERS" clause even has built-in illegal state > > detection in case you'd want to add some fault tolerance. > > If you're using an enumerated type, and you've covered all the > elements in the "real" cases, I'd expect the "others" clause will just > be chucked away by the synth - unless you have one with special > pragma's for making safe state-machines. > > Have you seen otherwise? > Good question Martin. I agree, we could assume synthesis tool will discard default case if # states =3D 2^n. But what about when number of elements (states) isn't multiple of 2^n? If I have, say, 11 states, and I want to code them to binary after the fact (i.e. register those states into separate 11-bit vector, assuming one-hot), I need 4 bits to encode the 11 possibilities. If there's some glitch, act of God, poorly-timed circuit, async inputs, whatever, and the result is that more than one flop goes high in my 11-bit vector (illegal!), how can we guarantee that the synthesis tool will go to any particular value? In the code above, I'm forcing it to go to all 1's--I could have encoded it to go to any value. Regards, JohnArticle: 149594
Hi, I am using a daisy chain of 2 xc3s4000 FPGAs and an EEPROM xcf16p. The chains goes like this : EEPROM -> FPGA1 -> FPGA2. Now the problem is that i brought up the board like 4 months back, it worked and then i put it back in closet. Today, when i needed it,i thought it as fine but when plugged it, my INIT_B signal was constantly low where as it should go high to 3.3V after few ms of POR. I checked all the signals i could think of, checked for any short circuits and stuff but couldn't find any clue. I checked my power rails and they were stable, VCCINT 1.2, VCCIO 3.3 , VccAux 2.5 . I have an external pull up to 3.3v through 4.7kohm on INIT_B signal. It has just stopped working. Can anyone give me some pointers? Regards --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149595
"william" <cuteworm@n_o_s_p_a_m.wildmail.com> wrote in message news:pIKdnYImkMdU_knRnZ2dnUVZ_s2dnZ2d@giganews.com... > Hi, > > I am using synplify pro. > In synplify constraint file I can add in the pin assignment for physical > FPGA mapping. > but I can not tell the difference add and not add. I did not see > significant timing improve or related information embedded into output > edf. > > is it the pin assignment really help timing/sythesis for final out come > result? > pin location constraints in the synplify .sdc file are forward annotated to the .ncf file, assuming the option to generate a .ncf file is set in the synplify project. The .ncf file is then read by ISE and the signal is placed as directed. I don't think a pin loc will make any change to an edif file, but I've never looked to see. --steveArticle: 149596
On Nov 9, 2:00=A0pm, jc <jcappe...@optimal-design.com> wrote: > On Nov 9, 8:42=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrote: > > > jc <jcappe...@optimal-design.com> writes: > > > I've had success referencing variables in binary-encode construct: > > > > CASE is pstate > > > =A0 WHEN idle =3D> pstate_binencode <=3D X"0"; > > > =A0 WHEN st_s1 =3D> pstate_binencode <=3D X"1"; > > > =A0 : > > > =A0 WHEN st_term =3D> pstate_binencode <=3D X"A"; > > > =A0 WHEN OTHERS =3D> pstate_binencode <=3D X"F"; > > > END CASE; > > > Is this not just a longer-winded version of pstate'pos (barring the > > "others" bit...) > > I suppose... > > > > In this case, my binencode sequence will follow what I expect from th= e > > > way the fsm was coded, regardless of how bits were synthesized or wha= t > > > new labels are used. The "pstate_binencode" signal should appear in > > > chipscope as a 4-bit vector that sequences from 0x0, 0x1, etc., for > > > normal sequence. The "OTHERS" clause even has built-in illegal state > > > detection in case you'd want to add some fault tolerance. > > > If you're using an enumerated type, and you've covered all the > > elements in the "real" cases, I'd expect the "others" clause will just > > be chucked away by the synth - unless you have one with special > > pragma's for making safe state-machines. > > > Have you seen otherwise? > > Good question Martin. I agree, we could assume synthesis tool will > discard default case if # states =3D 2^n. But what about when number of > elements (states) isn't multiple of 2^n? If I have, say, 11 states, > and I want to code them to binary after the fact (i.e. register those > states into separate 11-bit vector, assuming one-hot), I need 4 bits > to encode the 11 possibilities. If there's some glitch, act of God, > poorly-timed circuit, async inputs, whatever, and the result is that > more than one flop goes high in my 11-bit vector (illegal!), how can > we guarantee that the synthesis tool will go to any particular value? > In the code above, I'm forcing it to go to all 1's--I could have > encoded it to go to any value. > Regards, > John I think the part you're missing is that the same synthesis tool will optimize the re-encoding of your one-hot to binary. It PRESUMES that the one- hot codes are, well, one hot. So it can happily ignore your default case and just make sure that the 11 states it knows about will generate the proper binary number. In Verilog parlance, it presumes a parallel_case and full_case for the 11 known values. The simplest way to encode this uses only OR gates, and MIGHT give you a value outside the range of 0 to 10 if there are multiple states hot, however it WILL encode to zero if the machine goes zero-hot. This is indistinguishable from state zero (idle). The only time I don't see this behavior is when the synthesis option to create "safe" state machine logic is used. regards, GaborArticle: 149597
On Nov 9, 2:00=A0pm, jc <jcappe...@optimal-design.com> wrote: >and the result is that > more than one flop goes high in my 11-bit vector (illegal!), how can > we guarantee that the synthesis tool will go to any particular value? 1. By using a synthesis tool specific switch to generate a 'safe' state machine 2. Add the code to handle the other cases. Then verify that the tool is actually doing what you expect it to do. This might involve simulating a gate level model, finding the nodes that implements the states and forcing one or more of the bits to a value to create an illegal state for one clock cycle and see what happens. Verify that both binary and one hot encoded versions of the same source code will recover (if the synthesis tool switch is set to 'safe') and that it might not (if the synthesis tool switch is not set to 'safe'). > In the code above, I'm forcing it to go to all 1's--I could have > encoded it to go to any value. That's half of the battle...the other half is the synthesis tool switch. KevinArticle: 149598
Check your configuration data has been generated for the correct device. Also if you have increased configuration clock rate try turning that down to normal. You can gain a little more information using JTAG and doing a status read of each FPGA device. Look particularly for a CRC error but also check that your mode pins are set correctly in the status read data. John Adair Enterpoint Ltd. Home of Raggedstone2. The Spartan-6 PCIe Development Board. On Nov 9, 7:29=A0pm, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > Hi, > I am using a daisy chain of 2 xc3s4000 FPGAs and an EEPROM xcf16p. The > chains goes like this : EEPROM -> FPGA1 -> FPGA2. > > Now the problem is that i brought up the board like 4 months back, it > worked and then i put it back in closet. Today, when i needed it,i though= t > it as fine but when plugged it, my INIT_B signal was constantly low where > as it should go high to 3.3V after few ms of POR. > > I checked all the signals i could think of, checked for any short circuit= s > and stuff but couldn't find any clue. I checked my power rails and they > were stable, VCCINT 1.2, VCCIO 3.3 , VccAux 2.5 . > > I have an external pull up to 3.3v through 4.7kohm on INIT_B signal. > It has just stopped working. > > Can anyone give me some pointers? > > Regards > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.comArticle: 149599
Hello I'm Implementing controller using xilinx ISE 8.2 on FPGA board Virtex-II and anlyzing signals inside FPGA using chiscope analyzer. I instantiated cores using chipscope core inserter.My implementation was successful. Though the bit file was generated but when it comes to analyze it in chipscope ,,,I could get this problem Device 0 Unit 0:waiting for core to be armed, slow or stopped clock.. When I implemented the design..I could get the only warning ..i,e WARNING:Timing:3223 - Timing constraint PATH "TS_U_TO_D_path" TIG; ignored during timing analysis. and the rest like generating programming file everything is going well but when it come sto analyze it in chipscope after configuring it with bit file...I could get the error like Device 0 Unit 0:waiting for core to be armed, slow or stopped clock.. I have tried to manage it by reading so many forums...like nearly I changed all possible changes but still I could get this... Its a big design so I assigned pin only for clock signal with help of manual.. and the signal I selected for a clock to Chipscope is driven by a BUFG or BUFGMUX component... mhz_in signal is not being driven by the board. clock source (on-board) was driven by the pin I assigned to it in .ucf file...but still I could get this problem.. Can anybody help me ...Please.. --------------------------------------- Posted through http://www.FPGARelated.com
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