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On Dec 13, 7:15=A0am, Antti <antti.luk...@googlemail.com> wrote: > On Dec 7, 12:56=A0am, Gabor <ga...@alacron.com> wrote: > > > On Dec 6, 12:06=A0pm, d_s_klein <d_s_kl...@yahoo.com> wrote: > > > > On Dec 6, 3:13=A0am, Mike Harrison <m...@whitewing.co.uk> wrote: > > > > >http://www.youtube.com/watch?v=3Dh_USk-HNgPA&feature=3Dplayer_detail= page > > > > > Come on X and A - spice up your promo =A0videos! > > > > Everybody chooses what is important to them. =A0Some like snazzy vide= os, > > > some like to ship product to customers... > > > Well, then Lattice is doing both. =A0Their policy on new part > > announcement is to wait until they have at least _some_ silicon availab= le. =A0Xilinx is > > already announcing Virtex 8 while not shipping V7. > > well this time Lattice has broken thee policy, there are no MachXO > parts shipping? > > Antti If you are talking about XO2, they will probably ship before V7 ;-)Article: 150101
On 12/10/2010 3:57 PM, Thomas Stanka wrote: [snip] > Open cores tend to have a lack in documentation and verification, > which is a no-go for developing space electronics. There are documented results of projects that attracted space applications (http://opencores.org/newsletter,2010,09,#n5), proving that there is a certain interest in the open approach. > Even if you target on public science projects it is very likely that > you need to ensure the "space-readiness" in many aspects for a core > before you can use it. > The aim of the project is not to provide a "ready-to-use" solution, but to spread the use of spacewire protocol. The end-user is of course responsible for the entire process, but it can be foreseen a test campaign which will validate the IP on certain technologies (after all I am working at CERN and there are a lot of test-beams facilities here!). I just want to mention that on an FPGA based application the choice of the FPGA may guarantee certain level of radiation hardness, while specific design techniques may improve the level of hardness even further (TMR, data-scrubbing, EDAC.). > For spacewire interface I consider the effort to proof the quality of > a core clearly exceeding the effort for writting the core for your > own. > Indeed, nevertheless there are a good amount of projects which are neither proofing the quality of their cores, nor applying any standard protocol throughout their systems. > Are you firm with developing according to ECSS-Q 60 02? I would expect > a core development to be complaint to this before using it without > further quality checking in case of the core not beeing provided from > ESA for a ESA project. > Even though I believe that Space Agencies around the world are politically and technically bond to follow standardization processes based mostly on lessons learned, I also believe that a lot of industries and research institutes are buried under the burden of those standards where a good chunk of their budget goes. I am not advocating a deviation from the standards, on the contrary I believe that protocols (as can-bus, mil-std-1553, spi, I2C...) are key components of a reliable system and any effort should be made to make them popular. > In case of detailed questions you may also conntact me by sending an > email. You should change the receive-address to thomas > @domain_from_email when replying. > > best regards Thomas Al p.s.: I am just an enthusiast designer, willing to improve my skills and to share my knowledge.Article: 150102
Am 13.12.2010 13:15, schrieb Antti: > On Dec 7, 12:56 am, Gabor<ga...@alacron.com> wrote: >> On Dec 6, 12:06 pm, d_s_klein<d_s_kl...@yahoo.com> wrote: >> >>> On Dec 6, 3:13 am, Mike Harrison<m...@whitewing.co.uk> wrote: >> >>>> http://www.youtube.com/watch?v=h_USk-HNgPA&feature=player_detailpage >> >>>> Come on X and A - spice up your promo videos! >> >>> Everybody chooses what is important to them. Some like snazzy videos, >>> some like to ship product to customers... >> >> Well, then Lattice is doing both. Their policy on new part >> announcement is to wait until they have at least _some_ silicon available. Xilinx is >> already announcing Virtex 8 while not shipping V7. > > well this time Lattice has broken thee policy, there are no MachXO > parts shipping? > It seems you can buy at least samples of the LCMXO2-1200 in their online store. ThomasArticle: 150103
j. wrote:
> Given a Data Link that uses DS92LV1021 chip (16-40MHz 10-bit bus LVDS
> Serializer) to send data. Unfortunately it also sends start and stop
> bits, 12-bit each word total (@480MHz). Task is to build a receiver in
> FPGA. However, both Xilinx and Altera built-in SERDES circuits support
> only 10-bit words ("deserialization factor"). Is there any way to
> interface them with the above DS92LV1021 chip?
Have a look at:
http://www.missinglinkelectronics.com/files/papers/MLE-TB20091127.pdf
Looks like that one matches ;-)
Regards,
Lorenz
Article: 150104On Dec 13, 6:48=A0am, Jan Decaluwe <j...@jandecaluwe.com> wrote: > rickman wrote: > > On Dec 2, 10:32 am, Jan Decaluwe <j...@jandecaluwe.com> wrote: > >> rickman wrote: > > >> Of course, I'm sure this is all obvious to you and I realize that > >> it must have been my explanation that was inadequate. But there > >> really was no need for this confusion. You could have seen all > >> these things for yourself by just spending one minute to see > >> the screencast. Sigh. > > > I don't know what a screencast is > > I'll hold your hand: > > http://en.wikipedia.org/wiki/Screencast > > > and I have never seen a sales tool > > that conveyed any useful info in 1 minute. > > Look, I can assure you that many good engineers find such a > screencast very useful. I am also of the opinion that the > people who make such things, for people like you, through > hard work, deserve much better than this. Your prejudices > are so high that you don't even want to *try*, even though > it takes only a fraction of the time you spend on writing > posts with a much lower information content. Beats me. Wonderful for them! I find that nearly every video I have watched was far too slow paced, covered too little material at too shallow a level and has provided very little information relative to the marketing content. I just don't watch them unless it is a topic I am extremely interested in. This product has a lot of strikes against it, so in the end the minute details of what it does is not of great interest to me. It has been described here and I don't find it compelling. > Time to review good old school engineering practices. I have no idea what that means. But I find your analysis of my opinions to be rude and pointless. Clearly you wish to offend me. But it is much less clear if you think that somehow you are being persuasive. RickArticle: 150105
Hi, I've got some logic to simulate in ISIM. The problem is that it's quite complex and it takes 9 hours to simulate on my laptop. Is there any option that could help me gain a little speed-up? Thanks in advance.Article: 150106
On 14 Gru, 10:51, Przemys=B3aw Elias <pempus...@gmail.com> wrote: > Hi, > > I've got some logic to simulate in ISIM. The problem is that it's > quite complex and it takes 9 hours to simulate on my laptop. Is there > any option that could help me gain a little speed-up? > > Thanks in advance. I'd like to add, that ISIM uses as little as 5-10% of my CPU during that simulation. Simulating other modules takes 100% CPU and consequenty much less time.Article: 150107
>> I've got some logic to simulate in ISIM. The problem is that it's >> quite complex and it takes 9 hours to simulate on my laptop. Is there >> any option that could help me gain a little speed-up? >I'd like to add, that ISIM uses as little as 5-10% of my CPU during >that simulation. Simulating other modules takes 100% CPU and >consequenty much less time. More memory. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 150108
rickman wrote:
> On Dec 13, 6:48 am, Jan Decaluwe <j...@jandecaluwe.com> wrote:
>> Time to review good old school engineering practices.
>
> I have no idea what that means. But I find your analysis of my
> opinions to be rude and pointless. Clearly you wish to offend me.
No, but I am getting extremely frustrated that it is proving
impossible for me to have a meaningful discussion with you, though
I think the topics should be of mutual interest. No matter how hard
I try, I seem to fighting what I perceive as an attitude of
unwillingness, wasting everybody's time - this screencast
incident being an absolute low point.
Of course I should limit myself to deciding what I should do
and not try to tell you what you should do - that is
overreaction, and I take that back.
Jan
--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Python as a HDL: http://www.myhdl.org
VHDL development, the modern way: http://www.sigasi.com
Analog design automation: http://www.mephisto-da.com
World-class digital design: http://www.easics.com
Article: 150109On 14 Gru, 11:49, hal-use...@ip-64-139-1-69.sjc.megapath.net (Hal Murray) wrote: > >> I've got some logic to simulate in ISIM. The problem is that it's > >> quite complex and it takes 9 hours to simulate on my laptop. Is there > >> any option that could help me gain a little speed-up? > >I'd like to add, that ISIM uses as little as 5-10% of my CPU during > >that simulation. Simulating other modules takes 100% CPU and > >consequenty much less time. > > More memory. > > -- > These are my opinions, not necessarily my employer's. =A0I hate spam. That sounds like a solution, but this simulation is taking 300MB out of my 4GB at the moment. Are you sure that more memory would help? Aren't there any other solutions?Article: 150110
"Przemysław Elias" <pempushek@gmail.com> wrote in message news:94013131-6fdf-4483-a8ab-0b6979219dc8@29g2000yqq.googlegroups.com... On 14 Gru, 10:51, Przemysław Elias <pempus...@gmail.com> wrote: > Hi, > > I've got some logic to simulate in ISIM. The problem is that it's > quite complex and it takes 9 hours to simulate on my laptop. Is there > any option that could help me gain a little speed-up? > > Thanks in advance. >I'd like to add, that ISIM uses as little as 5-10% of my CPU during >that simulation. Simulating other modules takes 100% CPU and >consequenty much less time. Are you using the full version? if not then you might have hit the limit, Q. What is ISE Simulator Lite? A. ISE Simulator Lite is a limited version of the ISE Simulator. There is only one limitation. When the user design + testbench exceeds 50,000 lines of HDL code, the simulator will start to derate the performance of the simulator for that invocation. http://www.xilinx.com/products/design_tools/logic_design/verification/ise_simulator_faq.htm Hans www.ht-lab.comArticle: 150111
On 14 Gru, 15:45, "HT-Lab" <han...@ht-lab.com> wrote: > "Przemys aw Elias" <pempus...@gmail.com> wrote in message > > news:94013131-6fdf-4483-a8ab-0b6979219dc8@29g2000yqq.googlegroups.com... > On 14 Gru, 10:51, Przemys aw Elias <pempus...@gmail.com> wrote: > > > Hi, > > > I've got some logic to simulate in ISIM. The problem is that it's > > quite complex and it takes 9 hours to simulate on my laptop. Is there > > any option that could help me gain a little speed-up? > > > Thanks in advance. > >I'd like to add, that ISIM uses as little as 5-10% of my CPU during > >that simulation. Simulating other modules takes 100% CPU and > >consequenty much less time. > > Are you using the full version? if not then you might have hit the limit, > > Q. What is ISE Simulator Lite? > A. ISE Simulator Lite is a limited version of the ISE Simulator. There is only > one limitation. When the user design + testbench exceeds 50,000 lines of HDL > code, the simulator will start to derate the performance of the simulator for > that invocation. > > http://www.xilinx.com/products/design_tools/logic_design/verification... > > Hanswww.ht-lab.com Look's like this is an issue. I've got ISim from WebPack which is Lite Version. Thanks for pointing this out!Article: 150112
I have a fully debugged design in ISE 11.3 and now having trouble getting it to work in ISE 12.3. With XST option "Keep Hierarchy" unchecked, all my input ports other than “clock” are REMOVED during optimization. However, with "Keep Hierarchy" option turned on, the problem goes away and all the inputs show up in the pin report but it takes long time to compile. Has anyone experienced similar problem? Am I missing anything? Thanks --Rajeev --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150113
On Dec 14, 7:50=A0am, "Rajeev" <rajeevph@n_o_s_p_a_m.gmail.com> wrote: > I have a fully debugged design in ISE 11.3 and now having trouble getting > it to work in ISE 12.3. With XST option "Keep Hierarchy" unchecked, all m= y > input ports other than =93clock=94 are REMOVED during optimization. > However, with "Keep Hierarchy" option turned on, the problem goes away an= d > all the inputs show up in the pin report but it takes long time to compil= e. > Has anyone experienced similar problem? Am I missing anything? > > Thanks > > --Rajeev > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com It will be fixed in 12.4 ;) Seriously, open a web case. Something is very wrong - if the inputs are optimized away, then the outputs should be optimized away also. G.Article: 150114
Hi All, I am using a Spartan-6 FPGA in my design (XC6SLX16 -2CSG225). I am using a XILINX Serial Flash PROM (XC40FS) to boot the FPGA. Note : The size of my bit file is about 454KB ~ 3.5M bit. My concern is: Initially I have used a 2MHz CCLK as the ConfigRate and the time it took for the PROM to boot the FPGA was about 2sec (measured it on the scope). Then I increased the CCLK to be about 10MHz, and the time taken to boot the FPGA decreased to 0.7sec. And if I increase the rate anything more than 10MHz ( the max I can see is 26MHz), the boot time does not have any effect and remains at 0.7sec. Does the PROM take so long to boot the FPGA? Also, when I look at the datasheet for the PROM (XC40FS), the min clock period it could take was about 100ns i.e the max CCLK frequency would be 10MHz. But when I tried to use a ConfigRate of 26MHz, the FPGA still booted (and took the same time about 0.7sec). Does this mean the PROM does something with the clock if it higher than it can handle? Also, I do not have a lot of logic in my Verilog project but still the .bit file is about 3.5M bit. Is the file size very normal? Or am I missing something here? Can I compress the bit file? Thanks, Regards, Aditi.Article: 150115
Hi All, I am using a Spartan-6 FPGA in my design (XC6SLX16 -2CSG225). I am using a XILINX Serial Flash PROM (XC40FS) to boot the FPGA. Note : The size of my bit file is about 454KB ~ 3.5M bit. My concern is: Initially I have used a 2MHz CCLK as the ConfigRate and the time it took for the PROM to boot the FPGA was about 2sec (measured it on the scope). Then I increased the CCLK to be about 10MHz, and the time taken to boot the FPGA decreased to 0.7sec. And if I increase the rate anything more than 10MHz ( the max I can see is 26MHz), the boot time does not have any effect and remains at 0.7sec. Does the PROM take so long to boot the FPGA? Also, when I look at the datasheet for the PROM (XC40FS), the min clock period it could take was about 100ns i.e the max CCLK frequency would be 10MHz. But when I tried to use a ConfigRate of 26MHz, the FPGA still booted (and took the same time about 0.7sec). Does this mean the PROM does something with the clock if it higher than it can handle? Also, I do not have a lot of logic in my Verilog project but still the .bit file is about 3.5M bit. Is the file size very normal? Or am I missing something here? Can I compress the bit file? Thanks, Regards, Aditi Embedded Systems Engineer Signalogic IncArticle: 150116
On Tue, 14 Dec 2010 15:43:32 -0800 (PST) Aditi <aditi.groups@gmail.com> wrote: [snip] > Also, I do not have a lot of logic in my Verilog project but still > > the .bit file is about 3.5M bit. > > Is the file size very normal? Or am I missing something here? > > Can I compress the bit file? I'm not familiar with S6, but with S3A, there's a "-g Compress" option you can pass to the bitgen utility to make a smaller bitstream. Sorry, don't know anything about how to do it in the graphical environment if you're using that. How much difference that will make is of course a subject for your own experiments, but it's a trivial first thing to try! ChrisArticle: 150117
On Dec 13, 6:54=A0pm, Thomas Heller <thel...@ctypes.org> wrote: > Am 13.12.2010 13:15, schrieb Antti: > > > > > > > > > On Dec 7, 12:56 am, Gabor<ga...@alacron.com> =A0wrote: > >> On Dec 6, 12:06 pm, d_s_klein<d_s_kl...@yahoo.com> =A0wrote: > > >>> On Dec 6, 3:13 am, Mike Harrison<m...@whitewing.co.uk> =A0wrote: > > >>>>http://www.youtube.com/watch?v=3Dh_USk-HNgPA&feature=3Dplayer_detailp= age > > >>>> Come on X and A - spice up your promo =A0videos! > > >>> Everybody chooses what is important to them. =A0Some like snazzy vide= os, > >>> some like to ship product to customers... > > >> Well, then Lattice is doing both. =A0Their policy on new part > >> announcement is to wait until they have at least _some_ silicon availa= ble. =A0Xilinx is > >> already announcing Virtex 8 while not shipping V7. > > > well this time Lattice has broken thee policy, there are no MachXO > > parts shipping? > > It seems you can buy at least samples of the LCMXO2-1200 in their online > store. > > Thomas YES?? there are icons to click on that all show later 0 ZERO stock on any XO2 parts... so nothing available AnttiArticle: 150118
"HT-Lab" <hans64@ht-lab.com> writes: > one limitation. When the user design + testbench exceeds 50,000 lines of HDL Then something like this would get around the limitation: find vhdl-dir -iname '*.vhd' -print0 | xargs -0 cat | sed 's/\(.*\)--.*/\1/' | tr -d "\n\r" > oneliner.vhd :-) I always thought the limitation was given as a number of hdl tokens/statements. Petter -- .sig removed by request.Article: 150119
hi, i am using spartan 3 xc3s4000 in my design daisy chanied to an EEPROM xcf16p. They are connected in this manner: XCF16P -> spartan 3 It is a custom design and the problem is that my JTAG pins TCK and TDO are not getting pulled up to Vccaux, rather they are showing 0 constantly and TMS is pulled upto 3.3V whereas it should be 2.5v (vccaux). Correct me if i am wrong here. I have already checked the short circuits on the board and there isn't any apparently. My only guess now is the dry soldering of FPGA balls which has left the connection open. I dont want to take off the FPGA from the board before i am sure of my result so i need ur help in debugging this issue. Kindly give me pointers, what should i check next before arriving to my conclusion. another thing, i took off the EEPROM from board and then checked my JTAG pins, none was pulled upto 2.5V. I checked my connections and they were fine, so does this mean my FPGA is not working or what? thanks regards --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150120
"salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote in message news:o_WdnQVMl9hIDZXQnZ2dnUVZ_uGdnZ2d@giganews.com... > hi, i am using spartan 3 xc3s4000 in my design daisy chanied to an EEPROM > xcf16p. They are connected in this manner: > > XCF16P -> spartan 3 > > It is a custom design and the problem is that my JTAG pins TCK and TDO are > not getting pulled up to Vccaux, rather they are showing 0 constantly and > TMS is pulled upto 3.3V whereas it should be 2.5v (vccaux). Correct me if > i > am wrong here. > > I have already checked the short circuits on the board and there isn't any > apparently. My only guess now is the dry soldering of FPGA balls which has > left the connection open. > > I dont want to take off the FPGA from the board before i am sure of my > result so i need ur help in debugging this issue. Kindly give me pointers, > what should i check next before arriving to my conclusion. > > another thing, i took off the EEPROM from board and then checked my JTAG > pins, none was pulled upto 2.5V. I checked my connections and they were > fine, so does this mean my FPGA is not working or what? > The Spartan 3 has internal JTAG pull-up of a modest value. Yes the TMS ought to be pulled to 2.5V, but as long as you limit pin current and take steps to ensure Vccaux doesn't rise as per XAPP453 you'll be ok. I would first ensure that 2.5V Vccaux is present. Check orientation of FPGA, may sound silly but........ I would then use a DVM between 2.5V and JTAG lines to see what current, and equivalent value of pull-down you've got. Possibly remove the XCF16P if a leaded component to remove any doubt if above is showing low impedance. You should also get access to many of the signals close to the FPGA pads through vias on the underside. How confident are you that the assembler is competent? Generally BGAs go down well, so I would expect some of the connections to have been made if sufficient temperature has been applied. Before removing the FPGA, I would want an inspection, either camera or x-ray. Was the footprint a standard PCB library part.Article: 150121
Hi, i'm new on FPGA programming, so i've tried to build my soft core with a altera sopc builder. Generate procedure works, so files are generated....but: i'm trying to obtain .sof file for devboard: how can i do?I should start a new project? Which files i should include? thanksArticle: 150122
On Dec 15, 3:46=A0am, Antti <antti.luk...@googlemail.com> wrote: > On Dec 13, 6:54=A0pm, Thomas Heller <thel...@ctypes.org> wrote: > > > > > Am 13.12.2010 13:15, schrieb Antti: > > > > On Dec 7, 12:56 am, Gabor<ga...@alacron.com> =A0wrote: > > >> On Dec 6, 12:06 pm, d_s_klein<d_s_kl...@yahoo.com> =A0wrote: > > > >>> On Dec 6, 3:13 am, Mike Harrison<m...@whitewing.co.uk> =A0wrote: > > > >>>>http://www.youtube.com/watch?v=3Dh_USk-HNgPA&feature=3Dplayer_detai= lpage > > > >>>> Come on X and A - spice up your promo =A0videos! > > > >>> Everybody chooses what is important to them. =A0Some like snazzy vi= deos, > > >>> some like to ship product to customers... > > > >> Well, then Lattice is doing both. =A0Their policy on new part > > >> announcement is to wait until they have at least _some_ silicon avai= lable. =A0Xilinx is > > >> already announcing Virtex 8 while not shipping V7. > > > > well this time Lattice has broken thee policy, there are no MachXO > > > parts shipping? > > > It seems you can buy at least samples of the LCMXO2-1200 in their onlin= e > > store. > > > Thomas > > YES?? there are icons to click on that all show later 0 ZERO stock on > any XO2 parts... > > so nothing available > > Antti Being out of stock and not shipping are two different things. Anyone know if they have actually been sold in the store yet? Does the store list a lead time? RickArticle: 150123
On Dec 15, 4:00=A0am, Petter Gustad <newsmailco...@gustad.com> wrote: > "HT-Lab" <han...@ht-lab.com> writes: > > one limitation. When the user design + testbench exceeds 50,000 lines o= f HDL > > Then something like this would get around the limitation: > > find vhdl-dir -iname '*.vhd' -print0 | xargs -0 cat | sed 's/\(.*\)--.*/\= 1/' | tr -d "\n\r" > oneliner.vhd > > :-) I always thought the limitation was given as a number of hdl > tokens/statements. It is. They don't count YOUR lines, they parse the code and count what THEY consider to be lines. I am VERY surprised that Xilinx is crippling their own simulator!!! Isim is a Xilinx product no? So where is the marketing advantage to slowing down your simulations when you are working with larger code and most likely larger devices??? Do they really think it is a good idea to give away software that discourages the use of their larger part$? RickArticle: 150124
Hello
I'm using Xilinx EDK 11.5 with xps_spi core version 2.01b. Core is
correctly integrated in my SDK, I can see the signals on my DSO.
Everything seems to be allright. But I've got a little software problem.
In SDK I transfer my data with the function "XSpi_Transfer(&mySPI,
outBuffer, inBuffer, 2)" (see above). It works exactly one time and I
get XST_SCCUSS back. But if I call XSpi_Transfer again, I get
XST_DEVICE_BUSY back.
My program do the following steps:
1.) initalize SPI (function "XSpi_Initialize")
2.) set options (function "XSpi_SetOptions")
3.) select slave (function "XSpi_SetSlaveSelect")
4.) start SPI (function "XSpi_Start")
5.) transfer data (function "XSpi_Transfer")
Every function return XST_SUCCESS, but not Xspi_transfer when I call it
the second time.
So my question? Is there any bug in the core or have I forgot something?
I hope someone can help me. I tried to google, found a similar problem,
but no solution.
Thanks a lot,
Tobias
C-Code:
#include <stdio.h>
#include "platform.h"
#include "xbasic_types.h"
#include "xstatus.h"
#include "xparameters.h"
#include "xspi.h"
void SPIini(void);
void pause(void);
XSpi mySPI;
int main()
{
init_platform();
print("SPI Test\n\r");
pause();
Xuint8 inBuffer[4] = {0x00, 0x00, 0x00, 0x00};
Xuint8 outBuffer[4] = {0x00, 0xAA, 0xFF, 0xAA};
XStatus status = XST_SUCCESS;
SPIini();
for(Xuint8 i=0; i<100; i++) {
/* initialization */
status = XSpi_Transfer(&mySPI, outBuffer, inBuffer, 2);
switch(status)
{
case XST_SUCCESS: print("Status: Erfolgreich gesendet."); break;
case XST_DEVICE_IS_STOPPED: print("Status: Device stopped\n\r"); break;
case XST_DEVICE_BUSY: print("Status: Device busy\n\r"); break;
case XST_SPI_NO_SLAVE: print("Status: Device no slave\n\r"); break;
}
pause();
}
cleanup_platform();
return 0;
}
void SPIini(void)
{
XStatus status = XST_SUCCESS;
status = XSpi_Initialize(&mySPI, XPAR_TEST_SPI_DEVICE_ID);
switch(status)
{
case XST_SUCCESS: print("Status: Erfolgreich initialisiert\n\r"); break;
case XST_DEVICE_IS_STARTED: print("Status: Device is started\n\r"); break;
case XST_DEVICE_NOT_FOUND: print("Status: Device not found\n\r"); break;
}
Xuint32 options = XSP_MASTER_OPTION;
status = XSpi_SetOptions(&mySPI, options);
switch(status)
{
case XST_SUCCESS: print("Status: Erfolgreich option gesetzt\n\r"); break;
case XST_DEVICE_BUSY: print("Status: Device busy\n\r"); break;
case XST_SPI_SLAVE_ONLY: print("Status: Slave only\n\r"); break;
}
XSpi_SetSlaveSelect(&mySPI, 1);
XSpi_Start(&mySPI);
}
void pause(void)
{
for(int i=0; i<CPU_FREQ; i++);
}
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