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On Nov 25, 9:40=A0am, Petter Gustad <newsmailco...@gustad.com> wrote: > jc <jcappe...@optimal-design.com> writes: > >> Upgrade to Linux... > > >> Petter > > > You won't find me defending windows for its lack of robustness (among > > other nuisances), and I understand the impact Linux has had on EDA and > > general development environments, but I did notice from the links > > kkoorndyk provided that Xilinx' memory recommendations are identical > > for Windows and Linux, at least for Virtex-5... > > John > > My comment was out of context. I was thinking about some earlier > message which indicated that it was a cost related to upgrading to > large memory support on the Windows platform. Here Linux would help. I > did not mean that Xilinx SW on Linux requires any less memory than on > Windows. > > Petter > -- > .sig removed by request. It's times like this that make me think about "changing my stripes"... JohnArticle: 149851
On 11/28/2010 6:06 AM, FlorianB82 wrote:
> has really nobody a hint for me regarding this subject?
If you want to do it, just do it.
http://en.wikipedia.org/wiki/Distributed_revision_control.
If someone complains, talk to them.
If you want the tired arguments, google this group.
-- Mike Treseler
Article: 149852thanks for your answer =) >If you want to do it, just do it. >http://en.wikipedia.org/wiki/Distributed_revision_control. i'm doing it anyway, since the whole thing is for my diploma thesis =). the two main reasons for my plan of making it public are: - it just would be nice to share this one with other people interested in this subject (and there are people, who want to do such things like bitstream reversal). especially if there is anything like it available. - it would be a good recommendation for me, especially when applicating for a job. why did you suggest me a drc system? sure, i could use it, but why? is it for veiling me as the author of the library (if so, it defeats reason number two)? >If someone complains, talk to them. sounds reasonable =) >If you want the tired arguments, google this group. i did, but all i found was a mess of arguments, and beeing not familiar with such kind of things, some arguments sounded quite odd to me=). after all, this arguments are now a little bit old, and maybe something changed over the time... --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149853
>Do you have 2 DCMs in your design? You might have a clock generator in the >processor module and another dcm external to the processor. > >Jon > >--------------------------------------- >Posted through http://www.FPGARelated.com > Thanks for the reply. I did not use any DCM in my design. The clock I used is generated using the clock generator IP core of xilinx. This IP core can support up to 15 clock. I use its 4th out put . I define the following parameter in the mhs file and the code is as follows: # ####################### PARAMETER C_CLKOUT4_FREQ = 240000000 PARAMETER C_CLKOUT4_PHASE = 0 PARAMETER C_CLKOUT4_GROUP = NONE PARAMETER C_CLKOUT4_BUF = TRUE # ######################### PORT CLKOUT4 = clk_240_0000MHz PORT clk_240MHz = clk_240_0000MHz I really do not understand why there is no error if I compiling them separately. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149854
On Sun, 28 Nov 2010 23:17:49 -0600, "spacetimerake" <spacetimerake@n_o_s_p_a_m.n_o_s_p_a_m.hotmail.com> wrote: >>Do you have 2 DCMs in your design? You might have a clock generator in >the >>processor module and another dcm external to the processor. >> >>Jon >> >>--------------------------------------- >>Posted through http://www.FPGARelated.com >> > >Thanks for the reply. >I did not use any DCM in my design. The clock I used is generated using the >clock generator IP core of xilinx. This IP core can support up to 15 clock. >I use its 4th out put . I define the following parameter in the mhs file >and the code is as follows: > ># ####################### > PARAMETER C_CLKOUT4_FREQ = 240000000 > PARAMETER C_CLKOUT4_PHASE = 0 > PARAMETER C_CLKOUT4_GROUP = NONE > PARAMETER C_CLKOUT4_BUF = TRUE ># ######################### > PORT CLKOUT4 = clk_240_0000MHz > >PORT clk_240MHz = clk_240_0000MHz > >I really do not understand why there is no error if I compiling them >separately. When you compile your ip block separately do you set a 240 MHz clock constraint on it? Do you also constrain your input? What's probably happening is that you have unconstrained input on your ip block with a long delay and when you make your integrated block this path shows up. You have to look at the actual path which is failing. It's probably from a register in the bus (PLB?) implementation through some combination logic in your block to a register in your block. Make your peripheral implementation a registered one ie register the bus data before you use it. Most importantly make sure that your ip is properly constrained when you synthesize it by itself. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 149855
>On Sun, 28 Nov 2010 23:17:49 -0600, "spacetimerake" ><spacetimerake@n_o_s_p_a_m.n_o_s_p_a_m.hotmail.com> wrote: > >>>Do you have 2 DCMs in your design? You might have a clock generator in >>the >>>processor module and another dcm external to the processor. >>> >>>Jon >>> >>>--------------------------------------- >>>Posted through http://www.FPGARelated.com >>> >> >>Thanks for the reply. >>I did not use any DCM in my design. The clock I used is generated using the >>clock generator IP core of xilinx. This IP core can support up to 15 clock. >>I use its 4th out put . I define the following parameter in the mhs file >>and the code is as follows: >> >># ####################### >> PARAMETER C_CLKOUT4_FREQ = 240000000 >> PARAMETER C_CLKOUT4_PHASE = 0 >> PARAMETER C_CLKOUT4_GROUP = NONE >> PARAMETER C_CLKOUT4_BUF = TRUE >># ######################### >> PORT CLKOUT4 = clk_240_0000MHz >> >>PORT clk_240MHz = clk_240_0000MHz >> >>I really do not understand why there is no error if I compiling them >>separately. > >When you compile your ip block separately do you set a 240 MHz clock >constraint on it? Do you also constrain your input? >What's probably happening is that you have unconstrained input on your >ip block with a long delay and when you make your integrated block >this path shows up. You have to look at the actual path which is >failing. It's probably from a register in the bus (PLB?) >implementation through some combination logic in your block to a >register in your block. Make your peripheral implementation a >registered one ie register the bus data before you use it. >Most importantly make sure that your ip is properly constrained when >you synthesize it by itself. >-- >Muzaffer Kal > >DSPIA INC. >ASIC/FPGA Design Services > >http://www.dspia.com > Problem solved, thank you so much for the help!! --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149856
About Sigasi, rickman <gnuarm@gmail.com> writes: > To what extent does the editor "understand" the VHDL I type? I am > already using an editor that recognizes keywords, comments, numbers, > ect... and colors them as I require. What more does the Sigasi editor > do? > It understands the structure of the design - what instantiates what, what calls what functions. For example if you rename a port entry on an entity, it can go through the design changing all the instances of that entity to match. You *can* do this with careful use of global search/replace, but this "just works" Another example: you can take a process within the entity you're working on and say "make me an entity of this process", which it will do, putting the IO in and instantiating it where the process used to be. This involves much more than just "matching keywords". Get the eval and have a play :) (BTW, although I may sound like a salesman, I have no connection with Sigasi, other than being impressed with the demo :) I still haven't quite been torn away from Emacs vhdl-mode though... even though it's missing the two features above! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardwareArticle: 149857
"spacetimerake" <spacetimerake@n_o_s_p_a_m.n_o_s_p_a_m.hotmail.com> writes: > I did not use any DCM in my design. The clock I used is generated using the > clock generator IP core of xilinx. This IP core can support up to 15 clock. > I use its 4th out put . I define the following parameter in the mhs file > and the code is as follows: Just for completeness, that IP core will create as many DCMs as it needs to create the clock outputs you've asked for. Cheers Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardwareArticle: 149858
>"spacetimerake" <spacetimerake@n_o_s_p_a_m.n_o_s_p_a_m.hotmail.com> >writes: > >> I did not use any DCM in my design. The clock I used is generated using the >> clock generator IP core of xilinx. This IP core can support up to 15 clock. >> I use its 4th out put . I define the following parameter in the mhs file >> and the code is as follows: > >Just for completeness, that IP core will create as many DCMs as it >needs to create the clock outputs you've asked for. > >Cheers >Martin > >-- >martin.j.thompson@trw.com >TRW Conekt - Consultancy in Engineering, Knowledge and Technology >http://www.conekt.co.uk/capabilities/39-electronic-hardware > Thank you so much for the reply. From the log, it seems that the system is trying to adding a constrain for the DCM0 to generate a 240MHz clock, that is what I am using for the user IP. So when I manually add a constrain for that clock, the error was solved. Any way, thank you so much for the help! And thanks for this web site. It is really a good place to learning! sam --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149859
On Nov 29, 4:38=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrote: > About Sigasi, rickman <gnu...@gmail.com> writes: > > > To what extent does the editor "understand" the VHDL I type? =A0I am > > already using an editor that recognizes keywords, comments, numbers, > > ect... and colors them as I require. =A0What more does the Sigasi edito= r > > do? > > It understands the structure of the design - what instantiates what, > what calls what functions. > > For example if you rename a port entry on an entity, it can go through > the design changing all the instances of that entity to match. =A0You > *can* do this with careful use of global search/replace, but this > "just works" I'm not sure I understand what you are saying here. Are you saying it changes the name of the signal in the entity declaration? What about the rest of the entity? I guess I really don't see how this is different from a global search/replace. > Another example: you can take a process within the entity you're > working on and say "make me an entity of this process", which it will > do, putting the IO in and instantiating it where the process used to > be. =A0This involves much more than just "matching keywords". I can't say I have done this very often, if ever. I have split an entity into two but I don't recall ever taking a single process and promoting it to an entity. When the tool does this, does it also add the required signal declarations? How does it know which signals need to be in the ports list and which need to be declared as local signals? > Get the eval and have a play :) I learned a long time ago that before I spend the time to learn a tool, I need to have a pretty good reason to make the investment. So far I haven't see such a reason to learn the Sigasi tool. > (BTW, although I may sound like a salesman, I have no connection with > Sigasi, other than being impressed with the demo :) I still haven't > quite been torn away from Emacs vhdl-mode though... even though it's > missing the two features above! It has been very seldom that I have seen a tool which I decided I needed enough to drop an old tool and pick up the new. However, there has been a number of times that I realized that my present tool was not doing the job as well as I would like and I then started looking for a better tool. That is the case now, but I haven't seen any features of Sigasi that help deal with any of the issues I experience with CodeWright. One thing that could be done to expedite my code banging is auto- completion of my signal and variable names, or better, completion of lines like declarations. Or even automatically adding the entire declaration once I add a usage of a signal/variable. I find most of my "non-productive" typing has to do with the required support for the object in the design, not the actual usage of them. RickArticle: 149860
> One thing that could be done to expedite my code banging is auto- > completion of my signal and variable names, or better, completion of > lines like declarations. Or even automatically adding the entire > declaration once I add a usage of a signal/variable. I find most of > my "non-productive" typing has to do with the required support for the > object in the design, not the actual usage of them. I think Sigasi can do some of this. The downside for me is the EURO 499 ($650) _annual_ licence fee (or EURO 1500 [$1900] perpetual licence). Nial.Article: 149861
I do embedded development with C++ and VHDL in parallel and have always longed for an editing tool for the VHDL side that came even close to what is available for C/C++ development. I'm only a couple of days into my Sigasi trial but so far it feels like what I have been looking for. The tool understands VHDL and allows painless navigation around the design in addition to the code refactoring features (auto- completion, intelligent signal renaming, automatic declaration of signals missing from an instantiation etc...). I have nothing to-do with the people behind Sigasi but I think it is worth giving it a shot. Their support is very fast also if you have any questions.Article: 149862
Hi, i am trying to use OpenCores PCI Bridge but i have some doubts. Whats exactly is the Image Address and how it works? When i am receiving some information on PCI Target, how can i define the WishBone Slave that is being addressed? When i am sending some information with a WishBone Master to the Bridge Slave, how can i define to which PCI on the BUS i am addressing? Thank you! --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149863
openArticle: 149864
In article <icmns0$f6j$1@news.eternal-september.org>, glen herrmannsfeldt <gah@ugcs.caltech.edu> writes: >alessandro.strazzero@gmail.com <alessandro.strazzero@gmail.com> wrote: > >> I'm a newbye in VHDL and I would like to submit a question. I have a >> system wich is clocked at 24MHz by an external oscillator. >> This clock is the input of a PLL internal to the FPGA. >> The outputs of the PLL are two clocks: one at 48MHz to clock >> a CPU and a custom logic called "A", and the other one at 24MHz to >> clock a custom logic called "B". >(snip) > >> The question is: do the custom logic "B" signals have to be >> syncronized with the 48MHz clock ? > >If you can meet the setup and hold times, then you are safe. Right. But there are two tricky areas. One is that you have to include clock skew, and that includes the skew between the two clocks. The other is that you have to check the hold time. Several/many years ago, somebody reported this sort of problem on a Xilinx part. Xilinx doesn't check hold times. They are guaranteed-by-design. Except something didn't work if there was a little extra clock skew due to using two different clocks. Does Altera check hold times? -- These are my opinions, not necessarily my employer's. I hate spam.Article: 149865
Hal Murray <hal-usenet@ip-64-139-1-69.sjc.megapath.net> wrote: > In article <icmns0$f6j$1@news.eternal-september.org>, (snip on two clocks generated by PLL (is that DCM?) inside an FPGA) >>> The question is: do the custom logic "B" signals have to be >>> syncronized with the 48MHz clock ? (then I wrote) >>If you can meet the setup and hold times, then you are safe. > Right. But there are two tricky areas. > One is that you have to include clock skew, and that includes > the skew between the two clocks. Well, you have to include clock skew more than that included by the designers. In TTL, you can connect a FF output directly to a D input, and possibly not meed the hold time. For FPGA, the fastest you can get from one FF to the input of the next is through at least one LUT. (For most, anyway.) As long as the skew is small enough that, when added to the LUT delay, it meets hold for the following FF, then it works. > The other is that you have to check the hold time. Several/many > years ago, somebody reported this sort of problem on a Xilinx part. > Xilinx doesn't check hold times. They are guaranteed-by-design. > Except something didn't work if there was a little extra clock > skew due to using two different clocks. I believe that the DCM will generate two clocks, one twice the frequncy of the other, and such that when appropriate they transition close enough together not to cause clock skew problems. If you bring them from the outside, and don't resynchronize one, then you can easily have skew problems. Then again, if you have more than one clock period delay through the logic, then you could again fail hold (or setup). > Does Altera check hold times? -- glenArticle: 149866
On Mon, 29 Nov 2010 20:52:08 -0600, hal-usenet@ip-64-139-1-69.sjc.megapath.net (Hal Murray) wrote: >In article <icmns0$f6j$1@news.eternal-september.org>, > glen herrmannsfeldt <gah@ugcs.caltech.edu> writes: >>alessandro.strazzero@gmail.com <alessandro.strazzero@gmail.com> wrote: >> >>> I'm a newbye in VHDL and I would like to submit a question. I have a >>> system wich is clocked at 24MHz by an external oscillator. >>> This clock is the input of a PLL internal to the FPGA. >>> The outputs of the PLL are two clocks: one at 48MHz to clock >>> a CPU and a custom logic called "A", and the other one at 24MHz to >>> clock a custom logic called "B". >>(snip) >> >>> The question is: do the custom logic "B" signals have to be >>> syncronized with the 48MHz clock ? >> >>If you can meet the setup and hold times, then you are safe. > >Right. But there are two tricky areas. > >One is that you have to include clock skew, and that includes >the skew between the two clocks. > Xilinx tools (mainly PAR & TRCE which use the same timing engine) know how to add the phase shift while calculating timing path delays. Also clock skews of different paths are added to the source and/or target paths too. >The other is that you have to check the hold time. Several/many >years ago, somebody reported this sort of problem on a Xilinx part. >Xilinx doesn't check hold times. They are guaranteed-by-design. This is no longer true. TRCE is able and willing to do a fast path analysis correctly for single cycle paths. For multi-cycle paths there is a big acknowledged bug in the timing engine which won't get fixed till next gen tools. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 149867
I'm not sure what is wrong here. I have a design that I have used in the past and has worked ok. I am making modifications to it and my Hi- Z outputs are being grounded. This creates some problems during operation. The VHDL code is like this... TMS_B1 <= 'Z'; I just want this output to be Hi-Z for this design so that the pin output is not driven (which clobbers these signals from other sources). The lines for this output in the preference file are... LOCATE COMP "TMS_B1" SITE "36" ; IOBUF PORT "TMS_B1" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=8 SLEWRATE=SLOW ; When I load the design into the part, the output is always low and checking the design in Epic, I see the tri-state driver has a 0 on the input and a 0 on the enable. I believe the 0 on the enable turns on the output driver because that is how the outputs are configured. I also looked at the Technology View in Synplify and I find TMS_B1 is driven by a OB with a 0 on it's input. Is this a bug or is there something wrong with the way I am doing this? I made a lot of changes to the overall design before I discovered this bug so I'm not certain that the preference file lines have not been changed since this was working, but I don't see how they can be causing this problem. RickArticle: 149868
On Nov 29, 11:54=A0pm, rickman <gnu...@gmail.com> wrote: > I'm not sure what is wrong here. I have a design that I have used in > the past and has worked ok. I am making modifications to it and my Hi- > Z outputs are being grounded. This creates some problems during > operation. The VHDL code is like this... > > TMS_B1 <=3D 'Z'; > > I just want this output to be Hi-Z for this design so that the pin > output is not driven (which clobbers these signals from other > sources). The lines for this output in the preference file are... > > LOCATE COMP "TMS_B1" SITE "36" ; > IOBUF PORT "TMS_B1" IO_TYPE=3DLVCMOS33 PULLMODE=3DKEEPER DRIVE=3D8 > SLEWRATE=3DSLOW ; > > When I load the design into the part, the output is always low and > checking the design in Epic, I see the tri-state driver has a 0 on the > input and a 0 on the enable. I believe the 0 on the enable turns on > the output driver because that is how the outputs are configured. > > I also looked at the Technology View in Synplify and I find TMS_B1 is > driven by a OB with a 0 on it's input. > > Is this a bug or is there something wrong with the way I am doing > this? I made a lot of changes to the overall design before I > discovered this bug so I'm not certain that the preference file lines > have not been changed since this was working, but I don't see how they > can be causing this problem. > > Rick Rick, I suppose you have already convinced yourself that it is not the buskeeper circuit driving the line low. Bus Maintenance Circuit Each pad has a weak pull-up, weak pull-down and weak buskeeper capability. The pull-up and pull-down settings offer a fixed characteristic, which is useful in creating wired logic such as wired ORs. However, current can be slightly higher than other options, depending on the signal state. The bus-keeper option latches the signal in the last driven state, holding it at a valid level with minimal power dissipation. Users can also choose to turn off the bus maintenance circuitry, minimizing power dissipation and input leakage. Note that in this case, it is important to ensure that inputs are driven to a known state to avoid unnecessary power dissipation in the input buffer. ---------------------------------------------------------------------- Is it possible that the P&R is optimizing the signal out and that unused I/O are being strapped to '0'?Article: 149869
rickman <gnuarm@gmail.com> writes: > On Nov 29, 4:38 am, Martin Thompson <martin.j.thomp...@trw.com> wrote: >> About Sigasi, rickman <gnu...@gmail.com> writes: >> >> > To what extent does the editor "understand" the VHDL I type? I am >> > already using an editor that recognizes keywords, comments, numbers, >> > ect... and colors them as I require. What more does the Sigasi editor >> > do? >> >> It understands the structure of the design - what instantiates what, >> what calls what functions. >> >> For example if you rename a port entry on an entity, it can go through >> the design changing all the instances of that entity to match. You >> *can* do this with careful use of global search/replace, but this >> "just works" > > I'm not sure I understand what you are saying here. Are you saying it > changes the name of the signal in the entity declaration? What about > the rest of the entity? I guess I really don't see how this is > different from a global search/replace. Yes, it changes the entity delaaration, uses of that port inside the entity and the port mapping of the instantiation(s) of the entity. This is better than a global (ie multi-file) replace because when you change "write" on one entity to "write_n" you don't want every entity with a "write" pin changing! And heaven help you changing rd to wr - hope the characters 'rd' don't appear in any other pins anywhere else (like the "one_third" pin of your "divide_by_three" entity ;) http://www.sigasi.com/screencast/rename (1 minute video) > > >> Another example: you can take a process within the entity you're >> working on and say "make me an entity of this process", which it will >> do, putting the IO in and instantiating it where the process used to >> be. This involves much more than just "matching keywords". > > I can't say I have done this very often, if ever. Possibly because it's an awful lot of pain? > I have split an entity into two Which is a similar process (if you'll excuse the pun :). > but I don't recall ever taking a single process and > promoting it to an entity. When the tool does this, does it also add > the required signal declarations? How does it know which signals need > to be in the ports list and which need to be declared as local > signals? > Things that go "into" the process or "out of" the process are entity ports. There's no need for local signals, as it's just one process you're pushing. > >> Get the eval and have a play :) > > I learned a long time ago that before I spend the time to learn a > tool, I need to have a pretty good reason to make the investment. So > far I haven't see such a reason to learn the Sigasi tool. > Forgive me, but if you're still using Codewright (unless it has changed immeasureably since I migrated from it to Emacsin the CW5.x days) I'd be amazed if Sigasi wouldn't help. How much time do you spend copying "columns" from entities and changing : to => in port maps to instance a component? That used to drive me demented in CW. > >> (BTW, although I may sound like a salesman, I have no connection with >> Sigasi, other than being impressed with the demo :) I still haven't >> quite been torn away from Emacs vhdl-mode though... even though it's >> missing the two features above! > > It has been very seldom that I have seen a tool which I decided I > needed enough to drop an old tool and pick up the new. Me too. Migrating from CW to Emacs was the last time I recall doing it. And that was a *serious* learning curve, but still worth it. Sigasi is way easier IMHO. > However, there > has been a number of times that I realized that my present tool was > not doing the job as well as I would like and I then started looking > for a better tool. That is the case now, but I haven't seen any > features of Sigasi that help deal with any of the issues I experience > with CodeWright. > > One thing that could be done to expedite my code banging is auto- > completion of my signal and variable names Yes, it does that. I kind of took that as read (coming from VHDL-mode) > or better, completion of lines like declarations. If I understand you rightly, yes. > Or even > automatically adding the entire declaration once I add a usage of a > signal/variable. Not yet - that would be fun. I guess it would have to ask you what type to make the signal/variable, which might interrupt my flow of coding though. Some Other things it does (full list is at http://www.sigasi.com/featurelist): * Autocomplete templates for "if", "process", and the rest. * Line alignment (so all your : and <= and => line up nicely) * automatic reindentation * sensitivity list checking * generate makefiles * Built in errors and warnings (no need to compile, it does it on the fly) Having this "in-the-editing-loop" is more of a boon than you'd think until you've tried it (IMHO) * "Go to declaration" (CW might be configurable to do this?) > I find most of my "non-productive" typing has to do with the > required support for the object in the design, not the actual usage > of them. Indeed, that's precisely where the tools like Emacs' vhdl-mode and Sigasi come in. Anyway, I probably ought to shut up now and let the Sigasi people talk about their own tool, they'll no doubt be much more eloquent than I! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardwareArticle: 149870
On Nov 30, 2:35=A0am, Newman <newman5...@yahoo.com> wrote: > On Nov 29, 11:54=A0pm, rickman <gnu...@gmail.com> wrote: > > > > > I'm not sure what is wrong here. I have a design that I have used in > > the past and has worked ok. I am making modifications to it and my Hi- > > Z outputs are being grounded. This creates some problems during > > operation. The VHDL code is like this... > > > TMS_B1 <=3D 'Z'; > > > I just want this output to be Hi-Z for this design so that the pin > > output is not driven (which clobbers these signals from other > > sources). The lines for this output in the preference file are... > > > LOCATE COMP "TMS_B1" SITE "36" ; > > IOBUF PORT "TMS_B1" IO_TYPE=3DLVCMOS33 PULLMODE=3DKEEPER DRIVE=3D8 > > SLEWRATE=3DSLOW ; > > > When I load the design into the part, the output is always low and > > checking the design in Epic, I see the tri-state driver has a 0 on the > > input and a 0 on the enable. I believe the 0 on the enable turns on > > the output driver because that is how the outputs are configured. > > > I also looked at the Technology View in Synplify and I find TMS_B1 is > > driven by a OB with a 0 on it's input. > > > Is this a bug or is there something wrong with the way I am doing > > this? I made a lot of changes to the overall design before I > > discovered this bug so I'm not certain that the preference file lines > > have not been changed since this was working, but I don't see how they > > can be causing this problem. > > > Rick > > Rick, > I suppose you have already convinced yourself that it is not the > buskeeper circuit driving the line low. > > Bus Maintenance Circuit > Each pad has a weak pull-up, weak pull-down and weak buskeeper > capability. The pull-up and pull-down settings > offer a fixed characteristic, which is useful in creating wired logic > such as wired ORs. However, current can be > slightly higher than other options, depending on the signal state. The > bus-keeper option latches the signal in the > last driven state, holding it at a valid level with minimal power > dissipation. Users can also choose to turn off the bus > maintenance circuitry, minimizing power dissipation and input leakage. > Note that in this case, it is important to > ensure that inputs are driven to a known state to avoid unnecessary > power dissipation in the input buffer. Thanks for the suggestion, but yes, I eliminated that by looking at the I/O block settings in Epic, the layout editor. I originally saw this problem with an LED driving pin. I set it for hi-z and it was driving the LED on hard. A bus keeper wouldn't drive that hard. Besides, this pin is driving two LEDs, one up and one down. Hi-z is the only state where neither LED is on. When I use logic to select the three states, 1, 0, Z; then the hi-z state is enabled appropriately. I can always work around this by controlling it from some signal such as reset so that it is always hi-z after the FPGA is up. It is odd that this worked just fine before and now screws up. I haven't updated any of the development software that I know of, but I haven't messed with this design since 2008, so there's been a lot of water under the dam since then. If it is a tool problem, I may not get an update. My maintenance ran out long ago and this is a paid for copy. I'd hate to have to shell out a kilobuck to get a bug fix so I can continue using the software that I already paid for. RickArticle: 149871
I am building an FPGA data acquisition board which will interface with the PC over the PCI bus at 33Mhz. The fpga is going to be responsible for acquiring data from peripheral devices and passing this to the CPU. The data includes two separate video channels as well as some sensor readings. What are the pros and cons of implementing the FPGA as a PCI master versus as a PCI target? I will need to use DMA to do the actual transfers. What are the pros and cons of doing the DMA on the PC side versus on the FPGA side? Can anyone give me a high level overview of how DMA would work with PCI as a master versus a target? Thank you.Article: 149872
Why are you using PCI? Why not PCI Express? I would of thought PCI is pretty much dead now. All the new FPGA devices, even the cheap ones support PCI Express so you may be better looking at that route. Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149873
The fpga board will mate with a single board PC which only has a PCI interface (actually it is a PC/104+ stackable interface). On Nov 30, 9:21=A0am, "maxascent" <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote: > Why are you using PCI? Why not PCI Express? I would of thought PCI is > pretty much dead now. All the new FPGA devices, even the cheap ones suppo= rt > PCI Express so you may be better looking at that route. > > Jon =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.comArticle: 149874
On Nov 30, 8:18=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrote: > rickman <gnu...@gmail.com> writes: > > On Nov 29, 4:38 am, Martin Thompson <martin.j.thomp...@trw.com> wrote: > >> About Sigasi, rickman <gnu...@gmail.com> writes: > > >> > To what extent does the editor "understand" the VHDL I type? I am > >> > already using an editor that recognizes keywords, comments, numbers, > >> > ect... and colors them as I require. What more does the Sigasi edito= r > >> > do? > > >> It understands the structure of the design - what instantiates what, > >> what calls what functions. > > >> For example if you rename a port entry on an entity, it can go through > >> the design changing all the instances of that entity to match. You > >> *can* do this with careful use of global search/replace, but this > >> "just works" > > > I'm not sure I understand what you are saying here. =A0Are you saying i= t > > changes the name of the signal in the entity declaration? =A0What about > > the rest of the entity? =A0I guess I really don't see how this is > > different from a global search/replace. > > Yes, it changes the entity delaaration, uses of that port inside the > entity and the port mapping of the instantiation(s) of the entity. > > This is better than a global (ie multi-file) replace because when you > change "write" on one entity to "write_n" you don't want every entity > with a "write" pin changing! =A0And heaven help you changing rd to wr - > hope the characters 'rd' don't appear in any other pins anywhere else > (like the "one_third" pin of your "divide_by_three" entity ;) That's not a big deal. My editor, and I suspect many others, has a check box on the search that says "only full word match" so that write_n won't match a write search. > >> Another example: you can take a process within the entity you're > >> working on and say "make me an entity of this process", which it will > >> do, putting the IO in and instantiating it where the process used to > >> be. This involves much more than just "matching keywords". > > > I can't say I have done this very often, if ever. =A0 > > Possibly because it's an awful lot of pain? It's not a pain issue. I can't remember ever taking just a process and turning it into an entity. I typically have some amount of concurrent code to go with a process and the only times I can remember doing this it was more than one process. I don't like instantiation because of the verbosity. But I don't let that determine my code structure. > > I have split an entity into two > > Which is a similar process (if you'll excuse the pun :). I've also combined entities. Does the tool help with either combining or splitting processes at arbitrary margins? > > but I don't recall ever taking a single process and > > promoting it to an entity. =A0When the tool does this, does it also add > > the required signal declarations? =A0How does it know which signals nee= d > > to be in the ports list and which need to be declared as local > > signals? > > Things that go "into" the process or "out of" the process are entity > ports. =A0There's no need for local signals, as it's just one process > you're pushing. Exactly. I nearly always have some concurrent logic that goes with the process. > >> Get the eval and have a play :) > > > I learned a long time ago that before I spend the time to learn a > > tool, I need to have a pretty good reason to make the investment. =A0So > > far I haven't see such a reason to learn the Sigasi tool. > > Forgive me, but if you're still using Codewright (unless it has > changed immeasureably since I migrated from it to Emacsin the CW5.x > days) I'd be amazed if Sigasi wouldn't help. > > How much time do you spend copying "columns" from entities and > changing : to =3D> in port maps to instance a component? =A0That used to > drive me demented in CW. That's the part I have regex lines to handle. I have to tweek the last line of the port list so it has a terminator, apply the regex, tweek the terminator back and adjust the column alignments (manually, I am a little OCD about this part). Then I have everything perfectly formatted and even the comments within the port list are transferred. After a dozen or so passes with the regex it was tweeked enough to cover all the weird cases such as including "_" in the names, etc. I have one regex to generate the instantiation port map and another to generate signal declarations. I may spend a little more time with it so it will write the code for the entity body given a customer's description of the problem. ;^) > >> (BTW, although I may sound like a salesman, I have no connection with > >> Sigasi, other than being impressed with the demo :) I still haven't > >> quite been torn away from Emacs vhdl-mode though... even though it's > >> missing the two features above! > > > It has been very seldom that I have seen a tool which I decided I > > needed enough to drop an old tool and pick up the new. =A0 > > Me too. =A0Migrating from CW to Emacs was the last time I recall doing > it. =A0And that was a *serious* learning curve, but still worth it. > Sigasi is way easier IMHO. I only have two problems with Sigasi. One is spending time with it to be convinced that it is better in some so far, unidentified way. The other is that it is commercial software with an up front cost and I assume a recurring cost. Being a small shop I don't often pay for tools unless I am absolutely convinced I need them. Notice I said "need", not "would like" or "nice to have" or even "would be more productive if". When I am working the VHDL I bang code all day long. But I don't do it all the time. I also spend time designing the boards, writing test code, specs, docs and even conversing with customers... oh yeah, and that slightly important part, looking for customers. I'm not inclined to spend a kilobuck on something that will give me a minor improvement in what I do maybe 10% of the time. Then on top of it all, a tool that requires support from a company is already a rung lower on the ladder than a tool that is either static because it is already unsupported (Codewright and Eudora) or open source and supported by an active community. The most useful tools I have are (other than the FPGA tools that I have no choice with) are one of those two categories. The biggest bane to my existence, tool- wise, is the licensed tools I have to keep running, but only weekdays 9-5. I am having a problem with the Lattice tools right now that I am having to go through support (or around actually) to resolve. > > However, there > > has been a number of times that I realized that my present tool was > > not doing the job as well as I would like and I then started looking > > for a better tool. =A0That is the case now, but I haven't seen any > > features of Sigasi that help deal with any of the issues I experience > > with CodeWright. > > > One thing that could be done to expedite my code banging is auto- > > completion of my signal and variable names > > Yes, it does that. =A0I kind of took that as read (coming from VHDL-mode) This could be interesting. How does that work? My email program has auto-completion of email addresses and my browser has auto completion of form fields. As I type it pops up a list and as I type more the list grows shorter. At any point I use the up or down arrow keys to select the entry I want and hit enter. Sometimes in a web page they haven't implemented it correctly and using return causes the form to be submitted. Otherwise this is a real time saver. Is this the way it works in Sigasi with signal names? If you are typing a signal name as the first thing on a line, does it add the assignment operator? What happens the first time you type an assignment to a signal or variable? Does it add a declaration for the name? > > =A0or better, completion of lines like declarations. =A0 > > If I understand you rightly, yes. > > > Or even > > automatically adding the entire declaration once I add a usage of a > > signal/variable. > > Not yet - that would be fun. =A0I guess it would have to ask you what > type to make the signal/variable, which might interrupt my flow of > coding though. Yep, I don't know if the interruption would be worth it or not. Maybe selecting the name and using a function key. Keeping the declarations in line with my signal/variable usage is one of the time consumers/ wasters of my coding time. > Some Other things it does (full list is athttp://www.sigasi.com/featureli= st): > * Autocomplete templates for "if", "process", and the rest. Nice, but not a big deal, for me anyway. > * Line alignment (so all your : and <=3D and =3D> line up nicely) That would be nice. > * automatic reindentation This is a PITA for me. Regex scripting doesn't work so well here. You have to make a pass for each indentation level in use. > * sensitivity list checking > * generate makefiles > * Built in errors and warnings (no need to compile, it does it on the > =A0 fly) Having this "in-the-editing-loop" is more of a boon than you'd > =A0 think until you've tried it (IMHO) I would agree with that. I have been looking at a programming tool that has the philosophy of catching errors as soon in the development process as possible. Some errors that might not be caught until run time can be checked in a language aware editor. > * "Go to declaration" (CW might be configurable to do this?) No, CW doesn't understand the language that well. It really only knows keywords, names, numbers, comments and strings. Structure is beyond CW. > > I find most of my "non-productive" typing has to do with the > > required support for the object in the design, not the actual usage > > of them. > > Indeed, that's precisely where the tools like Emacs' vhdl-mode and > Sigasi come in. > > Anyway, I probably ought to shut up now and let the Sigasi people talk > about their own tool, they'll no doubt be much more eloquent than I! So far I've gotten a lot more from you than I have them. I seem to recall years ago Aldec was big on sending out CDs of their software for you to try. They would call me and push the CD so I would say "send it" and then it would sit waiting for me to spend the time to learn the stuff. I never did. Then I paid for my Lattice tools and was expecting a copy of Modelsim. By the time I called in to get the license keys, they had switched and would only license Aldec ActiveHDL. I was livid over the apparent "bait an switch". Having no choice, and believe me I tried!, I learned ActiveHDL and it turned out to be pretty durn good. I like it a lot now and it doesn't have the long running Modelsim memory allocation crash bug. I'll be finished with my VHDL coding in another week or two and won't want to spend time with a VHDL tool. I am going to look into a design using a multiprocessor chip that is micro power or nano power or pico power, what ever it is being called these days. Idle state is 100 micro watts per processor with 144 processors on the chip. Running full out they use 4.5 mW at over 500 MIPS! The transition between running and idle is just a matter of reading a processor I/O port with virtually no time wasted ramping clocks up and down. They have described a four node chip that I might use to design a radio controlled clock "atomic clock" as a demonstration of the low power capabilities. This will use a totally different set of tools than Sigasi, et al. Rick
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