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I am mainly refering to: http://www.techfocusmedia.net/embeddedtechnologyjournal/feature_articles/20101123-stellarton I think there will be some market for such a device, especially in the medical and industrial control market, maybe also networking. In fact we did already design a board with an FPGA connected to a Qseven Atom module by PCIe. Also I think, that $72 is a reasonable price for that kind of FPGA (so the Atom is really almost for free, if it is not even "negative" priced...) But I think there are some "buts": - There are 3 main (new) families of FPGAs from Altera (low-, mid- and high-end), all with some "sub-families" and a lot of different family- members varying in size (and price) dramatically. The same is with Xilinx, Lattice and Actel (ehm... Microsemi). And then there are some newcomers (e.g. Achronix, which is fabbed by, hmmm, Intel). From Intel, I can choose from one FPGA. At least the Atom offers different speed-grades... So, if I just want to add just 20 UARTs to my design, the FPGA will be way too large/expensive. For some high end number- crunching-support, or integrating a lot of south-bridge-functionality, it might still be too small. - To use the Atom, in the end you have to design a PC. I doubt there are many designers out there having experience with this (dealing with BIOS, etc.), it will be quite some design-effort. Projects with that size are typically cost-critical and will try to find cheaper solutions. The other option is to use this Atom+FPGA as a module (like the Qseven Atom-modules) which takes away a lot of design effort from the product developer. (There is already one available: http://de.kontron.com/products/boards+and+mezzanines/pc104+sbc+and+peripherals/microspace+pc104+cpus/msmst.html. Not sure how to connect e.g. a DDR2-SDRAM to the FPGA. The headers do not look very promosing...) (But as easily a module-manufacturer could integrate any FPGA on an Atom-module, no need to use the Intel-combo) - It is possible to integrate a soft-core-CPU that runs uC-Linux in a $10 FPGA. FPGA-Products with Cortex A9 are on the roadmap of Altera and I think also Xilinx (no idea about pricing yet, may be even more expensive...) Then there is also the option of using a Cortex-A8-CPU with many peripherals (or any other) + a FPGA. This will be the solutions that Intel has to compete with, both with pricing and also power-consumption. - In the past, Hard-Core-CPU + FPGA-combinations from Altera and Xilinx were no success. - Doubts if this product from Intel has a future, if they are really serious with it in the long term, may customers keep away from using it. I am curios how this develops. I think the module-solution, where you get a quite big FPGA for an attractive price, will be the most interesting thing. For this applications, pricing is not that critical, development should be easy/quick. But I am not sure if this market is large enough to satisfy Intel in the long term... Thomas www.entner-electronics.com P.S.: Sorry for cross-posting, but I think this is interesting for both newsgroups.Article: 149776
"RCIngham" <robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> writes: > Does your P&R tool run on a 64-bit OS? Can you afford the licence? Running Altera Quartus or Xilinx ISE P&R under 64-bit Linux does not cost any more than a 32-bit Windows license? Or are you thinking of the free downloadable version vs. the full version of the tools? The free tools only support the low end devices where you probably don't need the extra memory, at least for now... Petter -- .sig removed by request.Article: 149777
>On Nov 23, 9:43=A0am, Chris Maryan <kmar...@gmail.com> wrote: >> On Nov 22, 2:19=A0pm, "dila77" <dila77@n_o_s_p_a_m.live.com> wrote: >> >> >> >> > Hi, >> > please, how can I find out the minimum clock period (the maximum clock >> > frequency in MHz) of a combinational circuit (for example, for a full >> > adder) ? >> > After the synthesizing and implementation I got the following message: >> >> > Clock Information: >> > ------------------ >> > No clock signals found in this design >> > Asynchronous Control Signals Information: >> > ---------------------------------------- >> > No asynchronous control signals found in this design >> > Timing Summary: >> > --------------- >> > Speed Grade: -4 >> > =A0 =A0Minimum period: No path found >> > =A0 =A0Minimum input arrival time before clock: No path found >> > =A0 =A0Maximum output required time after clock: No path found >> > =A0 =A0Maximum combinational path delay: 9.033ns >> >> > Is there any way to know the minimum clock period ? >> >> > Thanks :) >> >> > --------------------------------------- =A0 =A0 =A0 =A0 >> > Posted throughhttp://www.FPGARelated.com >> >> You likely have no flip-flops in your design - i.e. you wrote >> something like >> begin >> =A0 Y <=3D A + B; >> end >> clock frequency is driven by the maximum amount of time required to >> get from one FF to another. What you probably want to do is put an FF >> on your inputs (A and B), and your output (Y), all clocked by the same >> clock signal. >> >> Alternatively, the maximum data rate through your adder is the >> reciprocal of the max combinatorial delay - but this essentially >> assumes there are ideal FFs on the input and output and that setup and >> hold times are met. >> >> Welcome to the wonderful world of digital logic. >> >> Chris > >But also note that the delay listed in the synthesis report is only >approximate, and if your design has nothing else in it, it represents >a pin to pin delay including the input and output buffers. The >actual delay through a combinatorial adder inside the chip will >be much less than the reported 9 ns. > >-- Gabor > thanks a lot for your replies :) actually I have an assignment (or you can say a small project). I have to compare between many types of adders (Ripple carry adder, carry skip adder, carry lookahead adder, parallel prefix adder) in terms of delay and area. So I'm confused how to do it, should I program it using the structural mode in VHDL or should I use a clk signal to know the delay of each of them. I'm a beginner in VHDL and I'm not sure how to do it? Can anyone please tell me what's the best way to find out the delay of each adder?? Thanks a lot --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149778
> >thanks a lot for your replies :) > >actually I have an assignment (or you can say a small project). I have to >compare between many types of adders (Ripple carry adder, carry skip adder, >carry lookahead adder, parallel prefix adder) in terms of delay and area. >So I'm confused how to do it, should I program it using the structural mode >in VHDL or should I use a clk signal to know the delay of each of them. >I'm a beginner in VHDL and I'm not sure how to do it? > >Can anyone please tell me what's the best way to find out the delay of each >adder?? > >Thanks a lot > I think that this is the wrong group to be posting to. Try comp.homework.freehelpwanted ;-) --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149779
"Thomas Heller" <theller@ctypes.org> wrote in message news:8ks9nqF329U1@mid.individual.net... > How are you doing prototyping with BGA packages? FPGA's I would prototype on an eval board. I don't use these myself, but look at http://www.emulation.com/ They may have some sockets that could just squeeze in.Article: 149780
Thomas Entner wrote:
> Not sure how to connect e.g. a DDR2-SDRAM to the FPGA.
There is no problem. You can connect it even to an el cheapo Spartan FPGA.
The only issue might be with the supply voltage -- you must reserve an
entire bank to match your memory chip's ratings, which can be a problem
in low pin devices.
> FPGA-Products with Cortex A9 are on the roadmap of Altera
> and I think also Xilinx
Which IMHO would be even better than x86.
> - In the past, Hard-Core-CPU + FPGA-combinations from Altera and
> Xilinx were no success.
I don't think the Virtex family is a failure.
> I am curios how this develops. I think the module-solution, where you
> get a quite big FPGA for an attractive price, will be the most
> interesting thing.
Yeah... the project may end up as a big, cheap FPGA with a built-in
x86-based bootloader. :D
Best regards
Piotr Wyderski
Article: 149781
> Instead of (rising_edge(clk)) I had used ('1' = clk).
Do you type in all your code?
I have a template set up so Ctrl-P inserts a 'standard' synchronous process
to save time and cut down this sort of problem.
Nial.
Article: 149782On Tue, 23 Nov 2010 11:47:12 +0000, Nial Stewart wrote: > Tis exactly the sort of situation the 1 pin interface was designed > for... > > http://www.1pin-interface.com/ > > All you need is one unused FPGA pin routed to a header (with a ground) > to give bi-directional control and status to the FPGA. > > If you're loading a custom debug build you can use any exisitng header > pin that has a fairly local GND. Shame my budget won't stretch to another £100+ debug pod.. that looks perfect for the DiscFerret ATE :( Anyway, I tracked down the problem -- the PLL isn't running. At all. ExtClkIn is toggling at 20MHz as it's supposed to, but the PLL never locks. All the internal logic runs off the PLL, including the Parallel Master Port. No PLL means no clock, no PMP function, basically "He's DEAD, Jim!" Now I need to figure out why I have two EP2C8As with dead PLLs. Then replace them. Those things are a pig to desolder, even with a hot-air station... -- Phil. usenet10@philpem.me.uk http://www.philpem.me.uk/ If mail bounces, replace "10" with the last two digits of the current yearArticle: 149783
On Nov 24, 12:03=A0am, Thomas Entner <thomas.ent...@entner- electronics.com> wrote: > I am mainly refering to:http://www.techfocusmedia.net/embeddedtechnologyj= ournal/feature_artic... > > I think there will be some market for such a device, especially in the > medical and industrial control market, maybe also networking. In fact > we did already design a board with an FPGA connected to a Qseven Atom > module by PCIe. Also I think, that $72 is a reasonable price for that > kind of FPGA (so the Atom is really almost for free, if it is not even > "negative" priced...) > > But I think there are some "buts": > - There are 3 main (new) families of FPGAs from Altera (low-, mid- and > high-end), all with some "sub-families" and a lot of different family- > members varying in size (and price) dramatically. The same is with > Xilinx, Lattice and Actel (ehm... Microsemi). And then there are some > newcomers (e.g. Achronix, which is fabbed by, hmmm, Intel). From > Intel, I can choose from one FPGA. At least the Atom offers different > speed-grades... So, if I just want to add just 20 UARTs to my design, > the FPGA will be way too large/expensive. For some high end number- > crunching-support, or integrating a lot of south-bridge-functionality, > it might still be too small. > - To use the Atom, in the end you have to design a PC. I doubt there > are many designers out there having experience with this (dealing with > BIOS, etc.), it will be quite some design-effort. Projects with that > size are typically cost-critical and will try to find cheaper > solutions. The other option is to use this Atom+FPGA as a module (like > the Qseven Atom-modules) which takes away a lot of design effort from > the product developer. (There is already one available:http://de.kontron.= com/products/boards+and+mezzanines/pc104+sbc+and+pe.... > Not sure how to connect e.g. a DDR2-SDRAM to the FPGA. The headers do > not look very promosing...) (But as easily a module-manufacturer could > integrate any FPGA on an Atom-module, no need to use the Intel-combo) > - It is possible to integrate a soft-core-CPU that runs uC-Linux in a > $10 FPGA. FPGA-Products with Cortex A9 are on the roadmap of Altera > and I think also Xilinx (no idea about pricing yet, may be even more > expensive...) Then there is also the option of using a Cortex-A8-CPU > with many peripherals (or any other) + a FPGA. This will be the > solutions that Intel has to compete with, both with pricing and also > power-consumption. > - In the past, Hard-Core-CPU + FPGA-combinations from Altera and > Xilinx were no success. > - Doubts if this product from Intel has a future, if they are really > serious with it in the long term, may customers keep away from using > it. > > I am curios how this develops. I think the module-solution, where you > get a quite big FPGA for an attractive price, will be the most > interesting thing. For this applications, pricing is not that > critical, development should be easy/quick. But I am not sure if this > market is large enough to satisfy Intel in the long term... > > Thomas > > www.entner-electronics.com > > P.S.: Sorry for cross-posting, but I think this is interesting for > both newsgroups. So Stellarton is basically a product that is the optimal choice for almost no application, almost always too small, or too expensive. So why did Intel have this one built? Who ordered it? Which is the One Single App where an Atom E and 60 000 fpga gates is the optimal combination? - Jan T=E5ngring, journalistArticle: 149784
Here's a head-scratcher. I have five boards with an Altera EP2C8AT144 FPGA and a Microchip PIC18F85J50 installed. Specifically, these are DiscFerrets: <http:// www.discferret.com>. Two of these boards have an "issue". The PLL won't work. At all. The LOCKED output stays low, and there's absolutely nothing on the clock output. Does anyone have any ideas why the PLLs might behave like this? As near as I can tell (based on a continuity and voltage check with a DMM), the PLL VCCs and grounds are all OK. Bypassing consists of a 10nf X7R on every Vcc or Vcore pin (yes, every single one!) plus a 100uF on the output of the SMPSU. There are also several 100nF capacitors on the same rail a few inches away, decoupling the power for the PIC. Thanks, -- Phil. usenet10@philpem.me.uk http://www.philpem.me.uk/ If mail bounces, replace "10" with the last two digits of the current yearArticle: 149785
Morten Leikvoll <mleikvol@yahoo.nospam> wrote: > "Thomas Heller" <theller@ctypes.org> wrote in message > news:8ks9nqF329U1@mid.individual.net... > > How are you doing prototyping with BGA packages? > FPGA's I would prototype on an eval board. > I don't use these myself, but look at http://www.emulation.com/ > They may have some sockets that could just squeeze in. Normally you prototype some circuit, where the FPGA is only soure and sink of data, with many connectins to the fpga. Using some FPGA prototype board means designing two time, first with the prototype board, then with the fpga on board... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 149786
> Shame my budget won't stretch to another £100+ debug pod.. I'd like to be selling it a bit cheaper but the volumes are prototype quantities, even the enclosure is > £10 per unit. The interface voltage is configurable so it can be used on any future FPGA board you design. The 'marketing' angle is that compared to your time it isn't that expensive, if you save an hour on three projects it's paid for itself. > that looks perfect for the DiscFerret ATE :( Eh? > Anyway, I tracked down the problem -- the PLL isn't running. At all. > ExtClkIn is toggling at 20MHz as it's supposed to, but the PLL never > locks. All the internal logic runs off the PLL, including the Parallel > Master Port. No PLL means no clock, no PMP function, basically "He's > DEAD, Jim!" > > Now I need to figure out why I have two EP2C8As with dead PLLs. Then > replace them. Those things are a pig to desolder, even with a hot-air > station... This isn't a problem I've seen in any of my designs so I'm afraid I can't offer any words of wisdom. Have you scoped your supply rails? I'd be careful to track down the problem so you know it isn't that something is marginal though. You don't want more units to start failing in the field. Nial.Article: 149787
> With 32-bit Windows, the maximum amount of RAM that the system can use is > no more than 4Gbyte. This PC has 3Gbyte. > > Does your P&R tool run on a 64-bit OS? Can you afford the licence? A great way to test your ram limits, as I found out, is to run Xilinx' SmartXplorer. It will run on as many processor cores as you specify, in parallel, and run through several iterations of map and par strategies, all the while collecting the statistics and timing scores so that you can select the best for a particular design (it may even stop when it reaches TS=0 if you tell it). With my i7 cpu running at 2.67G with 9G ram on a V5 SX240T design, I configured SmartXplorer to use 4 cores, since that's what my CPU has. Right away, it starts mapping four different strategies at the same time. As it "loads" the design into ram, I can see my ram utilization start creeping ever so high before it starts pushing the very limits, although the CPU usage wasn't nearly as taxing. I'm closing applications to make room, but I realize from all the "noise" I hear from my workstation hard drive activity (I think the term is 'thrashing') that I either (a) need more ram, or (b) need to specify less cores. Realizing that it could take days to complete if I let it continue to be encumbered by hard drive accesses, I re-started SmartXplorer with two cores, and it hummed along quietly, finishing up in several hours (not days). In my search for a memory upgrade, I realize that this particular system is limited to 16G ram because of the OS (Windows 7 Home Premium 64-bit). From what kkoorndyk stated about Xilinx recommendations, I'm going to need an OS upgrade if I want to handle semi-packed V6 designs completely in ram. Sigh. JohnArticle: 149788
On Nov 24, 8:40=A0am, jc <jcappe...@optimal-design.com> wrote: > > With 32-bit Windows, the maximum amount of RAM that the system can use = is > > no more than 4Gbyte. This PC has 3Gbyte. > > > Does your P&R tool run on a 64-bit OS? Can you afford the licence? > > A great way to test your ram limits, as I found out, is to run Xilinx' > SmartXplorer. It will run on as many processor cores as you specify, > in parallel, and run through several iterations of map and par > strategies, all the while collecting the statistics and timing scores > so that you can select the best for a particular design (it may even > stop when it reaches TS=3D0 if you tell it). > > With my i7 cpu running at 2.67G with 9G ram on a V5 SX240T design, I > configured SmartXplorer to use 4 cores, since that's what my CPU has. > Right away, it starts mapping four different strategies at the same > time. As it "loads" the design into ram, I can see my ram utilization > start creeping ever so high before it starts pushing the very limits, > although the CPU usage wasn't nearly as taxing. I'm closing > applications to make room, but I realize from all the "noise" I hear > from my workstation hard drive activity (I think the term is > 'thrashing') that I either (a) need more ram, or (b) need to specify > less cores. Realizing that it could take days to complete if I let it > continue to be encumbered by hard drive accesses, I re-started > SmartXplorer with two cores, and it hummed along quietly, finishing up > in several hours (not days). In my search for a memory upgrade, I > realize that this particular system is limited to 16G ram because of > the OS (Windows 7 Home Premium 64-bit). From what kkoorndyk stated > about Xilinx recommendations, I'm going to need an OS upgrade if I > want to handle semi-packed V6 designs completely in ram. Sigh. > > John Check out the Xilinx site for their recommendations on system specs: http://www.xilinx.com/ise/products/memory.htm http://www.xilinx.com/ise/ossupport/index.htm Note the memory requirements for the SX240T device: 3.7GB typical, 5.5GB peak --> times 4 when running smartXplorer using all 4 cores =3D 15-20GB! That's likely why you heard so much crunching from the HDD.Article: 149789
> Two of these boards have an "issue". The PLL won't work. At all. The > LOCKED output stays low, and there's absolutely nothing on the clock > output. How are you implementing the PLLs? ISTR that you can have a reset input (that I don't usually use). You haven't left this in have you? > Does anyone have any ideas why the PLLs might behave like this? > As near as I can tell (based on a continuity and voltage check with a > DMM), the PLL VCCs and grounds are all OK. On the web site you say... "This power supply is designed to bring up the 1.2V supply first: this is the core voltage for the FPGA, and it is essential that this be stable before the 3.3V I/O power supply is started." Are you sure about this, Altera devices aren't usually fussy about power sequencing but there _are_ some requirements about total power on delay (if I remember correctly). Can you remove the power on delays and just let everything come up as quickly as possible on one of these boards to see if that makes any difference? Are the devices getting at all hot? Nial.Article: 149790
jc <jcappello@optimal-design.com> writes: > A great way to test your ram limits, as I found out, is to run Xilinx' > SmartXplorer. It will run on as many processor cores as you specify, I did run something which was an earlier version of SmartXplorer on Solaris probably 10 years ago. In addition to running P&R's on a multicore CPU you could also run on multiple hosts (actually to run on multicore you specified the machine name multiple times using different casing). I ran the tool mostly across multiple machines as it scaled better in terms of memory cost. It was much cheaper to fit a set of smaller machines with a smaller amount of memory than to upgrade the big servers. I haven't used SmartXplorer so I don't know if you can run on multiple hosts. > in several hours (not days). In my search for a memory upgrade, I > realize that this particular system is limited to 16G ram because of > the OS (Windows 7 Home Premium 64-bit). From what kkoorndyk stated According to http://www.xilinx.com/ise/ossupport/index.htm Windows 7 will not be fully supported until ISE 13. > about Xilinx recommendations, I'm going to need an OS upgrade if I > want to handle semi-packed V6 designs completely in ram. Sigh. Upgrade to Linux... Petter -- .sig removed by request.Article: 149791
Hello everyone! For 10 month I am working on a c++ library for reading and interpreting bitstream files, which are used to configure Xilinx FPGAs belonging to the different virtex families. In short, my library is capable of: - open bitstream files, and interpret them to yield their raw configuration data (which would be written into the configuration SRAM of the FPGA if configured the normal way), i.e. the configuration frames. - interpret the so gathered configuration data again, yielding a netlist specifying the used ressources on the FPGA and the nets connecting them. I did this mainly for virtex 5, but it should be possible for all virtex families. I would like to share this library with public (as the guys from ulogic did with debit). My question regarding this: Can I put the source code (.cpp and .hpp files) of my library (all written by me), along with its documentation (also by me...) online under a GPL license? Or can i get in legal troubles with xilinx? i did not reverse engeneer any of their tools, just used the info public available from ulogic and the xilinx public documentation; and some test bitstreams along with their xdl files. Maybe some guys from xilinx are also here and can shed some light on this? Regards, Florian --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149792
One knows that our life seems to be high priced, however we need cash for different issues and not every man earns enough money. Therefore to receive quick <a href="http://bestfinance-blog.com/topics/personal-loans">personal loans</a> and just commercial loan would be good solution.Article: 149793
On Wed, 24 Nov 2010 15:31:01 +0000, Nial Stewart wrote: >> Two of these boards have an "issue". The PLL won't work. At all. The >> LOCKED output stays low, and there's absolutely nothing on the clock >> output. > > How are you implementing the PLLs? Input, two clock outputs, and a LOCKED output. No reset input, all built with the MegaFunction Builder. Input is 20MHz, outputs are 32MHz on OUT0 and 80MHz on OUT1. > "This power supply is designed to bring up the 1.2V supply first: this > is the core voltage for the FPGA, and it is essential that this be > stable before the 3.3V I/O power supply is started." > > Are you sure about this, Altera devices aren't usually fussy about power > sequencing but there _are_ some requirements about total power on delay > (if I remember correctly). This is a relic from when I was designing around another part which did require that 1V2 come up before VIO. If VIO came up before 1V2, the part let out the magic smoke. Shoddy development tools and poor availability ended my love affair with that part (though it was marginally little cheaper than the Cyclone2)... > Can you remove the power on delays and just let everything come up as > quickly as possible on one of these boards to see if that makes any > difference? Not easily. I'd have to perform microsurgery on a few 7mil pitch tracks around the power controller chip. There's only a few mm of clearance around that thing -- it's just about possible to replace with hot air, or get a piece of solder wick in to clear a bridged pad... > Are the devices getting at all hot? No. Nothing on the board is running at above ambient (they're cold to the touch). Utilisation on the FPGA is in the high single-digit percentage points, though -- only 8% of the LEs (654 of 8256) are in use. Thanks, -- Phil. usenet10@philpem.me.uk http://www.philpem.me.uk/ If mail bounces, replace "10" with the last two digits of the current yearArticle: 149794
On Nov 24, 12:28=A0pm, Philip Pemberton <usene...@philpem.me.uk> wrote: > > No. Nothing on the board is running at above ambient (they're cold to the > touch). Utilisation on the FPGA is in the high single-digit percentage > points, though -- only 8% of the LEs (654 of 8256) are in use. > The only thing that should stop the PLLs are: - Power (check with a scope too at the pin of the part, not just with a DMM just in case) - Clock (again, check at the pin) - Bitstream not getting loaded correctly (Do the configuration control and status signals all look proper?) - Held in reset - Bum parts KJArticle: 149795
On Nov 23, 5:00=A0pm, "Roger" <rogerwil...@hotmail.com> wrote: > The latest Xilinx PlanAhead seems to do everything that a project needs f= rom > VHDL input to bit stream. So what's ISE for now? > > Thanks, > Rog. My understanding is that the plan is for PlanAhead to replace ISE. Though I'm not sure at what point this will happen. ChrisArticle: 149796
Thanks everyone for your answers Looks like Linux and more ram is the best way to go...Article: 149797
dila77 <dila77@n_o_s_p_a_m.live.com> wrote: > please, how can I find out the minimum clock period (the maximum clock > frequency in MHz) of a combinational circuit (for example, for a full > adder) ? > After the synthesizing and implementation I got the following message: Put a register before and after the block you want times, and have the tools find the fastest clock for that system. That works as a first approximation, but isn't perfect, as it could includes much routing that you would not want in the timing, especially if your device (even if you aren't loading into an actual FPGA) might be way too big. You could try with two latches on each side, such that two would configure close to the actual logic, and two on the IOBs. Verify that the two are actually close, such that the timing is close. The actual result will depend on how they are configure into a real design. The above shouldn't be so far off, if you want to build systolic array processors. You could do a series of adders and registers for each test, maybe enough to fill up an FPGA to about half full. (As it gets fuller, the routing will be less optimal.) -- glenArticle: 149798
On Nov 24, 6:15=A0am, "Nial Stewart"
<nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote:
> > Instead of (rising_edge(clk)) I had used ('1' =3D clk).
>
> Do you type in all your code?
>
> I have a template set up so Ctrl-P inserts a 'standard' synchronous proce=
ss
> to save time and cut down this sort of problem.
I wish I had a smart(er) editor that understood VHDL a bit more. I
have some search/replace regex strings I copy and paste from one file
to another which change an entity port list into a port map or a
signal list. This helps with the tedium of instantiation.
I've never worried about the sync process before because I haven't
made a mistake like this without it showing up in the simulation.
That is the interesting part. With the way a simulation works,
comparing the clock to '1' gives exactly the same results as
rising_edge. Given the function of the sensitivity list, it seems
like the rising_edge function should be redundant. I believe it
includes some logic to only return true if the preceding state was a
'0' or 'L' rather than just any other value than '1'. I suppose a =3D
'1' simulation would not work the same triggering on a change from 'H'
to '1' as well as the others.
I'm not likely to forget this and even if I make the same mistake,
I'll likely catch it when I check the compile warnings...
But to answer your question, no, I use CodeWright and I could define
some macro to copy some text into the code, but it wouldn't be at the
correct indentation level. To do that would require getting to know
CodeWright far too well. I keep saying some day I'll look into
switching to... (insert your favorite editor here). I think EMACS is
the one I've heard the most about.
Rick
Article: 149799On Wed, 24 Nov 2010 09:40:29 -0800, KJ wrote: > The only thing that should stop the PLLs are: - Power (check with a > scope too at the pin of the part, not just with a DMM just in case) Ah HA! I just found high-resistance (i.e. "dry") solder joints on the PLL VCC lines. Resoldered, and the PLLs are running. Now I just have a dozen or so RAM Address Line Fault errors to resolve (i.e. flux the pins up good 'n' proper, and hit the little SOBs with a soldering iron). Well, it's one for the "possible faults" list at least. -- Phil. usenet10@philpem.me.uk http://www.philpem.me.uk/ If mail bounces, replace "10" with the last two digits of the current year
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