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I've made changes to my main.c file in SDK but the debugger acts as if it hasn't been changed. The debugger isn't stopping at the correct breakpoints either. I've tried everything I can think of. Can someone give me a suggestion? Thanks, DeWayneArticle: 149251
> >One obvious thing that can happen when you put a lot of logic in an >FPGA >is that the core power supply might not be strong enough to source the >required dynamic power. You can get an estimate of the power >requirements >using Xpower and make sure your power source can handle the current. >You can also put an oscilloscope on the Vccint near an FPGA pin or >ball, >and trigger on a low-going spike. This might either show that your >supply >cannot handle the current (usually when the spike goes very low or >stays >low for a long time) or that you have insufficient bypass caps to >handle >the sudden load increase. Typically right after configuration there >is >a sudden large rise in Vccint supply current requirement. > >One thing you might see when the supply cannot handle the load is >that the FPGA starts up, gets a glitch in internal power, and then >goes back to its power-on reset state due to internal power >monitoring. >Then the power supply comes back up to voltage because in this >state the FPGA again takes much less current. > >Regards, >Gabor > Hi Gabor, I tested the vccint and yeah it goes low when i program the FPGA and my JTAG stops working. But i tested the same design's previous revision on it and it worked perfectly fine. Vccint didn't go low. So i reevaluated my design and well the design that didn't work was hierarchical i.e. i made a partition in it and the design that has worked is Flat design i.e. without partitions. I don't know whether the design is hierarchical or flat matters or not. And well logically the Vccint shouldn't go low. Also i analyzed the design using xPower analyzer and it didn't give me any alarming situation. So can you think of any reason for this behaviour ? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149252
> >I don't know whether the design is hierarchical or flat matters or not. And >well logically the Vccint shouldn't go low. > Did you increase the amount of logic in the design? More power is usually the result of: - more outputs switching - more flip-flops toggling - faster clocks - clocks driven further around the inside of the chip --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149253
I'm integrating MIG generated core with big, formerly written and debugged design. The problem however is that the old design heavily relies on automatic generation of I/O buffers, while the MIG generated core requires the "-iobuf" option to be switched off. Is it possible to selectively switch off the automatic inferrence of the I/O buf for paticular signals (those provided by MIG generated core?). -- TIA, WojtekArticle: 149254
Hi all, I am new FPGA. I have input data stored in a txt file. i have to read data from file to FPGA for further processing. How do i store this value in to FPGA memory. Please help me. Thanks in advance --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149255
>> >>I don't know whether the design is hierarchical or flat matters or not. >And >>well logically the Vccint shouldn't go low. >> > >Did you increase the amount of logic in the design? > >More power is usually the result of: >- more outputs switching >- more flip-flops toggling >- faster clocks >- clocks driven further around the inside of the chip > > > >--------------------------------------- No i didn't. Only changed the design from flat to hierarchical.And my design is running at a clock speed of 125Mhz. My regulator can source upto 2.9A current. i don't think FPGA requires this much current, does it ? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149256
Hello,
I'm trying to use an IOBUFBS together with bidirectional IODELAYE1 and
IDDR und ODDR in a XC6VLX240T for a special DDR3 application.
When I connected the four primitives as described in the Virtex-6
Select IO User Guide I get an error from map (ISE12.2):
---
ERROR:Pack:2531 - The dual data rate register
"ddr3_controller_inst/G_lane[0].ODDR_dqs_t" failed to join the
"OLOGICE1"
component as required. The output signal for register symbol
ddr3_controller_inst/G_lane[0].ODDR_dqs_t requires general routing
to fabric,
but the register can only be routed to ILOGIC, IODELAY, and IOB.
---
If I use a (single ended) IOBUF instead of the IOBUFDS everything
works fine. I also tried the Select IO Generator which produced the
same connections and thus the same error is produces by map. Here my
code:
---
ODDR_dqs_o: ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "SYNC"
)
port map (
Q => dqs_o,
C => clk_400,
CE => '1',
D1 => dqs_o_a,
D2 => dqs_o_b,
R => '0',
S => '0'
);
-------------------------------
ODDR_dqs_t: ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "SYNC"
)
port map (
Q => dqs_t,
C => clk_400,
CE => '1',
D1 => dqs_t_a,
D2 => dqs_t_b,
R => '0',
S => '0'
);
-------------------------------
IODELAYE1_dqs: IODELAYE1
generic map (
CINVCTRL_SEL => FALSE,
DELAY_src=> "IO",
HIGH_PERFORMANCE_MODE => TRUE,
IDELAY_TYPE => "VAR_LOADABLE",
IDELAY_VALUE => 0,
ODELAY_TYPE => "VAR_LOADABLE",
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => 200.0,
SIGNAL_PATTERN => "DATA"
)
port map (
CNTVALUEOUT => open,
DATAOUT => dqs_i,
C => clk_400,
CE => '0',
CINVCTRL => '0',
CLKIN => 'Z',
CNTVALUEIN => dqs_lane,
DATAIN => 'Z',
IDATAIN => dqs_x,
INC => '0',
ODATAIN => dqs_o,
RST => dqs_lane_wr,
T => dqs_t(l)
);
-------------------------------
IOBUFDS_dqs: IOBUFDS
port map (
O => dqs_x,
IO => ddr_dqsp,
IOB => ddr_dqsn,
I => dqs_i,
T => dqs_t
);
---
Has anyone an idea how I get things to work?
Regards,
Michael
Article: 149257On Oct 9, 12:55=A0pm, Ulf Samuelsson <u...@notvalid.atmel.com> wrote: > Peter Alfke skrev: > > > On Oct 4, 7:27 pm, rickman <gnu...@gmail.com> wrote: > > >> Rick > > >> PS =A0I use the computer format for dates 20101004 or preferred 101004= , > >> at least in my code. > > > Rick, your sequence is also the official method used in Sweden. > > Yes, but it is actually an International Standard (ISO 8601). > You would normally write "2010-10-04" for readability. > "10-10-04" risk wraparound problems. Not in my lifetime! Six digits works just fine for my needs. I don't expect any of my code to survive for 90 more years either. > All Swedish citizens (and Companies) get a personal number: > "YYMMDD-XXXX" where YYMMDD is birthdate, and XXXX makes > the number unique. > > We have elderly people that get advertisement for baby stuff > after they reach 100+, since year is only two numbers. Depending on the dental care in Sweden they may be ready for baby food again. ;-) > The system copes with that, since your number changes to > "YYMMDD+XXXX" once you'r past 100, but it is rarely used > and many/most applications does not allow > you to feed in the "+" sign. So their systems have a "negative" attitude towards age? RickArticle: 149258
Any one who can give me VHDL code for text dynamic huffman Encoder/Decoder? Thanks --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149259
On Oct 12, 7:29=A0am, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > >>I don't know whether the design is hierarchical or flat matters or not. > >And > >>well logically the Vccint shouldn't go low. > > >Did you increase the amount of logic in the design? > > >More power is usually the result of: > >- more outputs switching > >- more flip-flops toggling > >- faster clocks > >- clocks driven further around the inside of the chip > > >--------------------------------------- =A0 =A0 =A0 =A0 =A0 =A0 > > No i didn't. Only changed the design from flat to hierarchical.And my > design is running at a clock speed of 125Mhz. > > My regulator can source upto 2.9A current. i don't think FPGA requires th= is > much current, does it ? =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com Which FPGA? What is the voltage? A Virtex 5 with its 1V Vccint can use more than 3 amperes if heavily loaded. How much Vccint did Xpower report? How big are your bypass caps on Vccint? Are you sure that when you re-ran the design without hierarchy that you didn't lose your .ucf file associations? Placing the pins randomly can certainly cause power draw problems. Regards, GaborArticle: 149260
Brian This might appear twice as I had a posting error. The Broaddown3 and Broaddown5 don't have much documentation on the website as yet but here are the outline details: Broaddown3 - PCIe (X4/X8) with XC6SLX75T as interface and controller + 2 x 2 array of Virtex-6 FPGAs in the FFG784 package. There is also DDR3 memory available to the array and 2 Gigabit Ethernet also from the controller FPGA. This product is aimed at HPC markets. Broaddown5 - As Broaddown3 except FPGA array is replaced with a monster XC6VLX760. This has a big I/O count around it and is aimed at ASIC prototyping. There are some of these details in one of the newsletters. The website should get some proper pages for these products before too long. John Adair Enterpoint Ltd. On 11 Oct, 11:04, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Mon, 11 Oct 2010 02:30:44 -0700 (PDT), John Adair <g...@enterpoint.co.uk> > wrote: > > >To some extent we can already do this with our Ethernet add-on > >modules. There is a plan for a Gigabit add-on module as well but no > >timescale on that as yet. > > >In the higher performance area our Broaddown3 and Broaddown5 that are > >just going into production have Gigabit capability built in. > > These don't appear to be on the website ... is there any information about them > yet? > > - BrianArticle: 149261
> My regulator can source upto 2.9A current. i don't think FPGA requires > this > much current, does it ? Note, if you are using LDO regulators, some of the fast ones can be very sensitive to noise if implemented bad. I've seen one [LP3966 from National to be specific] stop because of a closeby SMPS got started.Article: 149262
> >Which FPGA? What is the voltage? A Virtex 5 with its 1V Vccint can >use more >than 3 amperes if heavily loaded. How much Vccint did Xpower report? >How >big are your bypass caps on Vccint? Are you sure that when you re-ran >the >design without hierarchy that you didn't lose your .ucf file >associations? Placing >the pins randomly can certainly cause power draw problems. > >Regards, >Gabor > Hi Gabor, I am using spartan 3 xc3s4000 FPGA and vccint before programming is 1.25V and after programming it drops to 720mv. Xpower reported these things : Supply Source | Supply Voltage | Total Current (mA) | --------------------------------------------------------------------------------------------------------------- | Vccint | 1.20 | 113.80 | Vccaux | 2.50 | 55.00 My bypass cap is 100uF. And yeah i am sure i didn't lose the ucf file. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149263
On Oct 11, 7:35=A0pm, "heedaf" <digitalhomesolutions@n_o_s_p_a_m.q.com> wrote: > I've made changes to my main.c file in SDK but the debugger acts as if it > hasn't been changed. The debugger isn't stopping at the correct breakpoin= ts > either. I've tried everything I can think of. Can someone give me a > suggestion? > > Thanks, > > DeWayne Hi DeWayne, The Eclipse-based SDK environment takes some getting used to. Here's some general tips that might help avoid some frustration: - Make sure that your current build configuration matches what you are intending to debug (not always obvious) - Make sure compiler flags are set correctly - Sometimes the SDK needs to be rebooted ... HTH, MBArticle: 149264
On Oct 11, 12:16=A0pm, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > Hi, > I have a weird problem with my design. I am using xilinx 12.1 for its > synthesis and implementation. > The problem is that when i generate my bitstream with a chipscope core > inserted in the design and program my FPGA, programming fails saying that > "DONE did not go high" whereas when i take out the chipscope core or some > signals from the core, programming succeeds but after that my JTAG stops > working. If i try ti initialize JTAG chain in iMPACT it asks me whether i > have a BSDL or BIT file for this device or if i try to run chipscope,it > also gives a warning and doesn't start. I checked the JTAG voltages and > they were fine. > > Rarely does my design work, so, i am kind of stuck here as i cannot debug > my system altogether. Is there something wrong with the Bit file or my us= b > drivers? I tried reinstalling the drivers but didn't work. Then i > reinstalled xilinx 12.1,still same problem. > > Does it happen because of the size of the FPGA and the complexity of the > logic we are inserting in it ? I mean that if the FPGA is not big enough = to > hold the logic and it's a very tigh fit, can it lead to such behaviour ? > > Regards > SalimBaba =A0 =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com I've seen similar behavior with Spartan 2 and Spartan 3 devices where I have to erase the non-volatile memory, then load the FPGA from that empty bitstream before I can then program the FPGA from the JTAG with the new bitstream. It was bitstream dependent. Some images were no problem, while others with minor changes caused trouble. As others have mentioned it could be power supply related although I never managed to catch the problem. kevin It could beArticle: 149265
On Oct 11, 12:16=A0pm, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > Hi, > I have a weird problem with my design. I am using xilinx 12.1 for its > synthesis and implementation. > The problem is that when i generate my bitstream with a chipscope core > inserted in the design and program my FPGA, programming fails saying that > "DONE did not go high" whereas when i take out the chipscope core or some > signals from the core, programming succeeds but after that my JTAG stops > working. If i try ti initialize JTAG chain in iMPACT it asks me whether i > have a BSDL or BIT file for this device or if i try to run chipscope,it > also gives a warning and doesn't start. I checked the JTAG voltages and > they were fine. > > Rarely does my design work, so, i am kind of stuck here as i cannot debug > my system altogether. Is there something wrong with the Bit file or my us= b > drivers? I tried reinstalling the drivers but didn't work. Then i > reinstalled xilinx 12.1,still same problem. > > Does it happen because of the size of the FPGA and the complexity of the > logic we are inserting in it ? I mean that if the FPGA is not big enough = to > hold the logic and it's a very tigh fit, can it lead to such behaviour ? > > Regards > SalimBaba =A0 =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com The OP also has this thread on Xilinx Forums for any interested. http://forums.xilinx.com/t5/Implementation/JTAG-stops-working/td-p/95966 Ed McGettigan -- Xilinx Inc.Article: 149266
On 12 Okt., 13:09, "parvathi69" <parvathi69@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > Hi all, > > I am new FPGA. I have input data stored in a txt file. i have to read dat= a > from file to FPGA for further processing. How do i store this value in to > FPGA memory. > > Please help me. > > Thanks in advance =A0 =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com Hi, With Xilinx XST there's the exeptional feature to read data from a file and store it to a BRAM (used as a ROM) during synthesis. There's an example in the ISE Language Templates. Other synthesis tools may provide this feature too, but it is not standard VHDL. This approach is also just a single shot solution. Because you need to reprogram the chip every time you want to process new data. Can be useful in some cases, though, but the following approach will probably more useful for you: Whenever you have data to process, you normally provide some kind of interface. This can be a simple UART or a full grown network solution. It depends on the features of your target board and on your design skills too. Your data source (e.g. some PC) then can write the data via the interface to the FPGA and read back the results (if needed). Have a nice synthesis EilertArticle: 149267
hi every one. I don't know English very well,so excuse me. I generate core pci express and emplement on board(xc5vfx100t),ofcourse by vendor id=0x10EE ,device id=0x0007 .then plug it to pci express slot(x4). but pc didn't recognize it as a xilinx device. I chenge vendor id= 0x8086, device id=0x2944 and pc recognize it as a xilinx device.but rn_lnk_up_n isn't assert, didn't have clock and I can't work by windriver . in fact when pc recognize it as a new hardware ,it didn't want to install pci express drivers .please help me ucf is: NET "sys_reset_n" LOC = "AH17" | IOSTANDARD = LVCMOS25 | PULLUP | NODELAY NET "sys_clk_p" LOC = "AF4" ; NET "sys_clk_n" LOC = "AF3" ; INST "refclk_ibuf" DIFF_TERM = "TRUE" ; INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" LOC = GTX_DUAL_X0Y2; NST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i" LOC = GTX_DUAL_X0Y1; INST "ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep" LOC = PCIE_X0Y0; --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149268
Hi Everyone, I am designing a system where I am interfacing a Motorolla processor in my system for read and write data. This processor is on the board where my fpga will interact with it. The processor is the master mode always and the salave is my interface design and the fpga. The motoroll Processor will have LBC Local bus controller signals will be comunicating to my interface inside the FPGA. The processor can run at configurable clock of 33 MHz to 133 MHz. The address bus is 24 Bits and tye data bus is 32 bits. I have to design an interface where the control signals from the processor to my interface will be 1. LALE Used for latching address and making is two distict phases as data and address phase. The LALE when HIgh is an Address phase and when Address is low it is Data phase. (From processor to Design ) 2. LWE it is a read and write signal single bit active low. (From processor to Design ) 3. LOE Output enable active low (From processor to Design ) 4. LCS is active low signal from processor to my interface. It is used for selecting the chip/slave chip select 5. LA address 24 bits ( From processor to Design ) 6. LAD data 32 bits (Bidirectional) I am thinking about runing my design at 300 Mhx 3X then the processor LBC clock . The LBC clock is not coming from the processor to my interface in fpga . So in my Interface i dont have the reference clock from the processor and all the above mentioned signals are from Processor to my design except LAD which is bidirectional . I am using 2 flop synchronisers for the control signals and MUX-Latch model for data latching and synchronization across the cock domain . My Confusion is that when we have multiple control signal passing the clock domain . Can we synchronize with 2 flops all the control signals. Shall we use some glue logic to make sure we pass and synchronise only one control signal across the domain and later use this synchronous signal value to select the mux-latch of other control signals that are input to a latch and sampled when we get the synchronized signal. In the scenario like this has anyone used multiple control signals to pass the clock domain throgh individual 2 flop synchronizers for each control lines. I am using 3X clock in the destination clock domain and has ample time to sample the signal in the interface block. Any suggestion ideas will be highly appreciated Thanks VipulArticle: 149269
>> It's unbelievable and different from the asmi_parallel data sheet. >> The data sheet shows that only 3 us is needed after single byte write >> operation. >> So, I'd like to get some advice here what makes unexpected result. >> The signals I give asmi_parallel ip core, the write/wren/addr/data are >> exact. > > >I'd check the data sheet for whatever flash device you're using, that will >be what determines the delay (mostly), not the core. > > > >Nial. > > > Thanks for checking my question. You mean, the Serial Configuration Device determines the speed of writing ? Paul. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149270
A new release of FPGAOptim[1] is available. Highlights of this release include: * Support for 12.x toolchain * Support for S6/V6 devices * EDIF and NGC netlists, so the tool can be used earlier in the design process. Especially useful when you are "overmapped" and don't know why :) * More flexible column headings which will support future devices much more easily. (BTW, our website moved around, so those of you who have downloaded before should be receiving an email with a new link to the installer shortly) Cheers, Martin [1] http://www.conekt.co.uk/capabilities/49-fpga-optim -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardwareArticle: 149271
On 11 Okt., 13:27, Vips <thevipulsi...@gmail.com> wrote: > Hi Everyone, > > I am designing a system where I am interfacing a Motorolla processor > in my system for read and write data. This processor is on the board > where my fpga will interact with it. The processor is the master mode > always and the salave is my interface design and the fpga. > > The motoroll Processor will have LBC Local bus controller signals will > be comunicating to my interface inside the FPGA. > > The processor can run at configurable clock of 33 MHz to 133 MHz. The > address bus is 24 Bits and tye data bus is 32 bits. > > I have to design an interface where the control signals from the > processor to my interface will be > > 1. LALE Used for latching address and making is two distict phases as > data and address phase. The LALE when HIgh is an Address phase and > when Address is low it is Data phase. =A0(From processor =A0to Design ) > 2. LWE it is a read and write signal single bit active low. (From > processor =A0to Design ) > 3. LOE Output enable active low =A0(From processor =A0to Design ) > 4. LCS is active low signal from processor to my interface. It is used > for selecting the chip/slave chip select > 5. LA address 24 bits ( From processor =A0to Design ) > 6. LAD data 32 bits =A0(Bidirectional) > > I am thinking about runing my design at 300 Mhx 3X then the processor > LBC clock . The LBC clock is not coming from the processor to my > interface in fpga . So in my Interface i dont have the reference clock > from the processor and all the above mentioned signals are from > Processor to my design except LAD which is bidirectional . > > I am using 2 flop synchronisers for the control signals and MUX-Latch > model for data latching and synchronization across the cock domain . > > My Confusion is that when we have multiple control signal passing the > clock =A0domain . Can we synchronize with 2 flops all the control > signals. > > Shall we use some glue logic to make sure we pass and synchronise only > one control signal across the domain and later use this synchronous > signal value to select the mux-latch of other control signals that are > input to a latch and sampled when we get the synchronized signal. > > In the scenario like this has anyone used multiple control signals to > pass the clock domain throgh individual 2 flop synchronizers for each > control lines. > > I am using 3X clock in the destination clock domain and has ample time > to sample the signal in the interface block. > > Any suggestion ideas will be highly appreciated > > Thanks > > Vipul Hi, A simpler and always efective approach is to synchronize it _all_ within your FPGA. If you already have one, what for do you need external logic? And make sure of having everything synchronous within the FPGA, otherwise be prepared to fight hard to find and mitigate problems. Regards, JaaCArticle: 149272
On Oct 13, 5:38=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrote: > A new release of FPGAOptim[1] is available. =A0Highlights of this > release include: > > =A0* Support for 12.x toolchain > =A0* Support for S6/V6 devices > =A0* EDIF and NGC netlists, so the tool can be used earlier in the > =A0 =A0design process. =A0Especially useful when you are "overmapped" and > =A0 =A0don't know why :) > =A0* More flexible column headings which will support future devices > =A0 =A0much more easily. > > (BTW, our website moved around, so those of you who have downloaded > before should be receiving an email with a new link to the installer > shortly) > > Cheers, > Martin > > [1]http://www.conekt.co.uk/capabilities/49-fpga-optim > > -- > martin.j.thomp...@trw.com > TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://w= ww.conekt.co.uk/capabilities/39-electronic-hardware Just my $.02 - I would like to see a Linux version. I am so tired of the "looks great, who cares if it works" fluffiness of 'doze. RKArticle: 149273
On Oct 12, 11:23=A0pm, "allahdadian" <nana_nanaiii@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote: > hi every one. > I don't know English very well,so excuse me. > I generate core pci express and emplement on board(xc5vfx100t),ofcourse b= y > vendor id=3D0x10EE ,device id=3D0x0007 .then plug it to pci express slot(= x4). > but pc didn't recognize it as a xilinx device. > I chenge vendor id=3D 0x8086, device id=3D0x2944 and pc recognize it as a > xilinx device.but rn_lnk_up_n isn't assert, didn't have clock and I can't > work by windriver . > in fact when pc recognize it as a new hardware ,it didn't want to install > pci express drivers .please help me > > ucf is: > NET "sys_reset_n" =A0 =A0 =A0LOC =3D "AH17" =A0| IOSTANDARD =3D LVCMOS25 = | PULLUP | > NODELAY > > NET =A0"sys_clk_p" =A0 =A0 =A0 LOC =3D "AF4" =A0; > NET =A0"sys_clk_n" =A0 =A0 =A0 LOC =3D "AF3" =A0; > INST "refclk_ibuf" =A0 =A0 DIFF_TERM =3D "TRUE" ; > INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" LOC= =3D > GTX_DUAL_X0Y2; > > NST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i" LOC = =3D > GTX_DUAL_X0Y1; > INST "ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep" =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 LOC =3D > PCIE_X0Y0; =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com vendor id=3D0x10EE is not Xilinx, so it will not recognize it as a Xilinx device. If the driver is already loaded (it exists in %windir% \system32\drivers, and is enumerated in the driver cache) a new driver will NOT be loaded. Go to the device manager and delete the device, then restart the computer. RKArticle: 149274
On 11 Okt., 14:24, "Mile" <skymoon_h2s@n_o_s_p_a_m.hotmail.com> wrote: > Hello All, > > I am new in this forum. > I would like to ask if there is a way to calculate the SFDR in FPGA. > I have limited resources in the FPGA, so calculating the FFT is not so > preferable. If you know the input frequency, it is extremely likely that one of the first harmonics is the biggest spur. You can use a few sine generators to calculate the fourier coefficients only for these frequencies. (also note, that sin(x)*sin(x) = sin(2x), so you need less generators than you are evaluating frequencies...) If you can spare the time needed and the input signal is stable, you can also sweep the sine generator and compute all fourier coefficients sequentially. Kolja cronologic.de
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