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>Hi, > >I normally use a microcontrollers for my projects - I have used PIC's >and AVR's - I mainly use them for the quick and easy programming etc. >(Arduinos are great!) > >I've come across a case where a microprocessor can't meet my >performance requirements though, but parts of my problem is very >parallel, so an FPGA would be good. The entire thing is too complex >to do all in VHDL or something - I prefer C/C++ for the complex stuff. > >The exact use case is doing some linear arithmetic, using that to >calculate a pointer, and outputting the data at that memory location >serially to an IO device. Throughput needs to be around 3Mbits/sec, >where each bit will require the above operations, but no bit depends >on any other. > >Does any company sell a microprocessor what has a few thousand logic >elements of FPGA "on the side", which can interface fast with the >microprocessor, for example through shared memory. Ideally this would >be cheap (ie. tens of dollars rather than hundreds of dollars), and >easy to use (I don't want to have to be defining my own DMA controller >or something...) > >I know one can implement a CPU on an FPGA, but all the CPU's I can >find seem to be small and slow, and they somehow don't seem to be the >same "point and click" ease of programming an Arduino - they also >require development kits costing thousands of dollars. Also I need it >to be self contained - ie. a chip and maybe a crystal clock. I don't >really want to have to give it 3 regulated power supplies, 2 clocks, >and an external program flash memory and controller. > >Ideas welcome! > >Thanks >Oliver Hi Oliver, SmartFusion would give you what you need, and probably more. The CPU is a 100 MHz ARM Cortex-M3 with a full subsystem (DMA, eNVM, memory controller, SPI/I2C/UART, 10/100 Ethernet, etc.) The A2F200 version has 200,000 system gates (equivalent to 4,608 flip-flops). And a collection of analog blocks (incl. ADCs, DACs and comparators). The Evaluation Kit (A2F-EVAL-KIT) has a list price of $99. From a chip standpoint, I believe this should meet your criteria. The tools are available for free on Actel's website. Regarding the unit pricing posted by some online distributors, the volume pricing is much lower. Our local representative can give you a quote for larger volumes, if you want. I'd love to hear your feedback after you try it. This device is only 6 months old and we're constantly working on making it easier to design with. For this, we welcome user comments. We're very passionate about SmartFusion. And, I hope, like many people already have, you feel the same. Happy design! Christian Plante Director of Marketing Low-Power and Mixed-Signal FPGAs Actel Corp. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149401
On Thu, 21 Oct 2010 17:58:35 -0400, "MM" <mbmsv@yahoo.com> wrote: > >The question still remains why PlanAhead reports a much smaller number of >errors than the Post-Place & Route Static Timing Analysis even though the >top errors are exactly the same... Is there are a hidden limit on the number >of errors reported in PlanAhead, which I can't find? Given the name of the tool, is it reporting a prediction or estimate of the timing errors rather than the actual placed and routed design? If so, use it as guidance in the early stages, but once you have a routed design, ignore it and pay attention to the Post-P&R results instead. The important question is, why is your design not meeting post-P&R timing? One hint: The placement phase starts from a randomised initial placement, and refines it in multiple stages. But sometimes it yields a non-optimal result, with one LUT or FF (or a few) wildly far away from its logical neighbours. This placement is repeatable on subsequent runs. However, the least perturbation to the design can disrupt the initial placement, and destroy a good design, or mend a broken one... Xilinx allow you to change the seed for this placement (via the "-t" switch to MAP and PAR, or a GUI option) and this is a better way to perturb the placement. (You need to supply the same seed, between 1 and 100, to BOTH tools, as of about ISE9 or 10). If your design is close (say 5-10%) to meeting timing, and there is no obvious design problem in the error reports (long carry chains, or FFs that unexpectedly migrated into IOBs or multipliers, and therefore moved a long way from your logic), it is well worth re-running MAP and PAR with a different seed (or a few) before trying anything else. >When I tried running Report Timing from PlanAhead it quietly crashed... :( There are usually ways of quietly crashing the Xilinx tools. Learning how to avoid the minefields (and ideally, reporting them, if they are reproducible) is one of the bigger tasks.Article: 149402
On Oct 21, 8:18=A0pm, "cplante" <christian.plante@n_o_s_p_a_m.actel.com> wrote: > >Hi, > > >I normally use a microcontrollers for my projects - I have used PIC's > >and AVR's - I mainly use them for the quick and easy programming etc. > >(Arduinos are great!) > > >I've come across a case where a microprocessor can't meet my > >performance requirements though, but parts of my problem is very > >parallel, so an FPGA would be good. =A0The entire thing is too complex > >to do all in VHDL or something - I prefer C/C++ for the complex stuff. > > >The exact use case is doing some linear arithmetic, using that to > >calculate a pointer, and outputting the data at that memory location > >serially to an IO device. =A0Throughput needs to be around 3Mbits/sec, > >where each bit will require the above operations, but no bit depends > >on any other. > > >Does any company sell a microprocessor what has a few thousand logic > >elements of FPGA "on the side", which can interface fast with the > >microprocessor, for example through shared memory. =A0Ideally this would > >be cheap (ie. tens of dollars rather than hundreds of dollars), and > >easy to use (I don't want to have to be defining my own DMA controller > >or something...) > > >I know one can implement a CPU on an FPGA, but all the CPU's I can > >find seem to be small and slow, and they somehow don't seem to be the > >same "point and click" ease of programming an Arduino - they also > >require development kits costing thousands of dollars. =A0Also I need it > >to be self contained - ie. a chip and maybe a crystal clock. =A0I don't > >really want to have to give it 3 regulated power supplies, 2 clocks, > >and an external program flash memory and controller. > > >Ideas welcome! > > >Thanks > >Oliver > > Hi Oliver, > > SmartFusion would give you what you need, and probably more. The CPU is a > 100 MHz ARM Cortex-M3 with a full subsystem (DMA, eNVM, memory controller= , > SPI/I2C/UART, 10/100 Ethernet, etc.) The A2F200 version has 200,000 syste= m > gates (equivalent to 4,608 flip-flops). And a collection of analog blocks > (incl. ADCs, DACs and comparators). The Evaluation Kit (A2F-EVAL-KIT) has= a > list price of $99. > > From a chip standpoint, I believe this should meet your criteria. The too= ls > are available for free on Actel's website. > > Regarding the unit pricing posted by some online distributors, the volume > pricing is much lower. Our local representative can give you a quote for > larger volumes, if you want. > > I'd love to hear your feedback after you try it. This device is only 6 > months old and we're constantly working on making it easier to design wit= h. > For this, we welcome user comments. We're very passionate about > SmartFusion. And, I hope, like many people already have, you feel the > same. > > Happy design! > > Christian Plante > Director of Marketing > Low-Power and Mixed-Signal FPGAs > Actel Corp. Yes, the SmartFusion device is interesting, but not practical for many designs due to the cost, >$40. Is the high price because of the inherent complexity of building the part or is the price point set high because it is an early entry in the field and we can expect to see this as a $10 part sometime in the next year or so? At $40 it is more expensive than using separate components and so would only find niche markets. At $10 I have no doubt it would sell like hotcakes... at IHOP! RickArticle: 149403
Someone in a meetup group discussion is suggesting that there is a level of interoperability between different brands of tools for the User Constraint File (UCF). I guess I never thought about it and just assumed they would be proprietary. The Lattice tools are based on the same NeoCAD tools the Xilinx tools ar ebased on, so I am not surprised by some degree of commonality. But are Altera and Actel on the same page? Did they actually do something useful for engineers that might not be in their own best interests? I've seen that the PCB layout tools all have incompatible and mostly binary file formats and have staunchly resisted efforts to change. It would seem they all write converters so you can change to their tool, but they don't like in any way to help you to leave their tool. I would have expected this from the FPGA vendors as well. RickArticle: 149404
Synopsys Design Constraint file seems to be supported by more and more EDA companies. Hans www.ht-lab.com "rickman" <gnuarm@gmail.com> wrote in message news:70bebb4a-15f8-4945-8506-c83cbcd59e1e@u10g2000yqk.googlegroups.com... > Someone in a meetup group discussion is suggesting that there is a > level of interoperability between different brands of tools for the > User Constraint File (UCF). I guess I never thought about it and just > assumed they would be proprietary. The Lattice tools are based on the > same NeoCAD tools the Xilinx tools ar ebased on, so I am not surprised > by some degree of commonality. But are Altera and Actel on the same > page? Did they actually do something useful for engineers that might > not be in their own best interests? > > I've seen that the PCB layout tools all have incompatible and mostly > binary file formats and have staunchly resisted efforts to change. It > would seem they all write converters so you can change to their tool, > but they don't like in any way to help you to leave their tool. I > would have expected this from the FPGA vendors as well. > > Rick >Article: 149405
"Brian Drummond" <brian_drummond@btconnect.com> wrote in message news:dih2c61d7fg70b1l87dgjlp6rrt9rhqv7a@4ax.com... > On Thu, 21 Oct 2010 17:58:35 -0400, "MM" <mbmsv@yahoo.com> wrote: > >> >>The question still remains why PlanAhead reports a much smaller number of >>errors than the Post-Place & Route Static Timing Analysis even though the >>top errors are exactly the same... Is there are a hidden limit on the >>number >>of errors reported in PlanAhead, which I can't find? > > Given the name of the tool, is it reporting a prediction or estimate of > the > timing errors rather than the actual placed and routed design? > > If so, use it as guidance in the early stages, but once you have a routed > design, ignore it and pay attention to the Post-P&R results instead. The name of the tool might be confusing. However, in the latest Xilinx toolset it can used, among other things, for post-P&R timing analysis. And I should add that it has a very nice and convenient interface for that. The errors are not estimates, but the actual routed paths. However, it doesn't display the paths as routed, which is a little annoying. /MikhailArticle: 149406
On Oct 22, 9:38=A0am, "MM" <mb...@yahoo.com> wrote: > "Brian Drummond" <brian_drumm...@btconnect.com> wrote in message > > news:dih2c61d7fg70b1l87dgjlp6rrt9rhqv7a@4ax.com... > > > On Thu, 21 Oct 2010 17:58:35 -0400, "MM" <mb...@yahoo.com> wrote: > > >>The question still remains why PlanAhead reports a much smaller number = of > >>errors than the Post-Place & Route Static Timing Analysis even though t= he > >>top errors are exactly the same... Is there are a hidden limit on the > >>number > >>of errors reported in PlanAhead, which I can't find? > > > Given the name of the tool, is it reporting a prediction or estimate of > > the > > timing errors rather than the actual placed and routed design? > > > If so, use it as guidance in the early stages, but once you have a rout= ed > > design, ignore it and pay attention to the Post-P&R results instead. > > The name of the tool might be confusing. However, in the latest Xilinx > toolset it can used, among other things, for post-P&R timing analysis. An= d I > should add that it has a very nice and convenient interface for that. The > errors are not estimates, but the actual routed paths. However, it doesn'= t > display the paths as routed, which is a little annoying. > > /Mikhail You can see the routing if you open the design in the FPGA editor. You can also cross-probe to the FPGA editor from the post P&R timing report if you use the ISE GUI. FPGA editor also shows delays to each load for a selected net. Regards, GaborArticle: 149407
On Oct 18, 11:44=A0am, Tim Wescott <t...@seemywebsite.com> wrote: > On 10/18/2010 04:13 AM, Anssi Saari wrote: > > > > > Oliver Mattos<omat...@gmail.com> =A0writes: > > >> Does any company sell a microprocessor what has a few thousand logic > >> elements of FPGA "on the side", which can interface fast with the > >> microprocessor, for example through shared memory. =A0Ideally this wou= ld > >> be cheap (ie. tens of dollars rather than hundreds of dollars), and > >> easy to use (I don't want to have to be defining my own DMA controller > >> or something...) > > > Yes, Actel Smartfusion. It's a hard ARM Cortex M3 with hard basic > > peripherals and some programmable logic around that. Also, single 3.3V > > power supply. SW tools are free from Actel or you can buy from IAR or > > Keil. Eval kit is $99. > > > I had a visit from Actel recently, SmartFusion seems very interesting, > > but I've never designed anything with their FPGAs. > > > It's also interesting to note that Xilinx is going to do the same > > thing in their 7 series, hard ARM with hard peripherals ready to go, > > programmable logic around it. > > I remember a point ten years or so ago when we considered the Atmel > FPSLIC (too small, too Atmel), the Altera Cyclone (too Altera), and the > Xilinx part with the embedded PowerPC (too PowerPC). > > We ended up with a plain old Xilinx chip talking to the same little DSP > that we were putting in a bunch of other boards at the same time, with a > nice fast memory-mapped interface. > > So, don't overlook a plain old FPGA (or CPLD even) attached to a plain > old processor with the high-speed interconnect of your choice. Agree 100% I've designed a little dsPIC + Spartan 3A board that loads the FPGA up from a micro SD card: http://members.cox.net/ebrombaugh1/synth/dsPIC_fpga/index.html Uses a relatively fast SPI port for configuration and control, but has an option for a parallel interface as well. Micro SD is DOS FAT formatted so the bitstream is saved on it as a normal file which the dsPIC finds & loads at powerup. EricArticle: 149408
On Oct 17, 2:31=A0pm, Oliver Mattos <omat...@gmail.com> wrote: > Hi, > > I normally use a microcontrollers for my projects - I have used PIC's > and AVR's - I mainly use them for the quick and easy programming etc. > (Arduinos are great!) > > I've come across a case where a microprocessor can't meet my > performance requirements though, but parts of my problem is very > parallel, so an FPGA would be good. =A0The entire thing is too complex > to do all in VHDL or something - I prefer C/C++ for the complex stuff. Oliver, take a look at mbed, which is an ARM Cortex-M3 based microcontroller, 32 bit instruction set, running at 100 MHz. It may have the performance you want without needing any additional hardware. They're $60 in stock at Mouser. mbed is aimed at easing the task of building a prototype. To do this the development environment (C/C++) is hosted online so you don't have to install any tools, dongles, or ICE hardware. You just need a computer and a USB cable to the mbed. After you compile online save the resulting .bin file to your mbed (which appears as a flash drive) and the new firmware is installed and ready to go. Also, the microcontroller peripherals have been abstracted into C++ classes so you don't have to refer to the device datasheet for register definitions. Just instantiate an AnalogIn (for example) and use it. over at www.mbed.org you can read more and look at the shared libraries and programs people have created. --steveArticle: 149409
>On Oct 21, 8:18=A0pm, "cplante" <christian.plante@n_o_s_p_a_m.actel.com> >wrote: >> >Hi, >> >> >I normally use a microcontrollers for my projects - I have used PIC's >> >and AVR's - I mainly use them for the quick and easy programming etc. >> >(Arduinos are great!) >> >> >I've come across a case where a microprocessor can't meet my >> >performance requirements though, but parts of my problem is very >> >parallel, so an FPGA would be good. =A0The entire thing is too complex >> >to do all in VHDL or something - I prefer C/C++ for the complex stuff. >> >> >The exact use case is doing some linear arithmetic, using that to >> >calculate a pointer, and outputting the data at that memory location >> >serially to an IO device. =A0Throughput needs to be around 3Mbits/sec, >> >where each bit will require the above operations, but no bit depends >> >on any other. >> >> >Does any company sell a microprocessor what has a few thousand logic >> >elements of FPGA "on the side", which can interface fast with the >> >microprocessor, for example through shared memory. =A0Ideally this would >> >be cheap (ie. tens of dollars rather than hundreds of dollars), and >> >easy to use (I don't want to have to be defining my own DMA controller >> >or something...) >> >> >I know one can implement a CPU on an FPGA, but all the CPU's I can >> >find seem to be small and slow, and they somehow don't seem to be the >> >same "point and click" ease of programming an Arduino - they also >> >require development kits costing thousands of dollars. =A0Also I need it >> >to be self contained - ie. a chip and maybe a crystal clock. =A0I don't >> >really want to have to give it 3 regulated power supplies, 2 clocks, >> >and an external program flash memory and controller. >> >> >Ideas welcome! >> >> >Thanks >> >Oliver >> >> Hi Oliver, >> >> SmartFusion would give you what you need, and probably more. The CPU is a >> 100 MHz ARM Cortex-M3 with a full subsystem (DMA, eNVM, memory controller= >, >> SPI/I2C/UART, 10/100 Ethernet, etc.) The A2F200 version has 200,000 syste= >m >> gates (equivalent to 4,608 flip-flops). And a collection of analog blocks >> (incl. ADCs, DACs and comparators). The Evaluation Kit (A2F-EVAL-KIT) has= > a >> list price of $99. >> >> From a chip standpoint, I believe this should meet your criteria. The too= >ls >> are available for free on Actel's website. >> >> Regarding the unit pricing posted by some online distributors, the volume >> pricing is much lower. Our local representative can give you a quote for >> larger volumes, if you want. >> >> I'd love to hear your feedback after you try it. This device is only 6 >> months old and we're constantly working on making it easier to design wit= >h. >> For this, we welcome user comments. We're very passionate about >> SmartFusion. And, I hope, like many people already have, you feel the >> same. >> >> Happy design! >> >> Christian Plante >> Director of Marketing >> Low-Power and Mixed-Signal FPGAs >> Actel Corp. > >Yes, the SmartFusion device is interesting, but not practical for many >designs due to the cost, >$40. Is the high price because of the >inherent complexity of building the part or is the price point set >high because it is an early entry in the field and we can expect to >see this as a $10 part sometime in the next year or so? At $40 it is >more expensive than using separate components and so would only find >niche markets. At $10 I have no doubt it would sell like hotcakes... >at IHOP! > >Rick > Hi Rick, I don't disagree with that. There's another device in the hopper: A2F060 (60,000 gates). Information about it is already on our website. It's not sampling yet and we haven't set the final pricing either. But you can guess it's going to be much lower than the A2F200 and probably more in line with your expectations. It's still very early in the product's life. Thus, the current pricing found on online distributor sites. Thus, it's fair to say that pricing will be much lower next year. In the same vein, I would expect that the acquisition of Actel by Microsemi will also bring economies of scale that should impact SmartFusion's cost structure in the long term. In short, we're not ready for IHOP yet, but we're working on it. :) Christian --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149410
On Oct 22, 2:13=A0pm, "cplante" <christian.plante@n_o_s_p_a_m.n_o_s_p_a_m.actel.com> wrote: > >On Oct 21, 8:18=3DA0pm, "cplante" <christian.plante@n_o_s_p_a_m.actel.co= m> > >wrote: > >> >Hi, > > >> >I normally use a microcontrollers for my projects - I have used PIC's > >> >and AVR's - I mainly use them for the quick and easy programming etc. > >> >(Arduinos are great!) > > >> >I've come across a case where a microprocessor can't meet my > >> >performance requirements though, but parts of my problem is very > >> >parallel, so an FPGA would be good. =3DA0The entire thing is too comp= lex > >> >to do all in VHDL or something - I prefer C/C++ for the complex stuff= . > > >> >The exact use case is doing some linear arithmetic, using that to > >> >calculate a pointer, and outputting the data at that memory location > >> >serially to an IO device. =3DA0Throughput needs to be around 3Mbits/s= ec, > >> >where each bit will require the above operations, but no bit depends > >> >on any other. > > >> >Does any company sell a microprocessor what has a few thousand logic > >> >elements of FPGA "on the side", which can interface fast with the > >> >microprocessor, for example through shared memory. =3DA0Ideally this > would > >> >be cheap (ie. tens of dollars rather than hundreds of dollars), and > >> >easy to use (I don't want to have to be defining my own DMA controlle= r > >> >or something...) > > >> >I know one can implement a CPU on an FPGA, but all the CPU's I can > >> >find seem to be small and slow, and they somehow don't seem to be the > >> >same "point and click" ease of programming an Arduino - they also > >> >require development kits costing thousands of dollars. =3DA0Also I ne= ed > it > >> >to be self contained - ie. a chip and maybe a crystal clock. =3DA0I > don't > >> >really want to have to give it 3 regulated power supplies, 2 clocks, > >> >and an external program flash memory and controller. > > >> >Ideas welcome! > > >> >Thanks > >> >Oliver > > >> Hi Oliver, > > >> SmartFusion would give you what you need, and probably more. The CPU i= s > a > >> 100 MHz ARM Cortex-M3 with a full subsystem (DMA, eNVM, memory > controller=3D > >, > >> SPI/I2C/UART, 10/100 Ethernet, etc.) The A2F200 version has 200,000 > syste=3D > >m > >> gates (equivalent to 4,608 flip-flops). And a collection of analog > blocks > >> (incl. ADCs, DACs and comparators). The Evaluation Kit (A2F-EVAL-KIT) > has=3D > > a > >> list price of $99. > > >> From a chip standpoint, I believe this should meet your criteria. The > too=3D > >ls > >> are available for free on Actel's website. > > >> Regarding the unit pricing posted by some online distributors, the > volume > >> pricing is much lower. Our local representative can give you a quote > for > >> larger volumes, if you want. > > >> I'd love to hear your feedback after you try it. This device is only 6 > >> months old and we're constantly working on making it easier to design > wit=3D > >h. > >> For this, we welcome user comments. We're very passionate about > >> SmartFusion. And, I hope, like many people already have, you feel the > >> same. > > >> Happy design! > > >> Christian Plante > >> Director of Marketing > >> Low-Power and Mixed-Signal FPGAs > >> Actel Corp. > > >Yes, the SmartFusion device is interesting, but not practical for many > >designs due to the cost, >$40. =A0Is the high price because of the > >inherent complexity of building the part or is the price point set > >high because it is an early entry in the field and we can expect to > >see this as a $10 part sometime in the next year or so? =A0At $40 it is > >more expensive than using separate components and so would only find > >niche markets. =A0At $10 I have no doubt it would sell like hotcakes... > >at IHOP! > > >Rick > > Hi Rick, > > I don't disagree with that. There's another device in the hopper: A2F060 > (60,000 gates). Information about it is already on our website. It's not > sampling yet and we haven't set the final pricing either. But you can gue= ss > it's going to be much lower than the A2F200 and probably more in line wit= h > your expectations. Do me a favor, when you talk of the size of FPGA fabric, don't use "gates". That is a meaningless metric since there is no standard way to evaluate a design in terms of gates. A much better metric which is easy to measure is 4-input LUTs. They exist in your device, so rather than estimating, you can just count them. I wouldn't say that about Xilinx. They estimate "logic cells" rather than use LUTs. They seem to be smart guys, but they clearly don't know how to count!!! The A2F060 might be a good device for some, but I have two problems with it. The analog does not measure up, I need 2 channels of ADC/ DAC, preferably 16 bit 96 kHz sample rate. With only 1500 LUTs it may not be large enough for my designs. Oh yeah, one other nit is the package. CS and BGAs are nice for some apps, but for low cost apps a 100 pin QFP is much better. It costs extra to drill the tiny vias you need for these parts. No point in having a $10 part if it requires you to spend $10 extra on the PWB. > It's still very early in the product's life. Thus, the current pricing > found on online distributor sites. Thus, it's fair to say that pricing wi= ll > be much lower next year. That is good to hear. > In the same vein, I would expect that the acquisition of Actel by Microse= mi > will also bring economies of scale that should impact SmartFusion's cost > structure in the long term. That will be interesting to see. > In short, we're not ready for IHOP yet, but we're working on it. :) Ok, but if you do go there, stay away from the spaghetti dinner special!!! RickArticle: 149411
"Gabor" <gabor@alacron.com> wrote in message news:c8ba2148-1052-4627-99d6-9ba961ba5408@i5g2000yqe.googlegroups.com... > >You can see the routing if you open the design in the FPGA editor. >You can also cross-probe to the FPGA editor from the post P&R timing report >if you >use the ISE GUI. FPGA editor also shows delays to each load for a selected >net. Yes, thanks, I know all that. The PlanAhead just does some of that nicer by combining comprehensive device view with the timing report. /MikhailArticle: 149412
On Oct 22, 4:04=A0pm, "MM" <mb...@yahoo.com> wrote: > "Gabor" <ga...@alacron.com> wrote in message > > news:c8ba2148-1052-4627-99d6-9ba961ba5408@i5g2000yqe.googlegroups.com... > > > > >You can see the routing if you open the design in the FPGA editor. > >You can also cross-probe to the FPGA editor from the post P&R timing rep= ort > >if you > >use the ISE GUI. =A0FPGA editor also shows delays to each load for a sel= ected > >net. > > Yes, thanks, I know all that. The PlanAhead just does some of that nicer = by > combining comprehensive device view with the timing report. > > /Mikhail Well, I haven't really touched plan-ahead. Then again, I never used PACE or the old floorplanner either, so I'm more comfortable with the FPGA editor. But I've never seen the FPGA editor numbers disagree with the timing report either. Regards, GaborArticle: 149413
Hi, i am using this regulator by Texas Instruments to power up my FPGA i.e. tps75003, [h t tp://focus.ti.com/docs/prod/folders/print/tps75003.html] They have given an application note of 2A design which is available here : http://focus.ti.com/lit/ug/slvu116a/slvu116a.pdf i need to upgrade this design to 3A but i cannot figure out what changes do i need to make like which components do i need to change. if anyone has designed it for 3A, can he kindly share his design with me.Or if you have any suggestions on what components to use,that would be great too =) . Thanks Regards SalimBaba --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149414
"Gabor" <gabor@alacron.com> wrote > Well, I haven't really touched plan-ahead. Then again, I never used PACE > or the old floorplanner either, so I'm more comfortable with the FPGA > editor. > But I've never seen the FPGA editor numbers disagree with the timing > report either. Give it a try. It's easy. If you have a project in ISE (I am currently using the latest 12.3), in the processes view, under Place & Route you'll see Analyze Timing / Floorplan Design (PlanAhead). This will open your routed design in PlanAhead. Note that PlanAhead greys out certain functions depending on where it is open from. To see its full power you need to open it standalone and create a project. I actually think that Xilinx might one day replace ISE front-end with PlanAhead, it feels like a better organized and more powerful GUI. Although, I haven't used it much yet, and haven't tried RTL flow at all, so I might be wrong. What I like in it is how easy it is to create multiple jobs, launch them all and compare the results. Here is how I used it the most so far: I would synthesize the project in ISE, and then create a standalone netlist project in PlanAhead. After that you can create and launch multiple map/par strategies with a few mouse clicks. /MikhailArticle: 149415
On Oct 21, 5:18=A0pm, "cplante" <christian.plante@n_o_s_p_a_m.actel.com> wrote: > >Hi, > > >I normally use a microcontrollers for my projects - I have used PIC's > >and AVR's - I mainly use them for the quick and easy programming etc. > >(Arduinos are great!) > > >I've come across a case where a microprocessor can't meet my > >performance requirements though, but parts of my problem is very > >parallel, so an FPGA would be good. =A0The entire thing is too complex > >to do all in VHDL or something - I prefer C/C++ for the complex stuff. > > >The exact use case is doing some linear arithmetic, using that to > >calculate a pointer, and outputting the data at that memory location > >serially to an IO device. =A0Throughput needs to be around 3Mbits/sec, > >where each bit will require the above operations, but no bit depends > >on any other. > > >Does any company sell a microprocessor what has a few thousand logic > >elements of FPGA "on the side", which can interface fast with the > >microprocessor, for example through shared memory. =A0Ideally this would > >be cheap (ie. tens of dollars rather than hundreds of dollars), and > >easy to use (I don't want to have to be defining my own DMA controller > >or something...) > > >I know one can implement a CPU on an FPGA, but all the CPU's I can > >find seem to be small and slow, and they somehow don't seem to be the > >same "point and click" ease of programming an Arduino - they also > >require development kits costing thousands of dollars. =A0Also I need it > >to be self contained - ie. a chip and maybe a crystal clock. =A0I don't > >really want to have to give it 3 regulated power supplies, 2 clocks, > >and an external program flash memory and controller. > > >Ideas welcome! > > >Thanks > >Oliver > > Hi Oliver, > > SmartFusion would give you what you need, and probably more. The CPU is a > 100 MHz ARM Cortex-M3 with a full subsystem (DMA, eNVM, memory controller= , > SPI/I2C/UART, 10/100 Ethernet, etc.) The A2F200 version has 200,000 syste= m > gates (equivalent to 4,608 flip-flops). And a collection of analog blocks > (incl. ADCs, DACs and comparators). The Evaluation Kit (A2F-EVAL-KIT) has= a > list price of $99. > > From a chip standpoint, I believe this should meet your criteria. The too= ls > are available for free on Actel's website. Christian, Is there a tutorial that explains the design flow for the ProASIC3L devices that can use the ARM Cortex-M1 core? I've got all of the tools but I have no idea where to begin. My local FAE has not gotten back to me with an answer to this question. Ideally, the microprocessor core will coexist with some completely independent datapath logic. Thanks, -aArticle: 149416
If you like TI then use their Switcher Pro software. http://focus.ti.com/docs/toolsw/folders/print/switcherpro.html On 10/22/2010 5:51 PM, salimbaba wrote: > Hi, > i am using this regulator by Texas Instruments to power up my FPGA i.e. > tps75003, [h t tp://focus.ti.com/docs/prod/folders/print/tps75003.html] > > They have given an application note of 2A design which is available here : > http://focus.ti.com/lit/ug/slvu116a/slvu116a.pdf > > i need to upgrade this design to 3A but i cannot figure out what changes do > i need to make like which components do i need to change. if anyone has > designed it for 3A, can he kindly share his design with me.Or if you have > any suggestions on what components to use,that would be great too =) . > > > Thanks > Regards > SalimBaba > > --------------------------------------- > Posted through http://www.FPGARelated.comArticle: 149417
On Fri, 22 Oct 2010 16:51:22 -0500, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: >Hi, >i am using this regulator by Texas Instruments to power up my FPGA i.e. >tps75003, [h t tp://focus.ti.com/docs/prod/folders/print/tps75003.html] > >They have given an application note of 2A design which is available here : >http://focus.ti.com/lit/ug/slvu116a/slvu116a.pdf > >i need to upgrade this design to 3A but i cannot figure out what changes do >i need to make like which components do i need to change. if anyone has >designed it for 3A, can he kindly share his design with me.Or if you have >any suggestions on what components to use,that would be great too =) . Checkout the following document for different component selection options: http://focus.ti.com/lit/ds/symlink/tps75003.pdf Most important parts to be resized are the p-mos fets and the inductors. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 149418
Hi muzaffar i have gone through the datasheet and can't seem to figure out the component values that's why i asked for help =) . Can you kindly tell me, currently i am using the app note configuration of 2A, app note's link is given in the first thread. thanks regards --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149419
Hello, following situation: I have a board with a 10MHz oscillator which supplies a microcontroller and a spartan3e. The spartan uses a DCM to generate 50MHz for a global clock. The Controller has also a PLL to generate 50Mhz internal. Both, the controller and the spartan are connected over a parallel bus, the bus interface has a clock output (configured to 50MHz, permanently on). These clock signal is connected to a LHCLK input of the spartan. The simplest way for me would be to use the supplied bus clock at LHCLK-Pin as global clock for my design, but I get warnings when I try this. I can't feed a DCM with a LHCLK signal, at least I wasn't able to do this. Because the clocks have the same source, I could try to synchronize them. I tried to use the bus clock as feedback for the DCM, but when I Try this I get errormessages like "Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM site pair." Another solution I think about is to use the bus clock to feed the bus-interface and then building a fifo for clock domain crossing, but this is more complex. Any suggestion what would be the best way to solve this problem? regards ArneArticle: 149420
Hi,
I have got Spartan 3E starter board, now what I am trying to do is
get some data from external circuit. As suggested in this group I got
the FX2 Breadboard from Digilent Inc. I have made an AVR(AtMega 16)
based system which is capable of measuring temperature and relative
humidity. Now I ain't got any ideas to send the measured
data(temperature and humidity) to the FPGA board. I think voltage
level conversion is must, and except that are there any clock issues I
should take care of? Any suggestions/ideas are really appreciated.
San.
Article: 149421
On Oct 23, 8:14=A0am, Arne <a...@pagelnet.de> wrote:
> Hello,
>
> following situation:
>
> I have a board with a 10MHz oscillator which supplies a microcontroller a=
nd a spartan3e.
>
> The spartan uses a DCM to generate 50MHz for a global clock.
> The Controller has also a PLL to generate 50Mhz internal.
>
> Both, the controller and the spartan are connected over a parallel bus, t=
he bus interface has a
> clock output (configured to 50MHz, permanently on).
> These clock signal is connected to a LHCLK input of the spartan.
>
> The simplest way for me would be to use the supplied bus clock at LHCLK-P=
in as global clock for my
> design, but I get warnings when I try this.
> I can't feed a DCM with a LHCLK signal, at least I wasn't able to do this=
.
>
> Because the clocks have the same source, I could try to synchronize them.
> I tried to use the bus clock as feedback for the DCM, but when I Try this
> I get errormessages like "Place:1012 - A clock IOB / DCM component pair h=
ave been found that are not
> placed at an optimal clock IOB / DCM site pair."
>
> Another solution I think about is to use the bus clock to feed the bus-in=
terface and then building a
> fifo for clock domain crossing, but this is more complex.
>
> Any suggestion what would be the best way to solve this problem?
>
> regards
> =A0 =A0Arne
For use with a DCM you should really place the clock on a global (GC)
clock pin
rather than a side clock. However you can still force the design to
route with the
less optimal clocking connection. If you read the rest of the error
message it
should have a line that shows exactly what to place in your .ucf file
to override
the error and demote it to a warning. The down side of this is that
you will get
a fairly large delay in the path from the clock pin to the DCM (that's
why they
don't recommend this and make it an error by default). Perhaps a
better option
is to use the clock without a DCM. At 50 MHz, you might find this
option is
still good enough to meet timing. Assuming any IOB's that need to run
on this
clock are on the same half of the chip ("left" side as suggested by
the name
LHCLK), then this should prevent the errors. If you use IOB flip-
flops for
sampling the bus signals, you may need to instantiate IDELAY elements
to reduce the hold time requirement to zero. This was the default
for earlier devices, so I'm not sure if you need this for Spartan 3E
or not.
Also if you don't specify a clock buffer, the tools should insert a
regional
clock buffer by default. If not you may need to instantiate a BUFR on
this instead of BUFG.
Definitely add OFFSET IN timing constraints to your .ucf file to make
sure the clocking scheme is adequate.
HTH,
Gabor
Article: 149422On Oct 23, 9:24=A0am, Santosh <santos...@gmail.com> wrote: > Hi, > =A0 =A0 I have got Spartan 3E starter board, now what I am trying to do i= s > get some data from external circuit. As suggested in this group I got > the FX2 Breadboard from Digilent Inc. I have made an AVR(AtMega 16) > based system which is capable of measuring temperature and relative > humidity. Now I ain't got any ideas to send the measured > data(temperature and humidity) to the FPGA board. I think voltage > level conversion is must, and except that are there any clock issues I > should take care of? Any suggestions/ideas are really appreciated. > > San. What sort of external interfaces does your AtMega system have? Since I assume that you don't need the data to update really fast for this sort of application, I would choose the interface with the fewest wires if there are more than one to choose from. I think something like I2C would be perfect for this application - just two signal wires and a protocol that's easy to use. SPI or MicroWire are even easier from a protocol standpoint and have only a couple more wires. Any of these protocols can be run slow enough that you can oversample the signals with an internal clock in the FPGA. Then you don't need to be as concerned about signal integrity on your "clock" lines, which would be sampled, too. Otherwise no matter how slow the interface (including 100 MHz I2C) if you try to use the clock line directly as a clock you can have headaches. Regards, GaborArticle: 149423
> What sort of external interfaces does your AtMega system have? =A0Since
> I assume that you don't need the data to update really fast for this
> sort
> of application, I would choose the interface with the fewest wires
> if there are more than one to choose from. =A0I think something like I2C
> would be perfect for this application - just two signal wires and a
> protocol that's easy to use. =A0SPI or MicroWire are even easier
> from a protocol standpoint and have only a couple more wires.
> Any of these protocols can be run slow enough that you can
> oversample the signals with an internal clock in the FPGA.
> Then you don't need to be as concerned about signal integrity
> on your "clock" lines, which would be sampled, too. =A0Otherwise
> no matter how slow the interface (including 100 MHz I2C)
> if you try to use the clock line directly as a clock you can
> have headaches.
>
> Regards,
> Gabor
Hey,
I may be wrong but doesn't the AtMega output data on its clock
speed, which is run by external X-tal and FPGA runs at 50 Mhz. And due
to non-matching clocks, ain't there any conflicts. And I didn't get
the term oversampling, : P
San.
Article: 149424On Oct 24, 7:50=A0am, Santosh <santos...@gmail.com> wrote: > > What sort of external interfaces does your AtMega system have? =A0Since > > I assume that you don't need the data to update really fast for this > > sort > > of application, I would choose the interface with the fewest wires > > if there are more than one to choose from. =A0I think something like I2= C > > would be perfect for this application - just two signal wires and a > > protocol that's easy to use. =A0SPI or MicroWire are even easier > > from a protocol standpoint and have only a couple more wires. > > Any of these protocols can be run slow enough that you can > > oversample the signals with an internal clock in the FPGA. > > Then you don't need to be as concerned about signal integrity > > on your "clock" lines, which would be sampled, too. =A0Otherwise > > no matter how slow the interface (including 100 MHz I2C) > > if you try to use the clock line directly as a clock you can > > have headaches. > > > Regards, > > Gabor > > Hey, > =A0 =A0 =A0 I may be wrong but doesn't the AtMega output data on its cloc= k > speed, which is run by external X-tal and FPGA runs at 50 Mhz. And due > to non-matching clocks, ain't there any conflicts. And I didn't get > the term oversampling, : P > > San. Do you know the terms SPI or EIA-232? Or ain't you got to that point in your class yet? Rick
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