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gordon sumner <olgordy@gmail.com> writes: > I'm looking for a good FPGA dev board. My budget is not low, but > since I'm a grad student it's certainly not high. The primary > requirement is that I need gates, and lots (>1M) of them. I've had a > good experience with an XC3S500 board (Digilent) but my research is > pushing me further. If you like Digilent, they have (mostly) the same board with a S3E1600 which is considerably larger, for $225.Article: 149676
In comp.arch.fpga, kude <tadmas09@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > I have the following letters with frequency,and can anyone pls help me how > to start for the encoding the huffman tree? Thanks > <snip letters with frequency> > > just give me the hint pls,pls,pls Have you tried copy/pasting the last 4 words of your question in google? http://www.google.com/search?q=encoding+the+huffman+tree -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) BASIC is the Computer Science equivalent of `Scientific Creationism'.Article: 149677
>On Nov 11, 9:45=A0am, "noob13" ><matija.draganovic@n_o_s_p_a_m.hotmail.com> wrote: >> Hi, >> >> I'm developing a certain controller using Spartan3 FPGA. Since I have to >> communicate with another circuit that is using 5V signaling (similar to >> TTL, but HV level is above 3.5V) I was wondering if someone could recomme= >nd >> a good solution in a form of a "level shifter" circuit (I searched the >> internet and found a few ICs that could do the job. However, I could use = >a >> good recomendation though :) ). >> >> Tnx in advance.. > >A tried and true method is a "quick switch" circuit. This is a pass >transistor type gate that automatically limits the max voltage >conveyed from either side to the other to within approximately a volt >of Vdd if I remember correctly. They even have a version of the chip >that integrates a diode in the Vdd path so it can be powered by 5 >volts and the max level is just within the power rail of 3.3 volt >logic. If you need a logic high to be 3.5 volts, you would need to >add a pull up resistor to that side of the interface. > >A part number I have used in my designs is SN74CBTD3384CPW, a 10 >element part with a separate enable for each 5 elements. I like the >PW (TSSOP) packages as they are very small, but not BGA. They seem >easy to get. There should be parts without the diode if you want to >try to run without the pullups and can provide just the right Vdd >voltage so the FPGA doesn't fry and your 3.5 volt thresholds are >met... I'm not sure what the I/O max is on the spartans, so this may >not be possible on paper. > >Otherwise there are parts that actually drive the correct signal >voltage and have two power pins, one for each side. I don't have a >part number handy, but I should have an advertisement for these parts >available when I get back to the office. I'm not certain they are >bidirectional, but I believe they are and it doesn't make much sense >for them not to be... except if they drive both directions, they would >need direction and enable controls. > >Rick > Some time ago i was looking for level QSs to perform PCI level clamping. I could find here on the lab some SN74CBTD3384 but they seems to be useless because of the footprint (A and B at the same side of the IC). How can you manage to use it as a bus? Or you just use it with completely separated signals? Let me know if i was not clear. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149678
On 11/14/2010 09:26 AM, Gabor wrote: > > I'll also agree that schematics are broken, at least since they > dumped Aldec after Foundation version 4.1i. It's pretty clear > that schematics are very low on their software support priority > list. I stopped using schematics when I moved from the > Aldec-based Foundation tools to ISE. Actually, I thought the Aldec schematic tool was simply AWFUL, so bad I rigged up a system to use my preferred schematic entry (Protel 99) to generate architectural VHDL. It didn't make the VHDL quite the way Xilinx wanted it, so I had to hand edit - mostly to remove redundant duplications of library component declarations. But, I've been slowly learning the benefits of all-VHDL development, so this is much less an issue now than it was for me almost a decade ago. I still think their ise schematic is pretty bad, only slightly better than Aldec's, which seemsed like you could only get one gate and one FF on a page before the automated wire generator went nuts. Now, I can get 4 gates and 4 FFs on a page before the wiring gets messy. I mostly only use schematics for relatively simple, one-page glue logic for a CPLD, so it is OK. JonArticle: 149679
On Tue, 16 Nov 2010 14:23:22 -0600, Jon Elson <jmelson@wustl.edu> wrote: >On 11/14/2010 09:26 AM, Gabor wrote: > >> >> I'll also agree that schematics are broken, at least since they >> dumped Aldec after Foundation version 4.1i. It's pretty clear >> that schematics are very low on their software support priority >> list. I stopped using schematics when I moved from the >> Aldec-based Foundation tools to ISE. >Actually, I thought the Aldec schematic tool was simply AWFUL, so bad I >rigged up a system to use my preferred schematic entry (Protel 99) to >generate architectural VHDL. It didn't make the VHDL quite the way >Xilinx wanted it, so I had to hand edit - mostly to remove redundant >duplications of library component declarations. But, I've been slowly >learning the benefits of all-VHDL development, so this is much less an >issue now than it was for me almost a decade ago. I still think their >ise schematic is pretty bad, only slightly better than Aldec's, which >seemsed like you could only get one gate and one FF on a page before the >automated wire generator went nuts. Now, I can get 4 gates and 4 FFs on >a page before the wiring gets messy. I mostly only use schematics for >relatively simple, one-page glue logic for a CPLD, so it is OK. Schematics would be nice for high-level design where dataflows tend to dominate the reader's interest. I've never seen a package that worked well enough to use, though. I just use schematics for board level. I've always used VHDL only for programmable parts. OTOH, physical and logical viewers are useful to make sure synthesis is doing what the designer expects, though. The difference between such a viewer and a schematic entry package is the routing. The viewer doesn't (well) and the schematic capture package won't (you do). ;-)Article: 149680
Sink0 <sink00@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: <... many lines of useless quote deleted...> > Some time ago i was looking for level QSs to perform PCI level clamping. I > could find here on the lab some SN74CBTD3384 but they seems to be useless > because of the footprint (A and B at the same side of the IC). How can you > manage to use it as a bus? Or you just use it with completely separated > signals? Look at the 3861... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 149681
>Look at the 3861... >-- >Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > >Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt >--------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- > Yea i know, most of appications makes use of 3861, but i was wondering what kind of appication 3384 would be useful. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149682
On 16 Nov., 04:14, "atutu" <tuanna.hni@n_o_s_p_a_m.gmail.com> wrote: > Hello, > I want to use SPI between two xilinx's FPGA, but I don't know how maximum > speed can be make communication stable? > Thanks! Using LVDS-Signaling and dynamic phase alignment at least 1250Mbps should be possible in a Virtex-5 for the data pins. However, I believe that the clock path only supports 710 MHz. As SPI uses single data rate clocking the maximum data rate is therefore 710Mbps. If you are communicating only with your own designs you could modify the SPI spec to DDR to get the higher rate. KoljaArticle: 149683
Hi There, I have a project that will require the use of lower power fpga's (actel) which will require interfacing cmos camera, RAM, SD card, micro and other peripherals. The project's end focus to be able to stream video and save it into sd memory. I have done very little with fpga's. I am familiar with the HDL flow and have coded a little in VHDL. I need to get up to speed as quickly as possible and would like to get any useful recommendations on resources for doing this. I would love to hear of any recommended resource books, guides, dev boards, etc. that you think would be a good fit given my requirements. Thanks for the tips! --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149684
On Nov 17, 6:17=A0am, "Sink0" <sink00@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > >Look at the 3861... > >-- > >Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-da= rmstadt.de > > >Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt > >--------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- > > Yea i know, most of appications makes use of 3861, but i was wondering wh= at > kind of appication 3384 would be useful. > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com The 3384 is one of the first QuickSwitch products ever released. This came out at a time when fine-pitch SMT devices were fairly new and chip manufacturers were still in their old DIP package mindset. At that time they pinned out the chip whichever way made sense for the silicon layout without much regard to board-level concerns. If you look at most buffer and gate chips, you'll find that in almost all cases the earlier releases had inputs and outputs all over the place, and the flow-through pinout versions came later. The 3384 is probably still available to populate existing older designs. It was a very popular device when it first came out, and so many people may still use it because "it was there." Regards, GaborArticle: 149685
"fvnktion" <mjones@n_o_s_p_a_m.group8tech.com> wrote in message news:QJOdnS8r9-iid37RnZ2dnUVZ_g2dnZ2d@giganews.com... > Hi There, > > I have a project that will require the use of lower power fpga's (actel) > which will require interfacing cmos camera, RAM, SD card, micro and other > peripherals. The project's end focus to be able to stream video and save it > into sd memory. > > I have done very little with fpga's. I am familiar with the HDL flow and > have coded a little in VHDL. I need to get up to speed as quickly as > possible and would like to get any useful recommendations on resources for > doing this. I would love to hear of any recommended resource books, guides, > dev boards, etc. that you think would be a good fit given my requirements. The quickest way to get up2speed is to go on a VHDL course, there are some excellent courses from Doulos, Esperan, Mentor, Synthwork etc. They are not cheap but I suspect your time is more expensive (unless you are a student :-). Good luck, Hans www.ht-lab.com > > Thanks for the tips! > > > > --------------------------------------- > Posted through http://www.FPGARelated.com >Article: 149686
On 11/16/2010 4:06 PM, krw@att.bizzzzzzzzzzzz wrote: > On Tue, 16 Nov 2010 14:23:22 -0600, Jon Elson<jmelson@wustl.edu> wrote: > >> On 11/14/2010 09:26 AM, Gabor wrote: >> >>> >>> I'll also agree that schematics are broken, at least since they >>> dumped Aldec after Foundation version 4.1i. It's pretty clear >>> that schematics are very low on their software support priority >>> list. I stopped using schematics when I moved from the >>> Aldec-based Foundation tools to ISE. >> Actually, I thought the Aldec schematic tool was simply AWFUL, so bad I >> rigged up a system to use my preferred schematic entry (Protel 99) to >> generate architectural VHDL. It didn't make the VHDL quite the way >> Xilinx wanted it, so I had to hand edit - mostly to remove redundant >> duplications of library component declarations. But, I've been slowly >> learning the benefits of all-VHDL development, so this is much less an >> issue now than it was for me almost a decade ago. I still think their >> ise schematic is pretty bad, only slightly better than Aldec's, which >> seemsed like you could only get one gate and one FF on a page before the >> automated wire generator went nuts. Now, I can get 4 gates and 4 FFs on >> a page before the wiring gets messy. I mostly only use schematics for >> relatively simple, one-page glue logic for a CPLD, so it is OK. > > Schematics would be nice for high-level design where dataflows tend to > dominate the reader's interest. I've never seen a package that worked well > enough to use, though. I just use schematics for board level. I've always > used VHDL only for programmable parts. > > OTOH, physical and logical viewers are useful to make sure synthesis is doing > what the designer expects, though. The difference between such a viewer and a > schematic entry package is the routing. The viewer doesn't (well) and the > schematic capture package won't (you do). ;-) Having done some playing with the Aldec Active-HDL block diagram editor, if you're in the market you may find it worth a look. For doing actual schematic entry of low level blocks it's only mediocre, but for tying together the high level stuff it's pretty quick and clean. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 149687
> >The 3384 is one of the first QuickSwitch products ever released. This >came out >at a time when fine-pitch SMT devices were fairly new and chip >manufacturers >were still in their old DIP package mindset. At that time they pinned >out the >chip whichever way made sense for the silicon layout without much >regard >to board-level concerns. If you look at most buffer and gate chips, >you'll find >that in almost all cases the earlier releases had inputs and outputs >all over >the place, and the flow-through pinout versions came later. The 3384 >is >probably still available to populate existing older designs. It was a >very >popular device when it first came out, and so many people may still >use >it because "it was there." > >Regards, >Gabor > Thank you!! Thats explain a lot!! --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149688
I'm a novice at Verilog. I'm writing some glue logic to shift out data over SPI. My problem code is this: always @(negedge SPISS) begin ADCSPIShifter <= ADCTemp; end always @(posedge SPICLK) begin SPIMISO = ADCSPIShifter[63]; ADCSPIShifter = ADCSPIShifter << 1; end I have a register, ADCTemp, that I created in a different clock domain. I want to shift this data out over an SPI bus. When the chip select line (SPISS) goes low, I load the shift register from the ADCTemp register. On each rising edge of the SPICLK, I want to shift out a bit of the register. I know that I'm driving ADCSPIShifter from two sources. I just can't figure out how to solve it. The chip select line and the SPI clock line should never transition at the same time, but I don't know how to tell the synthesizer about that guarantee. I'm certain there's an easy prepackaged solution to this problem that everyone who knows anything about Verilog knows. I'm just not one of those people who learned Verilog the right way. If anyone can suggest a solution, I'd sure appreciate it.Article: 149689
You dont specify the frequency of the clocks. You may need to use an async fifo. Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149690
WindowsGeek <windowsgeek@gmail.com> wrote: > I'm a novice at Verilog. I'm writing some glue logic to shift out data > over SPI. My problem code is this: > always @(negedge SPISS) > begin > ADCSPIShifter <= ADCTemp; > end > always @(posedge SPICLK) > begin > SPIMISO = ADCSPIShifter[63]; > ADCSPIShifter = ADCSPIShifter << 1; > end > I have a register, ADCTemp, that I created in a different clock > domain. I want to shift this data out over an SPI bus. When the chip > select line (SPISS) goes low, I load the shift register from the > ADCTemp register. On each rising edge of the SPICLK, I want to shift > out a bit of the register. It helps if you think of gates and wires, instead of variables, like you would in C. If you wired this up with TTL, the outputs of your shift register would be wired to the outputs of the ADC, which would cause overheating in the output transistors. The simulator doesn't overheat, but it also doesn't know what to do. What you want is a loadable shift register. What you got was two registers with their outputs connected together. > I know that I'm driving ADCSPIShifter from two sources. I just can't > figure out how to solve it. The chip select line and the SPI clock > line should never transition at the same time, but I don't know how to > tell the synthesizer about that guarantee. From what you have given, I don't believe I can answer it. The shift register normally has one clock, and a load enable such that it loads when the load enable is active, and shifts when it isn't. -- glenArticle: 149691
On Nov 17, 12:21=A0pm, WindowsGeek <windowsg...@gmail.com> wrote:
> I'm a novice at Verilog. I'm writing some glue logic to shift out data
> over SPI. My problem code is this:
>
> always @(negedge SPISS)
> begin
> =A0 =A0 =A0 =A0 ADCSPIShifter <=3D ADCTemp;
> end
>
> always @(posedge SPICLK)
> begin
> =A0 =A0 =A0 =A0 SPIMISO =3D ADCSPIShifter[63];
> =A0 =A0 =A0 =A0 ADCSPIShifter =3D ADCSPIShifter << 1;
> end
>
> I have a register, ADCTemp, that I created in a different clock
> domain. I want to shift this data out over an SPI bus. When the chip
> select line (SPISS) goes low, I load the shift register from the
> ADCTemp register. On each rising edge of the SPICLK, I want to shift
> out a bit of the register.
>
> I know that I'm driving ADCSPIShifter from two sources. I just can't
> figure out how to solve it. The chip select line and the SPI clock
> line should never transition at the same time, but I don't know how to
> tell the synthesizer about that guarantee.
>
> I'm certain there's an easy prepackaged solution to this problem that
> everyone who knows anything about Verilog knows. I'm just not one of
> those people who learned Verilog the right way. If anyone can suggest
> a solution, I'd sure appreciate it.
You need to code it like this.
always @(posedge SPICLK)
begin
if (SPISS =3D 1'b0)
ADCSPIShifter =3D ADCTemp;
else
ADCSPIShifter =3D ADCSPIShifter << 1;
end
assign SPIMISO =3D ADCSPIShifter[63];
You load the register once with your load signal and then shift it out
as needed.
Ed McGettigan
--
Xilinx Inc.
Article: 149692On 11/17/2010 12:21 PM, WindowsGeek wrote: > I'm a novice at Verilog. I'm writing some glue logic to shift out data > over SPI. My problem code is this: > > always @(negedge SPISS) > begin > ADCSPIShifter<= ADCTemp; > end > > always @(posedge SPICLK) > begin > SPIMISO = ADCSPIShifter[63]; > ADCSPIShifter = ADCSPIShifter<< 1; > end > > I have a register, ADCTemp, that I created in a different clock > domain. I want to shift this data out over an SPI bus. When the chip > select line (SPISS) goes low, I load the shift register from the > ADCTemp register. On each rising edge of the SPICLK, I want to shift > out a bit of the register. > > I know that I'm driving ADCSPIShifter from two sources. I just can't > figure out how to solve it. The chip select line and the SPI clock > line should never transition at the same time, but I don't know how to > tell the synthesizer about that guarantee. > > I'm certain there's an easy prepackaged solution to this problem that > everyone who knows anything about Verilog knows. I'm just not one of > those people who learned Verilog the right way. If anyone can suggest > a solution, I'd sure appreciate it. My knee-jerk response to this would be to look for a clock domain that's fast enough (at least four times SPICLK, more = better), then do the whole thing in that clock domain, with an appropriate state machine. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 149693
On Nov 17, 3:56=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
> On Nov 17, 12:21=A0pm, WindowsGeek <windowsg...@gmail.com> wrote:
>
>
>
> > I'm a novice at Verilog. I'm writing some glue logic to shift out data
> > over SPI. My problem code is this:
>
> > always @(negedge SPISS)
> > begin
> > =A0 =A0 =A0 =A0 ADCSPIShifter <=3D ADCTemp;
> > end
>
> > always @(posedge SPICLK)
> > begin
> > =A0 =A0 =A0 =A0 SPIMISO =3D ADCSPIShifter[63];
> > =A0 =A0 =A0 =A0 ADCSPIShifter =3D ADCSPIShifter << 1;
> > end
>
> > I have a register, ADCTemp, that I created in a different clock
> > domain. I want to shift this data out over an SPI bus. When the chip
> > select line (SPISS) goes low, I load the shift register from the
> > ADCTemp register. On each rising edge of the SPICLK, I want to shift
> > out a bit of the register.
>
> > I know that I'm driving ADCSPIShifter from two sources. I just can't
> > figure out how to solve it. The chip select line and the SPI clock
> > line should never transition at the same time, but I don't know how to
> > tell the synthesizer about that guarantee.
>
> > I'm certain there's an easy prepackaged solution to this problem that
> > everyone who knows anything about Verilog knows. I'm just not one of
> > those people who learned Verilog the right way. If anyone can suggest
> > a solution, I'd sure appreciate it.
>
> You need to code it like this.
>
> always @(posedge SPICLK)
> begin
> =A0 =A0 =A0 if (SPISS =3D 1'b0)
> =A0 =A0 =A0 =A0 ADCSPIShifter =3D ADCTemp;
> =A0 =A0 =A0 else
> =A0 =A0 =A0 =A0 ADCSPIShifter =3D ADCSPIShifter << 1;
> end
>
> assign SPIMISO =3D ADCSPIShifter[63];
>
> You load the register once with your load signal and then shift it out
> as needed.
>
> Ed McGettigan
> --
> Xilinx Inc.
Well, that might work. But there are many SPI systems where the clock
does
not run constantly, so the load needs to be asynchronous. Most
designs work
around the asynchronous load requirement by using a (much faster)
internal
system clock to load the register as well as to sample the SPI clock
and data.
The OP did not say whether he has such a free-running clock in his
system.
If not he could code something like:
always @(posedge SPICLK or negedge SPISS)
begin
if (SPISS =3D 1'b0)
ADCSPIShifter =3D ADCTemp;
else
ADCSPIShifter =3D ADCSPIShifter << 1;
end
Then you get to find out whether asynchronous load shift-registers
synthesize
in the architecture of choice.
regards,
gabor
Article: 149694Hi! We have a design where an Altera Cyclone-3 (EP3C5) with LVDS inputs is connected to a sender on another board through a cable. In a number of cases on our prototype boards, the LVDS-inputs have been fried from this setup. Apart from any misdesign in the sender-board, does anyone have any suggestions on possible causes? Do these inputs have lesser ESD- protection? The cables used are shielded RJ45 TP-cables (ethernet cables) and I think the shield touches the connector before the signals, thus grounding away any accumulated potentials during assembly. I guess we'll put on external protection for the next board-spin, but I would just like some hints on if this is a common problem with these devices (if external protection is not used). Best regards, Bjorn WArticle: 149695
Hi, all. I got some error message when I use HDL Analysis and Lint (HAL) tool from Cadence on my design. It is, "Combinatorial path crossing multiple units drives a signal. The driver of flip-flop/output port has combinatorial assignment at multiple hierarchy levels." Since the code is just a normal register - combinational logic - register style, it seems usual to me. Can anybody explain why the analysis tool makes an error on this? Thanks in advance. - shjinArticle: 149696
On Wed, 17 Nov 2010 09:03:54 -0800, Rob Gaddi <rgaddi@technologyhighland.com> wrote: >On 11/16/2010 4:06 PM, krw@att.bizzzzzzzzzzzz wrote: >> On Tue, 16 Nov 2010 14:23:22 -0600, Jon Elson<jmelson@wustl.edu> wrote: >> >>> On 11/14/2010 09:26 AM, Gabor wrote: >>> >>>> >>>> I'll also agree that schematics are broken, at least since they >>>> dumped Aldec after Foundation version 4.1i. It's pretty clear >>>> that schematics are very low on their software support priority >>>> list. I stopped using schematics when I moved from the >>>> Aldec-based Foundation tools to ISE. >>> Actually, I thought the Aldec schematic tool was simply AWFUL, so bad I >>> rigged up a system to use my preferred schematic entry (Protel 99) to >>> generate architectural VHDL. It didn't make the VHDL quite the way >>> Xilinx wanted it, so I had to hand edit - mostly to remove redundant >>> duplications of library component declarations. But, I've been slowly >>> learning the benefits of all-VHDL development, so this is much less an >>> issue now than it was for me almost a decade ago. I still think their >>> ise schematic is pretty bad, only slightly better than Aldec's, which >>> seemsed like you could only get one gate and one FF on a page before the >>> automated wire generator went nuts. Now, I can get 4 gates and 4 FFs on >>> a page before the wiring gets messy. I mostly only use schematics for >>> relatively simple, one-page glue logic for a CPLD, so it is OK. >> >> Schematics would be nice for high-level design where dataflows tend to >> dominate the reader's interest. I've never seen a package that worked well >> enough to use, though. I just use schematics for board level. I've always >> used VHDL only for programmable parts. >> >> OTOH, physical and logical viewers are useful to make sure synthesis is doing >> what the designer expects, though. The difference between such a viewer and a >> schematic entry package is the routing. The viewer doesn't (well) and the >> schematic capture package won't (you do). ;-) > >Having done some playing with the Aldec Active-HDL block diagram editor, >if you're in the market you may find it worth a look. For doing actual >schematic entry of low level blocks it's only mediocre, but for tying >together the high level stuff it's pretty quick and clean. Market? Does it cost more than pocket lint? The Aldec rep has been bugging me to do a test drive, but there zero chance of spending money on such things. The big advantage I see in schematic entry at the top level is documentation. Schematics are (well, can be) intuitive. A pile of VHDL is very difficult to dig through. Having had to verify a subsystem with a few hundred ~10K line files...Article: 149697
Hi, I have a bunch of signals coming out of a module A, and these need to be stored in a single port RAM and immediately sent to another module B. My question is how do I instantiate my RAM (how do i use the en signal for both read and write). RAM r1 (.clk(clk), .rst(rst), .addr(addr), .en(en), indata(X), .outdata(Y));Article: 149698
Hello all, I am currently a PhD student at the University of Wisconsin-Madison. I am working on research where I'm interfacing CPUs directly with reconfigurable logic. Part of this work (and part of my thesis) is going to require me to have area estimates of portions of my interface system. Having these estimates is useful for two reasons: first, it allows me to better estimate the overhead (in terms of area) of the interface I've designed between the reconfigurable fabric and the cache hierarchy, and second, it will allow me to make better comparisons between using reconfigurable accelerators as compared to using other accelerator architectures such as vector processing units and GPUs. I would be most interested in Xilinx 65nm Virtex 5 devices (as the reconfigurable fabric I'm simulating in my research is assumed to be similar to the Virtex-5, and I use timing and area estimates for my accelerators using this device), in particular the LX 155 device, although any of them would likely prove to be useful for at least coming up with a ballpark estimate. If this isn't available, I'd be open to other recent devices, as I could likely extrapolate an approximate area, which would allow me to make better educated guesses concerning the system. These numbers would be useful to my work even if I can't publish exact figures, but only rough estimate comparisons. Any help would be greatly appreciated though. thanks, Phil GarciaArticle: 149699
On Nov 17, 10:01=A0pm, John Smith <redditor...@gmail.com> wrote: > Hi, > > I have a bunch of signals coming out of a module A, and these need to > be stored in a single port RAM and immediately sent to another module > B. You're likely not describing correctly what you intend because the obvious thing then would be to send the outputs of module A both to the RAM for storage and in parallel send those same outputs to module B. > My question is how do I instantiate my RAM (how do i use the en > signal for both read and write). > > RAM r1 (.clk(clk), .rst(rst), .addr(addr), .en(en), > indata(X), .outdata(Y)); Did you read the documentation for the RAM? KJ
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