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On Wed, 3 Nov 2010 06:10:44 -0700 (PDT), gordon sumner <olgordy@gmail.com> wrote: >I'm looking for a good FPGA dev board. My budget is not low, but >since I'm a grad student it's certainly not high. The primary >requirement is that I need gates, and lots (>1M) of them. I've had a >good experience with an XC3S500 board (Digilent) but my research is >pushing me further. In my world gates for dedicated resources don't >count (unless they can be commandeered for my own use) because I need >to create machine descriptions that are as "portable" as possible. >Any suggestions? http://www.enterpoint.co.uk/oem_industrial/hollybush2.html Spartan-3A DSP-3400 which means a fair few gates, and a lot of Block Rams and DSP blocks. - BrianArticle: 149551
Hi, I coded a combinatorial process. However when simulated in Modelsim, the output does not change when my input which is in the process sensitivity list changes.the output remains constant and takes into account only the initial value of my input. when i add a clk to my sensitivity list, i get the expected output. However my process should be combinatorial! there is nothing wrong with my SIMPLE combinatorial process. any help please?? I used ISE synthesiser tool to synthesise my programs . CHEERSArticle: 149552
Angus <angusdundee@googlemail.com> wrote in news:cc605b18-e83d-4ffd-82a9- 6b13ac150ee8@g26g2000vba.googlegroups.com: > Hi, > I coded a combinatorial process. However when simulated in Modelsim, > the output does not change when my input which is in the process > sensitivity list changes.the output remains constant and takes into > account only the initial value of my input. when i add a clk to my > sensitivity list, i get the expected output. However my process should > be combinatorial! there is nothing wrong with my SIMPLE combinatorial > process. any help please?? I used ISE synthesiser tool to synthesise > my programs . > > CHEERS > My crystal ball is broken today, and my extra-sensory perception doesn't seem to reach to your location. :-) Please provide your code. All of it. Pasted, not re-typed. I read your posting in comp.arch.fpga, but I am going to guess (since you didn't provide much information) that because you also posted to comp.lang.vhdl then your code is probably VHDL. Maybe it is not as SIMPLE and as combinatorial as you think. Thanks!Article: 149553
In comp.arch.fpga Angus <angusdundee@googlemail.com> wrote: > I coded a combinatorial process. However when simulated in Modelsim, > the output does not change when my input which is in the process > sensitivity list changes. That seems to mean that it isn't combinatorial. > the output remains constant and takes into > account only the initial value of my input. when i add a clk to my > sensitivity list, i get the expected output. It shouldn't have a clock, so how can you add one? OK, if you add to the sensitivity list and the output changes when that new signal changes, then it seems that the input is not in the sensitivity list. Could it be spelled wrong, so that it looks like it is in the list? > However my process should > be combinatorial! there is nothing wrong with my SIMPLE combinatorial > process. any help please?? I used ISE synthesiser tool to synthesise > my programs . -- glenArticle: 149554
On Nov 3, 1:36=A0pm, "Steve Ravet" <steve.ra...@arm.com> wrote: > ARM University relations is working on an easily available encrypted FPGA= netlist for academic use. =A0I don't know the details but I > have asked my colleage about it. > > In the =A0meantime ARM has a university program that you can contact at > > www.arm.com/support/university > > or univers...@arm.com > > regards, > --steve > > "Oliver Mattos" <omat...@gmail.com> wrote in messagenews:5d26e81a-576a-4f= f5-8e2f-490239880f46@f33g2000yqh.googlegroups.com... > > > There is talk here of the Cortex M1/3 processor here - is that the > > kind of thing you can just download and use in a softcore as a > > student, or do you have to pay a multi-million dollar license to get > > hold of it? > > > Thanks > > Oliver That reminds me of an ARM core that was developed and posted on OpenCores at one time. Seems the guy did such a good job that ARM contacted him about removing it. I'm not sure how I know this, but I want to say he ended up working for ARM... RickArticle: 149555
On 11/03/2010 06:22 AM, Nial Stewart wrote: >> Yes this is it. Now FPGA don't ground unassinged pins and in this way >> configure CPLD MAX configuration circuit. >> Thank You so much. > > OK, but if that is the fix you should check and drive that pin inactive > instead of allowing it to float (it might be tied inactive on the board, > I can't remember). > It won't float with the weak pull-up, although actively driving it to VCC is better for noise. -hpaArticle: 149556
On 4 Nov., 17:08, Matti Dun <matti....@gmail.com> wrote: > Hi, > I have seen a demo of LAVA 10 (SVGA Controller based on FPGA) on > youtube and I was wondering if there are some similar solutions like > this? I've read about generating VGA but first time about SVGA. Any > info about how fast processor I need to use that module? > Thanks, > Matti Hi Matti, SVGA has a higher pixel count than VGA, but with modern FPGAs that can work with DDR RAMs at above 100MHZ this is no problem anymore. There are reference designs available that read in DVI-Video (1280x1024@60Hz and larger) do some video processing and output the results on a DVI Output. This can be done with an ordinary S3E (and external DVI-(de)serializer chips). For SVGA you need a fast Video-DAC that can handle the up to 100MSPS Data rates. No sweat for the FPGA. When you say processor, are you refering to the CPU of some embedded system? That doesn't need to be fast. Only the video part (namely some counters, sync logic and the memory controller) need to work at or above pixel clock frequencies. Have a nice synthesis EilertArticle: 149557
all right here you go (I read there was A problem with MODELSIM in
simulating combinatorial processes):
SIGNAL DATA1 : Data_t:=(7,3,2);
SIGNAL DATA2 : Data_t :=(9,5,1);
PROCESS (SEL)
BEGIN
--
CASE SEL IS
WHEN "00" =>temp<=DATA1;
WHEN "01" =>temp<=DATA2;
WHEN OTHERS =>NULL;
END CASE;
Data<=CONV_STD_LOGIC_VECTOR(temp(2),4)&CONV_STD_LOGIC_VECTOR(temp(1),
4)&CONV_STD_LOGIC_VECTOR(temp(0),4);
END PROCESS;
when i change SEL in my testbench, Data does not change. I had to
embed my CASE within a clk edge detection to see the changes on
modelsim
CHEERS
Article: 149558On Nov 5, 7:21=A0am, Angus <angusdun...@googlemail.com> wrote: > all right here you go (I read there was A problem with MODELSIM in > simulating combinatorial processes): > > SIGNAL DATA1 : Data_t:=3D(7,3,2); > SIGNAL DATA2 : Data_t :=3D(9,5,1); > > PROCESS (SEL) > BEGIN > -- > =A0 =A0 =A0 =A0 =A0CASE SEL IS > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "00" =3D>temp<=3DDATA1; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "01" =3D>temp<=3DDATA2; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN OTHERS =3D>NULL; > =A0 =A0 =A0 =A0 END CASE; > > =A0 =A0 =A0 =A0 Data<=3DCONV_STD_LOGIC_VECTOR(temp(2),4)&CONV_STD_LOGIC_V= ECTOR(temp(1), > 4)&CONV_STD_LOGIC_VECTOR(temp(0),4); > END PROCESS; > when i change SEL in my testbench, Data does not change. I had to > embed my CASE within a clk edge detection to see the changes on > modelsim > > CHEERS i forgot to add SIGNAL temp : Data_t ;Article: 149559
On Nov 5, 7:21=A0am, Angus <angusdun...@googlemail.com> wrote: > all right here you go (I read there was A problem with MODELSIM in > simulating combinatorial processes): > > SIGNAL DATA1 : Data_t:=3D(7,3,2); > SIGNAL DATA2 : Data_t :=3D(9,5,1); > > PROCESS (SEL) > BEGIN > -- > =A0 =A0 =A0 =A0 =A0CASE SEL IS > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "00" =3D>temp<=3DDATA1; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "01" =3D>temp<=3DDATA2; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN OTHERS =3D>NULL; > =A0 =A0 =A0 =A0 END CASE; > > =A0 =A0 =A0 =A0 Data<=3DCONV_STD_LOGIC_VECTOR(temp(2),4)&CONV_STD_LOGIC_V= ECTOR(temp(1), > 4)&CONV_STD_LOGIC_VECTOR(temp(0),4); > END PROCESS; > when i change SEL in my testbench, Data does not change. I had to > embed my CASE within a clk edge detection to see the changes on > modelsim > > CHEERS obviously,my case statement has 4 conditions, that';s why SEL is of 2 bits. i simplified the code in order not to distract you from the real problem.Article: 149560
On Nov 5, 8:27=A0am, Angus <angusdun...@googlemail.com> wrote: > On Nov 5, 7:21=A0am, Angus <angusdun...@googlemail.com> wrote: > > > > > all right here you go (I read there was A problem with MODELSIM in > > simulating combinatorial processes): > > > SIGNAL DATA1 : Data_t:=3D(7,3,2); > > SIGNAL DATA2 : Data_t :=3D(9,5,1); > > > PROCESS (SEL) > > BEGIN > > -- > > =A0 =A0 =A0 =A0 =A0CASE SEL IS > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "00" =3D>temp<=3DDATA1; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "01" =3D>temp<=3DDATA2; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN OTHERS =3D>NULL; > > =A0 =A0 =A0 =A0 END CASE; > > > =A0 =A0 =A0 =A0 Data<=3DCONV_STD_LOGIC_VECTOR(temp(2),4)&CONV_STD_LOGIC= _VECTOR(temp(1), > > 4)&CONV_STD_LOGIC_VECTOR(temp(0),4); > > END PROCESS; > > when i change SEL in my testbench, Data does not change. I had to > > embed my CASE within a clk edge detection to see the changes on > > modelsim Your process isn't fully combinatorial: a process in order to be combinatorial has to contain in its sensitivity list ALL the inputs that can affect the output. In your case you only have the multiplexer selector in the sensitivity list, while the DATA1 and DATA2 are not included. Try to add them and it will work. Ciao! maurizioArticle: 149561
On Nov 5, 7:21=A0am, Angus <angusdun...@googlemail.com> wrote: > all right here you go (I read there was A problem with MODELSIM in > simulating combinatorial processes): > > SIGNAL DATA1 : Data_t:=3D(7,3,2); > SIGNAL DATA2 : Data_t :=3D(9,5,1); > > PROCESS (SEL) > BEGIN > -- > =A0 =A0 =A0 =A0 =A0CASE SEL IS > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "00" =3D>temp<=3DDATA1; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN "01" =3D>temp<=3DDATA2; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 WHEN OTHERS =3D>NULL; > =A0 =A0 =A0 =A0 END CASE; > > =A0 =A0 =A0 =A0 Data<=3DCONV_STD_LOGIC_VECTOR(temp(2),4)&CONV_STD_LOGIC_V= ECTOR(temp(1), > 4)&CONV_STD_LOGIC_VECTOR(temp(0),4); > END PROCESS; > when i change SEL in my testbench, Data does not change. I had to > embed my CASE within a clk edge detection to see the changes on > modelsim > > CHEERS As maurizio has pointed out, if you add DATA1 and DATA2 to the sensitivity list it will work. But one word of warning - this code will create latches, which is probably not what you want to do.Article: 149562
> As maurizio has pointed out, if you add DATA1 and DATA2 to the > sensitivity list it will work. > But one word of warning - this code will create latches, which is > probably not what you want to do. Yes, Tricky, I forgot the latches...sorry for that Angus, each time in an HDL statement you leave a default behavior that simply keeps the previous value of a signal (when others => null, actually does this) you will introduce a latch element. A small advice, when you are developing HW, never forget that you are not writing software, but describing HW. Try to ask yourself "how this behavior can result in gates?" you will reduce a lot the number of unwanted behavior. Good luck! maurizioArticle: 149563
Angus <angusdundee@googlemail.com> writes: > all right here you go (I read there was A problem with MODELSIM in > simulating combinatorial processes): > > SIGNAL DATA1 : Data_t:=(7,3,2); > SIGNAL DATA2 : Data_t :=(9,5,1); > > PROCESS (SEL) Do you not want DATA1 and DATA2 in here? Are you trying to latch your result *only* when SEL changes (and not when the data changes)? > BEGIN > -- > CASE SEL IS > WHEN "00" =>temp<=DATA1; > WHEN "01" =>temp<=DATA2; > WHEN OTHERS =>NULL; Here you've scheduled a transaction on temp to happen at the end of the process. > END CASE; > > > Data<=CONV_STD_LOGIC_VECTOR(temp(2),4)&CONV_STD_LOGIC_VECTOR(temp(1), > 4)&CONV_STD_LOGIC_VECTOR(temp(0),4); Here you are using temp, but it hasn't updated yet as the process hasn't suspended. To get this to update the way you seem to want you need to use a variable for temp. That updates immediately. BTW, you're using conv_std_logic_vector, which means you must have used ieee.std_logic_arith - don't do that, use ieee.numeric_std. Some other threads on this: https://groups.google.com/group/comp.lang.vhdl/browse_thread/thread/389677dd60f7b91c/af0ec67dda4ee7ba?hl=en&ie=UTF-8&q=numeric_std+vs+std_logic_arith&pli=1#af0ec67dda4ee7ba https://groups.google.com/group/comp.lang.vhdl/browse_thread/thread/549e1bbffd35914d/83cc0f19350fc392?hl=en&ie=UTF-8&q=numeric_std+vs+std_logic_arith#83cc0f19350fc392 http://www.alteraforum.com/forum/showthread.php?t=20925 And some notes I made after writing about it on newsgroups once too often: http://www.parallelpoints.com/node/3 > END PROCESS; > when i change SEL in my testbench, Data does not change. Are you sure you're not just seeing it change on the *next* change of sel? > I had to > embed my CASE within a clk edge detection to see the changes on > modelsim Well, that's probably a good plan anyway, as I doubt the description above is remotely synthesisable... That should also show a pipelined behaviour though (where data changes one extra tick after sel changes). Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardwareArticle: 149564
Also have a look at Raggedstone1, Raggedstone2, Drigmorn3, Drigmorn4. Links to product pages for these and others http://www.enterpoint.co.uk/boa= rdproducts.html. We operate a student and university discounts on all of these products. John Adair Enterpoint Ltd. On Nov 4, 8:43=A0pm, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Wed, 3 Nov 2010 06:10:44 -0700 (PDT), gordon sumner <olgo...@gmail.com= > > wrote: > > >I'm looking for a good FPGA dev board. =A0My budget is not low, but > >since I'm a grad student it's certainly not high. =A0The primary > >requirement is that I need gates, and lots (>1M) of them. =A0I've had a > >good experience with an XC3S500 board (Digilent) but my research is > >pushing me further. =A0In my world gates for dedicated resources don't > >count (unless they can be commandeered for my own use) because I need > >to create machine descriptions that are as "portable" as possible. > >Any suggestions? > > http://www.enterpoint.co.uk/oem_industrial/hollybush2.html > > Spartan-3A DSP-3400 which means a fair few gates, and a lot of Block Rams= and > DSP blocks. > > - BrianArticle: 149565
Hi Eilert, Yes, it seems that all logic you mentioned (sync logic and the memorycontroller) is already in that module so I can use any cortex and it will be sufficient. Thanks, MattiArticle: 149566
Hi,
I have installed a PCI parallel port card on my PC. And I want to run
XILINX and let it detect the card
so that I can use a XILINX Parallel Cable IV to work with it.
XILINX detects the card but gives an error message saying
"ECP port test failed." and does not work.
How do I get the PCI parallel card to work with XILINX?
Is there a particular PCI card which someone has worked with and knows
for sure will work with XILINX?
Can somebody please help me with this?
Note: I am using a PCI card from Chronos MP9715P-2 which has the
NetMos 9715 chipset.
I also tried it with another card from Syba (SD-PEX-1005),
which has the MosChip 9901 chipset.
Thanks,
Regards,
Aditi.
Article: 149567ERROR:HDLCompiler:25 - "C:/Documents and Settings/[username]/My Documents/My Dropbox/Comp Arch/FinalProject/top.vf" Line 1351: Module <ALU16Verilog_MUSER_top> does not have a port named <a>. ERROR:HDLCompiler:25 - "C:/Documents and Settings/[username]/My Documents/My Dropbox/Comp Arch/FinalProject/top.vf" Line 1352: Module <ALU16Verilog_MUSER_top> does not have a port named <b>. ERROR:HDLCompiler:25 - "C:/Documents and Settings/[username]/My Documents/My Dropbox/Comp Arch/FinalProject/top.vf" Line 1353: Module <ALU16Verilog_MUSER_top> does not have a port named <op>. ERROR:HDLCompiler:25 - "C:/Documents and Settings/[username]/My Documents/My Dropbox/Comp Arch/FinalProject/top.vf" Line 1354: Module <ALU16Verilog_MUSER_top> does not have a port named <r>. ERROR:HDLCompiler:25 - "C:/Documents and Settings/[username]/My Documents/My Dropbox/Comp Arch/FinalProject/top.vf" Line 1355: Module <ALU16Verilog_MUSER_top> does not have a port named <zero>. ERROR:Simulator:778 - Static elaboration of top level Verilog design unit(s) in library work failed what does this mean?Article: 149568
On 11/05/2010 12:18 PM, Aditi wrote: > > Note: I am using a PCI card from Chronos MP9715P-2 which has the > NetMos 9715 chipset. Ugh! I can't say specifically for Xilinx, but I know the Netmos 9705 had a severely buggy implementation of the EPP standard, and the handshaking would never work. I don't know about the 9715, but hear rumor that it isn't any better. I have used SIIG cards, and they do work. They require a Windows 95 program to set the default port mode, however, which is awfully obsolete. I can't believe they haven't updated this. JonArticle: 149569
Hi, I am using synplify pro. In synplify constraint file I can add in the pin assignment for physical FPGA mapping. but I can not tell the difference add and not add. I did not see significant timing improve or related information embedded into output edf. is it the pin assignment really help timing/sythesis for final out come result? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149570
> > Your process isn't fully combinatorial: a process in order to be > combinatorial > has to contain in its sensitivity list ALL the inputs that can affect > the output. > In your case you only have the multiplexer selector in the sensitivity > list, > while the DATA1 and DATA2 are not included. Try to add them and it > will > work. > > Ciao! > maurizio- Hide quoted text - > > - Show quoted text - Maurizio, Data1 and Data2 are constant. I think they don't have to be in the sensitivity list. I have fixed the problem as explained in my post belowArticle: 149571
On Nov 5, 10:33=A0am, Team C <war...@rose-hulman.edu> wrote: > > what does this mean? It means that you should have stayed awake during the lectures.Article: 149572
On Nov 5, 10:18=A0am, Aditi <aditi.gro...@gmail.com> wrote: > Hi, > > I have installed a PCI parallel port card on my PC. And I want to run > XILINX and let it detect the card > so that I can use a XILINX Parallel Cable IV to work with it. > XILINX detects the card but gives an error message saying > "ECP port test failed." and does not work. > > How do I get the PCI parallel card to work with XILINX? > > Thanks, > Regards, > Aditi. "ECP port test failed." usually means that the port is not in ECP mode.Article: 149573
On Nov 5, 1:06=A0pm, "william" <cuteworm@n_o_s_p_a_m.wildmail.com> wrote: > > is it the pin assignment really help timing/synthesis for final out come > result? > Why would you expect it to? Location constraints are just embedded into the netlist during synthesis.Article: 149574
d_s_klein <d_s_klein@yahoo.com> wrote: > On Nov 5, 10:18 am, Aditi <aditi.gro...@gmail.com> wrote: > > Hi, > > > > I have installed a PCI parallel port card on my PC. And I want to run > > XILINX and let it detect the card > > so that I can use a XILINX Parallel Cable IV to work with it. > > XILINX detects the card but gives an error message saying > > "ECP port test failed." and does not work. > > > > How do I get the PCI parallel card to work with XILINX? > > > > Thanks, > > Regards, > > Aditi. > "ECP port test failed." usually means that the port is not in ECP > mode. The original poster sould check in the BIOS -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z