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On Dec 29 2009, 4:37=A0pm, Rob Doyle <radioe...@gmail.com> wrote: > > I *need* one write port and three read ports - so I'm OK just > duplicating the RAM. > > I could save a clock cycle in the ALU if I could do two writes > and three reads. =A0If I have to stall the pipeline to implement > this, I've gained nothing. > > The timing won't permit 2 Register clock cycles per ALU clock cycle > to double-up the register accesses. > > The multi-port "flag" memory is the trick I was looking for. =A0The ALU > has 1024 registers so I can envision some tall data selectors, > multiplexers, and accompanying levels of logic to implement the > address decoders. > > I think I'm going to stay with simple for now and put this in my > back pocket as "Plan B". > > I greatly appreciate the help. > > Rob Doyle If you wanted fewer registers (1024, really?) there's a nice technique that can use LUT RAMs to provide (combinatorially) the read values you want with two write ports. Two writes to the same address would result in an undefined value but avoiding that condition results in seamless operation. Two write ports with three reads would use 8 dual- port LUT RAM arrays - (write_ports x (read_ports+1) ). The reason LUT RAMs are needed is the operation is a read-modify- write. One could get around the read-modify-write need by delaying the write one cycle but that method of selecting the read value or the delayed write value is still needed. I can provide more detail if needed. Multiple write ports start to eat resources but they're doable if the performance gain is worth the resource loss.Article: 144776
On Jan 1, 11:03=A0am, "Ghostboy" <Ghost...@dommel.be> wrote: > Nobody who can help me? You're asking for a LOT of work from someone or someone who happens to actively use a development board that's been discontinued from Xilinx (you can still purchase it from digilentinc.com) because the Virtex-II Pro devices are getting old. Besides, the link in your Dec 14th email is invalid.Article: 144777
From the bowels of my computer I resurrected a file written more than 3 years ago: Using Virtex-5 CLB as Multi-Port Memory The four M-LUTs in a half-CLB can be combined to form a quad-port RAM, ideally suited for register-file applications. The four LUTs, called A, B, C, and D are configured in such a way that the write address applied to D is automatically also multiplexed onto the write addressing of LUTs A, B, and C. Writing into D thus also writes into the same location in A, B, and C, but these three LUTs have their address inputs still available as read addresses. (In this application, LUT D is never read.) The structure functions as a quad-port RAM with one write port (address applied to D) and common data written into LUTs A, B, and C . There are three independent read ports (addresses applied to LUTs A, B, and C.) Writing is synchronous, reading is combinatorial. Each LUT can either be a 64 x 1, or a 32 x 2 RAM. A similar structure, using common read addresses and individual Data inputs, acts as simple dual-port memory, either 3 bits wide and 64 deep, or 3 bits wide and 32 deep. In the Virtex-5 MicroBlaze application, the 32 x 32 register file with one write port and two read ports, using 384 LUTs in Virtex-4, is reduced to 44 LUTs, a saving of over 88%. Peter Alfke, 3-21-06Article: 144778
wow, a great new year's present :-))) Peter Alfke wrote: > From the bowels of my computer I resurrected a file written more than > 3 years ago: > > Using Virtex-5 CLB as Multi-Port Memory <snip> > In the Virtex-5 MicroBlaze application, the 32 x 32 register file with > one write port and two read ports, using 384 LUTs in Virtex-4, is > reduced to 44 LUTs, a saving of over 88%. > > Peter Alfke, 3-21-06 Any more information, diagram, schematics, source code, appnote, or whatever, would be really appreciated :-) thanks and greetings, yg -- http://ygdes.com / http://yasep.orgArticle: 144779
>One of the simplest and most consistent multiplexers I've used is with >arrays of registers or wires. > >wire [p:0] my_sel; >wire [n:0] my_array [m:0]; // assign m+1 my_array values to the >desired inputs >reg [n:0] my_output; >// >always @(posedge clk) my_output <=3D my_array[my_sel]; > Thanks John that works great. Jon --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144780
I'm working on a multiprocessor architecture targeting spartan 3 starter
kit. (referring to the tutorial XAPP996). I'm stuck in the phase of run
implementation set, because I could not connect the MicroBlaze to the Debug
Module "mdm"!!I used XMD debug by typing the command "connect mb mdm", but
there is an error as follows:
Info: Autodetecting cable. Please wait.
Info: Connecting to cable (Parallel Port - LPT1).
Info: Checking cable driver.
Info: Driver windrvr6.sys version = 8.1.1.0.Info: WinDriver v8.11 Jungo (c)
1997
- 2006 Build Date: October 16, 2006 X86 32bit SYS 12:35:07, version =
811.
Info: LPT base address = 0378h.
Info: ECP base address = 0778h.
Info: Cable connection established.
JTAG chain configuration
--------------------------------------------------
Device ID Code IR Length Part Name
1 01414093 6 XC3S200
2 05045093 8 XCF02S
ERROR: Could Not Detect MDM Peripheral on Hardware. Check:
1. If FPGA is Configured Correctly
2. MDM Core is Instantiated in the Design
So please, if anyone knows the solution, pleaaase my answer!!I'm stuck
with all my great appreciation!!!
INES
---------------------------------------
This message was sent using the comp.arch.fpga web interface on
http://www.FPGARelated.com
Article: 144781
I'm working on a multiprocessor architecture targeting spartan 3 starter
kit. (referring to the tutorial XAPP996). I'm stuck in the phase of run
implementation set, because I could not connect the MicroBlaze to the Debug
Module "mdm"!!I used XMD debug by typing the command "connect mb mdm", but
there is an error as follows:
Info: Autodetecting cable. Please wait.
Info: Connecting to cable (Parallel Port - LPT1).
Info: Checking cable driver.
Info: Driver windrvr6.sys version = 8.1.1.0.Info: WinDriver v8.11 Jungo (c)
1997
- 2006 Build Date: October 16, 2006 X86 32bit SYS 12:35:07, version =
811.
Info: LPT base address = 0378h.
Info: ECP base address = 0778h.
Info: Cable connection established.
JTAG chain configuration
--------------------------------------------------
Device ID Code IR Length Part Name
1 01414093 6 XC3S200
2 05045093 8 XCF02S
ERROR: Could Not Detect MDM Peripheral on Hardware. Check:
1. If FPGA is Configured Correctly
2. MDM Core is Instantiated in the Design
So please, if anyone knows the solution, pleaaase my answer!!I'm stuck
with all my great appreciation!!!
INES
---------------------------------------
This message was sent using the comp.arch.fpga web interface on
http://www.FPGARelated.com
Article: 144782Hi In NOR-based flash memory, once a bit has been set to 0, only by erasing the entire block it can be changed back to 1. I am eager to know the reason for that behaviour/design ? Further, i wonder why can't NOR-based flash memory offer arbitrary random-access rewrite or erase operations ? Any ideas ? Thx in advans, Karthik BalaguruArticle: 144783
On Jan 1, 7:54=A0pm, Peter Alfke <al...@sbcglobal.net> wrote: > From the bowels of my computer I resurrected a file written more than > 3 years ago: > > Using Virtex-5 CLB as Multi-Port Memory > > The four M-LUTs in a half-CLB can be combined to form a quad-port RAM, > ideally suited for register-file applications. > The four LUTs, called A, B, C, and D are configured in such a way that > the write address applied to D is automatically also multiplexed onto > the write addressing of LUTs A, B, and C. > Writing into D thus also writes into the same location in A, B, and C, > but these three LUTs have their address inputs still available as read > addresses. (In this application, LUT D is never read.) > The structure functions as a quad-port RAM with one write port > (address applied to D) and common data written into LUTs A, B, and C . > There are three independent read ports (addresses applied to LUTs A, > B, and C.) Writing is synchronous, reading is combinatorial. > Each LUT can either be a 64 x 1, or a 32 x 2 RAM. > > A similar structure, using common read addresses and individual Data > inputs, acts as simple dual-port memory, either 3 bits wide and 64 > deep, or 3 bits wide and 32 deep. > > In the Virtex-5 MicroBlaze application, the 32 x 32 register file with > one write port and two read ports, using 384 LUTs in Virtex-4, is > reduced to 44 LUTs, a saving of over 88%. > > Peter Alfke, =A03-21-06 Greetings Peter, always a pleasure. You describe a physical implementation which folds beautifully into the Xilinx fabric showing how few routing resources are needed to implement the bits of the multi-port (read) memories. But isn't this precisely what one gets when inferring a single port write, multi-port read memory through HDL? For that, I wouldn't think example code would be needed since the inference can have the same physical implementation you describe. Without explicit placement constraints, both inferred and instantiated methods are left to the Place & Route to fold everything for each bit into single CLBs, aren't they? It's certainly easier to apply those constraints if the designer defines the names for each instance in the first place. The bigger challenge raised in this thread is the multi-port with two write ports which can be performed in CLBs very nicely but with a little overhead. If the reader has no interest in multi-port writes with CLB memories, you can ignore the rest of the message. reg [n:0] m1 [m:0], m2 [m:0]; wire [n:0] rd1, rd2, rd3; always @(posedge clk) if( we1 ) m1[wa1] <=3D wdata1 ^ m2[wa1]; always @(posedge clk) if( we2 ) m2[wa2] <=3D wdata2 ^ m1[wa2]; assign rd1 =3D m1[ra1] ^ m2[ra1]; assign rd2 =3D m1[ra2] ^ m2[ra2]; assign rd3 =3D m1[ra3] ^ m2[ra3]; Since m1 has 4 unique addresses, the inferred memory will be replicated for 4 total copies. Since 2 memories are needed for 2 writes, there are 2 sets of these 4 memory copies. Since writing a value to m1 doesn't affect m2, reading that address later results in rdx =3D=3D m1[was_wa1] ^ m2[was_wa1] =3D=3D (was_wdata1 ^ m2[was_wa1]) ^ m2 [was_wa1] =3D=3D was_wdata1 The XOR on the input and the output resurrects the original data written to that port independent of which read memory accesses it. The one caveat: two writes to the same address on the same clock results in no change to the existing data. Priority could be assigned to one write port by disabling the write on the other port when a conflict is detected instead. This is where CLB SelectRAM design gets interesting and fun!Article: 144784
On Jan 2, 11:30=A0am, karthikbalaguru <karthikbalagur...@gmail.com> wrote: > Hi > In NOR-based flash memory, once a bit has > been set to 0, only by erasing the entire block > it can be changed back to 1. I am eager > to know the reason for that behaviour/design ? > > Further, i wonder why can't NOR-based flash > memory offer arbitrary random-access rewrite > or erase operations ? > > Any ideas ? > > Thx in advans, > Karthik Balaguru The FPGA subgroup isn't the best place to ask about Flash fundamentals. Have you tried researching the issue? It comes down to how the floating gate transistors are arranged. See for instance http://www.eeherald.com/section/design-guide/esmod16.html for "Flash memory basics and its interface to a processor" where you'll see how the source lines (where word lines and bit lines also exist) are used in the erase.Article: 144785
On Jan 2, 10:03=A0pm, John_H <newsgr...@johnhandwork.com> wrote: > On Jan 2, 11:30=A0am, karthikbalaguru <karthikbalagur...@gmail.com> > wrote: > > > Hi > > In NOR-based flash memory, once a bit has > > been set to 0, only by erasing the entire block > > it can be changed back to 1. I am eager > > to know the reason for that behaviour/design ? > > > Further, i wonder why can't NOR-based flash > > memory offer arbitrary random-access rewrite > > or erase operations ? > > > Any ideas ? > > > Thx in advans, > > Karthik Balaguru > > The FPGA subgroup isn't the best place to ask about Flash > fundamentals. =A0Have you tried researching the issue? =A0 Okay, i have looped in comp.arch.embedded. Yeah, I have been searching regarding this & got other links but did not get a link that clearly conveys this info and hence this query. After lot of searches, got the below links - http://electronics.howstuffworks.com/flash-memory.htm http://www.embedded.com/columns/technicalinsights/165701775?_requestid=3D63= 5173 It seems that Flash memory uses in-circuit wiring to apply the electric field either to the entire chip or to predetermined sections known as blocks. This erases the targeted area of the chip, which can then be rewritten. Flash memory works much faster than traditional EEPROMs because instead of erasing one byte at a time, it erases a block or the entire chip, and then rewrites it. > It comes down to > how the floating gate transistors are arranged. =A0See for instance > http://www.eeherald.com/section/design-guide/esmod16.htmlfor "Flash > memory basics and its interface to a processor" where you'll see how > the source lines (where word lines and bit lines also exist) are used > in the erase. This link is good ! I understand that erasure operation is done through Quantum tunneling. Interesting to know that in NAND-flash, cells are connected in series resembling a NAND gate, and so the name. The series connection prevents the cells from being programmed individually. These cells must be read in series. So, it finally boils down to the design of flash memory that has dependency on predetermined sections known as BLOCKS or entire chip for its in-circuit wiring that applies electric field either to the entire chip or to predetermined sections known as BLOCKS !! Thx, Karthik BalaguruArticle: 144786
Hi, I need to write ASM hardware language for circuits. I wrote a lot about 10 years ago for Altera chip. Now I couldn't find the ASM hardware language definition file from Altera/Xilinx. Please help give a connection. Thank you. WengArticle: 144787
karthikbalaguru <karthikbalaguru79@gmail.com> wrote: > In NOR-based flash memory, once a bit has > been set to 0, only by erasing the entire block > it can be changed back to 1. I am eager > to know the reason for that behaviour/design ? First there was EPROM, which erased the whole chip with an external UV light source. Using avalanche breakdown to allow writing (storing charge on the floating gate), but no electronics to remove that charge. For some time there were EEPROMs that were electrically erasable, but the design was complicated and density not so high. The easy answer is that flash allows one to share the complication of the erase circuitry over a block. That allows for a significant increase in density. Some years ago there were ideas of using magnetic bubbles for non-volatile storage, and CCDs for volatile high density serial access storage, but neither caught on. Flash allows for very high bit density at reasonable access rates. Since many times block erase is needed, it fits in well with current needs. -- glenArticle: 144788
Weng Tianxiang <wtxwtx@gmail.com> wrote: > I need to write ASM hardware language for circuits. I wrote a lot > about 10 years ago for Altera chip. Now I couldn't find the ASM > hardware language definition file from Altera/Xilinx. I remember from XC4000 days the editor that would let one examine and modify the design at a very low level. I also used it to generate macros at a low level and instatiate those macros from high level verilog code. I never knew that called ASM, though. There are also the netlists, with the lowest one at the CLB or LUT level, which one might also be able to read, write, or modify. At FPGA densities, that is rarely useful or necessary. For lower density CPLD devices, I believe there is still a low level language to describe the design. -- glenArticle: 144789
Hi, I am using ISE 9.1 I had an old Digilab IIE board which i want to use. The Digilab IIE board can be programmed using the PC's parallel port. However, my PC has only USB ports. as such i bought an usb-DB25 cable to connect the parallel cable which comes with the board to my PC. Unfortunately when trying to configure FPGA through a simple design project, the cable is not recognised. the complete error log is attached below. Namely, the main error message is: Connecting to cable (Usb Port - USB21). Checking cable driver. File C:\WINDOWS\system32\drivers\xusbdfwu.sys not found. Driver file not found. Inf file version = 0. Driver xusbdfwu.sys version: 1021 (1029). Driver windrvr6.sys version = 8.1.0.0. WinDriver v8.10 Jungo (c) 1997 - 2006 Build Date: Aug 15 2006 X86 32bit SYS 14:21:34, version = 810. Cable connection failed. PROGRESS_END - End Operation. I have tried Xilinx Answer 30184) to noavail. any help please> Many thanks =========== error message // *** BATCH CMD : addDevice -p 1 -file "C:/iseProjects/Training/ BoardIIT/top_level.bit" '1': Loading file 'C:/iseProjects/Training/BoardIIT/top_level.bit' ... done. INFO:iMPACT:1777 - Reading C:/Xilinx91i/spartan2e/data/xc2s200e.bsd... INFO:iMPACT:501 - '1': Added Device xc2s200e successfully. ---------------------------------------------------------------------- ---------------------------------------------------------------------- Count ReleaseSemaphore rc = 298. GUI --- Auto connect to cable... // *** BATCH CMD : setCable -port auto AutoDetecting cable. Please wait. PROGRESS_START - Starting Operation. Connecting to cable (Parallel Port - LPT1). Checking cable driver. Driver windrvr6.sys version = 8.1.0.0. WinDriver v8.10 Jungo (c) 1997 - 2006 Build Date: Aug 15 2006 X86 32bit SYS 14:21:34, version = 810. Cable connection failed. Connecting to cable (Parallel Port - LPT2). Checking cable driver. Driver windrvr6.sys version = 8.1.0.0. WinDriver v8.10 Jungo (c) 1997 - 2006 Build Date: Aug 15 2006 X86 32bit SYS 14:21:34, version = 810. Cable connection failed. Connecting to cable (Parallel Port - LPT3). Checking cable driver. Driver windrvr6.sys version = 8.1.0.0. WinDriver v8.10 Jungo (c) 1997 - 2006 Build Date: Aug 15 2006 X86 32bit SYS 14:21:34, version = 810. Cable connection failed. Connecting to cable (Parallel Port - LPT4). Checking cable driver. Driver windrvr6.sys version = 8.1.0.0. WinDriver v8.10 Jungo (c) 1997 - 2006 Build Date: Aug 15 2006 X86 32bit SYS 14:21:34, version = 810. Cable connection failed. Connecting to cable (Usb Port - USB21). Checking cable driver. File C:\WINDOWS\system32\drivers\xusbdfwu.sys not found. Driver file not found. Inf file version = 0. Driver xusbdfwu.sys version: 1021 (1029). Driver windrvr6.sys version = 8.1.0.0. WinDriver v8.10 Jungo (c) 1997 - 2006 Build Date: Aug 15 2006 X86 32bit SYS 14:21:34, version = 810. Cable connection failed. PROGRESS_END - End Operation. Elapsed time = 4 sec. Cable autodetection failed. WARNING:iMPACT:923 - Can not find cable, check cable setup !Article: 144790
A common problem with USB to parallel port converters is they don't work. You will find many previous postings on this. Sometimes a Cardbus or Expresscard plug in parallel port will work but many laptops don't even have these. Some docking stations can offer a parallel port option and we can use the Xilinx and our own Prog2 Parallel Port cables like that with our HP laptops. Outside of the fairly expensive Xilinx USB cable there are a number of indirect USB solutions which don't work directly with Xilinx software. We also will be offering a low cost USB option (Prog3) with our own products, that is totally compatible with Xilinx software, later this month. We will also be offering this option to existing registered owners of Enterpoint boards. John Adair Enterpoint Ltd. On 3 Jan, 00:03, Angus <angusdun...@googlemail.com> wrote: > Hi, > > I am using ISE 9.1 > > I had an old Digilab IIE board which i want to use. The Digilab IIE > board can be programmed using the PC's parallel port. However, my PC > has only USB ports. as such i bought an usb-DB25 cable to connect the > parallel cable which comes with the board to my PC. Unfortunately when > trying to configure FPGA through a simple design project, the cable is > not recognised. the complete error log is attached below. Namely, the > main error message is: > > Connecting to cable (Usb Port - USB21). > Checking cable driver. > =A0File C:\WINDOWS\system32\drivers\xusbdfwu.sys not found. > Driver file not found. Inf file version =3D 0. > =A0Driver xusbdfwu.sys version: 1021 (1029). > =A0Driver windrvr6.sys version =3D 8.1.0.0. WinDriver v8.10 Jungo (c) 199= 7 > - 2006 Build Date: Aug 15 2006 X86 32bit SYS 14:21:34, version =3D 810. > Cable connection failed. > PROGRESS_END - End Operation. > > I have tried Xilinx Answer 30184) =A0to noavail. any help please> Many > thanks > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > error message > > // *** BATCH CMD : addDevice -p 1 -file "C:/iseProjects/Training/ > BoardIIT/top_level.bit" > '1': Loading file 'C:/iseProjects/Training/BoardIIT/top_level.bit' ... > done. > INFO:iMPACT:1777 - > Reading C:/Xilinx91i/spartan2e/data/xc2s200e.bsd... > INFO:iMPACT:501 - '1': Added Device xc2s200e successfully. > ---------------------------------------------------------------------- > ---------------------------------------------------------------------- > =A0Count ReleaseSemaphore rc =3D 298. > GUI --- Auto connect to cable... > // *** BATCH CMD : setCable -port auto > AutoDetecting cable. Please wait. > PROGRESS_START - Starting Operation. > Connecting to cable (Parallel Port - LPT1). > Checking cable driver. > =A0Driver windrvr6.sys version =3D 8.1.0.0. WinDriver v8.10 Jungo (c) 199= 7 > - 2006 Build Date: Aug 15 2006 X86 32bit SYS 14:21:34, version =3D 810. > Cable connection failed. > Connecting to cable (Parallel Port - LPT2). > Checking cable driver. > =A0Driver windrvr6.sys version =3D 8.1.0.0. WinDriver v8.10 Jungo (c) 199= 7 > - 2006 Build Date: Aug 15 2006 X86 32bit SYS 14:21:34, version =3D 810. > Cable connection failed. > Connecting to cable (Parallel Port - LPT3). > Checking cable driver. > =A0Driver windrvr6.sys version =3D 8.1.0.0. WinDriver v8.10 Jungo (c) 199= 7 > - 2006 Build Date: Aug 15 2006 X86 32bit SYS 14:21:34, version =3D 810. > Cable connection failed. > Connecting to cable (Parallel Port - LPT4). > Checking cable driver. > =A0Driver windrvr6.sys version =3D 8.1.0.0. WinDriver v8.10 Jungo (c) 199= 7 > - 2006 Build Date: Aug 15 2006 X86 32bit SYS 14:21:34, version =3D 810. > Cable connection failed. > Connecting to cable (Usb Port - USB21). > Checking cable driver. > =A0File C:\WINDOWS\system32\drivers\xusbdfwu.sys not found. > Driver file not found. Inf file version =3D 0. > =A0Driver xusbdfwu.sys version: 1021 (1029). > =A0Driver windrvr6.sys version =3D 8.1.0.0. WinDriver v8.10 Jungo (c) 199= 7 > - 2006 Build Date: Aug 15 2006 X86 32bit SYS 14:21:34, version =3D 810. > Cable connection failed. > PROGRESS_END - End Operation. > Elapsed time =3D =A0 =A0 =A04 sec. > Cable autodetection failed. > WARNING:iMPACT:923 - Can not find cable, check cable setup !Article: 144791
Hi, If someone can just give me directions how to start I would also be happy :) Sorry, this is the new link : http://www.mediafire.com/?h14dvjzn2zn The file to open is \PCI\pci\vhdl\example\xilinx\xlnx_auto_0.ise >On Jan 1, 11:03=A0am, "Ghostboy" <Ghost...@dommel.be> wrote: >> Nobody who can help me? > >You're asking for a LOT of work from someone or someone who happens to >actively use a development board that's been discontinued from Xilinx >(you can still purchase it from digilentinc.com) because the Virtex-II >Pro devices are getting old. > >Besides, the link in your Dec 14th email is invalid. > --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144792
"Ghostboy" <Ghostboy@dommel.be> writes: >Hi, >I want to send a video file from a pc to a FPGA (on a XUPV2P development >board) via the PCI interface. On the FPGA the video will be processed by an >algorithm. The result, after processing, will be send back to the pc. I >generated the VHDL-code of the algorithm in Simulink with Xilinx System >Generator (gateway_in and gateway_out are 8 bits wide). I also have the >VHDL-code of the PCI-core (from Xilinx). In Xilinx ISE I instantiated the >algorithm in the PCI-code. >The resolution of the video is 320x240. The device driver on the pc (Linux) >gives an interrupt at the beginning of every frame. Can someone tell me how >I have to adapt the code of the user application delivered by Xilinx ( code >can be found here : http://www.mediafire.com/?kyygtdm0wlj ) to give the >FPGA a sign to start processing the data and send the result back to the pc >after a frame has been processed? Is there a manner to check how many >bits/bytes/pixels passed by? >Thanks in advance. With the caveat that I know very little (and therefore this may not be useful :-)) is it a correct assumtion that the video is coming from another PCI card (such as a video capture card)? If so the interrupt being generated will be to the Linux device driver for the video card (not to the FPGA). It seems possible to me that the part you are missing isn't FPGA related at all but a linux device driver that will accept the video data from the source (driven by the frame interrupt) and send it via the PCI bus to the FPGA card for processing. You may find the PCI project (which has a linux device driver) at http://www.fpga4fun.com/PCI.html of use to you. The pci logic analyser code (assuming you can port it to your card of course) may help with the how many bytes made it across the interface. Peter Van EppArticle: 144793
Hello I am trying to write a vhdl code for DAC2624 on spartan3E,but I don't know how much I have to consider for SPI_SCK,should it be the same as my main clk which is 50Mhz? I wrote a vhdl code for ADC1407_1 and amplifier6912_1 on partan3E , I considerSPI_SCK to be 1Mhz in there ,but I don't know aboy DAC?should it be same? --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144794
Hello I am trying to write a vhdl code for DAC2624 on spartan3E,but I don't know how much I have to consider for SPI_SCK,should it be the same as my main clk which is 50Mhz? I wrote a vhdl code for ADC1407_1 and amplifier6912_1 on partan3E , I considerSPI_SCK to be 1Mhz in there ,but I don't know aboy DAC?should it be same? --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144795
mlajevar wrote: > I am trying to write a vhdl code for DAC2624 on spartan3E,but I don't know > how much I have to consider for SPI_SCK,should it be the same as my main > clk which is 50Mhz? First see the datasheet of the LTC2624, if such a high clock is allowed. But it doesn't make sense. Even if you want to update all 4 DACs with different values, you'll need 96 bits and the maximum bandwith of the DACs is 180 kHz, so the maximum required clock is 17 MHz. Create a clock which is sufficient for your required output update rate. And it is much easier to implement it with a DAC clock of 50MHz/n, with n>=2. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 144796
On 3 Jan, 19:15, John Adair <g...@enterpoint.co.uk> wrote: > A common problem with USB to parallel port converters is they don't > work. You will find many previous postings on this. Sometimes a > Cardbus or Expresscard plug in parallel port will work but many > laptops don't even have these. Some docking stations can offer a > parallel port option and we can use the Xilinx and our own Prog2 > Parallel Port cables like that with our HP laptops. > > Outside of the fairly expensive Xilinx USB cable there are a number of > indirect USB solutions which don't work directly with Xilinx software. > We also will be offering a low cost USB option (Prog3) with our own > products, that is totally compatible with Xilinx software, later this > month. We will also be offering this option to existing registered > owners of Enterpoint boards. > > John Adair > Enterpoint Ltd. Many thanks John for your reply. i hope XILINX with take this case seriously and prepare us a patch.Article: 144797
i found at last the datasheet@ http://www.digilentinc.com/Data/Products/D2E/D2E-rm.PDF (please p2 onwards re. the configuration cable). can my problem still be resolved?Article: 144798
On 1=D4=C21=C8=D5, =C9=CF=CE=E74=CA=B145=B7=D6, Ed McGettigan <ed.mcgetti..= .@xilinx.com> wrote: > On Dec 29, 6:42 pm, vcar <hi...@163.com> wrote: > > > > > > > On 12=D4=C229=C8=D5, =CF=C2=CE=E76=CA=B112=B7=D6, glen herrmannsfeldt <= g...@ugcs.caltech.edu> wrote: > > > > Frank Buss <f...@frank-buss.de> wrote: > > > > vcar wrote: > > > >> For certainreasons, I could not use battery on my board, so the > > > >> Virtex5 bitstream encryptioncould not be used. In this situation, = what > > > >> could I do to protect my design on areasonable level? > > > > Protecting against exact clones is difficult. In many cases, decodin= g > > > the bits back to logic is hard enough not to worry about that. > > > > > I don't know the answers to your questions, but I guess an attacker= could > > > > at least just desolder the XCF16P and reading it like the FPGA does= when > > > > booting, so even the read protection bit of the flash is useless. I= f you > > > > want to secure your device, I would use something like the DS2401. = This > > > > provides a unique id. You could save this in the flash and compare = it from > > > > the FPGA with the chip. The chip is available in packages which loo= ks like > > > > a capacitor or diode: > > > > As long as they don't read this newsgroup and know what to look for..= . > > > > -- glen > > > Hi, glen. > > My point is to protect my board from cloning, so the attacker do not > > need to decoding bit stream back to logic. Once they obtain the bit > > stream, they can produce my board themselves. > > I could not protect the PCB from cloning, so I have to do something on > > my bit stream. Otherwise it is very easy to copy my board.- Hide quoted= text - > > > - Show quoted text - > > If the bitstream is not using the AES encryption then there is very > little that you can do to prevent the entire board from being cloned > as anyone that has one of your original boards can easily extract the > data from the PROM. > > There are some alternatives, but they aren't as secure. See Xilinx > Whitepager WP266 and Application Note XAPP780 > > Ed McGettigan > -- > Xilinx Inc. Yeah, Now I decide to adopt DS2432 way.Article: 144799
On 2009=C4=EA12=D4=C230=C8=D5, =CF=C2=CE=E78=CA=B134=B7=D6, Frank Buss <f..= .@frank-buss.de> wrote: > vcar wrote: > > Comparing to DS2401, DS28E01 or DS2432 is more applicable. > > You are right, the DS2432 looks interesting with the SHA1 hash function. > But I couldn't find it at Digikey and you have to register at Maxim to ju= st > get the price for it, so maybe a small PIC (which has program read > protection) is better. > > > If I use these chips, need I use BSCAN_VIRTEX5 + ICAP_VIRTEX5 to > > monitor JTAG activities? > > I don't think this is needed, because an attacker could desolder the flas= h > anyway and simulate a FPGA to read the bitstream, or use a logic analyzer > for recording the FPGA boot process. > > -- > Frank Buss, f...@frank-buss.dehttp://www.frank-buss.de,http://www.it4-sys= tems.de Thank you for your advice. The short answer should be no any strange primitives in my final bit stream.
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