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>> >> I have recently become very interested in FPGA and DSP. Could somebody >> suggest to me a newbee started book and also a related experimental >> board. Some reputedly good books and resources on Verilog/VHDL and FPGA programming can also be found here: http://www.doulos.com/Article: 144851
Griffin wrote:
> Secondly, if I understand correctly, the pins of my custom peripheral
> are being removed from the project. I've looked around the internet a
> bit and suspect this might be done due to auto-optimization, but
> considering that these pins are, indeed, being used in the user_logic
It's not enough for a signal to be used by a process.
If a top level output port is not driven by a process -- no output pin.
If a top input input port is not read by a process -- no input pin.
> file, and the registers that they store their values in are being read
> out by my application C code,
correctly or all zeros?
-- Mike Treseler
Article: 144852
"rk" <ajrajkumar@gmail.com> writes:
>Hi Folks
> I have recently become very interested in FPGA and DSP. Could somebody
>suggest to me a newbee started book and also a related experimental board.
> I would also like to know the differences between the different Virtex
>families like Virtex 2, 4, 5 etc.
>Regards
>RK
Someone has already suggested fpga4fun which has tutorial articles for
newbies on various parts of fpga design. For books I like
http://www.fpgarelated.com/books.php
which has a fine collection of fpga books with reviews all in one place.
I'm considering ordering a couple that I have seen in there. Can't help on DSP
boards as I don't know anything about DSPs but if you elaborate on what you
want to do with the DSP, there are a lot of experienced and helpful people
in this newsgroup. You could do a lot worse than doing a search in the archive
for DSP in comp.arch.fpga for instance.
Peter Van Epp
Article: 144853>Hi Folks > > I have recently become very interested in FPGA and DSP. Could somebody >suggest to me a newbee started book and also a related experimental board. > > I would also like to know the differences between the different Virtex >families like Virtex 2, 4, 5 etc. > >Regards >RK > Altera has some very useful (free) online training for newbies, including a Basics of Programmable Logic course: http://www.altera.com/education/training/curriculum/fpga/trn-fpga.html. There are also free DSP courses: http://www.altera.com/education/training/curriculum/dsp/trn-dsp.html I work for Altera, so can't give you an unbiased view of Virtex chips =]Article: 144854
On Jan 7, 8:59=A0am, "RCIngham" <robert.ing...@gmail.com> wrote: > >On Jan 7, 2:41=3DA0am, "RCIngham" <robert.ing...@gmail.com> wrote: > >> >On Jan 6, 12:19=3D3DA0am, grigio <crowne...@gmail.com> wrote: > >> >> On 2 Gen, 19:21, Weng Tianxiang <wtx...@gmail.com> wrote: > > >> >> > Hi, > >> >> > I need to write ASM hardware language for circuits. I wrote a lot > >> >> > about 10 years ago for Altera chip. Now I couldn't find the ASM > >> >> > hardware language definition file from Altera/Xilinx. > > >> >> Perhaps PALASM? > > >> >Yes, it is similar language, but Altera has its own language name, an= d > >> >not called PALASM. > > >> >Weng > > >> Do you mean AHDL? > > >> --------------------------------------- =3DA0 =3DA0 =3DA0 =3DA0 > >> This message was sent using the comp.arch.fpga web interface > onhttp://www=3D > >.FPGARelated.com > > >Hi, > >Thank you. It is AHDL. Where can I find its definition file now? > > >Weng > > I suggest that you start at:http://quartushelp.altera.com/current/mergedP= rojects/hdl/ahdl/ahdl_in... > > If you have QuartusII on your local PC, the same information should be in > its help files. > > --------------------------------------- =A0 =A0 =A0 =A0 > This message was sent using the comp.arch.fpga web interface onhttp://www= .FPGARelated.com Hi, Thank you. That is what I want. WengArticle: 144855
I presume that's special pricing for "qualified educational institutions." On Jan 6, 4:10=A0am, David Fejes <fej...@gmail.com> wrote: > Hello everybody, > > can anyone tell me what is the difference between the University > Platform Cable (UW-USB-II-G) and the Platform Cable USB II (HW-USB-II- > G)? > There is almost no search result on the university platform cable, > however it is present at more webshops about half of price as platform > cable USB II. Has anyone tried it? Will it work with the iMPACT and > will it support the xilinx CPLDs? > > thank you in advanceArticle: 144856
On Jan 7, 5:54=A0pm, "Kati" <kwri...@altera.com> wrote:
> >Hi Folks
>
> > =A0 I have recently become very interested in FPGA and DSP. Could someb=
ody
> >suggest to me a newbee started book and also a related experimental
> board.
>
> > =A0 I would also like to know the differences between the different Vir=
tex
> >families like Virtex 2, 4, 5 etc.
>
> >Regards
> >RK
>
Different from Kati, I am more familiar with Xilinx. I worked there
for over 20 years...
"Virtex" is the generic name for the Xilinx FPGA families with highest
performance and most advanced features.
("Spartan" families emphasize lowest cost and lower power, but offer
less performance and fewer features.)
The numbers 2,4,5,6 represent the family evolution over time. Virtex6
is the newest family.
In almost every respect, any newer family is superior to its
predecessor, but members of the previous family are sometimes more
available, and might be better supported, especially with a wider
array of evaluation boards. For any new design, forget Virtex2: it is
really obsolete. Virtex 4,5,and 6 offer better features and more
performance for the money, and better software support. Explore
Virtex6 for its desirable features but also check the availability
(especially of evaluation boards), and compare it to the older, less
advanced but perhaps more widely available Virtex5. Use Virtex4 only
if there is a compelling reason, and when you have no need for the
better performance and more advanced features of the younger
families.
The basic structures of these families are very similar, if you are
familiar with one you can easily move to another.
For an overview of their capabilities, there are popular "User Guide
Lite" for Virtex5 and Virtex6 available on the web.
( www.pldesignline.com/howto/most_popular/ ).
Peter Alfke
Article: 144857
On Jan 7, 9:02=A0pm, Peter Alfke <al...@sbcglobal.net> wrote:
> On Jan 7, 5:54=A0pm, "Kati" <kwri...@altera.com> wrote:> >Hi Folks
>
> > > =A0 I have recently become very interested in FPGA and DSP. Could som=
ebody
> > >suggest to me a newbee started book and also a related experimental
> > board.
>
> > > =A0 I would also like to know the differences between the different V=
irtex
> > >families like Virtex 2, 4, 5 etc.
>
> > >Regards
> > >RK
>
> Different from Kati, I am more familiar with Xilinx. I worked there
> for over 20 years...
> "Virtex" is the generic name for the Xilinx FPGA families with highest
> performance and most advanced features.
> ("Spartan" families emphasize lowest cost and lower power, but offer
> less performance and fewer features.)
> The numbers 2,4,5,6 represent the family evolution over time. Virtex6
> is the newest family.
> In almost every respect, any newer family is superior to its
> predecessor, but members of the previous family are sometimes more
> available, and might be better supported, especially with a wider
> array of evaluation boards. For any new design, forget Virtex2: it is
> really obsolete. Virtex 4,5,and 6 offer better features and more
> performance for the money, and better software support. Explore
> Virtex6 for its desirable features but also check the availability
> (especially of evaluation boards), and compare it to the older, less
> advanced but perhaps more widely available Virtex5. Use Virtex4 only
> if there is a compelling reason, and when you have no need for the
> better performance and more advanced features of the younger
> families.
> The basic structures of these families are very similar, if you are
> familiar with one you can easily move to another.
> For an overview of their capabilities, there are popular "User Guide
> Lite" for Virtex5 and Virtex6 available on the web.
> ( =A0www.pldesignline.com/howto/most_popular/=A0 =A0).
> Peter Alfke
make that:
http://www.pldesignline.com/howto/most_popular/
Article: 144858There are not many linked books and boards that I have seen but I am not a DSP specialist so there might be something I don't know about.The problem for authors is the family, and the related development boards, turnover rate. Many boards effectively only have lifetime of aa couple of years although some vendors like ourselves supply them as OEM and COTS solutions giving a reason to extend board product lifetimes to 5,10 or 20 years. What materials I have seen are things like university course materials that typically use a usually a lower end board typically based on Spartan or Cyclone parts. You can find some of these materials by googling for something like FPGA DSP. The Virtex family general as said elsewhere you get more for your money going from Virtex (1) to now Virtex-6. In the later families the SX variants are more DSP orientated and have more ram and multiplier blocks the main resources generally needed. Depending on your application don't rule out the lower stuff as well. Some of the recent Spartan families are quite good in the mid-end DSP market and certainly can beat a DSP processor approach for performance. Some useful bits and pieces can be found on our website at http://www.enterpoint.co.uk/techitips/techitips.html. John Adair Enterpoint Ltd. On 7 Jan, 12:38, "rk" <ajrajku...@gmail.com> wrote: > Hi Folks > > =A0 =A0I have recently become very interested in FPGA and DSP. Could some= body > suggest to me a newbee started book and also a related experimental board= . > > =A0 =A0I would also like to know the differences between the different Vi= rtex > families like Virtex 2, 4, 5 etc. > > Regards > RKArticle: 144859
Thank you. I've checked it with the dealers and you have right, it is for the educational institutions. However - if anyone is interested - i've found a cheaper alternative: Digilent XUP USB-JTAG Programming Cable has the same capabilities and works with the iMPACT software. have a nice day, Dave On jan. 8, 05:43, mng <michael.jh...@gmail.com> wrote: > I presume that's special pricing for "qualified educational > institutions." > > On Jan 6, 4:10=A0am, David Fejes <fej...@gmail.com> wrote: > > > > > Hello everybody, > > > can anyone tell me what is the difference between the University > > Platform Cable (UW-USB-II-G) and the Platform Cable USB II (HW-USB-II- > > G)? > > There is almost no search result on the university platform cable, > > however it is present at more webshops about half of price as platform > > cable USB II. Has anyone tried it? Will it work with the iMPACT and > > will it support the xilinx CPLDs? > > > thank you in advanceArticle: 144860
"whygee" <yg@yg.yg> wrote in message news:hi5896$h18$1@speranza.aioe.org... > hi, > > Tom Kotwal wrote: >> - Core 2 Duo vs i7? > depends if you can find a laptop with it. > It seems to be quite worth it but the i7 is much > more expensive... It may have changed since the > last time I've looked, This month edition of PCPro (UK edition but I believe they use the same articles worldwide) tested 12 of the latest laptops and the winner is the Dell Studio 15 which comes with a 1.6GHz Core I7-720QM. According to the article the £653 (ex. VAT) Dell Studio beats many £2000 high-end Core2 laptops in performance. Unfortunately the battery life is not that great but then again I don't think you will be running a P&R session at the airport :-) Hans. www.ht-lab.com Intel has just announced > i7 derivatives (i5 and i3 from memory, look /.) > for desktops and laptops. > >> - How important is cache size? > very. So choose the laptop with the largest L2 & L3, > over raw speed : being memory access dependent, > many P&R algos will stall the CPU... > Also those algos are difficult to parallelize > so don't waste money on a quad-core, > one core will be busy with P&R while the other > will remain for the OS GUI. > > Oh, I think that some Toshiba have 2 (two !) > disk drive slots. Might be interesting in RAID :-) > >> - How much memory should I get? Is 4GB enough? > should be, add some swap too. > Check that your OS supports as much (well, the recent > kernels support at least 64GB but MS's marketing department has > crippled actual /use/ of detected RAM, see a past /. article). > But FAST memory and several channels are recommended. > Bandwidth and access time are to be preferred. > > With small designs on Actel, I have seen that I don't > consume as much memory as I thought. Like 500M peak or so... > Vista consumes about as much :-D > Now I have not succeeded in running it under Linux > but I expect much more comfort. > > ... > > I'm currently going the other route with a /small/ ACER ONE netbook > (Atom dual-thread CPU, XP and single DDR2 slot upgraded to 2GB) > so I can S&P&R in travel. I wonder what the results will be, > compared to the somewhat bulkier Toshiba with a Core2 > at the same CPU speed. Price and size have been halved, however :-) > > But given that most of the time is lost clicking the same dialogs > all the time, and that those damn antiviruses/toolbars/indexers/GUI widgets > waste RAM&cycles, I don't expect a big difference... > The much smaller size and the lower price make it more like > a commodity, something replaceable and that can be carried along... > >> Thanks! > happy hacking, > >> -Tom > yg > > -- > http://ygdes.com / http://yasep.orgArticle: 144861
HT-Lab wrote: > "whygee" <yg@yg.yg> wrote in message news:hi5896$h18$1@speranza.aioe.or= g... >> hi, >> >> Tom Kotwal wrote: >>> - Core 2 Duo vs i7? >> depends if you can find a laptop with it. >> It seems to be quite worth it but the i7 is much >> more expensive... It may have changed since the >> last time I've looked, >=20 > This month edition of PCPro (UK edition but I believe they use the same= articles=20 > worldwide) tested 12 of the latest laptops and the winner is the Dell S= tudio 15=20 > which comes with a 1.6GHz Core I7-720QM. According to the article the =A3= 653 (ex.=20 > VAT) Dell Studio beats many =A32000 high-end Core2 laptops in performan= ce.=20 > Unfortunately the battery life is not that great but then again I don't= think=20 > you will be running a P&R session at the airport :-) OK so there are i7 laptops that don't cost an arm and a leg, great :-) But then, the battery life is more important for me when i'm "away" (like, a couple of weeks, once a year or so...) because electricity can become very scarce. I spend maybe several minutes in P&R but I spend much more time ckicking my way through those damned dialogs... http://farm3.static.flickr.com/2490/3840160076_f178850077_b.jpg yes it's me under the tree, next to the tent, with 2 laptops... I also use them in the coach/bus (24h trip) so capacity is critical ;-) I'll try to hack a big LiIon pack for the laptops and I even plan to bring several solar panels next year :-) Whatever/However it looks, that's my most productive period in the year. I assume that the lack of Internet access is somewhat related to this increase... :-) wow, things have evolved so much in 10 or 15 years... > Hans. > www.ht-lab.com yg --=20 http://ygdes.com / http://yasep.orgArticle: 144862
On Thu, 07 Jan 2010 13:33:43 -0800, emeb wrote: > On Jan 7, 1:01Â pm, General Schvantzkoph <schvantzk...@yahoo.com> wrote: > >> One reason to get an iCore7 is that it can hold 12G of RAM at >> reasonable prices. The large members of the V5 family need more than >> 8G, the LX300 uses 10G for example. If you are only using smaller FPGAs >> then 8G is fine. I wouldn't consider anything less than 8G these days. >> >> You also need a 64bit OS. If you must use Windows then get a 64 bit >> version. > > Interesting - what version of ISE are you basing this on? I'm using > 10.1.3 to build against a V5 SX95T in only 4G on a Linux X86_64 system > and not running into any memory issues. > > Eric Xilinx also has a memory recommendation page. It's quite useful if you plan to dimension a pc for a specific device. http://www.xilinx.com/ise/products/memory.htm -- Regards, Maik H. <insert_my_first_name_here>@elektronensturm.deArticle: 144863
Thanks everyone for all the good advice. Its been a big help. A Dell Studio 15 had been at the top of my list already, and you've helped me to confirm that it will do the job nicely. The only remaining question I have is how Xilinx tools are on Windows 7. ISE doesn't officially support it, but I would imagine that it would still work. Does anyone have any personal experience with this? Thanks again. -TomArticle: 144864
On Fri, 08 Jan 2010 09:10:34 +0000, HT-Lab wrote: > "whygee" <yg@yg.yg> wrote in message > news:hi5896$h18$1@speranza.aioe.org... >> hi, >> >> Tom Kotwal wrote: >>> - Core 2 Duo vs i7? >> depends if you can find a laptop with it. It seems to be quite worth it >> but the i7 is much more expensive... It may have changed since the last >> time I've looked, > > This month edition of PCPro (UK edition but I believe they use the same > articles worldwide) tested 12 of the latest laptops and the winner is > the Dell Studio 15 which comes with a 1.6GHz Core I7-720QM. According to > the article the £653 (ex. VAT) Dell Studio beats many £2000 high-end > Core2 laptops in performance. Unfortunately the battery life is not that > great but then again I don't think you will be running a P&R session at > the airport :-) > > Hans. > www.ht-lab.com The benchmarks in magazines and on the hardware sites are useless. They are mostly testing gaming and multimedia performance which is completely irrelevant. When you see benchmarks where the iCore7 exceeds the performance of the Core2 it's because they are measuring the performance of the multimedia extensions to the instruction set. Those instructions aren't used by any CAE tools. What's important is basic integer performance which really boils down to cache size and latency.Article: 144865
On Jan 7, 2:21=A0pm, "rk" <ajrajku...@gmail.com> wrote: > >rk <ajrajku...@gmail.com> wrote: > >> Hi Folks > > >> =A0 =A0I have recently become very interested in FPGA and DSP. Could > somebody > >> suggest to me a newbee started book and also a related experimental > board. > > >> =A0 =A0I would also like to know the differences between the different > Virtex > >> families like Virtex 2, 4, 5 etc. > > >Where did you start? Where did you struggle? > > >Trywww.xilinx.com... > > >-- > >Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-da= rmstadt.de > > >Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt > >--------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- > > Hi > =A0 =A0Yes, I have been to that website, and I see a lot of datasheets > for Virtex-2, 4, 5, 6 etc, but I do not able to get a comprehensive > evolution of the family and the enhancements in sucessive 2, 4, 5 etc > families. > =A0 =A0Also, I am looking for a good book along with a board that I can > but and develop some hands on experience. > =A0 =A0Visitingwww.xilinx.comresults in an information overload for > a beginner. > > Regards > RK RK, I think you left me a phone message which I tried to return, but very late. Yes, learning FPGA design can be a daunting task. It is a combination of a number of areas, including logic design, system design, software and signal integrity among others depending on your application. Conceptually it is simple, you just decide what your design should do and you describe it in an HDL. Or is you are stuck in the past you can use schematics, but very, very few do these days. Once your design is described, it is compiled by the tools along with a preference file indicating what signals connect to what pins as well as any timing requirements (although timing specs can get a bit complicated). The resulting bit file is loaded into your part and you can test. Of course, it is much smarter to simulate your design before you try testing. It is much easier to see the innerds of the chip in a simulator than it is in the real chip. That is the simple view from 10,000 feet (3,000 meters). When you actually try to learn to do all this, there are so many details that it is much harder. Learning the details is the hard part of FPGA design. It is much easier if you learn it a little at a time, focusing on the immediate parts and ignoring the more complicated parts until later. For example, if you try some designs that are clocked at 10 MHz or lower, it is likely that it will work without timing constraints which can help a newbie. My personal preference is to design hardware, rather than write software. This is a philosophical difference. I think in terms of the hardware I want and describe that using the HDL. Others prefer to just think in terms of describing the functioning of the design and let the tools figure out what hardware is needed. This can be easier for a novice, but can result in some pretty inefficient implementations. Still, it isn't hard to learn how to write your code to be more efficient, so in some ways I think I am becoming a dinosaur. I would suggest that you buy a base level Spartan kit for under $100. The free webpack tools will give you all you need to get started. Rather than mess with a text book which will not be specific to your tools or hardware, use the tutorials with the tools and learn the basics that way. Then come here when you have trouble. There are tones of folks here who will enjoy helping you. RickArticle: 144866
General Schvantzkoph wrote: > On Fri, 08 Jan 2010 09:10:34 +0000, HT-Lab wrote: > The benchmarks in magazines and on the hardware sites are useless. They > are mostly testing gaming and multimedia performance which is completely > irrelevant. When you see benchmarks where the iCore7 exceeds the > performance of the Core2 it's because they are measuring the performance > of the multimedia extensions to the instruction set. Those instructions > aren't used by any CAE tools. What's important is basic integer > performance which really boils down to cache size and latency. and bandwidth too :-) However, I just tested the Atom-based ACER ONE with Actel's Libero and it does not seem to lag much behind the Core2 duo Toshiba that I have used since 2008. OK, my designs are small, so a lot of OS overhead and GUI clutter comes into the equation, but my point is : a cheap "netbook" is enough for small/medium designs. Price is lower and portability is better than "heating lap bricks". For the price of a PDA and about 2x the size, I can do full VHDL development so I'm satisfied :-) regards, yg -- http://ygdes.com / http://yasep.orgArticle: 144867
"General Schvantzkoph" <schvantzkoph@yahoo.com> wrote in message news:7qp0tdFhpkU5@mid.individual.net... > On Fri, 08 Jan 2010 09:10:34 +0000, HT-Lab wrote: > >> "whygee" <yg@yg.yg> wrote in message >> news:hi5896$h18$1@speranza.aioe.org... >>> hi, >>> >>> Tom Kotwal wrote: >>>> - Core 2 Duo vs i7? >>> depends if you can find a laptop with it. It seems to be quite worth it >>> but the i7 is much more expensive... It may have changed since the last >>> time I've looked, >> >> This month edition of PCPro (UK edition but I believe they use the same >> articles worldwide) tested 12 of the latest laptops and the winner is >> the Dell Studio 15 which comes with a 1.6GHz Core I7-720QM. According to >> the article the £653 (ex. VAT) Dell Studio beats many £2000 high-end >> Core2 laptops in performance. Unfortunately the battery life is not that >> great but then again I don't think you will be running a P&R session at >> the airport :-) >> >> Hans. >> www.ht-lab.com > > > The benchmarks in magazines and on the hardware sites are useless. They > are mostly testing gaming and multimedia performance which is completely > irrelevant. You may be right although I wouldn't call them useless, with any benchmark you have to use it as a rough indicator. > When you see benchmarks where the iCore7 exceeds the > performance of the Core2 it's because they are measuring the performance > of the multimedia extensions to the instruction set. Those instructions > aren't used by any CAE tools. Are you sure, do you know what each vendors is using for their algorithms? I wouldn't be surpriced if they use some of the SIMD capabilities. > What's important is basic integer > performance which really boils down to cache size and latency. Right, so a quick google showed that the SPECint for the slowest i7-920 is nearly 20% higher than the fastest Extreme QX9770. Benchmarking is notoriously difficult and even the SPECint won't tell you if a PC is fast or not given that it depends on so many other factors. PCPro seems to be using a multitude of applications ranging from office apps to multitasking so I guess it is better than nothing. Hans www.ht-lab.comArticle: 144868
On Fri, 08 Jan 2010 16:25:22 +0000, HT-Lab wrote: > "General Schvantzkoph" <schvantzkoph@yahoo.com> wrote in message > news:7qp0tdFhpkU5@mid.individual.net... >> On Fri, 08 Jan 2010 09:10:34 +0000, HT-Lab wrote: >> >>> "whygee" <yg@yg.yg> wrote in message >>> news:hi5896$h18$1@speranza.aioe.org... >>>> hi, >>>> >>>> Tom Kotwal wrote: >>>>> - Core 2 Duo vs i7? >>>> depends if you can find a laptop with it. It seems to be quite worth >>>> it but the i7 is much more expensive... It may have changed since the >>>> last time I've looked, >>> >>> This month edition of PCPro (UK edition but I believe they use the >>> same articles worldwide) tested 12 of the latest laptops and the >>> winner is the Dell Studio 15 which comes with a 1.6GHz Core I7-720QM. >>> According to the article the £653 (ex. VAT) Dell Studio beats many >>> £2000 high-end Core2 laptops in performance. Unfortunately the battery >>> life is not that great but then again I don't think you will be >>> running a P&R session at the airport :-) >>> >>> Hans. >>> www.ht-lab.com >> >> >> The benchmarks in magazines and on the hardware sites are useless. They >> are mostly testing gaming and multimedia performance which is >> completely irrelevant. > > You may be right although I wouldn't call them useless, with any > benchmark you have to use it as a rough indicator. > >> When you see benchmarks where the iCore7 exceeds the performance of the >> Core2 it's because they are measuring the performance of the multimedia >> extensions to the instruction set. Those instructions aren't used by >> any CAE tools. > > Are you sure, do you know what each vendors is using for their > algorithms? I wouldn't be surpriced if they use some of the SIMD > capabilities. > >> What's important is basic integer >> performance which really boils down to cache size and latency. > > Right, so a quick google showed that the SPECint for the slowest i7-920 > is nearly 20% higher than the fastest Extreme QX9770. > > Benchmarking is notoriously difficult and even the SPECint won't tell > you if a PC is fast or not given that it depends on so many other > factors. PCPro seems to be using a multitude of applications ranging > from office apps to multitasking so I guess it is better than nothing. > > Hans > www.ht-lab.com The only way to really find out what the fastest machine for your workload is to do the benchmarking yourself. Whenever I build a new machine I spend a few days benchmarking it versus my other machines. I'm primarily interested in NCVerilog performance and secondarily on Xilinx and Altera performance. I run a suite of Verilog simulations that generally take a few hours to complete. I measure single core performance and then multiple cores. My most recent machine is an iCore7 920 with 12G of RAM, it's the first machine that I've built that really disappointed me. My second most recent machine is a Core2 8400 with 8G. When running on a single core the Core2 is about 10% faster then the iCore7 on a clock for clock basis. However the Core2 can run at a much faster clock then the iCore7. I have both machines overclocked using a Thermalright Ultra 120 extreme. The Core2 is running at 4GHz, the fastest I could get the iCore7 to run is 3.3GHz. In both cases I used sys_basher (available in the Fedora repositories for F10, F11 and F12, and in the EPEL repository for CentOS5) to determine the fastest reliable clock speed for each machine. When you combine the actual clock rate with the per clock NCsim performance the Core2 beats the iCore7 by a substantial margin. On throughput the two machines are about even. The iCore7 has four cores vs two for the Core2. However the undersized cache on the iCore7, 8M/four cores, cripples it so that the two cores on the Core2 do as much work as the four cores on the iCore7. The iCore7 does out perform the Core2 on a clock for clock basis when running Xilinx tools. However the difference is smaller then the difference in actual clock speed so the the Core2 is a little faster even on Xilinx tools.Article: 144869
On Jan 7, 9:24=A0am, Tom Kotwal <tkot...@gmail.com> wrote: > Hi All, > > I'm speccing out a new windows PC that I'll use with Xilinx tools, > probably Webpack and Modelsim, and I'm looking for some advice to make > sure the tools will run fast. I know memory is important, but what > else? Also, what pitfalls should I watch out for? > > I'm not sure how relevant this info is, but I'm probably going to > target something in the ballpark of a Virtex-5 LX50. Also, I'm > planning on getting a laptop because I'll need to travel quite a bit > with it. > > Some specific questions: > > - Have people had any problems with Windows 7? 32 bit or 64? Is it > useful to have Win 7 Pro so that I can use XP mode? > - Core 2 Duo vs i7? > - How important is cache size? > - How much memory should I get? Is 4GB enough? > > Thanks! > > -Tom If you're only building an LX50, you should be fine with 4GB. I have a few different machines and have built LX50s on a 2 GB machine. Most new machines that we've procured are i7 based, although not because of Xilinx requirements. Some of our proprietary software takes advantage of the multithreading. The Xilinx tools do no generally but the i7's multi-channel memory allows you to do something else while running the Xilinx tools. We just installed a few Windows 7, 64-bit machines (both Professional and Home Premium) and haven't had any problems to report so far. On Windows Vista Home Premium, we had a few anomalies with the "Clock Report" function. On Windows Vista Home Premium, 64-bit, we saw problems when opening new files. The problem didn't exist on 32-bit machines and the problem didn't show up on 64-bit machines after all the files were established. -- Steve Knapp Prevailing Technology www.prevailing-technology.comArticle: 144870
> > Secondly, if I understand correctly, the pins of my custom peripheral > > are being removed from the project. I've looked around the internet a > > bit and suspect this might be done due to auto-optimization, but > > considering that these pins are, indeed, being used in the user_logic > > It's not enough for a signal to be used by a process. > If a top level output port is not driven by a process -- no output pin. > If a top input input =A0port is not read by a process =A0 -- no input pin= . Thanks, it was something along those lines; there was a missing 'in' declaration in one part of my project that EDK wasn't catching as it compiled; it was just optimizing that part out. Thanks! > > file, and the registers that they store their values in are being read > > out by my application C code, > > correctly or all zeros? Actually, at this point, it's neither. It's a bit of a dumb thing, but I haven't figured out how to actually run my firmware on my FPGA board. I'm using the ML402 (Virtex-4), which has a compact flash card that can store bitstreams or ACE files to configure the FPGA with, but I haven't been able to work out how to do it just yet (my compact flash reader being on backorder doesn't help either). I'm trying to figure out how to program the ML402 using ONLY the JTAG connector, but there are a whole bunch of settings (ACE, Linear Flash, Platform Flash, and 8 DIP switches for a 'configuration address') that I can't seem to find the right combination of. Has anyone got any experience programming the ML402 using only JTAG? Is it even possible? Thanks! Sean.Article: 144871
On Jan 10, 8:28=A0pm, Griffin <captain.grif...@gmail.com> wrote: > > > Secondly, if I understand correctly, the pins of my custom peripheral > > > are being removed from the project. I've looked around the internet a > > > bit and suspect this might be done due to auto-optimization, but > > > considering that these pins are, indeed, being used in the user_logic > > > It's not enough for a signal to be used by a process. > > If a top level output port is not driven by a process -- no output pin. > > If a top input input =A0port is not read by a process =A0 -- no input p= in. > > Thanks, it was something along those lines; there was a missing 'in' > declaration in one part of my project that EDK wasn't catching as it > compiled; it was just optimizing that part out. Thanks! > > > > file, and the registers that they store their values in are being rea= d > > > out by my application C code, > > > correctly or all zeros? > > Actually, at this point, it's neither. It's a bit of a dumb thing, but > I haven't figured out how to actually run my firmware on my FPGA > board. I'm using the ML402 (Virtex-4), which has a compact flash card > that can store bitstreams or ACE files to configure the FPGA with, but > I haven't been able to work out how to do it just yet (my compact > flash reader being on backorder doesn't help either). > > I'm trying to figure out how to program the ML402 using ONLY the JTAG > connector, but there are a whole bunch of settings (ACE, Linear Flash, > Platform Flash, and 8 DIP switches for a 'configuration address') that > I can't seem to find the right combination of. > > Has anyone got any experience programming the ML402 using only JTAG? > Is it even possible? > > Thanks! > > Sean. It's not that complicated. Just hook up the JTAG cable to the JTAG connector on the board and start iMPACT. The LinearFlash, PROM, and SystemACE settings are for power-on configuration only. Ed McGettigan -- Xilinx Inc.Article: 144872
I am using JTAG parallel cable to program FPGA, while programming the FPGA code into the internal flash power was disconnected and finally "PROGRAM FAILED" message was observed. I had tried to program several times but still not able to program. The observed log is below, please find it. INFO:iMPACT - Current time: Fri Jan 8 21:38:55 2010 // *** BATCH CMD : Program -p 1 -e -v PROGRESS_START - Starting Operation. Maximum TCK operating frequency for this device chain: 10000000. Validating chain... Boundary-scan chain validated successfully. '1': SPI access core not detected. SPI access core will be downloaded to the device to enable operations. INFO:iMPACT - Downloading core file C:/Xilinx/11.1/ProgrammingTools/spartan3a/data/xc3s200an_spi.cor. '1': Downloading core... done. '1': Reading status register contents... CRC error : 0 IDCODE not validated while writing FDRI : 0 DCM Locked : 1 status of GTS_CFG_B : 1 status of GWE : 1 status of GHIGH : 1 value of VSEL pin 0 : 1 value of VSEL pin 1 : 1 value of VSEL pin 2 : 1 value of MODE pin M0 : 1 value of MODE pin M1 : 1 value of MODE pin M2 : 0 value of CFG_RDY (INIT_B) : 1 DONEIN input from Done Pin : 1 SYNC word not found : 0 INFO:iMPACT:2219 - Status register values: INFO:iMPACT - 0011 1111 1110 1100 INFO:iMPACT:2492 - '1': Completed downloading core to device. INFO:iMPACT - '1': Checking done pin....done. '1': Core downloaded successfully. INFO:iMPACT - Address 0x00000000 is in sector 0. INFO:iMPACT - Start block = 0 for address 0x00000000. INFO:iMPACT - Address 0x0002480B is not located at the start of a sector boundary. The whole sector will be erased. INFO:iMPACT - Address 0x0002480B is in sector 3. INFO:iMPACT - End block = 95 for address 0x0002480B. INFO:iMPACT - Address 0x00000000 is in sector 0. INFO:iMPACT - Address 0x0002480B is not located at the start of a sector boundary. The whole sector will be erased. INFO:iMPACT - Address 0x0002480B is in sector 3. INFO:iMPACT - Address 0x00000000 is in sector 0. INFO:iMPACT - Address 0x0002480B is not located at the start of a sector boundary. The whole sector will be erased. INFO:iMPACT - Address 0x0002480B is in sector 3. INFO:iMPACT - '1': Sector '0' is protected. INFO:iMPACT - '1': Sector '1' is protected. INFO:iMPACT - '1': Sector '2' is protected. INFO:iMPACT - '1': Sector '3' is protected. '1': Some sectors addressed by the configuration file are data protected. '1': One or more sectors used by the current configuration file is protected. Perform stand-alone erase operation to clear the protection. '1': Configuration data download to FPGA was not successful. DONE did not go high, please check your configuration setup and spi mode settings. PROGRESS_END - End Operation. Elapsed time = 20 sec. Request your response at the earliest. Regards, Salma --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144873
Hey guys... I need a little help with my E1 interface. I have an internal clock and the E1 clock. When E1 chip (MT9076B) is present I use the E1 clock + E1 F0 signals, else I use the internal clock. I want to use a DCM to lock the phase of internal clock (4.096MHz) with the E1 external clock. Is it possible? Today I have a process to detect if E1 F0 signals is present. If its present, I switch from internal clock to E1 clock : clk_res <= clk_int when E1_present = 0 else clk_e1; I know its a very bad design technique, but its an old code from another guy and I am looking to make the things right. What is the best way to interface with E1? Can someone help me? Thanks!Article: 144874
Hey guys... I need a little help with my E1 interface. I have an internal clock and the E1 clock. When E1 chip (MT9076B) is present I use the E1 clock + E1 F0 signals, else I use the internal clock. I want to use a DCM to lock the phase of internal clock (4.096MHz) with the E1 external clock. Is it possible? Today I have a process to detect if E1 F0 signals is present. If its present, I switch from internal clock to E1 clock : clk_res <= clk_int when E1_present = 0 else clk_e1; I know its a very bad design technique, but its an old code from another guy and I am looking to make the things right. What is the best way to interface with E1? Can someone help me? Thanks! --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.com
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